TWI355660B - Non-volatile memory with boost structures and meth - Google Patents

Description

1355660 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to non-volatile memory. [Prior Art] Half-life '^ 5 彳 彳 体 ' has been used more and more - non-volatile semiconductor memory for cellular phones, digital cameras, personal digital help S, mobile computing f, Non-action computing equipment 4 and other devices. Erasable erasable programmable read only memory (EEPR0M) and flash memory

The system is the most common non-volatile semiconductor memory. The use of flash memory (also a type of EEPROM) can erase the entire memory array or a portion of the memory in a single step compared to a conventional, fully featured EEPROM. The EEPROM and the fast 丨 丨 椚 ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... The floating gate is located between the source region and the non-polar region. - (iv) The interpole is provided above and insulated from the floating gate. The critical value of the thus formed transistor is controlled by the amount of charge remaining on the pole. The minimum amount of voltage that must be conducted between the gate and the gate before the transistor is turned on. Floating power: Level control. Some of the book brains and flash memory are (four) a floating gate of the charge of the mind, and thus the port I can be programmed between two states (for example, a state and a stylized state). /Erase the memory* The flash memory device is sometimes called a binary flash memory device because: ^6503^ 1355660 A memory component can store one bit of data. The sigmoid 4 (also known as multi-level) flash memory device is implemented by identifying a plurality of different allowed/validized programmed threshold voltage ranges. Each memory device can store two memory elements in each of the four discrete charge bands of the U-threshold voltage range. Bit information. In general, the program applied to the control gate during the program operation should be a series of pulses whose magnitude increases with time. In the - possible method, the pulse magnitude is increased by a step size of, for example, 0.2 to 0.4 V with each successive pulse. VpGM can be applied to the control gate of a flash memory device. The verification operation is performed during the period between the program pulses. That is, the stylized levels of the components of the group of components that are parallelized are read between consecutive stylized pulses to determine that the level is equal to or greater than a verify level to which the component is being programmed. For a multi-state flash memory read array, an authentication step can be performed for each state of an element to determine if the element has reached its verification level associated with the material. For example, a multi-state memory element capable of storing data in four states may need to perform a verify operation for three comparison points. In addition, when programming an EEPROM or flash memory device (such as a nand flash memory device), it will typically be applied to the control interpole and ground the bit line, thereby enabling the cell or memory component. Electrons in the channel (for example, storage elements) are injected into the floating idler. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and 126503.doc 1355660 and the threshold voltage of the memory component rises to treat the memory component as being programmed. . More information on such stylization can be found in U.S. Patent No. 6,859,397 entitled "Source Side Self Boosting Technique For Non-Volatile US Patent Application No. 2005/0024939, entitled "Detecting 〇ver Pr〇grammed Memory"; both are fully incorporated herein by reference.

However, during the "stylization period", various problems such as program disturb may occur due to the need to apply a higher voltage to the word line. Accordingly, there has been a need to further optimize stylized operations as well as verify and read operations. SUMMARY OF THE INVENTION The present invention addresses these and other problems by providing a non-volatile memory for operating a pressurized structure. In an eight-body embodiment, a method for operating a non-volatile memory includes configuring a -NAND string to receive a boost voltage, wherein the dirty string comprises a plurality of storage elements and is at least partially formed on a substrate i, and An additional structure extends along the _ string. The method further includes applying a voltage to the NAND string to integrate the booster house to the boost structure via a location in which the (4) structure communicates with the substrate (e.g., the source/pole regions of the substrate). For example, the inner and outer selection gates of the first end of the storage element can be arranged between the first and outer terminals of the NAND string and the selected gate of the NAND string. After applying the boost voltage, V can be applied by applying a boosted voltage to the word line associated with the NAND string. Subsequently, the boost t can be ><RTIID=0.0>>><>> The level at which the boost structure is discharged can be controlled by controlling, for example, the voltage applied to the drain side of the NAND string via the bit line. After discharge, the stylization can occur by, for example, applying a stylized voltage to the storage elements within the nand string via the selected word line. Favorable, supplemented by a lower stylized voltage. In the verification procedure, it can occur between the stylized pulses, and the boost structure can be independently boosted and discharged to a level based on the verify bit for each NAND string. A voltage is then applied to the storage elements within each NAND string to characterize a stylized state of the storage elements. With this method, multiple storage elements along the edge line of different NAND# can be simultaneously characterized according to different verification levels while using a common word line voltage. The read program can contain several read cycles, one for each read level. The boosting structures are collectively boosted and discharged in each read cycle to a common level based on different read levels in each read cycle. In another embodiment, a method for operating a non-volatile memory includes applying a common boost voltage 'which is coupled to a first-dusting structure extending along a first ναν〇 string and along a second NAND string Extending the second pressurized structure. The method m includes discharging the first pressurized structure to a first level = discharging the second pressurized structure to a different second level. In another embodiment, a method for operating a non-volatile memory includes performing a number of consecutive read cycles for a read stylized state of a hash element of an individual NAND string. Each of the read cycles includes applying a common boost voltage that is lightly coupled to an individual boost structure extending along the individual N-nano strings, discharging individual 126503.doc 1355660 press structures to different read levels based on the respective read cycles. An ugly 7-bit quasi' and application of at least one of the library elements in each NAND string (4) for characterizing the stylized state of at least one of the storage elements in each of the strings relative to the read level . [Embodiment] An example of a non-volatile memory system suitable for use with the present invention uses a NAND flash memory structure in which a plurality of transistors are arranged in series between select gates in a -N_string. Figure i shows a top view of the (iv) NAND string. In practice, a plurality of such NAND strings can be placed in a two-dimensional array across a semiconductor device, optionally as shown in FIGS. 1 and 2, each of which includes four centrally-selected closed-poles. A series of transistors. In a particular embodiment, each NAND string includes two source side select gates and one drain side select gate. For example, the NAND string & includes transistors 100, 1〇2, 1〇4, and 106 sandwiched between the drain side selection gates (not shown) and the source side selection gates 〇 and 11〇. The select gates 108 and 110 can be connected to the control lines SGS2 and SGS1 of the associated nand string, respectively. The NAND string #2 includes transistors 134, 136, and 140 sandwiched between the source side selection gates 13A and 132 and the drain side selection gates 142. Select gates 130 and 132 can be connected (or provided as part of) control lines SGSi and SGS2 of associated NAND strings, respectively. It should be noted that the description of one of the end regions of NAND string #1 has been removed on the drain side. Depending on their position relative to the individual NAND strings, select gates 1 〇 8 and 132 can be considered as internal select gates and select gates 110 and 13 0 can be considered external select gates. In NAND string #1, for example, 'the drain side select gate (not shown) connects the 126503.doc •10-1355660 NAND string to the bit line contact on the -end (no w is shown, and gate 110 is selected) Connect the NAND string to the source line contact 12〇 on the other end. Similarly, in NAND string #2, select gate 142 connects that to the bit line contact 15〇 on one end, and selects the gate The NAND string is connected to the source line contact 丨2 另一 on the other end. The gate is controlled by applying an appropriate voltage through its control line. In this method, the NAND string is along the bit line direction. Alternately arranged from the source side to the source side and the drain side to the drain side. However, other methods can be used. Also 'in NAND string #1' transistor 1〇〇, ι〇2, 1〇4 And 1 and 6 each have a control gate and a floating gate. Specifically, referring to Fig. 2, the transistor 100 has a control gate 100CG and a floating gate 1〇〇FG. The transistor 102 includes a control gate i〇 2CG and floating gate i〇2FG. The transistor 104 includes a control gate 104CG and a floating gate 1〇4FG. The transistor 1〇6 includes a control gate 106C. G and floating gate I 〇 6FG. Control gates 1 〇〇 CG, 102 CG, 104 CG, and 106 CG may be provided as word lines WL3, WL2, WL1, and WL0, respectively. In a possible design, transistors 100, 102 , 104 and 106 are memory cells or non-volatile storage elements. In other designs, the 'memory element may comprise a plurality of transistors or may be different from those described in Figures 1 and 2. Again, in NAND string #2 The transistors 134, 136, 138 and 140 each have a control gate and a floating gate. The transistor 134 has a control gate 134CG and a floating gate n4FG. The transistor 136 includes a control gate 136CG and a floating gate 136FG. The transistor 138 includes a control gate 138CG and a floating gate 138FG ^ transistor 14 〇 including a control gate 140CG and a floating gate 14 〇 FG. The control gates 134cg, 126503.doc. 1355660 136CG, 138CG and 140CG can be respectively Provided as part of the associated word lines w1,, and WL2 and WL3. The word lines are different from the word lines associated with NAND string #1. In a possible implementation, F represents each memory element. Word line, control gate and floating gate width, and The spacing between the body elements. The source and drain select gates 15 may also have a width F ′ column>, and the spacing between the source side selection poles may be a multiple. The use of the double source side selection gate is through Selecting the gate prevents current on the source side of the NAND; it is useful to minimize leakage and control the boost structure. In particular, 'in one method' can provide a boost structure such as a conductive plate or wire for each of the financial constellations. In one method, the job string #1 includes a boost structure 115' that extends along the NAND string and its storage elements and connects the source/drain regions between the source side and the gates 108 and 110 via the substrate. The contact of 18 contacts the NAND string. The boost structure 115 is thus in communication with the substrate. As described in more detail below, the boost structure can be assisted in stylization, verification, and/or read operations to optimize such programs for individual NAND strings. Similarly, in the method, 'NAND string #2 includes a boost structure 145 that extends along the Ναν〇 string and its storage elements and selects the source/drain regions between the source side select gates 13 and 132. The contacts of the substrate 148 contact the NAND strings. Other booster configurations can also be provided, such as boost structures that are shared along the word line direction and in the bit line direction by - or adjacent NAND strings. For example, the boost structure can be extended on adjacent NAND strings, which use parity programming at different time intervals. This boost structure contacts the source/drain regions in adjacent nand strings. In another method, a plurality of rolling structures are associated with a NAND string. 126503.doc 12 1355660 In addition, other sources must be connected to the source/(four) area of the county board, but can be controlled by other means. In addition, other add-on structures can contact the substrate at a position other than between the two or more source side selection gates. The add-on structure can be used in a similar manner with a NAND string having a single source side or a drain side select gate. In another variation, the boost structure can contact the NAND string on the drain side, 'J as close to or adjacent to the drain side select gate or two or more drain side select gates' The two source side selection gates of Figures 1 and 2 are provided. The pressurized structure can have a variety of cross-sectional shapes. The pressurized structure may conform to the shape of the ND string or may extend in a straight line. The pressurized structure can have various cross-sectional shapes along its length, including rectangular shapes such as thin strips, circles, such as wires, and the like. In addition, the section can vary along the length. For example, a section can be thicker than other locations in some locations. Alternatively, the boost structure may extend along a portion of the nand string, such as only along one portion of the storage element, or along all of the storage elements of the NAND string. Other changes are also available. 3 is a top plan view of an alternate embodiment of two adjacent NAND strings. 4 is an equivalent circuit diagram of the NAND string of FIG. As described above, the spacing between the source-side selection gates in a method can be an integer multiple of F or ρ. In the present example, the distance between the source side selection gates 1 〇 8 and 1 ’ in the NAND string # 1 and the source side selection gates π 〇 and 丨 32 in the NAND string # 2 is 3F. This method mitigates the tolerances used to position the junction of the boost structure with the substrate 118 or 148 relative to the particular embodiment of Figures 1 and 2 using the spacing F. In particular, larger, non-self-aligned contacts can be used to couple the boost structure to the active area of the substrate, such as the source/drain regions. 126503.doc 13 1355660 Figure 5 is a circuit diagram depicting two NAND strings. The circuit diagram corresponds to the specific embodiment of Figures 1 to 4. A typical architecture for a flash memory system using a NAND structure includes several NAND strings. For example, three NAND strings 520, 540, and 560 are displayed in a memory array having more nand strings. In this example, each NAND string includes two source side select gates, four memory elements, and one drain side select gate. Although four storage elements are illustrated for simplicity, for example, modern NAND strings can have up to thirty-two or sixty-four storage elements.

For example, NAND string 520 includes a drain side select gate 522, storage elements 523 through 526, source side select gates 527 and 528, and a boost structure 530 having a junction with substrate 531. The NAND string 540 includes a drain side selection gate 542, storage elements 543 to 546, a source side selection gate "and", and a boost structure 55 〇e NAND_56 including a junction with the substrate 551, including a drain The side select gate 562, the storage elements 563 to 566, the source side select idle electrodes 567 and 568, and the boost structure 57A having a contact with the substrate 571. Each NAND string is connected to the source line by selecting the interpole. Select line or control line SGSMSGS2 is used to control the source side selection gate. The various NAND strings 52o, "o and connected to individual bit lines 521, 541, and 561 are selected by selecting a selection transistor within gates 522, 542, 562, etc. controlled by the immersion selection line or control line SGD. The transistors are selected. In other embodiments, the 'select lines do not have to be common in the NAND string, i.e., different select lines can be provided for different D strings. Word line WL3 and control gates for storage elements 523, (4), and (6) The word line machine 2 is connected to the control gates for the storage element, state and over. The word line WL1 is connected to the control gate for the storage element still, 126503.doc -14 - 1355660 545 and 565. 546 and 566 control, output, for storage components _ string contains storage element array or set: see = vertical line and WL2, WL1 and WL 〇) including the array: ": line (WL3, n ^ ^ Each of the pre-wires is connected to the control gate of each of the storage elements. ^^/flyer, which can be controlled by the word line itself. For example, the word line WL2 is the storage element 524, 544 and is controlled. Gate. In practice, it can be thousands of storage elements on a word line. In a specific embodiment, The program is stylized to store the contents along the common word line. Thus, 'one of the word lines is selected for stylization before applying the stylized pulses. This word line is called the selected word line... the remainder of the block A line system is referred to as an unselected word line. The selected word line may have one or two adjacent sub-lines. If the selected word line has two adjacent word lines, the adjacent word lines on the non-polar side are referred to as The adjacent word lines on the source side for the drain side adjacent word lines are referred to as the source side adjacent word lines. For example, if WL2 is the selected word line, WL1 is the source side adjacent word line and WL3 Each of the storage element blocks includes a set of bit lines forming a row and a set of word lines forming a column. In a specific embodiment, the bit lines are divided into odd bits. Lines and even bit lines. Also as described in connection with Figure i9, storage elements along a common word line and connected to odd bit lines are stylized at a time, along a common word line and connected to The storage element of the even bit line is stylized at another time ("odd/even stylized"). In another implementation In the example, the storage element is 'programmed along a word line for all bit lines in the block ('all bits are threaded"). In other embodiments, the bit line or region can be used. The block is decomposed into other groups (for example, left and right, more than two points 126503.doc 15 1355660 group, etc.). The other two storage elements can store data. For example, when the storage-bit number is rain two, the component will be stored. It is possible that the range of the critical electric energy M (Vth) is divided into the logical data "丨" and "〇" for the range. In the nand type flash memory-example, after erasing the storage element~ W is defined as a logical "i". program after the operation of the % is a positive number:, 疋 meaning for the logic. When % is negative and attempts to read, the store will be turned on to indicate that the logic is being stored. When the 'Η is positive and ", try to read the material 'storage component material will open the finger replenishment logic. The storage component can also store multiple levels of information, for example, multi-bit digital data. In this case, the range of % values is divided into the number of levels of the data. For example, if you store four levels of information, you will be assigned the data values "", , , , , ". "And the four ~ range of the back ^ in one of the N-type memory examples - after a erase operation ~ is a negative number and is defined as "11". The positive VTH value is used for, 1G", "Gl&quot ; and "(10)" status. The specific relationship between the f-materials programmed in the storage element and the critical voltage range of the component depends on the data encoding scheme employed by the storage elements. Various information encoding schemes for multi-state flash storage elements are described in the entirety of the disclosure by reference to U.S. Pat. No. 6,222,762, and U.S. Patent Application Serial No. 2004/0255090. The NAND type 'recognition phase' example and its operating system are provided in the following patents: US Patent Nos. 5,386,422, 5,522, 58〇' 5,57〇,315, 5'774'397 '6'046,935, 6, 4, B. and 6, 2, 580, which are incorporated herein by reference. 126503.doc -16- 1355660 When the component is flashed, the bit associated with the storage element is applied to the control element of the storage element, and the electrons from the channel are injected into the floating interpole. When electrons accumulate at the floating gate t', the floating closed-pole becomes negatively charged and the (iv) memory element's vTH rises. To apply this program to the control gate of the program being programmed, the program M will be applied to the appropriate word line. : Above, the storage elements in each NAND string share the same word line. For example, when the storage component 524 of Figure 5 is programmed, the control gates of components 544 and 564 will also be stored. > ...used as 'when stylizing and reading a given storage element and other storage elements with a certain degree of complication with a given storage element (eg, storage elements sharing the same word line or bit line)' The electrical storage stored in the storage element can occur that the offset of the stored charge level is due to the % coupling of the storage. Due to the improvement of the integrated circuit manufacturing technology, the problem is deteriorated with the reduction of the two divisions between the storage elements, and the two problems of the work are most apparently occurring two adjacent programs that have been programmed at different times. Between the storage component groups, the storage-memory component group is programmed into a new charge level, which corresponds to ", the bait material is programmed with the second group of f-materials, and the second storage component group is: - storage The charge level read by the component group often appears to be different from the electrical level due to the charge of the stored 70-group group and the capacitance of the first storage element group. Therefore, the matching effect depends on the program. The order in which the memory is stored is therefore 'depending on the order in which the word lines are crossed during the stylization. The D string is usually (but not always) programmed from the source side to the non-polar side, starting at the source side word line and Advance to the bungee side word 126503.doc • 17- ^55660 line 0 each time, for example, the capacitive coupling effect on a given storage device can be stored in the same word line and in the same just D string. Caused by the component. For example, element r? part of the first storage component group D ^ along a word shellfish health alternative material storage element may be a surface of the other storage element to store 524 and 564--. After the second data storage element group page of memory elements 544 ^ programmable memory element of group ", there will be

The capacitance of the element 544 is lightly combined. The coupling with the directly adjacent storage elements 524 and 564) on the word line is strongest. ^ Similarly, if the storage element 544 is programmed, the storage element 544' can be placed on the same NAND string 54 by the stylization of the storage element. For storage element 544, the coupling to the directly adjacent storage # component (which is storage element 543 and/or 545) on the NAND string is strongest. For example, if the storage elements in the string 540 are programmed in the following order: 546, 545, 544, 5 43 ' storage elements 544 can be affected by the storage element 543. general

In contrast, storage elements that are diagonally disposed relative to storage element 544, ie, storage elements 523, 563, 525, and 565, can provide approximately 20% of the coupling of storage element 544' on the same word line or NAND string. Direct adjacent storage elements 524 and 564 and 543 and 545 provide approximately 80% shank. In some cases, the coupling may be sufficient to offset the VTH of the storage element by approximately v 5 v ' which is sufficient to cause read errors and widen the vth distribution of the storage element group. Figures 6 through 10 depict the manufacture of a non-volatile reservoir having a pressurized structure. Figure 6 depicts a non-volatile reservoir. A cross-sectional view along several NAND strings is displayed. The corresponding structure can be further repeated right and left along the direction of the bit line extending outside the page and the direction of the word line toward 126503.doc -18·1355660. The description is simplified and does not have to provide all the details, and the description is not to scale. In the configuration provided, the NAND strings are alternately arranged from the source side to the source side and the drain side to the drain side. However, other configurations are also possible. The NAND string can be formed at least partially on the substrate 6A. In one method, a NAND string can be formed on the p-well region, which is higher than the n-well region of the p-type substrate. For example, a portion of NAND string 605 includes source side select gates 62A and 622 that are respectively connected to (or provided as part of) control lines SGS2 and SGS1 for associated NAND strings. The complete NAND string 610 includes source side select closes 626 and 628' which are respectively connected (or provided as part) control lines SGS2 and SGS1 for the associated NAND strings. Storage elements 630, 632, 634, and 636 and a drain side select gate 638 are also provided. The partial nand string 615 includes a drain side select gate 642 that is connected to (or provided as part of) the control line SGD for the associated NAND string. In one method, each nand string 605, 610, and 61 5 can be located in a different block of the memory array that is programmed or read at different times. Additionally, a source/drain diffusion region is provided between the storage element and the select gate ′ including source/drain diffusion regions 65〇, 652, 654, 656, 658, 660, 662, 664, and 666. The source line 624 is for controlling the supply of the source side selection gates 622 and 626, and the bit line 640 is for controlling the voltage of the drain side selection gates 63 8 and 642. Figure 7 depicts details of a portion of Figure 6. Each of the storage elements may include a control gate 636, a floating gate 639, a polysilicon interlayer dielectric layer 637 between the control gate and the floating gate, and an insulating layer between the floating gate 639 and the substrate 6 126503.doc 19 1355660 64 depicts a non-volatile reservoir of FIG. 6 after depositing an insulating layer. The insulating layer 800 can be deposited using a variety of techniques. In one method, the layer extends across the NAND strings, although in practice the insulating layer may be sufficient to extend across the storage element. In general, insulating layer 800 can conform to the shape of existing structures including storage elements and select gates. In one method, the insulating layer 8 may include a three-layer dielectric formed of yttrium oxide, lanthanum nitride, and yttrium oxide ("0N0").

Figure 9a depicts the non-volatile reservoir of Figure 8 after depositing a photoresist layer 9〇5. Figure 9b depicts the non-volatile reservoir of Figure 9a after selectively exposing and removing the photoresist, portions of layer 9〇5 and etching portions of the insulating layer. In this method, a mask 900 for selectively exposing the photoresist is used, which has an opening between the source side selection gates of the NAND string. Once the photoresist layer 9〇5 is selectively exposed, the mask 900 is removed and the exposed portions of the photoresist are removed using well known techniques. Therefore, a portion of the insulating layer under the removed portion of the photoresist is exposed. Additionally, an etch is performed to remove the exposed portions of the insulating layer 800 to expose the corresponding portions 91 and 92 of the source/drain regions 650 and 654, respectively. As described above, in conjunction with Figure 3, the spacing between the source side select gates can be a multiple of F to alleviate the tolerances used to locate the junction of the boost structure and the substrate. The example provided uses the source side to select the gate pitch F. After the etching, the remaining portion of the photoresist layer 9〇5 is removed, and the conductive layer is deposited. Figure 10 depicts the non-volatile memory of Figure 9b after deposition of a conductive layer providing a pressurized structure. A mask 1 can be used to deposit a conductive material, such as a polysilicon or a metal, such as tungsten, tantalum nitride or titanium nitride, on the NAND string. Conductive materials can be deposited using atomic layer deposition (ALD), chemical vapor deposition (CvD), physical vapor deposition, 126503.doc • 20-1355660 (pvd), germanium, and the like. The electrically conductive material provides a pressurized structure (portion) 1010 that contacts the substrate at the source/drain region portion 91, a boost structure 1020 that contacts the substrate in the source/drain region portion 92, and a pressurized structure (partial ) 1030. In general, the pressurized structure conforms to the shape of the insulating layer 8〇〇. The insulating layer 800 is used to insulate the control gate and the floating gate of the storage element from the pressurized structure. In addition, one or more additional layers may be provided on top of the pressurized structure, such as a second insulating layer, one of the pressurized structures. The advantage is that it provides shielding between the storage elements to reduce coupling effects because the boost structure can surround the control gate and the floating gate, which extends adjacent the substrate between the floating gates of adjacent storage elements (Fig. 10). This design also improves the coupling from the boost structure to the floating gate of the storage element. Figure 11 is a top plan view of another embodiment of two adjacent NAND strings having a boost structure. Figure 12 is an equivalent circuit diagram of Figure u. In this embodiment, the NAND string includes a single source side select gate, such as select gate 丨〇8 in NAND string #1 and select gate 132 in NAND string #2. In one possible approach, the boost structure 1115 in #1 has a junction with the substrate 1118 between the select gate 108 and the adjacent storage element 106. Similarly, in one possible approach, the boost structure 1145 in NAND string #2 has a junction with the substrate 1148 between the selected interpole 132 and the adjacent storage element 134. Figure 13 is a circuit diagram depicting three NAND strings with a single source side select gate and boost structure. The circuit diagram corresponds to the embodiment of Figures 11 and 12 and differs from the circuit diagram of Figure 5 in that the NAND string includes a source 126503.doc • 21 · 1355660 side select gate instead of two. Here, the NAND string 1320 includes a drain side selection gate 1322, storage elements 1323 to 1326, a source side selection gate 1327, and a boost structure 133 having a junction with the substrate 1331 (^ NAND string 1340 includes a drain Side selection gate 1342, storage elements 1343 to 1346,

The source side selects a gate 1347 and a boost structure 1350 having a contact with the substrate 1351. The NAND string 1360 includes a drain side select gate 1362, storage elements 1363 to 1366, a source side select gate 1367, and a boost structure 1370 having a junction with the substrate 1371. Each NAND string is connected to the source line by selecting a gate. The select line or control line SGS is used to control the source side select gate. The various NAND strings 132A, 1340, and 1360 are connected to individual bit lines 1321, 1341 and by selecting a transistor within the side gates 1322, 1342, 1362, etc.! 361. The select transistors are controlled by a drain select line or control line S(}D. The NAND string can be controlled in a manner similar to the embodiment in which one end of the NAND string includes a dual select gate. For example, in one method The charging of the booster structure can occur via a bit line.

Figure 14 depicts a procedure for fabricating a non-volatile reservoir having a pressurized structure. It should be noted that in this and other processes provided herein, the steps performed need not be performed in the order shown or as discrete steps. In addition, Cheng: provides a high-level overview. Step 1400 includes forming a storage element and selecting a gate on the substrate (Fig. 6). In the specific embodiment +, a _ string is formed. Step 1410 includes forming a source-drain region between the storage element and the select gate. Step 1420 includes forming a control line. For example, the steps may include protecting the control line of the source and the drain side and the control line of the source and the line. Step 丨430 includes forming an insulating layer on at least 126503.doc • 22·1355660 points of the storage element and the selected idle electrode (Fig. 8). Step 1440 includes forming a photoresist layer (Fig. 9a). Step 1450 includes, for example, selectively exposing the photoresist layer via mask 9 and removing the exposed portions of the photoresist to expose portions of the insulating layer (Fig. 9b). Step 1460 includes etching the exposed portion of the insulating layer to expose portions of the source/drain regions (Fig. 9b). Step 1470 includes removing the remaining photoresist. Step 1480 includes forming a uniform conductive layer that partially contacts the exposed portion of the source-drain region (Fig. 10). Additional insulating layers may also be provided on the conductive layer.

Figure 15 illustrates an example of an array 15 of NAND storage elements, such as shown in Figures 1 through 4, 11 and 12. Along the rows, bit line 15 〇 6 is coupled to 汲 terminal 1526 for the drain select gate of nand string 1550. Along the columns of the nand string, the source line 1504 can be connected to all source terminals of the source side of the NAND string to select the idle poles. The eNAND architecture limbs operate as part of the memory system - an example can be found in U.S. Patent No. 5 , 57〇, 3 i 5 ; and 6,046,935.

The array of storage elements is divided into a larger number of storage S-blocks. As with the flash EEPROM system, the block is the erase unit. That is, each block contains a minimum number of storage elements that are erased together. Each block is generally divided into several pages. One page is a program servant fire> Λ化早兀. In a specific embodiment, one: two Cl: eve fragments and the fragments may be included in the - basic stylized, the smallest number of storage elements written by the _ person - "Chi Nong 乂 面 一般 一般 储存In the column storage element. ::Information page = paragraph. , including user data and management: ==: The user data included in the section has been (ECC). One of the controllers Error Correction Code The knife (as described below) is programmed to program the data in the array 126503.doc • 23 - 1355660 ^ and also check it when reading data from the array. Or • 'These ECC and/or other management materials are different from the data on which they belong, stored on the page or even in different blocks. The section of the I(4) data is usually (four) 2 bytes, corresponding to the size of a section of the disk 4. Management information is generally - an additional 16 to 20 digits: '' and. - A larger number of pages form a block, for example from 8 pages up to implementation: two 128 or more pages, wherever they are... In some embodiments, a column of NAND strings contains a block. In a specific embodiment, the 'memory storage element is grounded by a voltage (for example, 2 〇 ^ _ - 旰 旰 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并 并Wipe it off. By well, the unselected word line 'bit line, select line, and C source are also 2 obvious parts of the erase voltage. Therefore, a strong electric field should be applied to the oxide layer. With the general (10) (four) mechanism, the electrons of the floating gates are emitted to the substrate side to erase the data of the δHai## 疋 疋 storage element ^ Now the electrons are transferred from the floating closed-pole = the area' - Select the criticality of the storage component (4). The erase can be performed on the ❹-column/row solution Hr component in Figure (4). "The 非 碣 and the read/write circuit of the non-volatile 2 memory system _ A read/write circuit for a page for reading and programming a material element in accordance with the present invention. The memory device (10) may include one or more 2^ body crystals 1698. Memory die 1698 includes a two-dimensional array of faulty components (10), control circuit deletion, and read/write circuit secrets. In some with 126503.doc •24 In the embodiment of the invention, in the embodiment of the invention, the storage element can be three-dimensional. The memory array ι500 can be passed through the column decoder 163, and the sub-line and the straw are passed through the row decoder 1660. Bit line addressing. The read/write circuit secret includes multiple sensing blocks and allows pages to be read or programmed in parallel. * The controller 1650 is included in the same memory device μ% (eg Remove the memory card) within the #-- or multiple memory die. It is transferred between the host and the controller (10) and via the line (6) controller and one or more memory modules. Command and Data Control circuit 1610 cooperates with read/write circuit 1665 to perform a memory operation on the memory array. Control circuit 1 (4) includes state machine m2, on-chip address decompressor 1614, and power control mode (four) heart. (1) Provides wafer level control for memory operation. On-wafer address decoding 1^614 provides the address interface between the address used by the host or memory controller and the hardware address used by the solution 1630 and 166G. Power control module 1616 is controlled in memory The power and voltage supplied to the word lines and bit lines during the memory operation. In some embodiments, certain components may be combined. In various designs, in addition to the storage element array, - or multiple components (alone or The combination can be regarded as a management circuit. For example, 'one or more management circuits can include control circuit state machine 1612, decoders 1614, 163 〇 and 166 〇, power control: 616, sense block 16 〇 °, read / Write circuit secret, controller secret # either or a combination. Figure m is a block diagram of a non-volatile memory system using a dual column/row deblocker and a read/write circuit. The memory device shown in I26503.doc -25· is additionally configured. Here, the various peripheral circuit access memory arrays 1500 are implemented in a symmetrical manner on opposite sides of the array such that the density of access lines and circuits on each side can be halved. Therefore, the column decoder is cut into column decoders 163a and 1630B and the row decoder is divided into row decoders 1660A and 1660B. Similarly, the read/write circuit is divided into a read/write circuit 1665A connected from the bottom to the bit line and a top of the array 15A.读取 A read/write circuit 1665β connected to the bit line. In this way, the density of the read/write modules is substantially halved. The apparatus of Figure 17 may also include a controller as described above with respect to the apparatus of Figure 16. Figure 18 is a block diagram of an individual sensing block 丨6〇〇 divided into a core portion (referred to as sensing module 168A) and a common portion 1690. In one embodiment, there is a separate sensing module 168 for each bit line and a common portion 1690 for a set of multiple sensing modules 168. In an example, the sensing block will A common portion 1690 and eight sensing modules 168A are included. Each sensing module within the group will communicate with the associated common portion via data bus 1672. For details, please refer to US Patent Application Publication No. 2006/0140007, published on Jun. 29, 2006, entitled "N〇n_v〇latile Mem〇ry &

Method with Shared Processing f〇r an Aggregate of Sense Amplifiers", which is incorporated herein by reference in its entirety. Sensing module 1680 includes sensing circuitry 1670 that determines whether a conduction current in a connected bit line is above or below a predetermined threshold level. Sensing module 1680 also includes a bit line latch 1682 that is used to set a voltage condition on the connected bit line. For example, a pre-clamp state latched in bit line latch 1682 will cause the connected bit line to be pulled to a specified state (eg, VDD). ^ Part i 690 contains a processor 1692 and a set of data latches VIII. 1/〇 = face 1696 between the HI group data latch 1694 and the data bus 1620. The processor 1692 performs the calculation. For example, one of its functions is to store the material in the sensing storage element and to rely on the determined data in the set of latches. The set of data latches is used to store the data bits determined by processor 1692 during a read operation. It is also used to store data bits from the data exchange port during the operation of the program. 2. The data bits that are imported represent the write poor materials that are attempted to be programmed into the memory. The I/O interface 1696 provides an interface between the data latch 1694 and the data bus 丨 62 。. During operation or sensing, the operation of the system is controlled by state machine i6i2, which controls the supply of different control gate voltages to the addressed storage elements. The sensing mode W(10) can trip at one of the electric dusts and pass through the busbar 1672 from the sensing module 1680 when passing various predefined control gate voltages corresponding to various memory states supported by the memory. Providing an output to the processor at this point, the processor 1692 determines the final event (4) H by the tripping event of the sensing module and the information about the control gate voltage applied from the state machine by the input line i 693. (4) The memory state is encoded in the code, and the final data bit is stored in the data latch 16% inner core. In another embodiment, the bit line latch 丨 682 has dual task energy, As a latch for latching the output of the sensing module "(9), also as the bit line latch described above. It is expected that certain implementations will include multiple processors 丨 692. In a specific implementation 126503.doc • 27· 1355660

In the embodiment, each processor 1692 will include an output line (not depicted in Figure 5) to connect or connect the various lines of the output line. In some embodiments, the output lines are reversed prior to being connected to a line or line. This configuration enables the fast completion of the program during the program verification process, because the receive line or state machine can determine when all stylized bits have reached the desired level. For example, when a leader has reached its desired level, a logical zero for one of the bits is sent to the line or line (or vice versa). When all bits output a data zero (or a reverse data one), the second machine knows to terminate the stylized program. Since each processor communicates with eight sensing modules, the state machine needs to read the line or line eight times, or add logic to the processor! 6 9 2 to accumulate the result of the associated bit line' causes the state machine (4) to read the line or line once. Similarly, by properly selecting the logical levels, the overall state machine can measure when the bit changes its state and changes the algorithm accordingly. During the stylization or verification period, the data to be stylized is stored in the set of f-block latches from the data bus 1620. Under the control of the state machine, the program operation consists of a series of programmed electric pulsations applied to the control gates of the god components. A readback _ can be performed after each stylized pulse to determine whether the storage element has been programmed into the desired memory state. Processor 1692 monitors the read back memory state associated with the desired memory state. When the two states are identical, the processor (10) sets the bit line latch (10) such that the bit line is pulled to the state specified by the _specified program. This prohibits the storage elements that are attached to the bit line from being further programmed, even if stylized pulses appear on their gates. In other specific examples of 126503.doc -28·1355660, the processor initially loads the bit ^^^^^ (d) during the verification procedure, which is considered to be _==2 and the sense negative latch The stack i694 contains a stack of devices. In one case, it should be in the sense module - data latch data latch. In this paste#〇隹一号心^不)), the data is latched = applied as a shift register to convert the parallel data stored therein into data bus 162 string, And vice versa. In the preferred

In the embodiment, all the resources corresponding to the read/write blocks of the m storage elements: the latches can be linked together to form a block shift register, so that the string transfer can be used. Enter or output a data block. Specifically, the r read/write module libraries are adapted such that each data latch of the data latch group n shifts the data sequentially or out of the data bus as if it were used for the entire The portion of the shift register that captures/writes the block. Additional information regarding the structure and/or operation of various embodiments of the non-volatile storage device can be found in the following documents: (丨) US Patent Application Publication No. 2004/0057287, issued March 25, 2014. No. "Non-Volatile Memory And Method With Reduced Source Line Bias Errors"; (2) U.S. Patent Application Publication No. 2004/0109357, published on January 10, 2004, entitled "Non-Volatile" Memory And Method with Improved Sensing"; (3) US Patent Application No. 11/0 15,199, filed December 16, 2004, entitled "Improved

(4) U.S. Patent Application No. 11/099,133, filed April 5, 2005, entitled "Compensating for Coupling During 126503.doc -29· 1355660

Read Operations of Non-Volatile Memory; (5) December 2005, 28 pp. U.S. Patent Application Serial No. 11/321,953, entitled

Reference Sense Amplifier For Non-Volatile Memory". The five patent documents listed above are incorporated herein by reference in their entirety. Figure 19 illustrates an example of organizing a memory array into blocks for all bit line memory architectures or for parity memory architectures. An exemplary structure of the storage element array 1500 is illustrated. As an example, the Nand flash EEPROM described herein will be split into 1, 24 blocks. The data stored in each block can be erased at the same time. In one embodiment, the block is the smallest storage element unit that is simultaneously erased. In this example, there are 8, 5 12 rows in each block, corresponding to bit lines BL0, BL1, ... BL8511. In one embodiment, referred to as an All Bit Line (ABL) architecture (Architecture 191A), all of the bit lines of the block can be selected simultaneously during read and program operations. The storage elements along a common word line and connected to any of the bit lines can be simultaneously programmed. In the example provided, four storage elements are connected in series to form a NAND string. Although each NAND string is shown to include four storage elements', more or less than four storage elements (e.g., 16, 32, material, or another number) may be used. One terminal of the NAND string is connected to the corresponding bit line via the drain selection gate, and the other terminal is connected to the 〇 source via the source side selection gate. In another embodiment, referred to as a parity architecture (architecture 1900), the bit lines are divided into even bit lines (BLe) and odd bit lines (Bl). In a parity-bit line architecture, the storage elements along the common word line and connected to the odd-numbered lines are stylized at time, along the common word line 126503.doc -30- 1355660 and The storage elements connected to the even bit lines are stylized at another time. Z programs the data into different blocks and reads them from different blocks at the same time. In this fe example, there is _ ^ at 8,512 仃 in each block, which is divided into even and odd lines. In this example, the four storage elements that are not in the figure are connected in series to form a NAND string. The singer shows that there are four storage elements in each NAND string, but the county recognizes that it uses more or less than four storage elements. At the time of reading and stylization, at the same time, during the state, 4,256 storage elements are selected at the same time. The stored items selected by the selected ones will have the same word line and the same type of bit line (for example, even or odd). Therefore, two data bytes forming a logical page can be simultaneously read or privately formed, and one block in the memory can be Us, - sub-to y eight logical pages (four word lines, The mother bar word lines each have an odd number of pages, one from the top, and the even one). For a multi-state storage 7G piece, when each storage element t stores one piece of data, if each of the two bits is stored in a different page, one block stores sixteen logics. page. Other sizes of blocks and pages can also be used. For ABL or parity architectures, the memory elements can be erased by raising the p-well to an erase voltage (e.g., 20 V) and grounding the word lines of a selected block. The source and bit lines are floating. Erasing can also be performed on the entire memory array, the separation block, or another storage element unit of one of the memory devices. The electrons are transferred from the floating idle of the storage elements to the P-well area to make the sum of the storage elements negative. In the read and verify operations, the port selects the idle poles (SGD and SGS) to be connected to the voltage m in the range of 2.5 to 4.5 V and the 4 unselected word lines (eg 126503.doc 1355660 eg, when WL2 When the selected word line is selected, WLO, \^1 and £3) are raised to a read transfer voltage Vpass (usually a voltage in the range t of 4.5 to 6 V) to enable such The transistor operates as a transfer gate. The selected word line WL2 is coupled to a voltage whose level is specified for each read and verify operation to determine if one of the associated storage elements Vth is above or below this level. For example, in a read operation for a two-bit quasi-storage element, the selected word line WL2 can be grounded to detect if Vth is greater than 〇 v. In the verify operation for the two-bit quasi-storage element, there is no boost structure, and the selected word line WL2 is connected to 〇·8 V, for example, to verify whether Vth reaches at least U V . The source and p wells are at 〇Ve and will select the bit line, assuming that the even bit line (BLe) ' is precharged to one of the levels, for example, 〇7 乂. If γη is higher than the read or verify level on the word line, the potential level of the bit line (BLe) associated with the non-conductive storage element associated with the storage element of interest remains high. On the other hand, if the Vth is lower than the reading or verifying level =, the potential level of the associated bit line (BLe) will be lowered because the conductive storage element will discharge the bit line. To the low level, for example, two 〇·5 V. Thus, the state of the storage element can be detected by an electrical comparator comparator sense amplifier connected to the bit line. The above erase, read and verify operations are performed in accordance with techniques well known in the art. Thus, the skilled person can change many of the details described. It is also well known in the art that (4) his erase, read and verify techniques. Figure 2 illustrates an exemplary threshold voltage distribution for storing an array of elements when each of the storage elements stores the two-bit data. For the storage of the erase (4) - the critical voltage distribution Ε. Also described are three 126503.doc •32· than 5660 t boundary voltage distributions A, B, and C for the programmed storage elements. In a particular embodiment, the voltage in the E distribution is negative and the critical electrical power in the A, B & c distribution is a positive number. The same threshold voltage range corresponds to the predetermined set of data bits. The characteristic relationship between the data in the storage element and the critical voltage level of the storage element depends on the data used by the storage elements. For example, U.S. Patent No. 6,222,762, issued on Dec. 16, 2004, and U.S. Patent Publications, the disclosure of which is incorporated herein by reference. It is incorporated herein by reference in its entirety. In a specific embodiment, the Gray code assignment is used to assign a data value to the critical ink range such that if the threshold voltage of the floating gate is erroneously shifted to its neighboring entity state, it will only affect One yuan. An example assigns "U" to the critical voltage range E (state Ε), "1〇" to the critical voltage range A (state A), "00" to the critical voltage range _ (state B) and "〇1" To the critical voltage range C (state c). However, in other embodiments, the Gray code is not used. Although four states are shown, the present invention can also be used with other multi-state structures to include structures that include more or less than four states. Three read reference voltages Vra, Vrb, and Vrc are also provided to retrieve data from the storage component. By testing the threshold voltage of a given storage element above or below Vra, Vrb, and Vrc, the system can determine the state of the storage element. In addition, three verification reference voltages Vva, Vvb and vvc are provided. When the storage elements are programmed to state A, the system will test whether the health storage elements have a threshold voltage greater than or equal to Vva. When the storage component program 126503.doc - 33 - 1355660 is converted to state B, the system will test whether the storage components have a threshold voltage greater than or equal to Vvb. When the storage elements are programmed to state c, the system will determine if the storage elements have a threshold voltage greater than or equal to ^. ♦ In the specific embodiment, referred to as full sequence stylization, the storage elements can be From the erase state E directly to any of the stylized states A, c, for example, 'a large number of storage elements to be programmed can be erased first, so that all the storage elements in the total number are in the erase state E. - series of stylized • buffers, such as the control gate voltage sequence of Figure 26, followed by direct programming of the storage elements to state A, B or Ce while staging certain storage elements from state E to state A 'Other storage elements are programmed from state e to state B and/or slave state to state c. When on the WLn from the state program T to the state C, under the WLn] and the adjacent floating gate parasitic combination number is maximized, because the number of charges on the floating pole under WLn changes virtual from the state E stylized The voltage to the state a or from the state is stylized to the state of the state. When staging from state E to state B, the number of facets with adjacent floating closed poles decreases 'but is still significant. When staging from state E to • I state A, the number of couplings decreases. Thus, the number of corrections required to subsequently read each state of WLnd will vary from the adjacent storage element on WLn. ~ Figure 21 illustrates an example of a two-pass technique for staging one of the multi-state storage elements for two different pages: one lower page and one higher page. Describe four states: state E (11), state A (1〇), state b (〇〇), and state C (01). For state E, both pages store a "1". 126503.doc •34- 1355660 In state A, the lower page stores a "〇, while the upper page stores a "". For state B, both pages store "〇". For state C, The lower page stores 1 and the lower page stores (4). It should be noted that a particular bit map has been assigned to each state of the states, but different bit pattern instances can also be assigned in the first pass stylization' depending on the bit to be programmed to the lower logical page. Yuan to set the critical electric house level of the storage component. If the bit is a logic 1 ', the voltage of the ^& boundary will not change, because the main glyph; because it has been erased earlier, it is in a "big state". However, if you want to program the bit system In a logical state, the critical level of the storage component is increased to state eight, as indicated by arrow 2 (10). It ends the first programming. In the second programming, it will be programmed to a higher logic page. The bit in the middle sets the threshold voltage level of the storage element. If the higher logic: the system wants to store a logic "", the stylization will not occur, because the number of parts stored in the lower page bit is based on the program. In one of (4), 'both carry - higher page bit 1'. If the higher page bit reads - logic "〇,, then the threshold voltage is offset. If the first pass causes the storage element to retain the erased state (four)' then the storage component is programmed in the second phase so that the threshold voltage is increased to state c, as indicated by arrow 212A. If the storage element has been programmed to state A' as a result of the first pass stylization, then the load element is further programmed in the second pass so that the threshold voltage ^ is added to state B as indicated by arrow 211A. The result of the second pass is to program the store to a state specified for the higher page material logic Y without changing the data for the lower page. The amount of depletion of the floating gates on the adjacent word lines in both Figure 2A and Figure 2 depends on the final state. 126503.doc • 35· 1355660 In a particular embodiment, if enough data is written to fill a full page, a system can be established to perform a full sequence of writes. If sufficient data is not written for a complete page, the stylized program can program the received data. Stylize the lower page. When the follow-up data is received, the system will continue with the program ' & higher 1 side ° in another embodiment - the system can start writing in the stylized - low page mode and if enough data is received later Filling a storage element of an entire (or most) word line converts to a full sequence stylized mode. US Patent Publication No. 2〇〇6/〇12_, issued on June 15, 2006, discloses a more detailed description of this particular embodiment, entitled "Pipelined Programming of N〇n_v〇latile Mem〇ries Hatred

Early Data", which is incorporated by reference in its entirety. 223 to 223 disclose another program for programming non-volatile memory for any particular storage element by writing the specific storage relative to a particular page by writing an adjacent storage element for a previous page. Components to reduce the floating gate to floating gate light-closing effect. In an exemplary embodiment, the non-# storage element uses four data states to store two data bits per per storage element. For example, 'the assumed state is the erase state and the state A' Β and the C system stylized state. State E storage _. State a stores data 〇1. State B stores data 1〇. Status (10) Save data. This is an example of non-Gray coding. The reason is that two bits change between adjacent states. Other codes for the status of the data to the entity data can also be used. Each storage unit 2 stores ... information. For the purpose of reference, these data pages will be referred to as two pages, and the lower page, however, may also be provided with other heart reference states A, higher page storage bits. , lower page storage bit 2 126503.doc • 36- 丄i. Referring to state B, the upper page stores the sub-bit 兀1, the lower page stores the bit reference state C, and both pages store the bit data 0. The stylized program is a two-step bed. In the first step, stylize the lower shell. The lower right page is protected by a thicker W. '枓, the state of the storage component remains in the shape of ~, E. The right data is stylized to 0, then _ _ then the critical value of the stored voltage is raised south to store the component program _ _ _ , to the state B,. Figure 22a thus shows the stylization of the storage element from state E to state B. State b, which is a discontinuity from B, is therefore described as ν*, which is lower than in a particular embodiment, after staging the storage element from state E to then 'with respect to its The lower page stylizes its adjacent storage elements (WLn+1) within the nand string. For example, referring to Figure 5', after stylizing the lower page for storage element 546, it will be programmed to store the lower page of the component. After staging the storage element 545, if the storage element (4) has a critical transition from state E to state ,ι, the floating closed-to-floating direct-to-floating effect will raise the apparent threshold voltage of the storage element 546. This point will have the effect that the threshold voltage distribution of the widened state B· is not critical to the critical voltage distribution of the critical electric dust distribution 2250 of the graph. This apparent widening of the critical voltage distribution will be fixed when staging higher pages. Figure 22c depicts a program that stylizes higher pages. If the storage element is in the erased state E and the upper page is to remain illusory, the storage element will remain in state E. If the storage element is in state E and its upper page data is programmed to γ ' then the critical dust of the storage element will rise 'so that the storage element is in state A. If the storage element is at an intermediate threshold voltage distribution 225 and the higher page data is maintained at 1, the storage element will be programmed to final state B. If the storage component is located in the middle critical data, it is stored in the -2200 and "the page data is changed to the critical power of the storage element (four) rises to the state C. Figure 5 α Α 1 The program described in Figure 22 & to e reduces the combined effect, because only the adjacent storage element #... pre-action gate is lightly dying _ from the south page of the display 70 pieces of stylized will be given: sub兀< The apparent threshold voltage has an effect. An alternative form is separated from the above; if the code is ^, ,, and the code is moved from the distribution 225 to the state C when the face data is 1. And when the inter-page is wise, it is moved to: =22aic provides relative to four data states and two data pages and two's but the concept taught can be applied to have more or less than four shapes.匕, and other implementations that differ from the two pages. Figure 233⁄4 - Timing diagram illustrating the possible programming of a program for stylizing non-volatile memory including four phases. For simplicity: 5 Xuan et al. and other schemas, the duration of the phase is shown as equal but in practice The duration of each phase can be optimized based on experimental results. The particular voltage used can be optimized based on experimental results. The relative voltage levels of the indications are not necessarily to scale and provide a high level guide. In particular embodiments, The NAND strings can each have their own individually driven boost structure. The boost structure can be used during stylization, erasing and/or reading operations to couple voltages to the storage elements. For example, the boost structure can be A significant amount of voltage is coupled to the floating gate of the storage element to increase the overall floating gate capacitance because the boost structure provides conductors to the two additional facets (eg, sides) of the storage element. Higher floating gate capacitance produces Good retention and high immunity to interference phenomena, as the charging capacity increases and the Coulomb blocking effect decreases. In addition, due to the pressurized junction 126503.doc -38·

The electrical waste of the structure is lightly coupled to the storage element Du, 70 pieces of A, and the voltage applied to the storage element through the word line can reduce the number of coupling voltages. Commonly applied voltages include the program voltage VPGM and the transfer voltage VD. For example, the voltage coupled to the floating gate of the selected storage element can be expressed by the following equation.

(1) VpGMxCRl+V

Boost structurexCR2=V

EFFECTIVE where CR1 is the ratio of the floating gate of the VpGM# storage element's floating gate' CR2 is the coupling ratio of the boosted structure voltage Vb〇〇ststruc_ to the floating gate, and Veffective is the effective or net voltage at the floating gate . Therefore, with respect to V with the CTIVE constant, Vnm can be reduced by Vboost structureX CR2/CR1. In one method, VBOOST STRUCT_ can be obtained from equation (1). Therefore, the boost structure can assist in stylizing the storage element. In addition, the number of auxiliary pixels provided can be independently set for each NAND string by applying a fixed boost voltage to one or more boost structures, and then independently discharging the boost structure via individual bit lines. As explained in detail below. The number of discharges can be controlled by the bit line voltage. An additional advantage of the boost structure is that a portion of the floating gate coupled to the storage element does not include a polysilicon inter-layer dielectric (see, for example, the polysilicon inter-layer dielectric layer 637 of Figure 7). This is because the portion of the coupled boost structure can be extended adjacent to the substrate and adjacent to the floating gate (see, for example, the boost structure 1 020 of FIG. 1). [The polysilicon interlayer dielectric is not in the boost structure and the floating gate. between. Therefore, the burden on the dielectric between the polysilicon layers is reduced. Also, the thickness of the dielectric between the polycrystalline layers can be reduced. The coupling of the boost structure may be significant 'because the coupling originates from the three facets of the floating gate (eg, from the top and both sides). 126503.doc -39- 1355660 In addition, the increased capacitance will increase the number of electrons on the floating gate, thereby reducing the problem of deteriorating retention and interference, which may be due to charge quantization effects in the floating gate with very small capacitance. For example, it is also possible to simultaneously verify the stylized states of multiple stores associated with the _ word line, since the potentials of the various structures can be independently set. In this case, the boost structure can be increased by a number of different verification levels for the multi-level storage element to be applied via the word line to the control enclosure of the selected storage element. For example, conventionally, the verification procedure includes controlling the gate of the storage element via the word line (4) the voltage Vva, ^ or we, and determining whether the storage element is turned on. If turned on, the storage element is less than the verification voltage. If the 'th storage element' is not turned on, the Vth system is larger than the verification house. This procedure is repeated for each verification voltage because only one verification voltage can be applied to the word line at a time. In contrast, with the M structure provided herein, a fixed voltage Vc"erify can be provided on the word line, and V just st STRUCTURE can be changed to simultaneously provide different verify voltages for different storage elements on a common word line. For example, the coupling from the boost structure to the control gate can be expressed by the following equation: σ (2) Vcg.verify+Vb〇〇st structurexCR3=Vcg effective f , , CR3 system boost structure voltage v_sT struc_ The ratio of the light-to-weight ratio of the component is controlled, and ~··- is connected at the control gate = effect:: voltage. ν—The ratio of the control gate is controlled by the sub-line—the heart provides the day (four) (four). You can set u_tstructure, cow phase, vCG-EFFECTIVE = Vva 'V... for the N Na associated with (4). See Figure 25. In a method ' can be obtained from equation (7) 126503.doc 1355660

VbOOST structure 0 In general, 'bit by bit (four) control of stylized operations, and simultaneous verification of multiple states, the number of stylized and validated operations can be added to the stylized window from the number of widths of the natural distribution of the stylized features. Reduce to the number of widths that only cover the natural distribution of stylized features. In addition, it is possible to reduce the number of verify operations after each stylized pulse to... This stylized increase in speed promotes a multi-level storage element with an increased number of states. ^ For example, eight states per storage element or more many. In addition, as described above, the significant reduction in the merging effect of the shielding function of the pressurized structure is also the enabling component of the multi-level storage element. In addition, 'the read program can be increased by multi-loop reading the boost structure in the program'. In each loop, the stylized read private order of one or more storage elements is determined to be similar to the verification program, except that it may be necessary Out of loop, because the read status is not known in advance. By analogy with the above verification procedure, the coupling from the boost structure to the control gate can be expressed by the following equation: (3) Vcg-read+Vb〇〇st structurExCR3=Ycg.effective , where VCG-READ is given reading Take the voltage on the word line in the loop. Therefore, vB00ST STRUCTURE can be set corresponding to the cg-read value. See also Figure 25° in the method 'can be used from the equation _#v coffee. In addition, the advantages provided by the boosting structure in the stylization, verification and reading procedures can be achieved independently. That is, the boost structure can be fully discharged so that it has no effect during the stylization, verification, and reading process, and the phase is clear. Figure 23 depicts four phases: a first boost phase, a second boost phase. 35 pressure structure discharge phase and stylized phase. Four Phases 126503.doc •41 · 1355660 The loop repeats for each stylized pulse. Waveform 2300 describes a voltage vS0URCE applied to the source side of the nand string. This voltage is the boost voltage because it is used to boost the potential of the boost structure. For example, Vs〇urce can be about 8 to 1 〇V. Waveform 23 10 describes the voltage applied to the selected gate, including VSGS2 and VSGD. Waveform 2320 describes the voltage on unselected word lines. Waveform 2330 describes the voltage Vswl on the selected word line. Waveform 234A describes the voltage Vbl on the bit line of the selected NAND string in the first method. Waveform 2345 describes the voltage on the bit line of the selected NAND string in the second method. Waveform 23 50 describes the final voltage of the boost structure using the first or second method. VBOOST STRUCTURE ° In the first boost phase, the potential of the boost structure is increased. In one method, the source supply line is common to a group of NAND strings, e.g., in a block, such that the boost structure within each NAND string is simultaneously boosted to the same level. To reach the booster voltage Vs〇urce to reach the boost structure, the first select gate is turned on, for example, the gate is selected closest to the source supply line, and the second select gate is turned off, such as the inner select gate. Therefore, the nand string is configured to receive the boost voltage. In particular, set VsGsi to a level sufficient to open the external selection gate. Vsgsi can turn on the transistor by selecting the threshold voltage of the gate beyond vS0URCE. The internal select gate can be turned off by setting a lower value for Vsgs2, e.g., below vS0URCE. Vuwl, VSWL& VBL can all be set to 〇 V. Waveform 235〇 describes how to increase the Vb〇〇st structure when applying vS0URCE. The source supply line is coupled to the boost structure via an external selection gate and its associated source/no-pole area electrical box. The first boost phase can optionally be used to further boost the boost structure of the 126503.doc -42· 1355660 bit. In this phase, the higher or higher voltage Vh applied to the word line is coupled to the boost structure to further increase its potential. In one possible approach, vHIGH = vPASS, which is the transfer voltage during the stylization. This boosts the boost structure to a higher voltage as it floats in phase. Specifically, by lowering VSGS1 to turn off the external selection gate, it is ensured that the boosted structure does not pass through and increases vUWL and vSWL to VHIGH. Therefore, turn off the pole. Waveform 2350 describes the increase in A B00ST STRUCTURE

Select the gate discharge and the external selection gate. The third phase includes a discharge of the boosted structure. This provides the ability to independently control VB〇〇ST STRUCTURE for each NAND string. In this phase, the external selection gate is turned off when the inner selection and the non-polar side are selected to be on. For example, the inner select gate and the gate side select gate (waveform 2310) can be turned on by setting vSGS2 and vSGD to a higher level, respectively. In addition, VUWL&VSWL can be maintained at a first level to keep all storage elements turned on during discharge. For example, this can be the highest read level used. The level at which the pressurized structure is discharged can be controlled according to the bit line of the application. In the first method, as indicated by waveform 2340, VBL can be set according to the stylized state to which the selected storage elements within the NAND string are to be programmed. For example, state C can be the highest stylized state (with the highest vth), state B can be the intermediate stylized state, and state A can be the lowest stylized state. For state c, vBL is set to a higher level to provide a smaller discharge of the boost structure, keeping the Vb〇〇st struuure at a higher level. For state B, set VBL to the intermediate level and k for the intermediate level discharge to maintain ST STRUCTURE at the intermediate level. For state a, VBL is set to a lower level to provide a higher number of 126503.doc • 43·1355660 discharges thus keeping vB00ST STRUCTURE at a lower level. The particular VBL value can be set according to a particular implementation, including the % heart position used. The spacing between vBL specific values can be non-linear. In the second method, as indicated by waveform 2345, vBL can be set to a fixed amplitude pulse, wherein the duration of the pulse varies with the stylized state to which the selected storage element within NAND_ is to be programmed. Specifically, longer pulses can be used for higher stylized states, such as state c, while shorter pulses are used for lower stylized states, such as state A. Therefore, the level to which the boost structure is discharged can be set according to the level and/or duration of the voltage applied to the drain side of the NAND string. It should also be noted that BOOST STRUCTURE can vary as VPGM changes with successively programmed pulses. The lower VB00ST STRUCTURE can compensate for the lower VPGM, while the lower VBOOST STRUCTURE can compensate for the higher VPGM. Vb00ST STRUCTURE is reduced in each case described by waveform 23 50. In the example provided, the boost structure is discharged to a charge retention level for all stylized states. In an option, for the highest stylized state, such as state C, the private pressure structure does not have to be discharged at all. In another option, the boost structure can be fully discharged for the lowest stylized state, such as state A. The fourth phase applies VpGM to the programmed pulse of the selected word line (waveform 2330). VPGM can be added in a stepped manner with each successive stylized pulse (Figure 26). When the boost structure is charged to various data dependent voltages, the bit lines are now available to the NAND string to deliver the program or disable the voltage. Here, turning off the inner and outer U-selective gates can apply the transfer voltage VpAss to the unselected word lines (waveform 2320) depending on the particular technique used. In some stylized techniques, the source 126503.doc -44 - 1355660 polar side and / or drain side adjacent unselected word lines receive voltages other than the unselected word lines that receive VpAss, such as ov or other lower Voltage. As described above, the voltage across the boost structure is coupled to the floating closed pole of the storage element to drive electrons into the floating gate and increase the threshold voltage. The boost structure increases the voltage coupled by the selected word line so that the effect is the same as if a larger Vpgm is used for the selected word line and a larger vPASS is used for the unselected bit line. However, avoid using a larger Vpgm4Vpass. Disadvantages such as program interference. Alternatively or in addition, the boost structure can reduce stylized time. It should be noted that the optimum value for the displayed voltage can be determined experimentally and varies with different memory devices. After the program pulse is completed in the fourth phase, the word line is lowered and the verification process is executed. The pressurized structure floats and is constrained downward by this action. Figure 24 depicts a timing diagram illustrating the procedure for verifying the stylized state of non-volatile memory, waveform 24, describing Vs〇urce, waveform 241, describing Vsgsi, VSGS2, and VsGD, waveform 242, describing Vuwl, waveform 243 〇 describes Vswl, waveforms 2440 and 2445 describe Vbl in two different methods, and waveform 2450 describes VB00ST STRUCTURE. In one embodiment, phases 1 and 2 are the same for the stylized program of Figure 23. Phase 3 can also be similar to the stylized program of Figure 23, except that the VBL can be slightly varied to discharge the boost structure in accordance with the verify level of the selected storage element. In the fourth phase, the source side select gate is turned on by raising Vsgsi and VsGS2 as shown by waveform 2410, and vS0URCE is raised to the highest required to verify the highest stylized state for the group of memory elements to be simultaneously verified. Positive voltage. Vsgd is also set to open the drain side selection gate. For the sake of clarity, the 126503.doc -45· 1355660 offset applies the word line and Vcgver to each of the storage elements to be verified via the associated word line. The effect of the Zengwu structure is to apply different 乂(10) coffee Y to each selected storage element, depending on the particular verification level at which the π pieces are stored. Therefore, 矸占田丁 π Μ using different verification levels while verifying the storage elements resulted in significant time savings. Therefore, a single pass of four phases may be sufficient to characterize the stylization of all storage elements on a word line with respect to the verify level. The number of states in the group of states that can be simultaneously verified depends on the VTH separation of adjacent states, the increased waste structure. The maximum range of allowable voltages to the floating closed-capacitor face and the auxiliary gate. In some cases, the threshold voltage of the storage element selected for verification may be used to verify that the selected storage element will be turned on. In this case, the storage element does not reach the target stylized state, such as verifying the level, and requires one or more additional stylized pulses. If the critical component of the storage element selected for verification is greater than the test. And the level 'selected storage element does not turn on' indicates that the storage element has reached the target stylized state and can be locked for further stylization. In addition, the VB00ST structure discharge is indicated by waveform 2450, and Vbl does not rise as known by wave open / 2445. The level at which Vbl rises indicates the % of the condition for the verification of the storage of 70 pieces. In particular, the verification procedure can be used as described in conjunction with the figure. Figure 25 is a diagram - graph depicting bit line voltage versus time for different stylized states. As mentioned above, it is possible to verify the level or read the level according to the target. During the verification phase, the line will initially be discharged and will begin to charge to a different level during the integration time until a body biases the storage element to stop charging. Figure 25 depicts Vbl charging to 126503.doc -46 - 1355660 steps. The bit line for verification of different target states can be sensed at the same time. The number of ugly operations is reduced to one or two. Specifically, when the storage elements are in state C, state B, state a, and erased state, curves 25A, 2510' 2520, and 2530 represent Vbl. When the curve 25 〇〇 exceeds the trip point 25 〇 5, the associated storage element is turned off. Similarly, when the curve 25 〇 exceeds the trip point 2515, the associated storage element is closed, when the curve 252 〇 exceeds the trip point 2525, the associated storage element is turned off, and when the curve 253 〇 exceeds the trip point 2535 The associated storage component is closed. The decision that the storage element has reached the target verification level can therefore be performed during the verification phase. Similarly, the decision that the stored item has reached a particular read level can be performed during the read phase. Therefore, the stylized condition of the storage element can be determined by monitoring Yu during the verification or reading process. Figure 26 depicts an exemplary waveform applied to the control closure of a non-volatile memory during the simplification process. The voltage waveform 26A includes a series of program pulses 26U), 2620, 2630, 2640, 265, ... applied to the word line selected for programming. In one embodiment, the stylized pulses have a voltage VPGM that begins at an initial level and increases the amount of enthalpy, e.g., 0.5 V, for each successive stylized pulse until the maximum level is reached. As described above, the VpGM level can be advantageously reduced by the booster structure described herein. The verify pulses 2615, 2625, 2635, 2645, 2655, ... are inter-program pulses. Additionally, in some embodiments, only one verification pulse is required. In other embodiments, there may be additional verify pulses. The verify pulse can have the amplitude of VCG'VERIFY as previously described (see Figure 24). Figure 27 depicts a timing diagram illustrating the procedure for reading the 126503.doc • 47-1355660 stylized state of non-volatile memory. Waveform 2700 describes VS0URCE, waveform 271 0 describes VSGS丨, vSGS2, and VSGD waveform 2720 Vuwl is depicted, waveform 2730 describes VSWL, waveforms 2740 and 2745 are described in Vbl in two different methods, and waveform 2750 describes νΒ00ST STRUCTURE. The first two phases and the fourth phase are similar to the verification procedure of Figure 24. Phase 3 may also be similar to the verification procedure of FIG. 24 except that the level and/or duration VBL may be referred to as a micro-variation to discharge the boost structure in accordance with the read level, which may vary from the verify level (eg, see FIG. 20). ). In the fourth phase, by raising the uv_ turn on the source side to select the gate 'as described by the waveform 271(), and raising the v to the pin and simultaneously reading the storage component group to read the highest program The highest positive voltage required for the state. VsGD is also set to open the non-polar side selection question pole. Waveform 27 10 is offset for clarity. The reading procedure is similar to the verification procedure. In addition to performing the phase-by-phase loop for each reading level, it is possible to program the program for multiple reading levels instead of a single verification level. status. Specific 疋. The first to third phases can be combined with the above stylized stylization and verification procedures.

The same is true in the sequence, except that all NAND strings are discharged to the same level, A - .. ', in the embodiment, based on the reading level for state A, B or C (such as ra , Vrb or Vrc), such as the current capture loop (waveform 2740). In addition, the fourth phase of 铱J ^ can be related to the fourth phase of the verification program of FIG. 24, as described in the following: except for the selected word line voltage system VCG READ, which is privately cooled with each reading cycle. - Suihua. For example, ' has a value based on the read level. In one party, eight lines private \rr-ni decree ‘ VcG-READ=Vra, Vrb or

Vix (Fig. 20) ’ without a booster junction. Figure 28: Lights, Ten, and North Songs*. Figure 28 depicts a timing diagram for the unselected location line during the stylization, verification or reading of the non-volatile record I26503.doc -48-1355660. As indicated by waveform 28〇〇, Vsgsi and VSGS2 can be held at 〇 V to keep the source side select gate off. The vSGD (waveform 2800) and Vbl (waveform 281〇) can be maintained at a lower comparable level to maintain the closed end of the off-pole selection. Therefore, the boost voltage VS0URCE is not light 5 to the boost structure' so Vbqgst strugt remains at 〇V. Figure 29 is a flow diagram illustrating a particular embodiment of a program for programming non-volatile memory. In the implementation, the storage element (in blocks or other units) is erased prior to stylization. In step 29, the controller issues a "data load" command and receives input (Fig. 16) by control circuit 1610. In step 29〇5, the slave or host will specify the page bit. The address data of the address is input to the decoder 1614. In step 291, the program data for one of the addressed pages is input to the data buffer for stylization. The data is latched into the appropriate set of latches. In step 2915, the UI controller issues, stylizes, and commands to the state machine 1612. After being triggered by the ''stylized" command, the data latched in step 291B will be stylized using the pulses 2610, 262〇, 263(), 2640, 2650, ... applied to the appropriate word line of Figure 26. Up to the selected storage elements controlled by state machine 1612. In step 2920, the program voltage VpGM is initialized to the start pulse and the program counter pc held by the state machine 1612 is initialized to zero. In step 2925, the stylization program begins (see also Figure η). Specifically, at step 2930, a common boost of the boost structure is performed. At step 2935, additional boosting of the boost structure can be performed. At step 294, a separate discharge of the boost structure occurs in accordance with the target stylized state of the associated selected storage element. At step 2945, the selection of the VpGM is performed on the selected word line. 126503.doc • 49· 1355660 = Stylization of the memory component. If the logic τ is stored in a specific data lock, indicating that the corresponding storage element should be stylized, the corresponding bit line is grounded. On the other hand, if the logic "丨" is stored in a specific latch ten, and the corresponding storage element should remain in its current data state, the corresponding bit line is connected to Vdd to prohibit stylization. At step 2950, the verification process begins. Specifically, at step 2955, a common boost of the enhanced structure is performed. At step (10), additional boosting of the boost structure can be performed. At step 2965' individual discharges of the boost structure occur based on different target verification levels in the storage element. In step MM, by applying Vcg_verify on the selected sub-line and characterizing the stylized state of the selected storage element, for example, by determining whether the storage element is turned on, verification of the selected storage element occurs (see also Figures 24 and 25). . If it is detected that the target threshold voltage of a selected storage element has reached the proper verification level, the data stored in the corresponding data latch becomes a logic" (". If the detected threshold voltage has not reached the appropriate verification bit Quasi' does not change the data stored in the corresponding data latch. In this way, there is no need to further program a bit line with a logical "Γ stored in its corresponding data latch. When all data When the latch stores the logic, the state machine (via the line or type mechanism described above) knows that all selected storage elements have been programmed. In step 2975, 'determines whether all data latches store logic τ. If the program is finished And succeeded 'because all selected storage elements have been programmed and verified, and the status of "pass" is reported in step 298. If it is determined in step 2975 that not all data latches store logic "1" The program continues. In step 2985, the program counter pc is checked according to a program 126503.doc -50 - 1355660 limit value PCmax. The system is twenty; however, other numbers can be used. If the program counter pc is not less than PCmax, the program has failed, and the status "failure" is reported in step 299. If the program counter PC is less than PCmax, then % The coffee increases the step size and increments the program counter pc in step 2995. After step 2995, the program loop returns to step 2925 to apply the next stylized pulse. Figure 30 is a flow chart illustrating the reading for non-volatile A specific embodiment of the program of the memory. The reading process begins in step 3 and may include a number of read cycles, one for each read state. In the first read cycle, step 3010 includes selecting a read. Take a level, such as Vrc, Vrb, or Vra (see Figure 2〇). When the storage element includes an extra shape (four) 'for example eight states instead of four ▲, an additional read cycle can be performed. In one method, the program is highest The read state, start, for example state c, has a read verify level Vrc. Step 3 20 includes performing a common boost of the boost structure, while the step brain includes additional boost to perform the boost structure. The structure is discharged to a common level according to the current read level. Step 3 (4) includes setting the control gate voltage Vcg.read according to the current read level, and the step touch includes applying VCG-READ to the selected word j. Step 3070 includes The characterization storage element is relative to the stylized state of the current month's position, for example, by determining whether the storage element is turned on when applied. For example, if the storage (4) is not turned on, it can be concluded that it is in state C. In the decision block 3090, decide whether to save the read loop. If there is a residual-extra loop, the program continues in step 3 by the lower delta take loop. The program continues until there is no additional read cycle, and the read cycle ends at this point (steps 3〇9〇). The foregoing detailed description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Inspired by the above teachings, there may be many modifications and changes. The specific embodiments are chosen to be illustrative of the principles of the invention and the application of the embodiments of the invention The present invention is utilized. It is intended that the scope of the invention be defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a top plan view of two adjacent NAND strings having a boost structure. 2 is an equivalent circuit diagram of the NAND string of FIG. 1. Figure 3 is a top plan view of an alternate embodiment of two adjacent NAND strings having a boost structure. 4 is an equivalent circuit diagram of the NAND string of FIG. Figure 5 is a circuit diagram depicting three NAND strings with dual source side select gates and boost structure. Figures 6 through 10 depict the manufacture of a non-volatile reservoir having a pressurized structure. Figure 6 depicts a non-volatile reservoir. Figure 7 depicts details of a portion of Figure 6. - Figure 8 depicts the non-volatile reservoir of Figure 6 after deposition of an insulating layer. Figure 9a depicts the non-volatile reservoir of Figure 8 after deposition of a photoresist layer. Figure 9b depicts the non-volatile reservoir of Figure 9a after selective exposure and removal of the photoresist and engraving portions of the insulating layer. Figure 10 depicts the non-volatile memory of Figure 9b after deposition to provide a pressurized layer of conductive material. 126503.doc •52· 1355660

Figure 11 is a top plan view of another adjacent N A N v <RTIgt; 12 is an equivalent circuit diagram of the NAND string of FIG. Figure 13 is a circuit diagram depicting two NAND strings having a single source side select gate and a zigzag structure. Figure 14 depicts (iv) the fabrication of a non-volatile storage having a pressurized structure. D sign Figure 1 is a block diagram of a NAND flash memory device array.

Figure 16 is a block diagram of a non-volatile memory system using a single column/row decoder and read/write circuits. X Figure 17 is a block diagram of a non-volatile memory system using a double column/row card to cry a good memory and/or a read/write circuit. Figure 18 is a block diagram depicting one embodiment of a sensing block. Figure 19 illustrates an example of organizing a memory array into blocks for all bit line memory architectures or for even-on-residence architectures. Figure 20 depicts a set of exemplary threshold voltage distributions. Figure 21 depicts another set of exemplary threshold voltage distributions. Figure 22a to each of the Dragons „distributes and describes the procedure for stylizing non-volatile memory. Figure 2 3 depicts a timing diagram, soymeal, and the program used to program non-volatile memory. Also described - the timing diagram' describes a procedure for verifying the stylized state of non-volatile memory.

Figure 2 5 is a graph, 1 beginning # ^ L ^ /, the structure of the bit line for different stylized states 126503.doc -53- u55660 voltage versus time. Figure 26 depicts an exemplary waveform that should be poled during stylization. Control gate for non-volatile memory

Figure 27 depicts a program for the stylized state of a sequence diagram. Description of the description for reading non-volatile memory Figure 28 depicts a timing diagram for stylizing non-volatile memory for unselected positioning elements. Figure 2 is a flow chart, a specific embodiment of the program. Figure 30 is a flow chart, a specific embodiment of the sequence. During verification or reading, its description is used to program non-volatile memory. Its description is used to read non-volatile memory. [Main component symbol description] 100 Transistor 100CG Control gate 100FG Floating gate 102 Transistor 102CG Control Gate 102FG Floating Gate 104 Transistor 104CG Control Gate 104FG Floating Gate 106 Transistor 106CG Control Gate 106FG Floating Gate 126503.doc • 54- 1355660

108 Source side selection gate 110 Source side selection gate 115 Boost structure 118 Substrate 120 Source line contact 130 Source side selection gate 132 Source side selection gate 134 Transistor 134CG Control gate 134FG Floating gate Pole 136 transistor 136CG control gate 136FG floating gate 138 transistor 138CG control gate 138FG floating gate 140 transistor 140CG control gate 140FG floating gate 142 drain side selection gate 145 boost structure 148 substrate 150 bits Line contact 520 NAND string 126503.doc -55- 1355660

521 bit line 522 drain side select gate 523 storage element 524 storage element 525 storage element 526 storage element 527 source side select gate 528 source side select gate 530 boost structure 531 substrate 540 NAND string 541 bit line 542 drain side select gate 543 storage element 544 storage element 545 storage element 546 storage element 547 source side select gate 548 source side select gate 550 boost structure 55 1 substrate 560 NAND string 561 bit line 562 bungee Side Select Gate 126503.doc · 56· 1355660 563 Storage Element 564 Storage Element 565 Storage Element 566 Storage Element 567 Source Side Select Gate 568 Source Side Select Gate 570 Pressurization Structure 571 Substrate 600 Substrate 605 NAND String 610 NAND String 615 NAND string 620 Source side select gate 622 Source side select gate 624 Source line 626 Source side select gate 628 Source side select gate 630 Storage element 632 Storage element 634 Storage element 636 Storage element 637 Polysilicon Interlayer dielectric layer 638 drain side select gate 639 floating gate 126503.doc .57 · 1355660

640 bit line 641 insulating layer 642 drain side select gate 650 source/drain diffusion region 652 source/drain diffusion region 654 source/drain diffusion region 656 source/polar diffusion region 658 source/ Bottom diffusion region 660 source/drain diffusion region 662 source/drain diffusion region 664 source/drain diffusion region 666 source/drain diffusion region 800 insulating layer 905 photoresist layer 900 mask 910 corresponding portion/ Source/drain region portion 920 corresponding portion/source/drain region portion 1000 mask 1010 pressurized structure (partial) 1020 pressurized structure 1030 pressurized structure (partial) 1115 pressurized structure 1118 substrate 1145 pressurized structure 126503 .doc 58- 1355660

1148 Substrate 1320 NAND string 1321 bit line 1322 drain side select gate 1323 storage element 1324 storage element 1325 storage element 1326 storage element 1327 source side select gate 1330 boost structure 1331 substrate 1340 NAND string 1341 bit line 1342 汲Polar side selection gate 1343 storage element 1344 storage element 1345 storage element 1346 storage element 1347 source side selection gate 1350 boost structure 1351 substrate 1360 NAND string 1361 bit line 1362 drain side select gate 126503.doc -59. 1355660

1363 Storage element 1364 Storage element 1365 Storage element 1366 Storage element 1367 Source side selection gate 1370 Boost structure 1371 Substrate 1500 Memory array / storage element 1504 Source line 1506 Bit line 1526 No terminal 1528 Source terminal 1550 NAND String 1600 Sensing Block 1610 Control Circuit 1612 State Machine 1614 On-Chip Address Decoder 1616 Power Control 1618 Line 1620 Line/Data Bus 1630 Column Decoder 1630A Column Decoder 1630B Column Decoder 1650 Controller 126503.doc -60- 1355660

1660 Line Decoder 1660A Line Decoder 1660B Line Decoder 1665 Read/Write Circuit 1665A Read/Write Circuit 1665B Read/Write Circuit 1670 Sensing Circuit 1672 Data Bus 1680 Sensing Module 1682 Bit Line Latch 1690 Common Part 1692 Processor 1693 Line 1694 Data Latch/Data Latch Stack 1696 Memory Device / 1/0 Interface 1698 Memory Die 1900 Architecture 1910 All Bit Line Architecture 2100 Arrow 2110 Arrow 2120 Arrow 2250 Threshold Voltage Distribution 2300 Waveform 2310 Waveform 126503.doc -61 - 1355660 2320 Waveform 2330 Waveform 2340 Waveform 2345 Waveform 2350 Waveform 2400 Waveform 2410 Waveform 2420 Waveform 2430 Waveform 2440 Waveform 2445 Waveform 2450 Waveform 2500 Curve 2505 Jump Point 2510 Curve 25 15 Jump Detachment 2520 Curve 2525 Trip point 2530 Curve 2535 Trip point 2600 Voltage waveform 2610 Program pulse 2615 Verify pulse 2620 Program pulse 126503.doc -62 1355660

2625 Verify Pulse 2630 Program Pulse 2635 Verify Pulse 2640 Program Pulse 2645 Verify Pulse 2650 Program Pulse 2655 Verify Pulse 2700 Waveform 2710 Waveform 2720 Waveform 2730 Waveform 2740 Waveform 2745 Waveform 2750 Waveform 2800 Waveform 2810 Waveform SGS1 Control Line SGS2 Control Line WLO Word Line WL1 Word Line WL2 Word Line WL3 Word Line 126503.doc ·63·

Claims (1)

I35566Q 〇961429〇2 Patent Application Date Revision Replacement Page Chinese Patent Application Replacement (August 100) X. Patent Application Range: 1. A method for stylizing non-volatile storage, comprising: a NAND string to receive a boost voltage, the NAND string comprising a plurality of storage elements, the NAND string being formed at least partially on a substrate, a boost structure extending along the NAND string; and ^ one of the NAND strings The boost voltage is applied to one end and the boost voltage is transmitted to the boost structure along a position where the NAND string contacts the substrate via the boost structure. φ 2. The method of claim 1, wherein: the boost voltage is applied to the first end of the NAND string via a source side of the NAND string. 3. The method of claim 1, wherein: the boost structure is in contact with the substrate in a source/drain region along the NAND string. 4. The method of claim 1, wherein: the plurality of storage elements are disposed between: (a) inner and outer select gates of the first end of the NAND string, and (b) a second end of the NAND string, and the boosting structure is in contact with the substrate along the NAND string at a / source/drain region, and the boosting structure is between the inner and outer select gates between. 5. The method of claim 4, wherein: the configuring includes turning the outer select gate on and turning off the inner select gate. 6. The method of claim 1, wherein the voltage of one of the boosting structures is raised to return a step to be applied, the method further comprising: 126503-1000810.doc when the voltage of the boosting structure is boosted to the NAND The word line associated with the string applies an elevated voltage. The method of claim 6, wherein the plurality of storage elements are disposed between: (a) inner and outer selection gates of the first end of the NAND string, and (b) the NAND string At a second end, the method further comprises: - turning off the inner and outer select gates when the elevated voltage is applied. 8. The method of claim 6, further comprising: at least partially discharging the boost structure during application of the elevated voltage. 9. The method of claim 8, wherein the plurality of storage elements are disposed between: (a) the first end of the NAND string and (b) a select gate of the second end of the naND string And the discharge of the boost structure includes opening the select gate. 10. The method of claim 8, wherein: the boosting structure is discharged to a level based on a stylized state, at least one of the storage elements being programmed to the stylized state. The method of claim 8, further comprising: controlling a level of the voltage of the boost structure by controlling a level and/or period of the voltage applied to the one bit line, the bit being applied Meta-line. For one of the NAND strings, the drain side. 12. A non-volatile storage system comprising: a NAND string comprising a set of storage elements, the nanD string being at least partially formed on a substrate; 126503-1000810.doc -2 - 1,355660 the NAND string - an inner and outer select gate of the first end; and a k C structure extending along the NAND string, the boost structure being along a position between the inner and outer select gates of the NAND string The substrate is in contact. 13. The non-volatile storage system of claim 12, wherein: the 忒 position comprises a source/drain region along one of the NAND strings. 14. The non-volatile storage system of claim 12, wherein: the pressurized structure comprises an elongated conductive material. 15. The non-volatile storage of claim 12 (4), wherein: the inner and outer selection gates are provided on one of the source sides of the NAND string. 16. The non-volatile storage system of claim 12, further comprising: one or more control circuits 'which communicate with the NAND string to perform a stylized operation' - the control circuit application - boost A voltage is transmitted to the boost structure via the location. 17. The non-volatile storage system of claim 16, wherein: the boosted electric dust is applied via a source side of the NAND string. 18. The non-volatile storage system of claim 16, wherein the storage element is disposed between: (4) an inner and outer selection pole, the first end of the N-string, And (8) one of the second ends of the NAND string, and applying the increased power-dissipation when the one or more control circuits turn on the external selection gate and turn off the internal selection gate. 19. The non-volatile storage system of claim 16, wherein: the one or more control circuits apply an increase to a word line associated with the 126503-1000810.doc 1355660 NAND string after applying the update voltage And the set of storage elements are disposed between: (a) the inner and outer select gates, the first end of the NAND string, and (b) one of the NAND strings The second end, and the one or more control circuits turn off the inner and outer select gates when the elevated voltage is applied. 20. The non-volatile storage system of claim 16, wherein the one or more control circuits discharge the pressurized structure at least partially after applying the boosted voltage, the set of storage elements being configured in the following two Between (a) the inner and outer select gates, the first end of the NAND string, and (b) a select gate at a second end of the NAND string, and the one or more The control circuit discharges the boost structure by turning on the select gate at the first end of the nand string. 126503-1000810.doc 1355.660 A patent application No. 096142902 Chinese map replacement page (August 100) Figure 30 126503-fig-1000810.doc 22-