TW200822119A - Method and system for reverse reading in non-volatile memory with compensation for coupling - Google Patents

Abstract

Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored in adjacent (or other) charge storage regions. Although not exclusively, the effects are most pronounced in situations where adjacent memory cells are programmed after a selected memory cell. To account for the shift in apparent charge, one or more compensations are applied when reading storage elements of a selected word line based on the charge stored by storage elements of other word lines. Efficient compensation techniques are provided by reverse reading blocks (or portions thereof) of memory cells. By reading in the opposite direction of programming, the information needed to apply (or select the results of) an appropriate compensation when reading a selected cell is determined during the actual read operation for the adjacent word line rather than dedicating a read operation to determine the information.

Description

200822119 IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The specific embodiments of the present disclosure relate to non-volatile memory technology. [Prior Art] Half-thickness devices have become more and more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, inactive computing devices, and other devices. Electrically erasable programmable read only memory (EEPr〇m) (including flash EEPROM) and electronically programmable read-only memory (epr〇m) are among the most popular non-volatile semiconductor memories. An example of a flash memory system uses a NAND structure that includes a plurality of transistors arranged in series between two select gates. The series transistors and the t»海荨k gate are called a NAND string. Figure 1 shows a top view of a NAND string. Figure 2 is an equivalent circuit thereof. The NAND string shown in the figure includes four transistors 10, 12, 14 and 16 connected in series between a first selection gate 12 and a second selection gate 22. Select gate 12 connects the NAND string to bit line terminal 26. Select gate 22 connects the NAND string to source line terminal 28. The selection gate 12 is controlled by applying an appropriate voltage to the control gate 20CG via the selection line Sgd. The selection gate 22 is controlled by applying an appropriate voltage to the control gate 22CG via the selection line SGS. Each of the transistors 10, 12, 14 and 16 includes a control gate and a floating gate which form a gate element of a memory cell. For example, the transistor 1A includes a control gate 10CG and a floating gate 1〇FG. The transistor 12 includes a control gate 12Cg and a movable gate 12FG. The transistor 14 includes a control gate 14CG and a floating 124907.doc 200822119 gate 14FG. The transistor 16 includes a control gate 16C:C} and a floating gate 16FG. The control gate i〇cg is connected to the word line WL3, the control gate 12CG is connected to the word line WL2, the control gate 14 is connected to the word line WL1, and the control gate 16CG is connected to the word line WL0. It should be noted that although Figures 1 and 2 show four memory cells within a NAND string, the use of four transistors is for illustrative purposes only. A NAND string may have less than four memory cells or more than four memory cells. For example, some NAND strings will include 8 memory cells, 丨6 memory cells, 32 memory cells, and the like. The discussion herein is not limited to any particular number of memory cells within a NAND string. A typical architecture of a flash memory system using a NAND structure would include several NAND strings. A related example of a NAND-type flash memory and its operation is provided in the following U.S. Patent/Patent Application, the entire disclosure of which is incorporated herein by reference in its entirety, U.S. Patent No. 5,570,315, U.S. Patent No. 5,774,397, U.S. Patent No. 6, U.S. Patent No. 5,386,422, U.S. Patent No. 6,456,528, and U.S. Patent Application Serial No. 9/893,277, the disclosure of which is incorporated herein. Other types of non-volatile memory other than NAND flash memory can also be used in accordance with specific embodiments. When programming an EEPROM or flash memory device, a stylized voltage is typically applied to the control gate and the bit line is grounded. The electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell rises, causing the memory cell to be in a stylized state. The floating gate charge and threshold voltage of the cell may indicate a particular state corresponding to the stored data. For more information on the stylization of 124907.doc 200822119, more information can be found in US Patent Application No. 10/379,608, filed March 5, 2003, entitled ''Self-pressurization Technology'" and July 29, 2 U.S. Patent Application Ser. Ο Ο Because the electric charge is based on one of the charges stored in the adjacent floating gates, the apparent charge shift stored on a floating gate can occur. This floating gate-to-floating gate coupling phenomenon is described in U.S. Patent No. 5,867,429, the entire disclosure of which is incorporated herein by reference. This floating gate-to-floating gate coupling phenomenon occurs most prominently between sets of adjacent memory cells that have been programmed at different times, but not all. For example, the programmable-first-memory unit can be added to add a charge level to its floating gate, which corresponds to a set of data. Subsequently, one or more adjacent memory cells are programmed to add a charge level to their floating gate, which corresponds to the group of bakes. After stylizing the adjacent memory cells - or a plurality of mouths and hidden bodies early 70 'because the charge system on the adjacent memory cells is coupled to the 4th-memory unit, The level of charge read by the first memory cell may appear to be different from when it was programmed. The coupled person from the adjacent memory unit can receive w $ &< the scam can read the apparent charge level offset from a selected memory unit - enough to cause erroneous reading of the stored data. As the memory cell is large + _ J is continuously small, it is expected that the self-suppressing and erasing distribution of the threshold voltage will also be due to short... '耘 coupled, field in short channel effect, larger oxide thickness / light 5 is increased by k-like and more channel doping dopant fluctuations, thereby reducing the available interval between adjacent evils. The 匕 effect for multi-state memory is more than just using the binary memory of the two states 124 > The reduction in space between word lines and at the beginning of the bit also corresponds to the coupling between the line toughness & I 9 plus the phase-shifted gate. The slamming gate to the eccentric gate coupling effect system is more involved in multi-state dreaming, and the mouth is allowed to limit the voltage range and the prohibition " body state is not the same. The range between the target range of the voltage from the tongue 1 is more narrow than in the binary device. Therefore, when the system is 々, 卜立鳞 -, the pre-action of the gate to the eclipse can be caused by 极 Ο [Inventive content] The voltage-limited dry-circle is offset to the forbidden range. == Apparent charge shift stored in the storage area (eg, a floating, volatile gate) stored in an adjacent (or other) charge storage region . Not all of the officials are like this, but in the case of a ^ ^ , after the carcass unit is programmed to be adjacent to the stone body, the state of the state is very prominent. In order to solve the apparent ^ ^ ^, and the stored charge of the spring storage element to read "the yoke plus one or more compensation. The efficiency of the second:: by: reverse the memory block of the memory unit ( Or part of it) (.. Hunting is performed by reading in the opposite stylized direction. During the 2nd reading operation, it is decided to read the 4th sub-line (or select the result): - Appropriate compensation determines the information. (4) Dedicated η ❹ - read operation - The specific embodiment includes starting with a first sub-line of one of the gates and ending with a second one. ^ ^ ^ One of the last word lines of the pole is programmed to couple to a plurality of word lines that are not _ non-volatile storage elements. Stylization includes changing one of the selected ones of the 70 pieces of the special storage according to a target memory state 124907. Doc 200822119 threshold voltage. The component that reads the surface to the plurality of word lines starts at the last word line and ends at the 胄 (4) storage left; from 4 _L to the line. Reading the storage elements includes Each word line outside the last word line is based on an online application of one or a group of selected gates Reading -, " multiple compensations of adjacent word lines in the direction. Another embodiment includes receiving - to - combining to a plurality of word lines - and storing the information in the non-volatile storage element Pure person..., 仔 之 。 。 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 。 。 。 。 。 。 。 。 。. The non-volatile storage element m word line is adjacent to one of the plurality of word lines and the second word line. The response should be ^, to: start to lightly connect to the storage element of the last word line and end to face to the first a sequence of storage elements to read the set of non-volatile storage devices, wherein the storage elements that are read to the first word line include charges stored in the storage elements based on the second word line Applying _ or multiple offsets. The read-in step includes buffering data from the storage elements of the second word line, buffering storage from the second word line, prior to reading the storage elements of the first word line After the component data, buffer the data from the storage element of the first word line, and buffer The buffer data from the storage element of the second word line is maintained after the data of the storage element of the first word line. [Embodiment] The threshold voltage through the manipulation unit 'memory unit can be used for storing in analogy or digital form. The data represented by the 。 愔 贝 贝 β 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 〖 State, which refers to _ 124907.doc -10- 200822119 data 1 and 〇. Generally, at least one reference threshold voltage level is established to divide the threshold voltage memory window of the memory unit into two ranges. By reading a predetermined, fixed voltage (eg, reading a reference voltage) corresponding to the reference threshold voltage level to its gate to read the cell, its source/no-pole conduction state is compared by conducting the conduction Breakpoint level or reference current is built. If the current is higher than the current of the reference current level, it is determined that the single w element is 'on' and in a logic state. If the current is less than the reference current level, the unit is determined to be ''off. "And in other logical states." In one example of a NAND type flash memory, the voltage threshold is negative 'after the erase of the memory cell' and is defined as a logic one. The threshold voltage is positive after a stylized operation and is defined as a logic zero. When the threshold voltage is negative and a read is attempted by applying 〇 V to the control gate, the memory cell is turned "on" and the logic 1 is stored. When the threshold voltage is positive and a read operation is attempted by applying 〇 V to the control gate, the memory cell does not turn on to indicate that the logic 正 is being stored. 〇 A memory unit can also store multi-bit digital data by using two or more threshold voltage ranges to represent different memory states. a threshold voltage window can be used to resolve the individual states

A plurality of voltage breakpoint levels divided into the number of desired memory states. For example, four threshold voltage ranges, which are known as the multi-state flash memory unit, are described in the application No. 10/461,244 "Tracking Units for Memory Systems" The coding scheme, both of which are incorporated herein by reference. There are many ways for π to measure the _ memory • I % conduction current during a read or verify operation. In the example, the conduction current of the memory cell is measured according to the discharge rate of a dedicated capacitor in the sense amplifier. ‘ 纟 — — — — — 范例 范例 范例 m m m m m m m 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导 传导The charge on the bit line is measured after a period of time to see if it has been discharged. Another type of memory cell for a flash EEPROM system utilizes a non-conductive dielectric material in place of a conductive floating interpole to store charge in a non-volatile manner. Such a unit is described in the article by Chan et al., entitled, True Single Crystal Oxide_Nitride_Oxide eepr〇m Device, IEEE Transactions on Electronics, Journal _8, No. 3 , i98#3, pp. 93-95. From the oxidized stone eve, the nitrite and the oxidized stone eve (,, 〇n〇,,) shape (J is a three-layer dielectric system sandwich and a conduction control The gate is between the surface of the conductive substrate on the channel of the memory cell. The cell is programmed by injecting electrons from the cell channel into the nitride, and the electrons are captured and stored in the nitride in a restricted region. The stored charge is then changed in a detectable manner to change the threshold voltage of a portion of the cell channel. The cell is erased by injecting a thermal hole into the nitride. See also N〇zaki et al. for semiconductor disc applications. EEPROM with MONOS memory cell, (IEEE Solid State Circuits, Vol. 26, No. 4, April 1991, pages 497 to 501), which illustrates a similar unit using a separate gate configuration, 124907 .doc -12- 200822119 A doped polysilicon gate A part of the memory cell channel is formed to form a separate selection transistor. The foregoing two articles are incorporated herein by reference. "Non-volatile semiconductor memory technology" edited by William D. Brown and Joe E. Brewer The stylization technique mentioned in (2) of IEEEA Edition, 1998, is also described in this section for application to dielectric charge trapping devices. The memory cells described in this paragraph can also be used. Thus, the technique described herein is also applicable to the light coupling between the dielectric regions of different memory cells. Another scheme for storing two bits in each cell has been described by Eitan et al. - A new type of regionalized capture, 2-bit non-volatile memory unit " (Journal of IEEE Transactions on Electronics, Vol. 21, No. 5, November, pp. 543-545). The electrical layer extends across the channel between the source and the drain diffusion. The charge of one data bit is localized in the dielectric layer adjacent to the drain, and the charge of the other data bit is Regionalization in the dielectric layer adjacent to the source Multi-state data storage is obtained by separately reading the binary states of the spatially separated charge storage regions within the dielectric. The memory cells described in this paragraph can also be used. Figure 3 illustrates an exemplary NAND string 50. The array is 1 〇〇, such as a string of pixels. Along the rows, a bit line 27 is coupled to one of the bit line select gates for the NAND string 50 without the terminal 26. NAND strings along each column, A source line 29 can be connected to all of the source terminals 28 of the source line selection gates of the NAND strings. The memory cell array 100 is divided into blocks of a plurality of memory cells. Like a flash EEPROM system, a block erase unit can be referred to as a wipe or block. 124907.doc -13- 200822119 Block or physical block. Each block may include a minimum number of memory cells that are erased together. In Figure 3, a block (e.g., block 30) includes all of the cells connected to a set of pong-word lines WL0 through WLi. Each block is generally divided into pages. A page is typically a minimal stylized or read unit, but can be programmed or read more than one page in a single operation. In another embodiment, the individual pages can be divided into a plurality of segments and the segments can include a minimum number of cells that are written once as a basic stylized operation. One or more pages of material are typically stored in a column of memory cells. A page can store data for one or more segments, the size of which is generally defined by a host system. One section includes user data and management materials. The management data typically includes an error correction code (ECC) that has been calculated from the user data for the segment. One part of the controller (described below) calculates the ECC when the data is programmed into the array and also checks it when reading data from the array. Alternatively, the ECC and/or other management materials are stored in pages or even different blocks within the pages or blocks of the user data to which they belong.一个 One of the sections of user data is usually 512 bytes, corresponding to the size of the section that is commonly used in the drive. Management data is generally an additional 16 to 20 bytes. A larger number of pages form a block, for example from 8 pages to 32, 64 or more pages, wherever they are. In some embodiments, a column of NAND strings includes a block. In a particular embodiment, the memory cell is raised by the P-well to the erase voltage (eg, 2 GV) for a sufficient period of time and the selected block word by the time when the source and bit lines are moving. Wire the ground to erase it. Thus, a strong electric field is applied to the pass-through oxide layer of the selected memory cell, and the selected memory cell is erased as the electrons of the 124907.doc -14·200822119 sub-gate are emitted to the substrate side.兀 兀 。. As the electrons are transferred from the floating open to the # region, J is degraded = the unit that prohibits erasing such as the 临 之 限 μ 使其 使其 使其 禁止 禁止 禁止 禁止 禁止 禁止 禁止 禁止 禁止 禁止 禁止 禁止 禁止 禁止 禁止 禁止 禁止 禁止 禁止 禁止 禁止Since the capacitive facets also raise the unselected word lines, bit lines, select lines, and common source lines to a distinct portion of the erase voltage, the erase of the unselected cells is inhibited. Erasing can be performed on the entire array of memory arrays, detached blocks, or other units. Each memory cell block includes a set of bit lines forming a row and a set of word lines forming a column. In a particular embodiment, the bit lines are divided into odd bit 7G lines and even bit lines. Memory cells along a common word line and connected to odd bit lines are programmed at one time, while memory cells along a common word line and connected to even bit lines are programmed at another time. ("odd/even stylized"). In another embodiment, the memory cells ("all bit threading" are programmed along a word line for all bit lines within the block. In other embodiments, such The bit line or block is decomposed into other groups (eg, left and right, more than two groups, etc.). Figure 4 illustrates a memory device 110 having read/write circuits for parallel reading and staging a page. The memory unit 1 can include one or more memory dies or wafers 112. The memory dies i 12 include a two-dimensional memory cell array 100, a control circuit 120, and a read/write circuit 130A. And 130B. In one embodiment, each peripheral circuit access memory array 100 is implemented in a symmetric manner on opposite sides of the array such that the density of access lines and circuitry on each side is halved. The equal read/write circuits 130A and 130B include a plurality of sensing blocks 200 that allow parallel reading of 124907.doc -15-200822119 fetch or stylize-page seedlings - U body early 7^. Memory array 100 Can be used by column decoders 14GA and 14GB by word lines and via lines The code 142 142 142B is addressed by a bit line. In a typical embodiment, a controller 144 is included in the same memory device 110 as one or more memory dies (eg, removable) Within the memory card or package, instructions and data are transferred between the host and controller 144 via line 132 and between the controller and one or more memory dies 112 via line 134. The controller can be specific

In her case, she included a RAM memory 丨3丨 to assist in data transmission. Control circuit 120 cooperates with the read/write circuits 13A and 13B to perform memory operations on memory array 100. The control circuit 12A includes a state machine 122, an on-chip address decoder 124, and a power control module 126. State machine 122 provides wafer level control of memory operations. The on-chip address decoder 124 provides an address interface between the address used by the host or a memory controller and the hardware address used by the decoders 140, 1403, 142, and 1426. The power control module 126 controls the power and voltage supplied to the word lines and bit lines during the memory gymnastics. An optional RAM memory 1 33 is provided in a particular embodiment to aid in memory operation. FIG. 5 is a block diagram of an additional sensing block 200 that is divided into a core portion (referred to as a sensing module 210) and a common portion 220. In one embodiment, there is a separate sensing module 210 for each of the plurality of sensing modules 210 and a common portion 220 for a plurality of sensing modules 210. In one example, a sensing block will include a common portion 220 and eight sensing modules 2 10 . Each of the sensing modules within a group will communicate with the associated common portion via a data bus 2 〇 6 124907.doc -16 - 200822119. For more information, please refer to U.S. Patent Application Serial No. 11/26,536, filed on Dec. 29, 2004, entitled "Non-Volatile Memory and Common Processing Methods for Sensing Amplifier Sets," The sensing module 210 includes a sensing circuit 204 that determines whether a conduction current in a connected bit line is higher or lower than a predetermined threshold level. The sensing mode group 210 is also A bit line latch 2〇2 is included for setting a voltage condition on the connected bit line. For example, a predetermined state latched in the bit line latch 202 will cause the bit to be connected. The line is pulled to a specified stylized inhibit state (eg, Vdd). The same boring tool 220 includes a processor 212, a set of data latches 214 and a coupled to the set of data latches 214 and data bus 134. Between the sides 216. Processor 212 performs the calculations. For example, one of its functions is to determine the data stored in the sensing memory unit and store the determined data in the data latch of the group. The set of data latches 214 is used to store the data bits determined by the process 212 during a read υ # operation. It is also used to store data bits that are imported from the data bus 134 during a stylized operation. The data bits that are imported represent the write data that is attempting to be programmed into the memory. I/O interface 216 provides an interface between data latch 214 and data bus 134. During reading or sensing, the operation of the system is controlled by state machine 122 of Figure 4, which supplies different control gate voltages to the addressing unit via word lines. As it gradually passes through various predefined control gate voltages corresponding to the various memory states supported by the memory, the sensing module 21 will trip at one of the voltages of 124907.doc • 17- 200822119 An output is provided from the sense amplifier 210 to the processor 212 via the bus 206. At this time, the processor 212 determines the generated memory m state by considering the (equivalent) trip event of the 忒 sensing group and the information about the applied control gate voltage from the state machine via the input line 208. The binary code is calculated for the memory state and the resulting poor bit bits are stored in the data latch 214. In another embodiment of the core portion, the bit line latch 2 〇 2 serves the dual task and serves as a latch for latching the output of the sensing module 210 and also as described above. Bit line latch. During stylization or verification, the data to be stylized is stored in the data latch 214 from the data bus 134. The stylized operation controlled by the state machine includes a series of stylized voltage pulses applied to the control gates of the addressed memory cells. A readback (verification) is performed after each stylized pulse to determine if the unit has been programmed to the desired memory state target threshold voltage. Processor 212 monitors the Q-back memory state associated with the desired memory state. When the two states are identical, the processor 212 sets the bit line latch 202 to cause the bit line to be pulled to a condition that specifies a program inhibit (e.g., Vdd). This prohibits the single 耦合 coupled to the bit line from being further programmed, even if stylized pulses appear on its control gate. In other embodiments, the processor is initially loaded with bit line latch 202, and the sensing circuit sets it to a disable value during the verification routine. The data latch stack 214 includes a data latch stack corresponding to the sense module. In one embodiment, each of the sensing modules 21 has three 124907.doc -18-200822119 data latches. In the case of a sound #+ & 存俜你千(仁不需要), the data locks the target is a shift temporarily UΜ^ ^ * The wind is saved in parallel. The φ column f material is used for ^, θ ^ 十汇机排排134, and vice versa. In a preferred embodiment, all of the 1-block latches of the read/write block on the opposite side [, , in the ancient order μ u + w 17 '" body early 70 can be formed to form a The block shift is temporarily stored so that a data block can be input or output by serially transmitting ^^^. Special Ο 欠 ......: The fetch/write module library is adapted so that the data latches of the data latch group move the data in or out of the data bus in the same way as the system - for the entire read The portion of the shift register of the block is fetched/written. In general, parallel operation _ w memory unit. Thus, a corresponding number of sensing modules 21G are operated in parallel. In a particular embodiment, a one-page controller (not shown) conveniently provides control and timing signals to the parallel operational sensing modules. For a detailed description of the sensing module 21 and its operation, please refer to U.S. Patent Application Serial No. 11/99,133, filed on Apr. 5, 2005, entitled "Non-Volatile Memory Read Operation Coupling white compensation, all of which are incorporated herein by reference. Additional information regarding the structure and/or operation of various embodiments of non-volatile storage devices can be found in (1) Announcement, March 25, 2004 U.S. Patent Application Publication No. 2004/0057287, "Non-Volatile Memory and Methods of Reducing Source Line Bias Errors"; (2) US Patent Application Publication No. 2004, published on June 10, 2004 /0109357, "Non-Volatile Memory and Methods of Improved Sensing"'; (3) US Patent Application No. 11 / 015, 19 9, filed December 16, 2004, entitled "Improved Memory Sense" Measuring circuit and method for low-voltage operation '', the inventor's ruler mad 111-person (11^11.6〇1; (4) April 2005 5 124907.doc •19-200822119 Medium 11/G99, 133, titled, during the read operation period of non-volatile memory "Coupling compensation", inventor Jian Chen; and (5) U.S. Patent Application Serial No. 1 1/321,953, filed on December 28, 2005, which is incorporated herein by reference. , Siu Lung Chan and Raui_Adrian Cernea. All five patent documents of the above-listed patent documents are hereby incorporated by reference in their entirety herein in the entirety of The memory is 7L early. The word line can be referred to as a selected word line. The remaining word lines of a block are referred to as unselected word lines. The selected word line can have one or two adjacent word lines. The line has two adjacent word lines, and the adjacent ones on the drain side are referred to as the drain side adjacent word lines and the adjacent word lines on the source side are referred to as the source side adjacent word lines. For example, if WL2 in Figure 2 is a selected word line, then WL1 is the adjacent source line on the source side and WL3 is the adjacent word line on the drain side. At the end of a successful stylization program, the threshold of the memory cells Electric Ο | 适# should be in the poemized memory unit - or multiple threshold voltage knives or In the threshold voltage distribution for one of the erased memory cells. Figure 6 illustrates the threshold voltage distribution for a memory bank when each memory cell stores two bits of data. Figure 6 shows The first threshold voltage distribution E of one of the erased memory cells and the three threshold voltage distributions A, B&C for the programmed memory cell 70. In a specific embodiment, in the E-knife The threshold voltage in the middle is negative and the threshold voltage in the distribution of A, 6 and c is positive. The different threshold voltage ranges in Figure 6 correspond to the predetermined 124907.doc -20- 200822119 values of the data bits. The specific relationship between the data programmed into the memory unit and the cell threshold voltage level depends on the data encoding scheme used by the units. In a specific embodiment, assigning a data value to a threshold voltage range using a Gray code assignment such that if a threshold voltage of a floating gate is erroneously shifted to its neighboring physical state, only one bit is affected . However, in other embodiments, Gray coding is not used. An example assignment, 1 1 ” to the threshold voltage range • E (state E), “10, to the threshold voltage range A (state A), “〇〇,, to the threshold voltage range B (state B) And, 〇1, to the threshold voltage range C (state C). Although Figure 6 shows four states, embodiments in accordance with the present disclosure may also be used with other binary or multi-state structures, including These include more or less than four states of structure. Figure 6 shows three read reference voltages Vra, Vrb, and Vrc for reading data from a memory cell. By testing a given memory cell Whether the threshold voltage is higher or lower than Vra, Vrb and Vrc, the system can determine the state of the memory unit. If a memory unit is conducted because Vra is applied to its control gate, the memory The unit is in state E. If a memory unit conducts at Vrb and Vrc but does not conduct at Vra, then the memory unit is in state A. If the memory unit is conducted at Vrc, but at Vra and If Vrb is not conducted, the memory unit is in state B. If the memory is single το in Vra, Vrb or V If rc is not conducting, the memory unit is in state 。. Figure 6 also shows three verification reference voltages Vva, vvb, and vvc. When the memory unit is programmed to state A, the system tests the memory sheets. Whether or not there is a threshold voltage greater than or equal to Vva. When the memory unit is programmed to state B, the system will test whether the memory unit is 124907.doc -21 - 200822119 has a greater than or equal to Vvb The threshold voltage. When the memory cells are programmed to state C, the system will determine if the memory cells have a threshold voltage greater than or equal to Vvc. Figure 6 also depicts a complete sequence stylization technique. In the complete sequence stylization, 'program the memory unit directly from the erase state E to any of the stylized states A, B or C. You can erase a group of memory cells to make all memory The cells are all in erased state E. A series of programmed voltage pulses are then applied to the control gates of the selected memory cells to program the memory cells directly into states A, B or c. Do Some memory cells are being programmed from state E to state A, but other memory cells are being programmed from state E to state 6 and/or from state E to state C. Figure 7 One of the two-pass technology of the multi-state memory unit, the multi-state memory such as A, is for two different pages: the lower page and the upper page to store data. Describe four states. For state E, two pages = store a "1". For domain A, the lower page stores a 0 and the upper page stores: Bu stores G for both states B'. For state c, the lower page stores 1 The page stores 0. Although a particular bit pattern is assigned to each state of the states, different bit patterns can be assigned. In the first pass of the stylization, the unit's voltage level is intended to be programmed; Set in the logical page. In the limit of thunder H, the right 4 digits are a logic 1, then the power will not change, because it is in the proper shape because ^ m φ ^ However, if you want to program the threshold imitation / 旳 70 70 a logical 〇, then the F level of the unit is added to the state A, as the arrow does not. Thus the end 124907.doc -22- 200822119 Stylized once. In a second pass of stylization, the threshold voltage level of the unit is set according to the bit to be programmed in the upper logical page. If the upper logical page bit will store a logic 1, then No stylization takes place, due to the stylization of the lower page bits, the unit is in this class One of the states E or A, such a state carry the upper page bit 1. If the upper page bit to be logic into a square,

' Then offset the threshold voltage. If the first pass causes the cell to remain in the erased state E, then in the second pass, the cell is programmed to increment/add the threshold voltage to state C, as indicated by arrow 254. If the unit has been programmed to state A due to the first pass, the memory unit is further programmed in the second pass such that the threshold voltage is increased to state B as indicated by arrow 252. The result of the second pass is that the unit is programmed to store a logic Π0 for the state of the upper page, without changing the program for the lower page. Figures 8A to 8C disclose a program for stylizing non-volatile memory. ◎ For any particular memory cell, the floating gate to the oceanic gate coupling is reduced by writing to the particular memory cell relative to a particular page after writing to the adjacent memory cell of the previous page . This technique can be referred to as last first mode (LM) stylization in this paper. In the example of Figures 8-8c, four data states are used, and each cell stores two bit data per cell unit. Erasing state E stores data, state A stores data 〇ι, state B stores data 1 〇, and state C stores data 00. Other codes for the physical to lean state can also be used. Each memory unit stores the file of two logical page data. For reference purposes, the pages are referred to as the upper page and the lower page 124907.doc -23-200822119 page but other labels may be given. State A is coded to store bit 0 for the upper page and store bit 1 for the lower page, state coded to store bit 1 for the upper page and store bit 〇 for the lower page, while state C is The code is used to store bits 〇 for two pages. The data of the lower page of the memory unit for the word line WLn is programmed in a first step as shown in FIG. 8A and used for the upper page of the unit as shown in FIG. 8 (: In the second step, the program is programmed. If the lower page data retains the data 1 for a unit, the threshold voltage of the unit remains in the state E during the ρ and 1 steps. If the lower page information is to be programmed As a result, the threshold voltage of the memory cell is raised to state B'. State B is an intermediate state β having a verification level Vvb' lower than Vvb. In a specific embodiment, After the page data under the stylized memory unit, 'the adjacent memory cells at the adjacent word line WLn+1 will be programmed relative to their lower page. For example, the memory at WL2 in Figures! to 3 The lower page of the cell can be programmed to be Q after the lower page of the memory cell at WL1. In the case where the threshold voltage of the memory cell 1 is raised from the state E to the state β after the staging memory unit 12, Floating gate coupling can raise the apparent threshold of memory unit 12 The cumulative effect on the memory cells at WLn will broaden the apparent threshold voltage distribution for the threshold voltages of the cells, as shown in Figure 8B. The word lines of interest can be programmed The upper page remedies the apparent broadening of the threshold voltage distribution as shown in Figure 8C.

Figure 8C depicts the procedure for stylizing the upper page of the unit at WLn. If a memory cell is in erase state E and its upper page bit is intended to remain at the frame, then the memory cell remains in state E. If the memory unit is in state E 124907.doc -24- 200822119 Ο 且 and its upper page data bit is to be programmed to 0, then the threshold voltage of the memory unit is raised to the state Within the scope. If the memory cell has been in an intermediate threshold voltage distribution B and its upper page data is to remain 1 ', the memory cell is programmed to final state B. If the memory cell is within an intermediate threshold voltage distribution B and its upper page data is to become a material ’ ', the threshold voltage of the memory cell is raised to be within the range for state c. The procedure shown in Figures 8A through 8C reduces the effect of floating gate coupling because only the top page stylization of adjacent memory cells affects the apparent threshold voltage of a given memory cell. An alternative state for this technique = the code example is moved from the middle (four) B to the center C at the upper page data system 1 and to the state B when the upper page is negative. Although Figures 8-8 through 8C provide examples of four data states and two data pages, the concepts can be applied to embodiments with more or less than four states and different page counts.

4 You are one of the master or verification programs that iterate during the various ## acts. Q I Ding is the iteration of the program of Fig. 9 for the use of each of the δ ** recalls. If the memory cells are binary memory cells, the order of the interface y can be performed once. If the memory is a multi-state memory cell and θ + has four states (such as Ε, A, Β, and C), then the program of Figure 9 can be executed three times for each memory mask ( Three senses are staying). In general, during the read failure ^ ^ ^ ^ and the verify operation, the selected word line is connected to a read reference voltage, / 卞 ^ ^ ιν . ^ , a standard is specified for each read and Verify the knowledge, so as to decipher the relevant record 一 w ~ one body 7 临 one of the threshold voltage has reached 124907.doc • 25 - 200822119 This level. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the voltage applied to the word line is turned on to turn on the memory cell. If the measured conduction current is greater than a particular value, it is assumed that the memory cell is turned "on" and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the measured conduction current is not greater than the specific value, it is assumed that the memory cell is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured based on the rate of discharge of a dedicated capacitor in the sense amplifier. In another example, the conduction current of the selected memory cell allows (or is not allowed to) the NAND string release bit line charge including the memory cell. The charge on the bit line is measured after a period of time to see if it has been discharged. Figure 9 shows signals SGD, WL_unsel, WLn+1, WLn, SGS, Selected BL, BLCLAMP and Source starting at Vss (about 0 volts). The SGD system selects the gate selection line of the gate on the drain side. The source side of the SGS system selects the gate selection line of the gate. WLn is selected for the word line for reading/verification. WLn+ is tied to the unselected word line of the adjacent word line on the drain side of WLn. WL_unsel indicates other unselected word lines except the adjacent word line on the non-polar side. Selected BL is the bit line selected for reading/verification. Source is used for the source lines of these memory cells (see Figure 3). BLCLAMP is an analog signal that sets the value of the bit line when charging from the sense amplification. It should be noted that two forms of SGS, Selected BL, and BLCLAMP are described. A set of these signals SGS (B), Selected BL (B), and BLCLAMP (B) 124907.doc -26- 200822119 describes a read/verify operation for a memory cell array by determining bit lines Whether it has been discharged to measure the conduction current of a memory cell. Another set of these signals SGS (C), Selected BL (C), and BLCLAMP (C) are described for one read/verify operation of a memory cell array that is discharged by a dedicated capacitor within the sense amplifier. Rate to measure the conduction current of a memory cell. First, the behavior of the sensing circuits and memory cell arrays will be discussed with respect to SGS (B), Selected BL (B), and BLCLAMP (B). The sensing circuits and memory cell arrays are related to determining bit bits. Whether the line has been discharged to measure the conduction current of a memory cell. At time t1 of Figure 9, the SGD is raised to Vdd (e.g., about 3.5 volts), and the unselected word lines (WL-unsel) are raised to Vread (e.g., about 5.5 volts), the drain side phase The adjacent word line (WLn+Ι) is raised to VreadX, and the selected word line WLn is raised to Vcgr (eg, Vra, Vrb or Vrc of FIGS. 6, 7, and 8A to 8C) for a read operation or a The verify level (eg, Vva, Vvb, or Vvc of Figure 11) is used for a verify operation, and BLCLAMP (B) is boosted to a precharge voltage to precharge the selected bit line Selected BL (B) (eg, to approximately 0.7 V). The voltages Vread and VreadX are used as the transfer voltage because they cause the unselected memory cells to be turned on (regardless of physical state or threshold voltage) and used as a transfer gate. At time t2, BLCLAMP (B) is reduced to Vss, so the NAND string can control the bit line. Also at time t2, the source side selection gate is turned on by raising SGS (B) to Vdd. This provides a path to consume the charge on the bit line. If the threshold voltage of the memory cell selected for reading is greater than Vcgr or the verify level applied to the selected word line WLn, the selected memory 124907.doc -27-200822119 body unit will not be turned on and the bit line Will not discharge, as shown by signal line 26〇. If the threshold voltage of the memory cell selected for reading is less than or less than the verify level applied to the selected word line WLn, the memory cell selected for reading is turned on (conducted) and the bit is turned on. The line voltage is consumed as indicated by signal line 262. After time 12 and at some point prior to time ( (as determined by the particular implementation), the sense amplifier will determine if the bit line has consumed a sufficient amount. Between 12 and 13, BLCLAMp (b) is raised to cause the sense amplifier to measure the evaluated BL voltage and then decrease. At time t3, the signals shown will be reduced to Vss (or another value for standby or recovery). It should be noted that in other embodiments, the timing of certain apostrophes of the signals may be changed (e.g., the signal applied to the neighbors by the offset).

Next, the behavior of the sensing circuits and memory cell arrays will be discussed with respect to SGS (C), Selected BL (C), and BLCLAMP (C), which are measured by the rate at which a dedicated capacitor charge in the sense amplifier is released. The conduction current of a memory cell. At time t1 of Figure 9, the SGD is raised to Vdd (e.g., about 3.5 volts), the unselected word lines (WL - two rises to Vread (e.g., about 5.5 volts), the bucker side adjacent words The line (WLn+Ι) is raised to Vreadx, and the selected word line WLn is raised to Vcgr (eg, 乂^, Vrb, or Vrc) for a read operation or a verify level (eg, 11 of Vva, Vvb or Vvc) is used for a verify operation 'and raises BLCLAMP (C). In this case, the sense amplifier keeps the bit line voltage constant, regardless of the ongoing operation of the NAND string, so the sense The amplifier measures the current being flowed while the bit line is "clamped" to this voltage. Therefore, BLCLAMP (C) rises at tl and does not change from t1 to t3 to 124907.doc -28- 200822119. After time t1 and At some point prior to time t3 (determined by the particular implementation), the S-sampling amplifier will determine if the capacitor in the sense amplifier has consumed a sufficient amount. At time 13, the signals shown will Reduce to Vss (or another value for standby or recovery). It should be noted that in other specific embodiments The timing of certain signals of the signals may be changed. Figure 10 illustrates the use of non-volatile memory cells (such as those memory cells programmed according to Figures 6, .7 or 8A through 8C). A flow chart of one of the specific embodiments of the reading data. Figure 10 provides a reading program at the system level. In step 3〇0', a request to read data is received. In step 302, the response should be read. Request for data, performing a read operation for a particular page. In a specific embodiment, when staging a page of material, the system will also generate additional bits for error correction code (ECC) along with the The data pages are written together with the ECC bits. ECC techniques are well known in the art. The ECC programs used may include any suitable ecc program as is known in the art. At step 3〇4, the Ecc bits are used to determine if there is any error in the data. The ECC program can be executed by the controller, the state machine, or elsewhere in the system. If there is any error, then in step 3〇6, to the user If the error is found in step 304, then in step 3〇8, it is determined whether the error is correctable. The error may be caused by floating gate to floating pole face or other reasons. Various ECC methods have the ability to correct The number of _ in the group data is incorrect. If the ECC program can correct the data, then in step 31, the ECC program is used to correct the material and in step 312, the user is notified that the corrected mc program cannot be corrected. For this information, a data recovery procedure is performed at 124907.doc -29- 200822119 314. In some embodiments, an ECC procedure is performed after step 314. More details on the data recovery procedure are explained below. After the data is restored, the data is reported at step 316. At step 318, if an additional page is to be read or terminated at step 32, the program loops back to step 302. It should be noted that the procedure of Figure 15 can be used with data that is stylized using all-bit threading or odd/even bit threading. Figure 11 is a flow chart showing one embodiment of a program for performing a one-page read operation (step 302 of Figure 10). The program of Figure 可执行 can be executed for one page, which includes all bit lines of one block, odd bit lines of only one block, even bit lines of only one block or other bits of one block A subset of meta lines. At step 340, the read reference voltage Vra is applied to the appropriate word line associated with the page. At step 342, the bit lines associated with the page are sensed to determine whether the addressed memory cells are turned "on" based on applying Vra to their control gates. The conductive bit lines indicate that the memory cells are turned on; therefore, the threshold voltage of the memory cells is lower than Vra (e.g., in state E). At step 344, the results of the sensing for the bit lines are stored in appropriate latches (e.g., latches 2〇2) for the bit lines. At step 346, the read reference voltage Vrb is applied to the word line associated with the page being read. At step 348, the bit line is sensed as described above. At step 35, the results are stored in appropriate latches for the bit lines. At step 352, the read reference voltage Vrc is applied to the word lines associated with the page. At step 354, the bit lines are sensed to determine which memory cells are turned "on" as described above. At step 356, the result of the sensing step is stored in 124907.doc • 30-200822119 for the appropriate latch of the bit line. At step 358, the data values for the individual lines are determined. For example, if a memory cell is conducted at Vra, the memory cell is in state E. If a memory cell is conducted at Vrb and Vrc instead of at Vra, the memory cell is in state a. If the memory unit is conducted at Vrc rather than at Vra and Vrb, then the memory is in the early B. The right memory unit is not conducting under Vra, Vrb or Vrc, and the memory unit is in state C. In a specific embodiment, the data values are determined by processor 212. At step 360, processor 22 stores the decision data values in appropriate latches (e.g., 'latch 2 14') for each bit line. In other embodiments, the various levels (Vra, Vrb, and Vrc) may be sensed in different orders. Steps 340 through 344 may include performing the operations illustrated in Figure 9 at Vcgr = Vra and VreadX = Vread. Steps 346 to 350 may be included in Vcgr=Vrba

Under VreadX=Vread, the operation shown in FIG. 9 is performed. Steps 352 through 356 may include performing the operations shown in Fig. 9 at Vcgr = Vrc and VreadX = Vread. The floating gate lag during the capture operation may cause an error. Because of the electric field coupling associated with the charge stored in a floating gate or other charge storage region (e.g., a dielectric charge storage region) of an adjacent memory cell, the charge stored on the floating gate of a memory cell may experience An apparent shift. Although theoretically the electric field from the charge on the oceanic gate of any memory cell in a memory array can be coupled to the floating gate of any other semaphore cell in the array, the effect is for adjacent memory cells. More prominent and significant. Adjacent memory cells may include adjacent 124907.doc -31 - 200822119 memory cells on the same bit line, adjacent memory cells on the same word line, or both adjacent bit lines and adjacent word lines Thus in a pair of adjacent memory cells adjacent to each other in the green direction. This apparent charge shift may cause an error when reading the memory state of the 一 愔 一 田 田 田 〇 〇 隐 隐 隐 。 。 。 。 。 。 。 。 。 。 。 。 。

The effect of the floating gate coupling is extremely prominent in the case of staging the memory cell adjacent to the target memory cell, but the effect can be seen in other situations. The portion of the charge or the charge placed on the floating gate of the adjacent memory cell will be effectively coupled to the target memory cell through the electric field coupling, thereby causing one of the threshold voltages of the target memory cell. Observed offset. After stylization, the apparent threshold voltage of a memory cell can be shifted to such an extent that a read reference voltage is applied as desired for a memory cell in a memory state in which it was desired to be programmed. Next, it will not turn on and off (conducted). In general, a multi-column memory cell is programmed from a word line (WL 〇) that selects a gate line adjacent to the source side. Subsequent to the string of words, the word lines (WL1, WL2, WL3, etc.) are sequentially programmed to complete the stylization of the preceding word lines (WLn) (the units of the word lines are placed in their final state) After that, at least one data page is programmed in an adjacent word line (WLn+Ι). This stylized pattern causes an apparent shift in the threshold voltage of one of the memory cells after stylization due to the floating gate coupling. For each word line to be programmed except for the last word line of a NAND string, an adjacent word line is programmed after completion of the stylization of the word line of interest. The negative charge of the floating gate of the memory cell added to the adjacent, later stylized word line increases the apparent threshold voltage of the memory cell on the word line of interest. 124907.doc -32- 200822119 Figure 12 graphically illustrates the concept of floating gate to floating gate coupling. Figure 12 depicts adjacent floating gates 372 and 374 that are tied to the same NAND string. Floating gates 372 and 374 are located above NAND channel/substrate 376 having source/drain regions 3 78, 3 80 and 382. Above the floating closed-end Γ Ο 3 72 is a control gate 3 84 to which it is connected and a partial word line WLn. Above the floating gate 374 is a control gate 386 to which it is connected and a portion of the word line WLn+1. Although floating gate 372 may be affected by coupling from a plurality of other floating gates, for simplicity, Figure 12 only shows the effect from an adjacent memory cell. Figure 12 shows three coupling components that are supplied from the neighboring floating gate 372 to the floating gate: 1«1, 1>2 and (^. Component "1 series adjacent floating gates (372 and 374) The coupling ratio between the two is calculated as the sum of the capacitances of the adjacent juice gates divided by the sum of all capacitive couplings of the floating gate 327 to all other electrodes around it. Component r2 is the floating gate 372 and the drain The coupling ratio between the side adjacent control gates 386 is calculated as the sum of the capacitance of the floating gate 372 and the control gate 386 divided by the capacitive sum of the floating gate 327 to all other electrodes around it. The heart system controls the gate face ratio and is calculated as the sum of the capacitance between the floating gate 374 and its corresponding control gate (10) divided by the sum of all capacitive faces of the floating gate 372 to all other electrodes around it. The apparent threshold voltage distribution of the column of memory cells before (real curve) and after (dummy curve) of a column of memory cells (eg, 'WLn). Negative charge to the floating of the memory cells of adjacent word lines The gate is widened. Because the floating gate is combined with the negative charge of a post-Jesus stylized memory cell on Dezhou, 124907.doc • 33 - 200822119 is raised on WLn connected to the same bit line. Apparent threshold voltages for a memory cell. Distributions 400 and 402 represent cells of a selected word line WLn in state A before and after staging adjacent word lines WLn+1, respectively. Distributions 404 and 406 represent The unit of WLn in state B before and after stylizing WLn+1. Distributions 408 and 41〇 represent the units of WLn in state C after stylized WLn+Ι, respectively, because the distribution is widened, It is possible to erroneously read the memory cells in an adjacent state. The dsian cells on each of the distributions may have an apparent threshold voltage above a corresponding read comparison point. For example, when a reference voltage is applied At Vrb, a particular memory cell that is programmed to state A may not be sufficiently conductive due to its apparent threshold voltage offset. These cells may be erroneously read as being in state B, causing a read error. Post-stylized units can also affect the connection Apparent threshold voltages of memory cells connected to WLn of different bit lines, such as those connected to adjacent bit lines. Figure 14 graphical depiction can be used to solve some of the tables shown in Figure π One of the techniques for reading the threshold voltage offset. Figure 15 is a flow chart illustrating the technique. When reading data on the word line WLn, the data of the word line WLn+1 is also read (step 420). And if the data on the word line WLn+Ι has interfered with the data on the WL, the reading procedure for WLn can compensate for the interference. For example, when the word line WLn is read, the word line WLn+Ι can be determined. The state or charge level information of the memory cells to select an appropriate read reference voltage for reading individual memory cells of word line WLn. The program of Figure 11 can be used to read WLn+Ι. Figure 14 depicts an individual read reference voltage for reading WLn based on the state of an adjacent memory cell at word line WLn+1. In general, use 124907.doc -34- 200822119 to read the different offsets of the reference voltages Vra, Vrb, and Vrc (for example, 〇V, 0·1 V, 〇·2 V, 0.3 V) and The result of the sensing at different offsets is selected as a function of the state of one of the memory cells on an adjacent word line. In one embodiment, the memory at word line WLn is sensed using respective read reference voltages (including offsets) of the different read reference voltages. For a given memory cell, the sensing result of one of the read reference voltages can be selected based on the state of the adjacent memory cell at the word line WLn+1. In some embodiments, the read operation for WLn+1 determines the actual data stored at WLn+1, while in other embodiments, the read operation for WLn+1 determines only those units. The level of charge, which may or may not accurately reflect the data stored at WLn+丨. In some embodiments, the number of levels and/or levels used to read WLn+1 may not be exactly the same as the number of levels and/or levels used to read WLn. In some embodiments, an approximation of the floating gate threshold may be sufficient for WLn correction purposes. In a particular embodiment, the read result at run +1 can be stored in latch 214 at each bit line for use in reading WLn (step 422). A read operation may first be performed for the word line of interest WLn at the nominal read reference voltage levels vra, Vrb, and Vrc that do not compensate for any coupling effects (step 424). The read results at the nominal reference levels are stored in appropriate latches for the bit lines used to previously determine the memory cells of the adjacent cells in state E at WLn+1 (step 426). For other bit lines, ignore the data and maintain the WLn+i data. At step 428, a read operation is then performed for the word line WLn using the first set of offsets of one of the reference voltages, 124907.doc - 35 - 200822119. The reader can use + 0·1 v) ' Wbi + (U v) and Vrcl (Vrc + 01 V) in the program of Figure u. In the step Ο

430. The result of using the reference values is a bit line stored in a memory cell having adjacent memory cells at WLn+Ι in state A. Ignore data for other bit lines. Then use the read reference level Vra2 (Vra + 0·2 V), Vrb2 (Vrb + 〇2 ” and force ^ (Vrc + 0·2 V) in the program of the figure, in a second set of offsets. A read operation is performed at step 432. At step 434, the results are stored in a latch for a bit line of a memory cell having a neighbor at a state of WLn+丨. For other bit lines, in step 436, the reference levels Vra3 (Vra + 〇.3 v), Vrb3 (Vrb + 〇3 ^ and 13〇^ + ().3¥) are used in the program of Figure u. At the third set of offsets, an execution-read operation is used for the word line WLn. At step 438, the results are stored for the memory cell of the adjacent cell of WLn+Ι in state c. Equipotential lines. In some embodiments, no offset is used at Vra, and ^ is a larger natural boundary between state E and state A. Such a specific embodiment is shown in Figure 14. '纟中单-read reference voltage^ is described in state A. Other embodiments may also use offsets for this level. This procedure can be used to recover data (eg, Step 314) of Figure 1Q or as an initial read procedure (e.g., step 3〇2). The different offsets of the nominal read reference voltages may be selected as the state of the memory cells on adjacent word lines. a function. For example, the _ group offset value may include a -0 V offset, which corresponds to a neighboring order 124907.doc -36 - 200822119 yuan in state E, a 0. 1 V offset, It corresponds to an adjacent cell in state A, a 0.2 V offset, which corresponds to an adjacent cell in state B, and a 〇·3 V offset, which corresponds to state c. An adjacent unit. The offset values will vary depending on the implementation. In a specific embodiment, the #offset value is equal to the table resulting from the stylization to the corresponding state of the adjacent unit. The number of threshold voltage offsets. For example, 〇·3 V can represent the apparent threshold voltage of a unit at WLn when a neighboring unit of WLn+1 is programmed to state c after WLn is programmed. Offset. The offset values need not be the same for each reference voltage. For example, the offset values for the Vrb reference voltage can be The system 〇V, Ο"ν, 〇·2 乂 and 〇3 V, and the offsets for the Vrc reference voltage may be 〇ν, 〇15 ν, 〇·25 ν, and 〇·35 V. The offset increments are not necessarily the same for each state. For example, a set of offsets in a particular embodiment may include 〇V, 〇.i V, 0·3 V, and 0.4 V for respectively. In the state E, a, adjacent cells. Another technique for compensating for the floating gate coupling effect provides compensation to one of the adjacent memory cells of a selected memory cell in order to reduce the adjacent memory cell The coupling effect on the selected memory cell. One such specific embodiment includes setting the conditions required to apply compensation to adjacent memory cells later during the verification procedure. In such embodiments, the pass voltage applied to WLn+1 (also referred to as Vread) is reduced from a typical value (e.g., 6 V) that interacts in a selected word line to, for example, 3 V. The voltage used during the verify phase of the stylization/verification operation is compared, which is composed of applying a higher voltage to WLn+1 during a read operation performed on WLn. The compensation can include a change/difference. AVread = {[Vread (WLn+1 in WLn read period 124907.doc -37-200822119)] - [Vread (WLn+l during WLn verification)]}. The advantage of using a lower Vread value during verification is to allow the nominal Vread value to be applied later during the read operation while maintaining the desired AVread. If a value less than the nominal Vread value is used during verification, the necessary value of Vread during the read that is allowed to apply sufficient ΔVread will not be (for example) 6 + 3 = 9 V, which would cause a possible read. Take the larger voltage of the interference condition. An example of such a later compensation setting is depicted in Figure 9 as applying VreadX to the drain side adjacent word line while other unselected word lines receive Vread. In many prior art devices, all unselected word lines receive Vread. In the particular embodiment of Figure 9, except for the drain side neighbors, all unselected word lines will receive Vread while the non-polar side neighbors receive VreadX. For the verification procedure of staging the memory cell from the source side to the drain side, it is guaranteed that all memory cells on the word line WLn+1 are erased when writing the word line WLn (eg, state E) ) (Note: This is true for the complete sequence, but not true for the LM mode. See above for explanation). Word line WLn+1 will receive a voltage level VreadX, where VreadX = Vread4 (as described below). In one embodiment, Vread4 is equal to 3.7 volts. In another embodiment, VreadX = Vread. Other values may also be used in other embodiments. In various embodiments, different Vread4 or VreadX values can be determined based on device characteristics, experiments, and/or simulations. In a specific embodiment, the amount of AVread required to be compensated can be calculated as follows: 124907.doc -38- 200822119 l^Vread - {/^VTn +1)-^—— 1+(rl)(Cr) where AVTn +l is the threshold voltage change of the memory cell of the left-side neighbor between the stylized/verified time of WLn and the current time. AVTn+l and r 1 are the root causes of the parasitic consumption of the word line to word line reduced by the method. AVread is used to compensate for this effect. Figure 16 illustrates a flow diagram of one embodiment of a procedure for performing an initial read operation (step 302) or restoring data (step 3 14) using the techniques described above. The procedure shown in Figure 16 applies to the complete sequence stylization described above with respect to Figure 11, in which the two-bit system of a logical page is stored in each unit and will be read and reported together. At step 450, a read operation for the adjacent word line WLn+1 is performed. This may include the procedure of Figure 11 for adjacent word lines. At step 452, the results are stored in the appropriate latches. At step 454, a read procedure is performed for the word line of interest WLn. This can be done using VreadX = Vreadl (Figure 9) to perform the procedure of Figure 11. In a specific embodiment, Vreadl = Vread. Thus, all unselected word lines (see WL-unsel and WLn+Ι in Figure 9) receive Vread. This provides maximum compensation since the compensation is due to the difference between the Vread value currently used on WLn+Ι during the read operation and the Vread value used earlier during the verification phase of the stylization/verification. Decide. The compensation value compC can be defined as follows·· compC=Vread 1 -Vreadp=5.5-3=2.5 v, where Vreadp is the Vread value used during stylization/verification. The results of step 454 are stored in step 456 as appropriate latches 124907.doc -39. 200822119 which were previously determined to be in the bit line of the memory cell of WLn+Ι neighboring cell in state C (at step 450). Inside. Therefore, the maximum compensation CompC is used for the unit whose neighboring side neighbors experience the highest threshold voltage change due to staging from state E to state C. It should be noted that the bungee-side neighbors were in state E before the stylization/verification period of WLn, but are now in state C. In all cases, the required compensation is the state change of the neighboring side of the WLn+Ι on the WLn+Ι between the WLn write time and the WLn current read time. For other bungee-side neighbors, the bit line in state C is not currently detected, and the data read by WLn is ignored. The WLn reads Vreadl used on WLn+Ι. At step 458, a read program is executed for WLn at the drain side neighbor word line WLn+1 receiving Vread2 (VreadX = Vread2); wherein Vreadl is compared, the Vread2 value is closer to the Vreadp used during the stylized verification. . Delivery is suitable for smaller compensation of the bungee side neighbors now in state B. An example of compensation is compB=Vread2-Vreadp=4.9-3 = 1.9 V. Thus, Vread2 differs from Vreadp by compB. At step 460, the results of step 458 are stored for bit lines of memory cells having adjacent memory cells at WLn+Ι in state B. Ignore data for other bit lines. At step 462, a read procedure is performed for WLn in the case where word line WLn+1 receives Vread3. (VreadX=Vread3), where Vread2 is compared, Vread3 is closer in value to Vreadp used during stylization. The delivery is suitable for the bungee side neighbors now having a smaller compensation amount in one of the states A. An example of a compensation amount is compA=Vread3-Vreadp = 4.3-3 = 1.3 V. Thus, Vread3 differs from Vreadp by compA. At step 464, the results of step 462 are stored for the bit line of the memory cell having the adjacent § 彳 彳 body unit at WLn+1 124907.doc -40 - 200822119 in state A. Ignore data for other bit lines. At step 466, a read routine is executed for WLn, while word line WLn+Ι receives Vread4 (Vreadx = Vread4), where ν Γ 4 is equal to the Vreadp value used during the characterization. This does not deliver any compensation for units that are now in the state E of the pole side neighbors, since they are tied to the programming/verification time. The number of compensations is 〇 = 〇 · 0 V. At step 468, the results of step 466 are stored for the bit lines of the memory cells having adjacent memory cells at WLn+1 in state E. Ignore data for other bit lines. In the procedure of Figure 16, the adjacent bit line will receive four voltages. However, each selected memory cell of the WLn in the read uses or selects the result only when sensing at an appropriate voltage corresponding to its state at the adjacent cell at WLn+丨. In various embodiments, the values of different VreacU, Vread2, Vread3, and Vread4 can be determined based on device characteristics, experiments, and/or simulations. For more information on the technology of the figure, please refer to U.S. Patent Application Serial No. 1 1/384,057 to Nima Mokhlesi, entitled "Reading Operation with Non-Volatile Storage for Face Compensation", all of which The content is incorporated herein by reference. In a typical operation involving accessing a non-volatile memory system, the host device will request multiple pages of data that may span multiple word lines. Traditionally, memory systems have been used to Stylize to the same order of multiple memory word lines to read the data lines such as the edge of the word line. The word line generally begins with the adjacent source side selects the word line of the interpole and ends with the word of the adjacent gate on the adjacent drain side. The line is stylized, but the reverse order can also be used. Returning to Figure 3, the physical area containing the early element connected to the word line wl〇 to 124907.doc -41- 200822119 WLi begins to program the scorpion line WL0. After the stylization of the word line WL0 is completed, a temple. After the body is completed, the stylization will proceed to the word lines WL1, WL2, etc., and σ is on the sub-line WLi. When receiving a request from this The physical block reads all the pounds have In the case of Bessie, the read operation will be the same as the stylized plug; the master will start at word line WL0 and then proceed sequentially until the word line WLi is reached. The description is based on the method of using the traditional technique of transmitting __V, eve An, upper urinary urinary use or eve compensation, the method of the physical (four) block-flow chart. In the example of Fig. 17, the consistent body block contains four The word lines are assumed to be stylized starting at word line (4) and converged on word line WL3. At step 5 〇〇 'a read operation is performed for word line wu. (4) No compensation is used when word line WL1 is taken, due to this read The fetch operation is only performed to obtain data or level bins that can be used to finer (d) the fetch line wL. In a specific embodiment, the word line and the read operation are performed according to the technique of FIG. After the reading is performed for the word line and the reading is performed, the results (data value or charge level information) are stored in step 502. In a specific embodiment, step 5〇2 corresponds to step 360 of Figure 1. After storing the result for the word line WL1, one or more compensations are used to read W in step 5〇4. L0. The f-values read from the WLG are stored in the appropriate data latch 214 at step 5. 6 after performing a read operation on the line WL0 and storing the data values in step 5. In step 5, /, the data from word line WL0 is reported to the host. In a specific embodiment, step 504 (and steps 514, 5 as follows may include performing several sub-reads at the selected word line. 524) Embodiment 124907.doc -42- 200822119 'In step 5G4 (5 14, 524) application - or multiple compensations comprising steps 424, 428, 432 and 436 corresponding to Figure 15, performing four sub-reads (each comprising three One sensing operation, assuming four state memory cells). In another embodiment, step 504 (514, 524) includes four sub-reads (each comprising three sensing operations) corresponding to steps 454, 458, 462, and 466 of FIG. unit). • In other embodiments, other techniques for applying one or more supplements may be used. For example, in some embodiments, a single sub-read can be used by applying a one-line specific compensation. Compared with the bit line|main compensation shown in FIGS. 15 and 16, one bit line specific compensation can be (4) address each memory unit, so that each memory unit is parallel to a common memory of a common word line in a read. The body unit receives its appropriate compensation at the same time. A set of conditions applies the word lines ' while the bit lines are set based on the state of adjacent memory cells of the bit line on adjacent word lines. In this way, a single sub-read can be used. For example, a trip point voltage for determining whether a single cell is conductive or non-conducting after applying a read reference voltage may be tailored for each bit based on the state of the WLn+Ι neighboring cell for the bit line. line. Other parameters such as integration time and pre-charge voltage can also be used to provide bit line specific compensation so that a single-sub-read can be utilized. In a specific embodiment, a combination of the various parameters can be used. At step 510, a read operation for one of word lines WL2 is performed. In a specific embodiment, step 510 can also include performing the read method illustrated in Figure n. No compensation is used when reading word line WL2, since this read operation is only performed to obtain information or charge 124907.doc -43- 200822119 level information that can be used to more accurately read word line wli. At step 512, the data value or the charge level information read from the word line is stored. In a specific embodiment, step 51 corresponds to step 660 of FIG. After storing the data values or charge level information for word line deselection 2, at step 514, one or more complement, reimbursement-read operations are performed for word line wu. The data values determined at step 516 are stored in the appropriate data latches in step 516 and reported to the host device in step 518.进行 Performing a read operation for word line machine 3 at step 52G', which may include performing the method of FIG. At step 522, the data value or charge level information is stored in the appropriate latch for word line WL3. A read operation is performed for word line WL2 at step m, which includes one or more compensations. The data values for the sub-line WL2 are stored in the appropriate data latches in step 526 and reported to the host device in step 528. At step 53A, a read operation is performed for the word line machine 3. In the example of Figure 17, the word line wu is used for the last stylized and sold word line of the memory system. Therefore, no compensation is used at the 纟 纟 word line WL3. The data values are stored in step 352 for word line WL3 and reported to the host at step 534. The conventional technique of reading in the (four) order of the (four) (four) word lines as shown in Fig. 17 must perform an additional read operation at the adjacent word lines when reading the selected word lines other than the last word line. For example, to read a word line machine, word line WL1 must first be read to determine its data state or charge level information to apply appropriate compensation when word line WL0 is read. Before step (4) ^ takes the line WL1 to obtain its actual data for the host to refer to, it must = line: for the read operation of the sub-line WL2. These additional read operations _, N plus may 124907.doc -44- 200822119 will affect system performance due to the requirement to complete the read operation for a longer time. Figure 18 is a table depicting the number of operations that must be sensed in such a memory system in some embodiments. In Figure 18, a 丨6 word line entity or erase block is described. The row 550 sequentially sorts out the word lines of the physical block, and the sub-line WL 15 at the top of the page, that is, the word line of the drain side selection gate of the adjacent physical block and the word line WL0 at the bottom of the page, that is, adjacent to The source side of the physical block selects the word line of the gate. The 程式 程式 stylized sequence of the memory cells for the word lines is depicted in row 552. Styling the physical block begins at word line WL0 and thereafter proceeds to word line WU5. The sequence for reading the physical data block is depicted in line 554. The word line wl 先 is read first, followed by the word line WL1, and then sequentially proceeds to the word line and 5. The line description explains what is necessary to perform each word line read operation. For example, to read word line WL0, the word line sum must be read first, as shown by line... After reading the word line sum to determine its data value or charge level information, the word line WL() is taken from the word line WL1 to apply - appropriate compensation (or result). 558 proposes the sensing operation and sub-reading necessary for each (5) fetch operation (4): the number 2 refers to the word line WL 〇 ' again, for example, the word line is read first (4) ^ ^ Stays (false one-four state memory unit ). Use the reference level vra to stick a ^, ^ ^ ^ first sensing operation, use the second reading spring test voltage level Vrb^ " a second two sensing operation and use the third read reference voltage level Vrc performs one-to-one 4^^. The first sensing action. The three sensing operations are included in a sub-green at the word line WL1. After the word line WL 1 is taken, the sorcerer line WL0 is read using the "sub-line WL 1> material to apply or select 124907.doc -45-200822119 at the appropriate compensation. result. The read word line WL0 involves 12 sensing operations 'which correspond to four sub-reads at the word line. A first sub-read includes three sensing operations at the levels Vra, vrb, and Vrc. A second sub-read includes three sensing operations at a read reference level Vra plus a first offset, Vrb plus a first offset, and Vrc plus a first offset. A third sub-read includes three sensing operations at a level Vra plus a second offset, Vrb plus a second offset, and Vrc plus a second offset. The four sub-reads will include three additional sensing operations at level Vra plus a third offset, Vrb plus a third offset, and Vrc plus a third offset. In a solution using the technique shown in FIG. 6, 'a different vread level can be applied to sense adjacent word lines when sensing the word line of interest. In such techniques, the first sub-read will be included in Three sense operations at word levels Vra, Vrb, and Vrc when word line WL1 receives Vreadl. A second sub-read will also include applying a read reference when word line WL1 will receive Vread2. The voltage levels Vra, Vrb, and Vrc. The third sub-read will include three sensing operations at the Vra, Vrb, and Vrc levels when word line WL1 receives Vread 3. Finally, the fourth sub-read It will also be included to apply the read reference voltage levels yra, Vrb and Vrc to the word line WL0 when the sub-line WL1 receives Vread 4. As can be seen in general, in order to read the word lines of the physical block, a total of 15 senses must be used. Operation. This point is for each word line of the block except the last word line of the block to be read. Figure 8 presents the total number of sensing operations in block 6丨〇. It can be seen that 'in order to utilize Figure 5 Or one of the compensation schemes of 丨6 to read a 16-word line physical block, a total of 228 sensing operations must be used. If a single sub-read at the word line of interest is used, the bit line is specifically supplemented with 124907.doc -46- 200822119 compensates, the number of sensing operations can be reduced, but when reading a selected word line, the reading will include additional reads for adjacent sub-lines. Looking at word line WL0 again, still executing Read word line WL1, but reading WL0 will only include i sub-reads (3 sensing operations). When reading all 16 word lines The total number of sensing operations will be 93, as shown in Figure 18. Ο 寻求 In accordance with a specific embodiment of the present disclosure, it is sought to reduce the number of sensing operations for read operations across multiple word lines, such as responding to a slave A physical or erased block requires a read operation of the request for data. Figure 19 is a cross-reading technique similar to the one shown in the figure - a specific example of the reverse reading technique. The series is in line 570. The stylized sequence begins at word line WL0 and ends at and 5, as shown in line 572. 574 proposes a sequence of items that begins at the word line and ends at word line k. The manner in which the word lines are kissed to complete the read sequence 574 is within line 576. Each word line of the material word line is selected (4) for reading 2' without having to read any other word lines to complete a compensation technique. It is known that the results of the application, selection-appropriate reading compensation are used to select the word line two =: line? News. By reverse reading, it can be taken from the word line that has been bound by only 5 贝. For example, when the 16th sub-line of the sequence is used to avoid repeated reading of WL0 for reading, the word line can be selected during ##. This is performed in line 556 of Figure 18. The WL1 read operation of the line crane, must technology, in order to read the word line WL1 read. ', the receiver at - later time repeated in the line 5 7 8 proposed, 丨 4 (four) for the number. When the word line WL15 is read, 124907.doc -47· 200822119 Ο 仃 performs one sub-reading and three sensing operations, since WL15 does not have any later stylized neighbors. Then reads the word line buttocks It is known that the data read from the memory cells of the word line is then maintained (e.g., data latch 214) while the word line WL14 is being read. Therefore, 12 sense operations are required at word line WL14. The four sub-reads are all necessary to accurately read the word line. This is compared with Figure 18. 'Reading the word line in Figure 18 first requires reading WL15' and thus requires an extra sub-read and three Sensing operation. Block 580 presents the total number of sensing operations when using the technique of Figure 19. Comparing the requirements of 228' using the technique of Figure 18 183 sensing operations. Improved performance when reading a non-volatile memory system by reducing the number of sensing operations 攸 228 to 183 '. If a single sub-read at the word line of interest utilizes bits For the specific compensation of the line, the total number of sensing operations will be 48. Each word line will be read by one reading using three sensing operations. This will also provide an improvement over conventional techniques, which will sense The number of operations is reduced from Μ to %. The picture is called a complete sequence of ribs, upper and lower page stylization, and a read sequence of the unit programmed by the last priority mode (LM) stylization. Sensing operation and sub-reading The number may differ for upper and lower page reads or LM reads, but those skilled in the art will appreciate this. Although for the purposes of the demonstration, the complete sequence of stylized units is presented for most of the discussion, but this is not The inner valley is also applicable to other unit programs. = (d) A flow chart of a method for reading a physical memory unit block in reverse according to 1. For a demonstration purpose, a four-word line = sad memory, body System, but the technology disclosed is applicable For systems with other numbers of sub-wires and memory states. At step 6, read the last word line WL3 to be programmed for the entity 124907.doc -48 - 200822119 block. Because the last word line does not have A later programmed word line, no compensation is applied and the method of Figure u can be applied. The mosquito is used to say that the data values of 3 are stored in the latches of the corresponding bit lines (for example, locks) The data values are buffered at step 604 for later reporting to the host device, as described below. Using one or more compensations, a step is performed for word line WL2 at step 6〇6. The read operation '#° may be performed in a specific embodiment based on the data values determined for the word line WL3 at step _ (for example, FIG. 15 or 16) and selected (four) for each of the bit lines. Read the results as appropriate. Alternatively, one or more of the bits 70 can be applied for the main line compensation for each bit line and with a single sub-read. At step 608, the data from the appropriate sub-read or the data from the single sub-read when the bit line compensation is used is stored in the data latch of each bit line. In a particular embodiment, at step 6G8, the data values shared at step 6() 2 are replaced with the WL2 values. As shown in Figures 15 and _, it may be executed between or as part of the sub-reads at step 606. <at step 608. In a particular embodiment utilizing the technique of FIG. 15, steps 606 and 608 can include performing the steps of FIG. 15 to 438. In a particular embodiment utilizing the different Vread values shown in Figure η, steps 6〇6 and 6〇8 may include performing steps 454 through 468 of Figure 16. After the data values for word line WL2 are stored in the latches II, the data values are buffered at step 61. At step 612, a item fetch operation is performed for word line 1 using compensator read or bit line compensation. Since the word line WL2 is read in step 606, the word line WL3 is not required to be the word line WL2. The value stored in the latch of each π line in step 6〇8 can be used to select the appropriate read result or 124907.doc •49- 200822119 yoke plus appropriate bit line compensation. At step 614, the data values for the word lines are stored in the data latches. In a particular embodiment, the data stored in the latches in step 608 is overwritten. After storing the data values for the sub-line WL1, the data values are buffered at step 616. At step 618, a read operation is performed on word line WL0 using compensator read or bit line compensation. The data values for the memory cells at the word line are stored in the appropriate latches at step 62. At step ^ 622, the data values stored at step 620 are buffered. At step 624, the data buffered at steps 604, 610, 6 16 and 622 is reported to the host or requester device. Figure 21 is a flow diagram illustrating one method for reporting data to a host or requestor device, as performed at step 624 of Figure 20. At step 63, the data buffered at steps 604, 610, 616, and 622 is reordered. Reordering the data may include first placing data from the word line WL, followed by data from the word line WL1, data from the word line WL2, and finally from the word line (j WL3 data. The data is in step 604, 610, 616, and 622 stylize their opposite sequences for placement in the buffer. In general, the host device will expect data in a stylized order of the data. Thus, the data is reordered to conform to the stylized sequence. Step 632, reporting the data from the word line WL0 to the host device. In step 634, reporting the data from the word line WL1 to the host device. In step 636, reporting the data from the word line WL2 to the host device, and finally At step 638, the data from word line WL3 is reported to the host device. Buffering the data values and reporting them to the host may be according to an implementation. 124907.doc -50 - 200822119 'Under normalization, for example, can be read Each individual word line then reports data from each word line to the host. For example, after reading word line WL3 and storing the data value in the latches, the data can be immediately reported to the host. It may not be necessary to buffer the data values in step 604 in this embodiment. The host device will receive the data in the reverse stylized order and reorder the data if necessary. The memory location for buffering the data and The type may vary depending on the embodiment. In one embodiment, the data is buffered within a memory (e.g., RAM 13 1) (Fig. 4) within controller 144 or accessible to controller 144. The controller can reorder the data and report it to the host. In another embodiment, the data is buffered in a memory (such as RAM 133) or available to control circuitry 12 within control circuitry 12A. The control circuit or controller may reorder the data for delivery by the controller to the host. In some embodiments, buffering a large amount of data associated with a physical block may not be practical or desirable. Therefore, in one embodiment, the memory block is divided into read blocks to reduce the amount of data that needs to be buffered in the current time and thus the memory size used for buffering. The memory system can be reversed. Reading (d) the portion of the physical block (read block), buffering the data and reporting the data to the host device. The memory system can read a read block below the physical block when the data is reported. And buffering the data from the next read block in its location. If necessary, the program can be executed as much as possible until the entire physical block requested by the host device has been read and reported. According to different embodiments, The various sizes and manners of dividing the physical block into individual read blocks can be utilized. 124907.doc -51 - 200822119 Figure 22 illustrates a table utilizing one of the read blocks in accordance with an embodiment. Line physical blocks, but other sizes of physical blocks can be divided in a similar manner. The word lines listed from WL1 5 through WL0 in row 650 begin at word line WL0 and then sequentially proceed to word line WL15 for programming, as shown at line 652. The physical block of Figure 21 has been divided into four individual read blocks. The read block 1 includes word lines WL0, WL1, WL2, and WL3. The read block 2 includes word lines WL4, WL5, WL6, and WL7. The read block 3 includes word lines WL8, WL9, WL10, and WL11. The read block 4 includes word lines WL12, WL13, WL14, and WL15. More or fewer read blocks can also be used, including a different number of word lines. A sequence for reading the physical block is proposed in line 654. Upon receiving a request for a request for material (including the physical block), the memory system begins to read and report individual read blocks. The read sequence begins with reading word line WL3 within block 1. Word line WL3 is the last stylized for this read block. These individual operations for reading the selected word line are presented in line 656. In order to read the word line WL3, its adjacent drain side word line WL4 is read first. The actual data value or charge level information can be read from the units of word line W L 4 . When the word line WL4 is read, no compensation is utilized. A single sub-read and three sensing operations (assuming a four-state device) can be used as shown in row (4). After reading word line WL4, the read word line is lower by three. When using the word line compensation scheme of Figure 15 or 16, the read word line includes four sub-predicates and 12 sensing operations. The data values for each sub-read based on the state of the corresponding adjacent memory cells at word line 4 will be selected for the individual bit lines. An appropriate 124907.doc -52 - 200822119 bit line compensation can be alternatively applied in the specific embodiment. After reading word line WL3, the read sequence proceeds to word line WL2. The read word line WL2 includes only four sub-reads and one sensing operation. The performance of an additional read operation at word line WL3 is not required since the data from sub-line WL3 is known. After the word line WL2 is read, the read sequence proceeds to the word line WL1 and the word line WL〇. After reading the block i and buffering the data, the data can be reported to the host device. Reporting the data may include reordering the data to begin at word line WL and ending at WL3, as shown in FIG. Reading block 2 can be read after the data from the read block has been reported to the host device. In a specific embodiment, the read read block 2 can begin when the data from the read block 1 is being reported. The material from the read block 2 can replace the data from the read block 1 when it is reported from the buffer memory to the host. The read read block 2 begins with word line WL7, which includes a first read word line WL8 to determine the data value or charge level information that can be used when reading word line WL7. The remainder of the read read block 2 is as described with respect to read block 1, buffering the data from each word line. The data from word line WL4 can be started, followed by word line WL5, followed by word line WL6, and last word line WL7, reordering the data and reporting it to the host. After reading from the read block 2 and reporting the data, the memory system will begin reading data from the read block 3 at word line WL11, as shown in line 654. Reading word line WL11 will include the first read word line WL12w applying a compensation when reading WL11, as shown by row 656. After the word line WL11 is read based on the data from the word line and the appropriate values are selected, the data is buffered in the memory system. The reading proceeds to word lines WL10, WL9 and WL8 in a manner similar to that already described, followed by 124907.doc -53-200822119. The memory system will begin at word line WL8 and end at word line WL11 to reorder the data and report this information to the host device. After reading the read block 3, the memory system continues to read the read block 4. ΊBuy Ί buy block 4 begins on the sub-line WL1 5 ’ as done in line 654. Since the word line WL15 is the last stylized person, it is not necessary to read any other word lines. After reading word line WL15, the data from WL15 is used to read word line WL 14 to apply an appropriate compensation. After reading and buffering the data from the word lines of the remaining word lines ^ 1 of the read block 4, the word line WL12 can be started and terminated at the word line WL15 to reorder the data and report it to the host device. The read block partitioning of Figure 22 utilizes a total of 192 sensing operations when using a word line compensation scheme, as shown at 660. If a one-line compensation scheme is used, 57 sensing operations are used. As can be seen by looking at Figure 18, the read block technique of Figure 22 provides a smaller number of sensing operations while maintaining the required buffer memory size reduction. Q Figure 23 is a flow chart showing a method of reading non-volatile memory in a reverse manner using individual read blocks. The embodiment of Figure 23 is presented with exemplary conditions for four read blocks, as previously shown in Figure 22. However, other implementations may include different numbers of read blocks. Performing a read operation on the first word line of the 'reading' two read block. The first word line pointer refers to the first word line to be programmed for the second read block, and FIG. 〇 will include reading the word line muscle 4. The δ buy # at step 7^00 does not include any compensator reading (or bit line complement) because the ° item is used for the purpose of the system. Information used in reading the source side phase 124907.doc -54 - 200822119 adjacent word line. In step 702, the data value (or charge level information) for reading the first word line of block 2 will be used. Stored in the data latches. At step 704, a reverse is performed for the first read block

读取 Read. Reversing the first read block will include first reading the last word line of the first read block based on the first word line of the second read block. The bit lines of the last word line will store data from the appropriate sub-reads based on information determined from reading the first word line of the second read block. After reading the last word line of the first read block, the first to last word lines of the first read block are read and based on the previous read of the last word line of the first read # block To select this data value. This will continue until the first word line of the first read block to be programmed is read. Referring again to Figure 22, step 7G4 will include reading word line WL3, followed by word line hunger 2, then word line WL1 and last word line WL 〇 at step 706, the memory system will buffer read from the first read Block information. In a particular embodiment, the buffering will include buffering the data from the respective word lines of the first read block after step 704 has been read. After buffering the data and reading the word lines of the first read block, the memory system will reorder the data to correspond to the order in which the data is programmed into the read block. Referring again to Figure 22, this will include reordering the data to begin with data from word line WL0 and ending with data from the word line. After the data has been reordered in steps, the memory system reports the first read data to the host device in step 7〇8. At step 710, a read operation is performed for the first word line of the third read block. Referring again to Figure 22, step 71G will include reading the word line WL8 of the read block 3 124907.doc -55 - 200822119. The read operation for reading the first word line of block 3 does not include compensation. At step 712, the data values read from the first word line of the read block 3 are stored in the latches. At step 7丨4, a reverse read operation for one of the second read blocks is performed. This reverse read operation will first include reading the last word line of the read block using the compensation based on the information determined by reading the first word line of the read block 3 at step 710. Referring again to FIG. 22 'Execution step 714 may include reading word line WL7 (using data from WL8), followed by word line WL6 (using data from WL9), word line WL5 (using data from WL6), and last word line WL4 (Use data from WL5). At step 716, the data from the reverse read read block 2 is buffered. Also buffering the data may include buffering the data after reading the respective word lines of the read block 2. After the word lines have been read and the data has been buffered, the tenth system will also reorder the data of the read block 2 in step 71. After reordering the data, the data is reported to the host device at step 718. Referring again to Figure 22, step 718 can include reporting data from word line WL4, followed by data from word line WL5, followed by information from word line and ending with data from word line WL7. At step 720, a read operation for the first word line of the fourth read block is performed. Likewise, this can include reading word line WL12 as shown in the row for word line WL11 in FIG. In step 722, the data values for the first word line of the fourth read block are stored in the data latches. At step 724, a reverse read operation for one of the second getter blocks is performed as described for read blocks 1 and 2. This will include reading the last word line of the third read block to be stylized first. At step 726, the memory 124907.doc -56-200822119 Ο 系统 system will buffer and reorder the data in the order of the original stylized data. At step 728, the reordered material is reported to the host device. At step 730, a reverse read of one of the fourth read blocks is performed. Since the fourth read block is the last read block and includes the last word line to be privateized for the physical block, it is not necessary to read any word lines outside the read block 4. In the embodiment of Fig. 22, the reverse read read block 4 may include a read word line WL15 followed by a word line WL14 followed by a word line WLn and ending with a word line WL12. The data from the individual word lines are buffered at step 732. Also in step 732, the memory system will reorder the data to begin with data from word line WL12 and end with data from word line WL15. The reordering material is then reported to the host device at step 734. In a particular embodiment, the amount of privacy of the data requested from the host device is utilized in turn to determine whether to perform a reverse read operation and a degree of execution. Figure 24 depicts a specific embodiment utilizing two such thresholds. In the step, a request to read data is received from the host device. At step : 42' the memory system determines the size of the requested data. In step (4) 4, the memory system compares the size of the requested data with the _first-threshold value. If the requested data size is smaller than the first reverse read operation. Guhai host '"Bei factory,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,

The quick item takes the request data and provides it to the host device. The L 750 performs a standard read operation using compensation. The __ step will be implemented as shown in Fig. 15 or Fig. 16. For example, if the request data is large = step::5. The operation performed corresponds to a word line or smaller, then 124907.doc -57- 200822119 The memory system can read the appropriate adjacent word lines, as shown in step 420 of Figure 5 or step 450 of Figure 16. After reading the adjacent word line, the selected word line will be read using the compensator read, as shown in steps 422 through 43 8 of Figure 15 or steps 452 through 468 of Figure 15. Bit line compensation can also be used. If the size of the request data corresponds to more than one word line, the individual performance of Figures 15 and 16 can be used to read the plurality of word lines. If the size of the request data is greater than the first threshold, then at step 746, the memory system will compare the size of the request data with a second threshold. The second threshold size is greater than the first threshold. If the size of the requested lean material is greater than the first threshold, but less than the second threshold, then performing one of the one or more read blocks in step 752 to perform a reverse read operation, for example, in steps 752 performs a reverse read of one of the read blocks (eg, read block 1) containing the requested data. If the size of the request profile is greater than the second threshold, then a reverse read operation for one of the one or more physical blocks may be performed at step 748. Q can utilize various variations of the techniques disclosed in FIG. For example, if the request profile is not greater than the first threshold, then one of the at least one read block can be reverse read in all cases. The host can request this material later and read and buffer it to avoid post-fetch readings that may be more efficient. In this case, reading one or more read blocks in reverse at step 752 may always include reverse reading at least two read blocks. Another embodiment may utilize a single threshold. In this case, if the request data is smaller than a first threshold size, the memory system can perform the standard read operation shown in Figs. 15 and 16 without performing reverse reading. In another embodiment, if the request data is 124907.doc -58 - 200822119 at the first threshold value of 4, the memory system can start with the request word, and then continue in the opposite stylized direction. To the end of the physical block to reverse the 'body block only. Another option may include moving the right stem word line in the direction of the run before starting the reverse read. In the case of using a threshold, if the size of the bedding material is greater than the threshold value, the memory system can reversely read the corresponding physical block. The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The specific embodiments are chosen to best explain the principles of the invention and the embodiments of the embodiments of the invention The present invention is preferably utilized. It is intended that the scope of the invention be defined by the scope of the appended claims. [Simple diagram of the diagram] Figure 1 is a top view of a NAND string. 2 is an equivalent circuit diagram of one of the NAND strings of FIG. 1. Figure 3 is a block diagram of a NAND flash memory cell array. Figure 4 is a block diagram of a non-volatile memory system. Figure 5 is a block diagram of one embodiment of a sensing block. Figure 6 depicts a set of exemplary threshold voltage distributions and a complete sequence stylization program. Figure 7 depicts an exemplary set of threshold voltage distributions and an upper page/lower page programming procedure. Figures 8A through 8C depict a set of exemplary threshold voltages and a two-pass stylized program 124907.doc -59 - 200822119. Timing of a specific signal behavior Figure 9 is an explanation of the read/verify operation period. Figure 0 Figure 10 is a diagram for reading non-volatile memory. 〆 Flow of a Specific Embodiment FIG. 11 is a flow chart of a specific embodiment for performing a read operation for non-volatile memory. Ο Ο Figure 12 is a block diagram of (iv) the capacitance of two adjacent memory cells. Figure 13 is a set of exemplary threshold voltage distributions illustrating the effects of floating gates. Figure 14 illustrates an exemplary set of threshold voltage distributions for one of the techniques for compensating for floating gate coupling. Fig. 15 is a flow chart for compensating the floating gate using the technique of Fig. 14. Figure 16 is a flow diagram for compensating a floating gate handle using another technique. Figure 17 is a flow diagram illustrating one of the sequences of reading a set of memory cells using compensation in accordance with the prior art. Figure 18 illustrates a table for reading a set of memory cells using compensation in accordance with the prior art. Figure 19 illustrates a table for reading a set of memory cells using compensation in accordance with a particular implementation. Figure 20 is a flow diagram for reading a set of memories 124907.doc - 60 - 200822119 early using compensation in accordance with an embodiment. Figure 3 is a flow diagram for reporting data to a host in accordance with a specific embodiment. Figure 22 illustrates a table of reading a set of memory cells under compensation using a read block in accordance with an embodiment. Figure 23 is a flow diagram of one of the steps for reading a set of memory cells using a read block in accordance with one embodiment.

Figure 24 is a flow diagram for reading a set of memory cells using a threshold request data size. Ο [Main component symbol description] 10 Transistor/memory unit 10CG Control gate 10FG Floating gate 12 First selection gate / transistor / memory unit 12CG Control gate 12FG Floating gate 14 Transistor 14CG Control gate 14FG Floating Gate 16 Transistor 16CG Control Gate 16FG Floating Gate 20CG Control Gate 22 Second Select Gate 124907.doc • 61 _ 200822119 22CG Control Gate 26 Bit Line Terminal / 汲 Terminal 27 Bit Line 28 Source Line Terminal 29 Source Line 30 Block 50 NAND String 100 Two-Dimensional Memory Cell Array 1 110 Memory Device 112 Memory Die 120 Control Circuit 122 State Machine 124 On-Chip Address Decoder 126 Power Control Module 130 Α Read The fetch/write circuit is shy 130Β 读取 The read/write circuit 131 selects the RAM memory 132 line 133 selects the RAM memory 134 line/data bus 140 Α column decoder 140 Β column decoder 142 解码 row decoder 142 Β row decoder 124907. Doc -62- 200822119 144 Controller 200 Sensing Block 202 Bit Line Latch 204 Sensing Circuit 206 Poor Material Bus 208 Input Line 210 Sensing Module 212 Processor 214 Data Latch 216 I/O Interface 220 Common Part 250 Arrow 252 Arrow 254 Arrow 260 Signal Line 262 Signal Line 372 Adjacent Floating Gate 374 Adjacent Floating Gate 376 NAND Channel /Substrate 378 Source/Drain Region 380 Source/> and Polar Region 382 Source/Drain Region 384 Control Gate 386 Control Gate 124907.doc -63- 200822119 400 Distribution 402 Distribution 404 Distribution 406 Distribution 408 Distribution 410 Distribution 550 Line 552 Line 554 Line 556 Line 558 Line 560 Line/Box 570 Line 572 Line 574 Line 576 Line 578 Line 580 Box 650 Line 652 Line 654 Line 656 Line 658 Line 124907.doc -64-

Claims (1)

200822119 X. Patent application scope: 1. A method for operating non-volatile storage, comprising: starting with a first word line adjacent to a first group of selected closed poles and ending with a second group of selected gates The pole-final word line is programmed to fit into the non-volatile storage element of the complex word line. The stylization includes one of the latter to change the storage elements according to the status of the head «the status; and the power, ▲ Beginning at the last word line and ending at the first word line to read the non-volatile storage elements that face the plurality of word lines, the reading including for each word line except the last word line, Applying - or multiple compensations based on reading the word line adjacent to each of the word lines in the direction of one of the second set of select gates. Method of Mooncake 1 'where words other than the last word line a line, applying one or more compensations includes: reading the word line adjacent to the word lines in the direction of the second set of selection gates to perform a plurality of sub-reads for each of the storage elements of the word lines Select one of the results of one of these sub-reads. 3 The method of claim 2, wherein the performing a plurality of sub-reads for each word line other than the last word comprises: reading a reference voltage from the first group to the word lines and sensing the word lines The material elements are configured to perform - the first sub- and the 呗, by applying - the second set of reading reference voltages to the word lines and sensing the material-like materials of the sub-lines The method of claim 3, wherein the method of selecting one of the sub-reads comprises: selecting a result of the first sub-read for each of the Each of the word lines of the word line has a neighboring memory cell on the adjacent word line that is determined to be in a first physical state during the reading of the word line adjacent to the word line; Selecting a result of the second sub-read for each storage element of the word lines, the word lines having an adjacent memory cell at the adjacent word line in the adjacent adjacent word lines The word line period is determined to be in a second physical state. 5. The method of claim 2, wherein Performing a plurality of sub-reads on each of the word lines outside the last word line includes: applying a set of read reference voltages to the word lines, applying a first voltage to the word lines adjacent to the word lines, and Applying the set of read reference voltages and the first voltage to sense one of the storage elements of the word lines to perform a first sub-read; and hunting by applying the set of read reference voltages to the respective a word line, applying a second voltage to the word line adjacent to the word lines, and sensing one of the memory elements of the | word line when the set of read reference voltages and the k voltage are applied Performing a second sub-read. The method of claim 5, wherein selecting one of the sub-reads results comprises: selecting (four) the _ sub-reading - the result is for each storage element of the word lines 'The word lines have the adjacent memory cells in the adjacent word lines. The period of the adjacent memory cells is determined by the period of 124907.doc 200822119. a first physical state; selecting the second sub-reading - the result is for each storage element of the word lines The word lines having a word line in the adjacent - second physical state - adjacent memory cell is determined during which the word lines of the word line adjacent to the reading. 7. The method of claim 1, the volatile storage component one comprising: a portion of the non-memory devices coupled to the plurality of word lines, the method further beginning with non-volatile from coupling to the last word line The information of the storage element ends with data from the non-volatile storage element coupled to the first word line, and the data from the plurality of non-volatile storage elements is stored in the memory device. 8. The method of claim 7, further comprising: starting with a non-volatile storage element from the first word line And the information from the non-volatile storage elements coupled to the plurality of word lines is provided to the memory The method of claim 7, wherein: the non-volatile storage element coupled to the plurality of word lines is formed on one or more memory chips; and temporarily storing from the plurality of Information on the non-volatile storage element includes buffering the data at the one or more memory wafers. The method of claim 7, wherein the non-volatile storage elements of the plurality of word lines form a force, and the one or more memory chips are The memory chip is coupled to: a controller on the same wafer; and storing data from the plurality of non-volatile storage elements including buffering the data at different wafers. The method of claim 7, wherein: Ο Ο : storing data from the plurality of non-volatile storage elements includes . One of the corpus callosum devices buffers the data in random access memory. 12. If the request item ^ i ·, line, complement, , /, applies one or more compensations for each word, , and complement except the last word line, including: The word line of the line applies at least one of the "main compensation" for each of the memory elements that are surface-to-faced to the word lines, and performs the reading one morning and one time. 13. As shown in the method of claim 2, The at least one of the storage elements is included: u is a primary compensation control: the sensing module is configured to read at least one of an integration time, a pre-charge voltage, and a breakpoint voltage of the storage elements. The method of claim 1, further comprising: reading data values of the storage elements for the word lines after reading the storage elements of the word lines and before reading the other word line storage elements The bank is associated with a bit line associated with one of the storage elements; and after the storage of the data values for the storage elements of the word lines, 124907.doc 200822119: Buffering these data values in different memories. 1 5 · As in the method of claim i 4, The data values stored for each of the green word lines of the word lines include, for each word line except the taken word line, overwritten in one or more data latches. One of the adjacent word lines first stores one of the 70 pieces or a plurality of materials, such as a shell buffer, and the like, for each word line except the last word line. The data values are stored with the data values of the previously read storage elements from the adjacent word lines. The method of month 1 wherein the non-volatile storage elements that are stylized to the plurality of word lines comprise programmatically program the non-volatile storage elements by a complete sequence. π is the method of requesting t where the program (4) is coupled to the plurality of word lines: the non-volatile storage element includes programming the non-volatile storage elements using the upper page/lower page stylization. ◎ Method </ RTI> wherein the non-volatile storage elements such as the hexagrams that are programmed to be lightly coupled to the plurality of word lines include stylized the non-volatile storage elements using a last priority mode stylization. 19. The method of claim 1, wherein the non-volatile storage elements are multi-state non-volatile storage elements. 20. The method of claim 1, wherein the non-volatile storage elements are part of a NAND flash memory system. 21 - a non-volatile memory system comprising: a first set of select gates; 124907.doc 200822119 a second set of select gates; a plurality of subsequent word lines including adjacent ones of the S-group selection a gate-first word line and a last word line adjacent to the second set of select gates; a plurality of non-volatile storage elements that are coupled to the plurality of word lines; and a government circuit Transmitting, by the plurality of non-volatile storage elements, the management circuit starts at the first word line and ends at the last word line by changing a threshold value of a selected one of the storage elements according to a target memory state Staging the storage elements, the management circuit begins at the last word line and ends at the first word line to read the non-volatile storage elements, the management circuit is based on one of the second group of selected gates Reading up the phase (4) word line - word line (4) Apply one or more compensations when removing each word line except the last word line. 22. The non-volatile memory (four) system of claim 21, wherein the management circuit applies one or more compensations when reading word lines other than the last word line: based on the second group selection Reading the adjacent sub-word lines in one direction of the gate, performing a plurality of sub-reads and selecting one of the sub-reads results for each of the storage elements of the word lines. 23. The non-volatile memory system of claim 22, wherein the managing circuit performs a plurality of sub-reads for each word line other than the last word line comprises: applying a first set of read reference voltages to the Each word line senses one of the storage elements of the word lines to conduct a first sub-read; and 124907.doc 6-200822119 fine-applies-the second set of read reference voltages to the word lines And sensing the conduction of the storage elements of the word lines to perform - the second sub-read. 24. The non-volatile memory system of claim 23, wherein the management circuit selects one of the sub-reads as a result comprises: selecting the first-sub-read-result for the word lines Each of the erroneous elements 'the word lines having adjacent memory cells on the adjacent word lines - is determined to be in a state of symmetry during the reading of the word lines adjacent to the word lines; The object selects the second sub-read - the result is used for each of the word lines of the word lines, the word lines having an adjacent memory in the adjacent word line = 疋 the read phase The word line period &amp; adjacent to the word line is determined to be in the state. The non-volatile memory system of claim 22, wherein the management circuit performs a plurality of sub-reads for each of the word lines except the last word line, including a way to apply a set of read reference voltages Up to the word lines, applying - the first to the words and lines adjacent to the word lines, and sensing the storage of the word lines when the set of read reference voltages and the first voltage are applied Conducting a first sub-read of the component; and applying a set of read reference voltages to the word lines, applying a first voltage to the word line adjacent to the word lines, and applying the set The storage elements that sense the word lines are sensed to perform a second sub-read when reading the voltages and the second voltages. 26. The non-volatile memory system of claim 25, wherein the one of the management switches selects one of the sub-reads comprises: ", 124907.doc 200822119 Selecting one of the first sub-read results for Each of the word lines of the word lines, the word lines having an adjacent memory cell 2 of the adjacent word line during the reading of the word line adjacent to the word lines is determined to be in a first state; And s selecting the second sub-read - the result is for each storage element of the word lines, the word lines having - (4) memory lines in the (four) word line, the reading of the adjacent word lines The word line period is determined to be in a second state. Ο 27. The non-volatile memory system of claim 21, wherein the management circuit begins with a non-volatile storage element from the light-bonded to the last word line. The tribute ends with data from the non-volatile storage element that is bonded to the first word line, and temporarily stores the data from the plurality of non-volatile storage elements in a memory. 27 non-volatile memory system, which further envelops people. Output: 3 wherein the management circuit begins with a loyalty from the non-volatile storage component coupled to the first word line and ends with the face-to-face The non-volatile storage element of the word line follows the sequence of the 1 000 Becker's to provide the information from the non-smoke-small-storage pieces that are integrated into the plurality of sub-lines to the input irj 〇29 The non-volatile memory (10) system of claim 27, wherein: the plurality of words green, λ ^ ^ ^ ^ non-volatile storage elements are formed on one or more memory chips; and the management The circuit is temporarily stored in ice from the plurality of non-volatile storage elements 124907.doc 200822119 30. 31.Ο 32. Ο33. 34. The data is included in the data storage of the memory chip or the plurality of memory chips. Non-volatile memory system, wherein: the non-volatile storage elements that are coupled to the plurality of word lines are formed on one or more memory chips; at least a portion of the management circuit is on a different wafer ; and = management circuit Pro Storing data from the plurality of semaphore storage elements includes buffering the data on the different wafers. The non-volatile memory system of claim 27 includes: The memory is temporarily stored from the plurality of non-volatile data including buffering the data in the random access memory. For example, the non-volatile money and body system of claim 21, wherein the tube reads When the word lines except the last word line are removed, only 4 shoulders are compensated for the 4th bit. 7. Based on the word line reading the adjacent word lines, at least one element line is applied as the main compensation for the consumption. Each of the word lines stores a single sub-read. π, as in the non-volatile memory system of claim 32, the management circuit applies at least one bit line as the main compensation for each storage element including: controlling a sensing module for reading the respective etches A non-volatile memory system, such as the non-volatile memory system of claim 21, further comprising: one or more data latches; , which is associated with the respective stores; ... - 7L line 124907.doc 200822119 ^ stomach (four) (four) (four) after the storage of each word line (four) and before reading the storage elements of another word line, will be used for the word lines The poor value of each stored item (4) is in the one data latch associated with the storage element; 35 Ο 36. u 37. 38. 39. wherein the management circuit is used for the word The data values of the storage elements of the line are then buffered in different memory sources. The non-volatile memory system of claim 34, wherein: the management circuit stores data values for each of the storage elements of the word lines, including - or more for each word line except the last word line The data latch overwrites one or more data values of the previously read storage element from the adjacent word line; and the management circuit buffers the data values including the word lines except for the last word line And storing the data values and the data values of the previously read storage elements from the adjacent word lines. A non-volatile memory system as claimed in claim 21, wherein the management circuit is programmed to modulate the non-volatile storage elements coupled to the plurality of word lines using a τ. The non-volatile memory system of claim 21, wherein the management circuit uses upper page/lower page programming to program the non-volatile storage elements coupled to the plurality of word lines. The non-volatile memory system of claim 21, wherein the management circuit is programmed with a last priority mode to program the non-volatile storage elements coupled to the plurality of word lines. The non-volatile memory system of claim 21, wherein the non-volatile 124907.doc -10 - 200822119 storage element is a multi-state non-volatile storage element. 40. The non-volatile memory system of claim 21, wherein the management circuit comprises at least one of a controller and a state machine. 41. The non-volatile memory system of claim 21, wherein the plurality of non-volatile memory elements are part of a NAND flash memory system. 〇 〇 124907.doc