TWI355051B - Lead frame structure and its chip package method - Google Patents

Description

1355051 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a chip packaging technique, and more particularly to a lead frame structure and a wafer packaging method thereof. [Prior Art] When the conventional lead frame is packaged, a layer of tape is attached to the surface of the lead frame to prevent the glue from overflowing onto the pad of the lead frame. However, 9 tapes are prone to contamination of the lead frame pads by residual glue. When the tape is poorly attached, there is still a problem of overflowing. In addition, in the packaging process, it is necessary to add a process of attaching tape, removing tape, removing glue, etc.; after removing the tape, the lead frame is to be subjected to a surface treatment process such as tin plating for the adhesive bonding of the rear surface. In addition to increasing costs, it is also likely to cause loss of yield. In addition, traditional lead frame manufacturing requires the purchase of copper or iron plates. Both copper and iron plates have a certain thickness, so production specifications are limited. SUMMARY OF THE INVENTION In order to solve the above problems, one of the objects of the present invention is to provide a lead frame structure and a wafer packaging method thereof, which eliminates the need for any tape in the packaging process and avoids the problem of residual glue. - One of the objects of the present invention is to provide a lead frame structure and a wafer packaging method therefor. The soldering surface of the lead frame can be used for surface adhesive packaging without performing a surface treatment process such as plating. 5 1355051 The object of the present invention is to provide a lead frame structure and a method for sealing the same by using a plurality of metal layers to form a lead frame, which can be made to have an unlimited thickness according to requirements. One of the objects of the present invention is to provide a lead frame structure and a wafer sealing method thereof, which can produce a wire frame structure with a very thin thickness, which can effectively reduce the height of the whole body. One of the objects of the present invention is to provide a lead frame structure and In the wafer sealing method, the soldering portion of the lead frame can be designed to protrude from the package, which can increase the reliability of soldering in the package. One of the objects of the present invention is to provide a lead frame structure and a chip packaging method thereof, which can use the existing equipment for BB chip packaging without additional equipment or processes, can reduce the cost of the chip package, and can shorten the traditional process and Improve product yield. The genus layer is formed on the metal carrier plate of the patterned opening and is composed of a plurality of metal layers. In order to achieve the above object, a lead frame structure according to an embodiment of the present invention includes: a metal carrier; a first insulating layer is disposed on the metal carrier, wherein the first insulating layer has a Wei-like opening exposing gold Lai board; and - ugly divination, Sun heat to recognize the group also 71 nr * - . Which patterned the first metal layer

The metal layer extends to the surface 6 of the second insulating layer and the second metal layer is disposed on the pin on the surface of the second insulating layer, and the third metal layer in the basin can also be selected (4) disposed in the hybrid® The second gold layer is formed on the surface of the layer of the present invention. The wafer sealing method of the invention further comprises: providing a metal carrier; forming a first insulating layer on the metal carrier, wherein the first insulating layer is Having a plurality of patterned openings to expose the metal carrier; forming a patterned metal layer on the metal carrier; wherein the first metal layer is composed of a plurality of metal layers, and is formed on the bottom layer And the metal layer of the top layer are respectively used for soldering and wire bonding or ball planting; at least _ wafer; at least one of the insulating layer and the portion of the patterned first metal layer; electrically connecting the wafer to the patterned metal-metal On the layer; providing - the encapsulating material covers the wafer, the first insulating layer, the patterned first metal layer; and removing the metal carrier. The invention relates to a wafer packaging method comprising: providing a metal carrier plate forming a first insulating layer on a metal carrier, the substrate having a plurality of patterned openings to expose the metal carrier; forming - patterning the first metal layer on the metal carrier, wherein the patterned first metal layer is composed of a plurality of metal layers, and is used for welding, wire bonding or ball placement in the metal layer of the bottom layer and the top layer The second insulating layer covers the first insulating layer and the patterned first metal layer, wherein the second insulating layer has a plurality of through holes exposing (10) portions of the deuterated metal layer; and the second metal layer is applied to the second insulating layer a portion of the patterned first metal layer and a portion of the second insulating layer are exposed on the layer, wherein the patterned second metal layer is a plurality of (10), and the pin is connected to the patterned first metal in the via hole And extending to the surface of the second insulating layer; forming a third metal layer on the pin on the surface of the second insulating layer, wherein the third metal layer is selectively formed on the partially patterned second metal layer On the surface; at least - the wafer is in the second insulation At least one of the layer, the partially patterned ^-metal layer and a portion of the second metal layer; the electrical connection "provides a bond to the pin 丨, the patterned first - Jinlin, the patterned second metal Layer, second metal layer; and removal of metal carrier plate 1355051 [Embodiment] Please refer to ® lAHc, in this implementation, the guide wire structure package includes: metal carrier 10, - first insulation layer 20 and - The first metal layer 3G is patterned, wherein the 'first insulating layer 2G is disposed on the metal carrier 1GJL and the first insulating layer 2 has a plurality of patterned openings 21 exposing the metal carrier 1 〇. Patterning the first metal layer 30 The first metal layer is patterned in the patterning opening 21 and the patterned first metal layer is composed of a plurality of metal layers. Following the above description, the method of manufacturing the lead frame structure includes providing a metal carrier board. The layer 20 is on the metal carrier 10. The first insulating layer 1 having a plurality of patterned openings 21 is formed by an image transfer process, a stamping process, a bonding process, a pasting process, and a laser direct imaging process. This is like nn_g 'LDI) or printing process The patterned opening 21 exposes the metal carrier - 10. After that, the patterned first metal layer 30 is formed on the metal carrier 1 , wherein the patterned first metal layer 30 is composed of a plurality of metal layers The plurality of metal layers may be formed by a combination of tin, lead, gold, nickel, silver, palladium, copper, tin and lead. The plurality of metal layers may be plated, sputtered, vapor deposited or printed. Or made by electroless plating. In addition, the metal layer on the bottom layer and the top layer are used for welding and wire bonding or ball planting respectively. • Therefore, the material of the metal layer of the bottom layer is selected from a metal material for soldering, such as tin. , wrong, gold, nickel, silver, palladium, copper or tin-lead. The metal layer of the top layer is made of a metal material such as gold, nickel, silver, copper, palladium, which can be used for wire bonding, electrical connection or ball bonding. Tin or tin lead. Thus, the fabrication of this leadframe structure is completed. Wherein, the patterned first metal layer 30 in the leadframe structure can be divided into carrier wafers or pins. Referring to FIG. 2A to FIG. 2B, in one embodiment, the chip packaging method includes other steps in addition to the manufacturing steps of the lead frame structure. The wafer 4 is placed on the first insulating layer 20 and the partially patterned first metal layer 30. Next, the wafer 4 is electrically connected to the patterned first metal layer 30. The crystal moon 40 and the patterned metal layer 3 can be electrically connected by a wire bonding method. In another embodiment, as shown in FIGS. 3A to 3B, the wafer 8:: gold =: ^ or _ = = is shown in FIG. 3C and FIG. 3D. In the package of:=, as shown in Fig. 2C, Fig. 2D, the outermost part of the package, the middle and middle cutting processes can also directly cut out part of the first metal layer H, so that the sidewall of the sealing body can be exposed. The manual visual inspection method is carried out by the side/first metal layer 30 in the post-SMT condition, and the elasticity of the X-up test is not required. Due to the condition of _Hmt on the tin, the process is increased - the metal impurities available for welding can be used. Therefore, the completed package does not need to be surface plate 10 for the tan junction, and the metal of the lead frame structure carries a plurality of patterned grooves 21, and the pattern 21 is disposed. Metal carrier board ^=== 竿Communication process, _process or stamping process. The wire j mounting body is as shown in Figs. 5A, 5B, 5C and 5D in the welded portion of the package, so that the reliability at the time of soldering can be increased. In the case of the actual material, the body is cut in the cutting village, and the metal layer 3G is exposed to the side wall of the package. In the first embodiment, the guide is waste w3 - the insulating layer 2g is patterned first =: one 22; a patterned second metal layer 32; and a third description, the first insulating layer 2g is placed on the metal carrier ig. The first figure shows that the 0^th plurality of patterned openings (not shown) expose the metal carrier ι〇. The pattern metal layer 30 is disposed on the metal carrier 1〇 of the patterned opening. Among them, 1355051 patterned metal-layer 3G is made of electro-mineral method or electroless ore method, and the plural=two-fiber or printed layer material is made of metal material for welding. The metal of the bottom layer is used to wire and electrically connect the metal of the ball (4). The metal layer of the layer is one for the second insulating layer 22 to cover the first insulating layer 2, wherein the second insulating layer 22 has a plurality of exposed portions of the through holes 2; the layer =: 32 the first insulating layer 22. Partially patterning the second metal layer 32

23 _ _ —_ 3G and extending to the second extruding second metal layer. a pin on the surface of the insulating layer 22 (pattern

Continuing with reference to the drawings, Fig. 6B, Fig. 0C and the drawings, the above-described lead frame manufacturing method includes other steps in addition to the steps described in Figs. 1A to 1B. A second insulating layer 22 is formed to cover the first insulating layer 2 and the pattern-metal layer 30 by a coating process, a spraying process, a lithography process, a printing process, a pressing process, or a molding process. The second insulating layer 22 has a plurality of through holes 23 exposing a portion of the patterned first metal layer 30. This through hole 23 can be made by laser drilling, blind drilling, printing, spraying or lithography. Forming a patterned second metal layer 32 on the second insulating layer 22 by electroplating, evaporation, ruthenium plating or electroless plating to expose a portion of the patterned first metal layer 30 and a portion of the second insulating layer 22» Among them, the partially patterned second metal layer 32 is used as a plurality of pins. And these pins are connected to the patterned metal layer 30 in the via hole 23 and extend to the surface of the second insulating layer 22. A third metal layer 34 is formed on the pins on the surface of the second insulating layer 22 by plating, evaporation, ruthenium plating or electroless plating for wire bonding or ball implantation. Wherein, the third metal layer can be formed by a plurality of metal layers. In an embodiment, the third metal layer is formed on the non-bow; the second metal layer is patterned on the second metal layer. 10 1355051 Continuing the above description, please refer to FIG. 7A, FIG. 7B, FIG. 8A and FIG. 8B. In one embodiment, the chip packaging method further includes disposing the wafer 40 on the second insulating layer 22 and partially patterning the second metal layer. 32. Electrically connecting the wafer 4 〇 and the lead (patterning a metal layer 32) as shown in FIG. 7A and FIG. 8A. Then, a package material 50 is provided to cover the wafer 40, and patterned. The first metal layer 3, the patterned second metal layer 32, the third metal layer 34; and the metal carrier 10 are removed. Finally, the package can be cut along the cutting line. The package can also be cut into the package during cutting. The outermost patterned first metal layer 30 exposes a portion of the first metal layer 3〇 to the sidewall of the package. In an embodiment, not shown, the wafer may be disposed on the third metal layer.

In another embodiment (not shown), if the metal carrier is designed to have a plurality of patterned recesses disposed in the _insulating pattern contact, the package completed by the wafer packaging method of the above embodiment is completed. There is a portion protruding from the package as shown in FIGS. 9A and 9B. One of -+ W uses an insulating layer to define the size of the lead frame of the lead frame' so that the step of removing the photoresist can be omitted. The wafer = wire grain can be placed directly on the metal layer or the insulating layer. The solder wire can be selectively designed to protrude from the surface of the package, so as to use the electric ore, steaming, miscellaneous or no Electrolytic plating can be combined to reduce the glue to the soldering surface of the lead frame during filling: In addition, the present invention can also produce a very thin multi-layered guide. In addition, the wire (4) of the present invention is Reduction line: 'The thickness can be made according to the requirements. The production line kill structure can effectively reduce the overall package body. It can be designed without the need for Wei and other surface treatment processes, that is, the welding pad of the wire frame. Protruding out of the package: can be used; the reliability of soldering. This lead frame structure is not required (4) or system;: = 11 1355051 The existing equipment is packaged in the chip, and no adhesive tape is needed in the packaging process, so the problem of overflow or residual glue can be avoided. The present invention can reduce the cost of wafer packaging and shorten the traditional manufacturing process and improve product yield. The embodiments described above are merely illustrative of the technical spirit and the characteristics of the present invention. The purpose of the present invention is to enable those skilled in the art to understand the contents of the present invention and to implement the present invention. That is, the equivalent variations or modifications made by the spirit of the present invention should still be included in the scope of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A, FIG. 1B, FIG. 1C and FIG. 1D are schematic views showing an embodiment of the present invention. 2A, 2B, 2C and 2D are schematic views of an embodiment of the present invention. 3A, 3B, 3C and 3D are schematic views of an embodiment of the present invention. 4A and 4B are schematic views showing an embodiment of the present invention.

5C and FIG. 5D are schematic views showing a package body formed by different embodiments of the chip package method of the present invention. 6A, FIG. 6B, and FIG. 6C and FIG. 6D are not schematic views of an embodiment of the present invention. Figure 7 is a schematic view of the embodiment of Figures 6A to 6D. The schematic diagram of the embodiment of the above-mentioned FIG. 6A to FIG. 6D is not shown in FIG. 8 and the diagram is intended to be the wafer seal 12 1355051 made by different embodiments of the crystal thin method of the present invention. [Main component symbol description] ίο Metal load Plate 20 first insulating layer 21 patterned opening 21' patterned groove 22 second insulating layer 23 through hole 30 patterned first metal layer 32 patterned second metal layer 34 third metal layer 40 die 50 encapsulation material

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Claims (1)

2. 4. 5. 6. Patent application garden: A lead frame structure comprising: - a metal carrier; - a first insulating layer disposed on the metal carrier, wherein the first insulating layer has a plurality of patterns The opening is exposed to the metal carrier; and a patterned first metal layer is disposed on the metal carrier j of the plurality of openings, wherein the patterned first metal layer and the plurality of metal layers are combined. The leadframe structure of item 1, wherein the metal carrier has a plurality of patterned grooves corresponding to the patterned openings. The lead frame structure described in item 1 wherein the gold systems are formed by electroplating, such as the electrolysis method of the sister I electrolytic method, the steaming method or the printing method. The lead frame structure described in the item 's, the item 3, the metal layer of the towel on the bottom layer is a metal material for welding. The material of the butterfly layer in the top layer is the lead frame structure as claimed in claim 1, and further includes: the insulating layer in the basin is covered with the first insulating layer and the patterned first metal layer, and the second insulating layer The layer has a plurality of via holes exposing portions of the patterned first metal red-neutral layer' disposed on the pins on the surface of the second insulating layer, and the surface metal layer is also optional The shed pattern of the second metal layer is as shown in claim 6. The patterning concave _ money shaft port setting _ has a plurality of 8. The lead frame structure as described in claim 6 These genus layers are electrically isolated from the pins. A chip packaging method comprising: providing a metal carrier; forming a "first insulating layer" on a metal carrier, wherein the first plurality of patterned openings expose the metal carrier; ... forming a patterned first metal layer on the metal carrier, the metal layer is composed of a plurality of metal layers, and is used for soldering, wire bonding or ball bonding in the bottom layer and the top layer 2 layer respectively; At least one metal of the layer t metal is electrically connected to the patterned first metal layer to the patterned first metal layer; and the encapsulating material covers the crystal #, the first _Insulation layer, the patterned first metal layer; and 晶片 'Removing the metal carrier 》 Μ 9 9 9 9 9 , , , , , , , , , , , , , , , , , , , , , , , , , , , , 9 9 9 The wafer packaging method of claim 10, wherein the patterned grooves are formed using a depth control process, an etching process, or a stamping process. 12. The chip package of claim 9. Method, wherein the first The insulating layer is formed by an image transfer process, a lamination process, a press process, a die press process, a laser direct process, or a printing process. The chip packaging method according to claim 9, wherein the metal layer is formed. The method of wafer encapsulation according to claim 9, wherein the wafer and the patterned first metal layer are formed by using a plating method, an electroless ore method, a * bond method, a steaming method, or a printing method. Electrical connection by wire bonding or ball bonding. 15 1355051 i5mr/ The chip packaging method described, (4) The step of removing the paste carrier is performed by a stripping process or an etching process. The chip packaging method includes: providing one a metal carrier; forming: a first insulating layer on the metal carrier, wherein the first insulating layer is a plurality of patterned openings to expose the metal carrier; and: a chemicalized - gold lining on the metal She is a combination of several layers of metal layering, Jinlin, and the layers of the bottom layer and the top layer are used for tandeming, wire bonding, electrical connection or ball planting; The second insulating layer covers the first The layer and the patterned first metal layer have a plurality of through holes exposing a portion of the hard-to-defect first layer, and the layer is layered on the layer and exposed to the portion of the layer a first edge layer, wherein the portion of the patterned second metal pin is connected to the patterned first metal layer in the via holes and extends to a surface of the second insulating layer And forming a third metal layer on the pins on the surface of the second insulating layer, and the second metal layer may also be selectively formed on a portion of the patterned second metal layer And a portion of the layer and the portion electrically connected to the wafer and the pins; ^ for a package material covering the wafer, the second metal layer of the pattern, the third metal layer; and phase-removing the metal Carrier board. The wafer packaging method of Figure 12, wherein the metal plate has a plurality of patterned grooves corresponding to the respective opening openings. The wafer packaging method of claim 17, wherein the patterned grooves are formed using a depth control process, an etching process, or a stamping process. 19. The wafer packaging method of claim 16, wherein the first insulating layer is formed by an image transfer process, a lamination process, a press process, a die press process, a laser direct imaging process, or a printing process. 20. The wafer packaging method according to claim 16, wherein the step of forming the metal layers is performed by an electroplating method, a sputtering method, an evaporation method, or a printing method or an electroless plating method. 21. The method of claim 16, wherein the wafer is electrically connected to the pins by wire bonding or ball bonding. 22. The wafer packaging method of claim 16, wherein the step of removing the metal carrier is performed using a lift-off process or an etching process. 23. The wafer packaging method of claim 16, wherein the second insulating layer is formed by a coating process, a spray coating process, a lithography process, a printing process, a press process, or a molding process. 24. The wafer packaging method of claim 16, wherein the through holes are made by laser drilling, blind drilling or lithography. 17