CN1068710C - Tape and reel automatic soldering ball array integrated circuit packaging method - Google Patents
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本发明涉及一种集成电路封装方法,尤其是一种卷带自动焊接球阵式集成电路封装方法。The invention relates to an integrated circuit packaging method, in particular to a tape and roll automatic welding ball array integrated circuit packaging method.
现今TAB-BGA型集成电路封装电路板的制法而论,基本如图4A~I所示,图中所示为3M公司典型的制程,首先是在图4A的聚酰亚胺膜90(POLYIMIDE)基材上方通过溅镀方式(PVD或CVD)形成薄厚度的溅镀铜91,以形成一含薄铜层的聚酰亚胺膜,然后为如图4B所示,表面以电镀方式覆盖一薄厚度的电镀铜92,之后,为如图4C所示,于顶底面处压合干膜以及通过曝光和显影的步骤,而形成位于顶底面呈多个具缺口的块状干膜93,其次,则为如图4D所示,于顶部位置进行电镀铜的步骤,以形成位于各干膜93之间的较厚电镀铜94,其次,则为如图4E所示,对聚酰亚胺膜90进行蚀刻的步骤,而形成供后续进行植入锡球的锥度孔97,而后,为如图4F所示,进行电解电镀镍及电解电镀铬的步骤,令位于上表面的较厚电镀铜94以及底部的锥度孔97处形成电解电镀镍和电镀铬层96,之后,为去除顶底层的干膜93而形成如图4G的型式,并经蚀刻铜层的步骤,对图4G内部夹层位置的电镀铜92以及溅镀铜91蚀刻,而转变为如图4H的型态,最后,则为对底部的各锥度孔97位置进行植入锡球的步骤,而在图4I所示的相关部位形成供外接的锡球98,至于位于表面适当位置的外突的电镀镍和电镀铬层96,其一处供粘着芯片40,并同时将芯片40各引脚通过互连机(BONDER)以金属线41跨接至相关位置处。但上述现有的TAB-BGA集成电路封装电路板的制法有如下缺点:首先,于聚酰亚胺膜90上方为溅镀(SPUTTERING)方式形成的薄厚度的溅镀铜91,虽通过溅镀方式形成铜箔可达到较均匀且较薄的厚度,然这种溅镀制程不仅较为昂贵,且在聚酰亚胺膜表面进行大面积的溅镀作业时,成本更属高昂,无法符合经济性的要求。其次,外接接点为使用→植锡球→方式为之,由于锡球大小有一定限制,而相应供锡球植入的锥度孔亦必须设计适当的许用误差,故导致外接接点的大小及间隔距离无法大幅缩减,造成外接接点无法细微化的缺点,且植入锡球的方式是令锡球于电路板上滚动而落入各锥度孔中,然后再通过高温与锥度孔内部的金属结合,此举,更有着定位精确度不足的现象,亦即无法确保各锡球全部对准,故而欲达到更高精密度及更小接点的需求下,乃无法实现。再者,由于其供连接芯片的接点上形成铬金属,故而必须使用金线焊接方式(Au Wire Bonding)来与芯片接点之间进行跳线连接,此种通过跳线连接芯片的封装方式较占用电路板面积,导致整个封装电路板的尺寸较大,无法符合高密度的要求。In terms of the manufacturing method of the current TAB-BGA type integrated circuit package circuit board, it is basically shown in Figure 4A~I, shown in the figure is the typical manufacturing process of 3M Company, at first it is polyimide film 90 (POLYIMIDE) in Figure 4A ) above the substrate by sputtering (PVD or CVD) to form a thin thickness of
本发明的目的在于提供一种可使各外接接点精密定位,形成更细小外接接点,并且可适当地缩小封装电路板面积的卷带自动焊接球阵式集成电路封装方法。The object of the present invention is to provide a tape-and-roll automatic soldering ball-array integrated circuit packaging method that can precisely position each external contact, form smaller external contacts, and appropriately reduce the area of the packaged circuit board.
本发明的目的是这样实现的,一种卷带自动焊接球阵式集成电路封装方法,其特征在于包括下列步骤:取用含有双面薄铜的聚酰亚胺膜作为基材;对基材双面进行第一干膜的压合、曝光和显影,而仅令上表面形成缺口;为在第一干膜未覆盖的上表面处依次进行电镀铜、电镀镍、电镀金以及电镀镍等多层电镀;去除第一干膜;对基材双面进行第二干膜的压合、曝光和显影,而仅令下表面形成缺口;运用第二干膜为掩模,以对下层薄铜进行蚀刻;运用下层薄铜作为掩模,对基材的聚酰亚胺膜部位进行激光蚀刻,藉薄铜的阻挡以及激光能量的控制,形成未贯通的孔洞图形;在基材上表面压合第三干膜,以保护上表面电镀层;在聚酰亚胺膜的各孔洞实施电解电镀而形成填满各孔洞及略外突的电解电镀接点;去除第三干膜;蚀刻介于各个多层电镀层之间呈外露的上层薄铜,而使相邻电镀层相互隔开,以及蚀刻去除位于多层电镀层表面的电镀镍层,而使电镀金层外露;及,对基材中央及需形成贯通的部位进行激光钻孔,以分别形成位于基材中央的芯片安装孔及外围的激光贯孔,以使芯片安装孔部位外围形成由多层电镀层所形成的接触悬臂,供焊接结合芯片。The object of the present invention is achieved like this, a kind of tape and reel automatic welding ball array type integrated circuit packaging method, it is characterized in that comprising the following steps: get and use the polyimide film that contains double-sided thin copper as base material; Carry out the lamination, exposure and development of the first dry film on both sides, and only make the upper surface form a gap; in order to carry out electroplating copper, electroplating nickel, electroplating gold and electroplating nickel etc. in sequence on the upper surface not covered by the first dry film layer electroplating; remove the first dry film; press, expose and develop the second dry film on both sides of the substrate, so that only the lower surface forms a gap; use the second dry film as a mask to carry out the thin copper on the lower layer Etching: use the lower layer of thin copper as a mask to perform laser etching on the polyimide film of the substrate, and use the blocking of thin copper and the control of laser energy to form a non-through hole pattern; press the upper surface of the substrate Three dry films to protect the electroplating layer on the upper surface; electrolytic plating is performed on each hole of the polyimide film to form electrolytic plating contacts that fill each hole and slightly protrude; remove the third dry film; etch between each multilayer There is an exposed upper layer of thin copper between the electroplating layers, so that the adjacent electroplating layers are separated from each other, and the electroplating nickel layer on the surface of the multi-layer electroplating layer is etched away, so that the electroplating gold layer is exposed; and, for the center of the substrate and the required Laser drilling is performed on the part where the through hole is formed to form the chip mounting hole in the center of the substrate and the laser through hole on the periphery, so that a contact cantilever formed by a multi-layer electroplating layer is formed on the periphery of the chip mounting hole for welding and bonding chips .
本发明的目的还可以通过下述方法来实现,一种卷带自动焊接球阵式集成电路封装方法,其特征在于包括下列步骤:取用含有双面薄铜的聚酰亚胺膜作为基材;对基材双面进行第一干膜的压合、曝光和显影,而仅令上表面形成缺口;在第一干膜未覆盖的上表面处依次进行电镀镍、及电镀金的双层电镀;去除第一干膜;对基材双面进行第二干膜的压合、曝光和显影,而仅令下表面形成缺口;运用第二干膜为掩模,对下层薄铜进行蚀刻;运用下层薄铜作为掩模,对基材的聚酰亚胺膜部位进行激光蚀刻,薄铜的阻挡以及对激光能量的控制,形成未贯通的孔洞图形;在基材上表面压合第三干膜,以保护上表面电镀层;在聚酰亚胺膜的各孔洞实施电解电镀而形成填满各孔洞及略外突的电解电镀接点;去除第三干膜;蚀刻介于各个多层电镀层之间呈外露的上层薄铜,而使相邻电镀层相互隔开;及,对基材中央及需形成贯通的部位进行激光钻孔,以分别形成位于基材中央的芯片安装孔及外围的激光贯孔,以使芯片安装孔部位外围形成由多层电镀层所形成的接触悬臂,供焊接结合芯片。The purpose of the present invention can also be achieved by the following method, a tape and reel automatic soldering ball array integrated circuit packaging method, which is characterized in that it includes the following steps: taking the polyimide film containing double-sided thin copper as the base material Carry out lamination, exposure and development of the first dry film on both sides of the substrate, and only make the upper surface form a gap; sequentially perform double-layer electroplating of electroplating nickel and electroplating gold on the upper surface not covered by the first dry film ; remove the first dry film; carry out lamination, exposure and development of the second dry film on both sides of the substrate, and only form a gap on the lower surface; use the second dry film as a mask to etch the lower layer of thin copper; use The lower layer of thin copper is used as a mask to perform laser etching on the polyimide film of the substrate, and the blocking of the thin copper and the control of the laser energy form a hole pattern that is not penetrated; the third dry film is laminated on the upper surface of the substrate , to protect the upper surface electroplating layer; implement electrolytic plating in each hole of the polyimide film to form electrolytic plating contacts that fill each hole and slightly protrude; remove the third dry film; etch between each multi-layer electroplating layer The exposed upper layer of thin copper between them separates the adjacent electroplating layers from each other; and, laser drilling is performed on the center of the substrate and the parts that need to be formed through to form the chip mounting hole in the center of the substrate and the laser holes on the periphery, respectively. Through holes, so that the periphery of the chip mounting hole is formed with a contact cantilever formed by a multi-layer electroplating layer for soldering and bonding of the chip.
本发明的目的还可以通过下述方法来实现,一种卷带自动焊接球阵式集成电路封装方法,其特征在于包括下列步骤:取用含有双面薄铜的聚酰亚胺膜作为基材;对基材双面进行第一干膜的压合、曝光和显影的步骤,而仅令上表面形成缺口;在第一干膜未覆盖的上表面处依次进行电镀铜、及电镀镍的双层电镀;去除第一干膜;对基材双面进行第二干膜的压合、曝光和显影,而仅令下表面形成缺口;运用第二干膜为掩模,对下层薄铜进行蚀刻;运用下层薄铜作为掩模,对基材的聚酰亚胺膜部位进行激光蚀刻,藉薄铜的阻挡以及对激光能量的控制,形成未贯通的孔洞图形;在基材上表面压合第三干膜,以保护上表面电镀层;在聚酰亚胺膜的各孔洞实施电解电镀而形成填满各孔洞及略外突的电解电镀接点;去除第三干膜;在基材顶底部盖合第四干膜,并经曝光和显影,而仅在顶部特定位置形成缺口;对顶部缺口进行镀金,而形成镀金凸点;蚀刻介于各个双层电镀层之间外露的上层薄铜,而使相邻电镀层相互隔开;对基材中央及需形成贯通的部位进行激光钻孔,以分别形成位于基材中央的芯片安装孔及外围的激光贯孔,以使芯片安装孔部位外围形成由双层电镀层以及镀金凸点所形成的接触悬臂,供焊接结合芯片。The purpose of the present invention can also be achieved by the following method, a tape and reel automatic soldering ball array integrated circuit packaging method, which is characterized in that it includes the following steps: taking the polyimide film containing double-sided thin copper as the base material Carry out the steps of pressing, exposing and developing the first dry film on both sides of the base material, and only make the upper surface form a gap; Carry out electroplating copper and electroplating nickel in sequence on the upper surface not covered by the first dry film. Layer electroplating; remove the first dry film; press, expose and develop the second dry film on both sides of the substrate, and only form a gap on the lower surface; use the second dry film as a mask to etch the lower layer of thin copper ;Using the lower layer of thin copper as a mask, laser etching is performed on the polyimide film of the substrate, and through the blocking of the thin copper and the control of the laser energy, an incomplete hole pattern is formed; the upper surface of the substrate is laminated Three dry films to protect the electroplating layer on the upper surface; electrolytic plating is performed on each hole of the polyimide film to form electrolytic plating contacts that fill the holes and slightly protrude; remove the third dry film; cover the top and bottom of the substrate Combine the fourth dry film, and after exposure and development, only a gap is formed at the top specific position; the top gap is gold-plated to form a gold-plated bump; the upper layer of thin copper exposed between each double-layer electroplating layer is etched, and Separate the adjacent electroplating layers from each other; perform laser drilling on the center of the substrate and the part that needs to be formed to form a chip mounting hole in the center of the substrate and a laser through hole on the periphery, so that the periphery of the chip mounting hole is formed The contact cantilever formed by double-layer electroplating and gold-plated bumps is used for soldering and bonding chips.
本发明与已有技术相比优点和积极效果非常明显。由以上的技术方案可知,在本发明的前段制程中,由于直接取用已预先压合或粘合有双面薄铜的聚酰亚胺膜作为基材,基材的成本显然可较前述传统方式进行溅镀薄铜的步骤低廉,有着降低成本的优点,而通过对聚酰亚胺膜10进行激光蚀刻形成孔洞12以及形成电解电镀接点17的步骤中,即使得各接点得以自动对准(SELF-ALIGN)于各孔洞12内,而不致产生偏移或过度误差,故而提供精确定位的优点外,且可使各接点17之间的间距可控制在相当窄小的程度(20μm),更可符合细微接点的特性,此外,对于图1R、图2R以及图3S的供接合芯片40处的芯片安装孔22位置所形成的多层电镀层或形成有镀金凸点20的悬臂构造,更为形成一种可直接通过单点焊接(SINGLE POINT BOND)方式予以接合芯片40,无需通过跳接金线方式连结,此举,亦使得TAB-BGA封装电路板整体尺寸缩小,诚为一较传统TAB-BGA制法更具高密度化效果及可使外接接点更趋精确及细小的制法,再者,经使用双面薄铜的聚酰亚胺膜,下层薄铜亦可用作激光钻孔的掩模,更使得激光钻孔更趋精确。Compared with the prior art, the present invention has obvious advantages and positive effects. It can be seen from the above technical solutions that in the front-end process of the present invention, since the polyimide film that has been pre-pressed or bonded with double-sided thin copper is directly used as the base material, the cost of the base material can obviously be compared with the aforementioned traditional ones. The step of sputtering thin copper in this way is cheap, and has the advantage of reducing cost, and in the step of forming the
以下结合附图进一步说明本发明的具体结构特征及目的。The specific structural features and purposes of the present invention will be further described below in conjunction with the accompanying drawings.
图1是本发明的第一实施例制法剖视示意图。Fig. 1 is a schematic cross-sectional view of the manufacturing method of the first embodiment of the present invention.
图2是本发明的第二实施例制法剖视示意图。Fig. 2 is a schematic cross-sectional view of the manufacturing method of the second embodiment of the present invention.
图3是本发明的第三实施例制法剖视示意图。Fig. 3 is a schematic cross-sectional view of the manufacturing method of the third embodiment of the present invention.
图4是传统的TAB-BGA制程的剖视示意图。FIG. 4 is a schematic cross-sectional view of a traditional TAB-BGA manufacturing process.
本发明具有三种不同的实施例,而其间仅各制程的电镀层的材料不同而导致制程略有变动,以下即依次就本发明的各实施例说明之,首先如图1A~R所示,在图1A中,本发明为直接使用已压合或粘合有双面薄铜11、111的聚酰亚胺膜10作为本发明的基材,而无需如传统制程必须先对聚酰亚胺膜基材上附加溅镀铜的步骤,据以免除薄铜金属需进行溅镀所衍生的作业复杂性以及基材成本过于高昂的问题,而在图1B中,为于上、下层薄铜11、111进行压合第一干膜13、131以及进行曝光和显影的步骤,以在上表面形成多个块状干膜13,然后为如图1C所示,依次电镀形成电镀铜141、电镀镍142、电镀金143以及电镀镍144等多层式电镀层,经去除前述图1干膜13后,即如图1D所示,为形成朝上突起的电镀层,其后,为如图1E所示,实施第二干膜16、161的压合、曝光和显影的步骤,而仅在底部形成外露缺口,即经图1F对下层薄铜111蚀刻,而在去除第二干膜16、161后,即形成如图1G所示,令下层薄铜111蚀刻形成具有多个缺口112的型态,其后,为如图1H所示,运用该下层薄铜111作为掩模,以激光蚀刻方式对聚酰亚胺膜10底部进行蚀刻,通过对激光能量的控制,使聚酰亚胺膜10蚀刻形成多个未贯穿的孔洞12(此等孔洞供后续电解电镀形成向下延伸的接点),然后为如图1I所示对上表面压合第三干膜19)以使前述位于上表面的各图形受到保护之后,再图1J所示去除下层薄铜111,其次,则进行如图1K的对聚酰亚胺膜10的各孔洞12部位进行电解电镀的步骤(镀镍或镀铜),而在各孔洞处填满以及外端呈外突型式的电解电镀接点17(形成此封装电路板的外接接点),然后,为去除覆盖在上表面的第三干膜19(如图1L),之后,为如图1M、N所示,依次对底面进行覆盖一保护膜18、覆盖第4干膜51,然在图1O的步骤中,去除位于电镀层顶部的电镀镍144以及介于各电镀层之间的上层薄铜11,而使电镀层的电镀金143呈外露状态,并进行如图1P的去除前述第四干膜51以及保护膜18的步骤,最后,则为如图1Q所示,对中央位置以及其他位置实施激光钻孔的步骤,以形成位于中央及外围位置的芯片安装孔22以及激光贯孔21,至此即完成封装电路板的制程,而安装芯片的方式,为如图1R所示,由于位于芯片安装孔22位置侧边的多层电镀层基本形成一悬臂状,且该图1R最上方位置的电镀层的表层位置为电镀金143的材料,故即可直接经单点焊接技术,直接结合芯片40。The present invention has three different embodiments, and only the material of the electroplating layer in each process is different, resulting in a slight change in the process. The following will describe each embodiment of the present invention in turn. First, as shown in Figures 1A-R, In Fig. 1A, the present invention directly uses the
本发明的另一实施例如图2A~R所示,其间的差异处仅在于图2C的电镀层的材料仅为依次电镀形成电镀镍142以及电镀金143两项材料而已,而在图2O中为仅需蚀刻去除介于各电镀层之间的上层薄铜11即可,其余均相同,而上述两种制程均可达到相同的效果。Another embodiment of the present invention is shown in FIGS. 2A-R. The only difference is that the material of the electroplating layer in FIG. It is only necessary to etch and remove the upper layer of
本发明的第三实施例如图3中的A~S图所示,其间的差异仍在于图3C中的电镀层材料为仅以一厚电镀铜14以及一电镀镍15构成的双层型式的电镀层,而在图3N的第四干膜的压合、曝光和显影的步骤中,为将上、下表面均同时形成上、下层第四干膜51、511,仅在上表面近中央位置形成缺口512,而在图3O的步骤中,对缺口512位置进行电镀形成镀金凸点20,而在图3P的剥离第四干膜51、511以及在最终步骤(图3S),该等形成于表层电镀镍15上方的镀金凸点20即可作为供单点焊接芯片40的焊接点。在第三实施例的细部制程方面,如图3A所示,本发明是直接使用已压合或粘合有双面薄铜11、111的聚酰亚胺膜10作为本发明的基材,而无需如传统制程必须先对聚酰亚胺膜基材上附加溅镀铜的步骤,据以免除薄铜金属需进行溅镀所衍生的作业复杂性以及基材成本过于高昂的问题,而在图3B中,为于上、下层薄铜11、111进行压合第一干膜13、131以及进行曝光和显影的步骤,以在上表面形成呈多个块状干膜13的型式,然后为如图3C所示,依次电镀形成一厚电镀铜14以及一电镀镍15的双层电镀层,经去除前述第一干膜13、131后,即如图3D所示,形成朝上突起的电镀层,其后,为如图3E所示,实施第二干膜16、161的压合、曝光和显影的步骤,而仅在底部形成外露缺口,即经图3F对下层薄铜111蚀刻,而去除第二干膜16、161后,即形成如图3G所示,令下层薄铜111蚀刻形成具有多个缺口112的型态,其后,为如图3H所示,运用该下层薄铜111作为掩模,以激光蚀刻方式对聚酰亚胺膜10底部进行蚀刻,通过对激光能量的控制,使聚酰亚胺膜10蚀刻形成多个未贯穿的孔洞12(此等孔洞供后续电解电镀形成向下延伸的接点),然后为如图3I所示对上表面压合第三干膜19以使前述位于上表面的各图形受到保护后,再如图3J所示去除下层薄铜111,其次,则进行如图3K的对聚酰亚胺膜10的各孔洞12部位进行电解电镀的步骤(镀镍或镀铜),而在各孔洞处填满以及外端呈外突型式的电解电镀接点17(形成此封装电路板的外接接点),然后,为去除覆盖在上表面的图3干膜19(如图3L),之后,为如图3M所示,对底面进行覆盖一保护膜18以及在图3N中进行第四干膜51、511的压合、曝光和显影的步骤,而仅在上方特定位置形成缺口512,然后在图3O的步骤中,对前述缺口512进行金材料电镀的步骤,以形成镀金凸点20,而经图3P去除顶底部的第四干膜51、511及保护膜18后,即在该顶面近中央位置的厚电镀镍15上表面形成可供焊接芯片的镀金凸点20,更如图3Q所示,蚀刻去除介于相邻厚电镀铜14之间的上层薄铜11,最后,则为如图3R所示,对中央位置以及其他位置实施激光钻孔的步骤,以形成位于中央及外围位置的芯片安装孔22以及激光贯孔21,至此即完成封装电路板的制程,而安装芯片的方式,为如图3S所示,由于位于芯片安装孔22位置侧边的厚电镀铜14及电镀镍15基本形成一悬臂状,且该最上方位置的镀金凸点20,可直接经单点焊接技术,直接结合芯片40。The third embodiment of the present invention is shown in Figures A to S in Figure 3, and the difference between them is that the material of the electroplating layer in Figure 3C is a double-layer electroplating that only consists of a thick electroplated
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| US5244833A (en) * | 1989-07-26 | 1993-09-14 | International Business Machines Corporation | Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer |
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| US5244833A (en) * | 1989-07-26 | 1993-09-14 | International Business Machines Corporation | Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer |
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