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CN1068710C - Tape and reel automatic soldering ball array integrated circuit packaging method - Google Patents

Tape and reel automatic soldering ball array integrated circuit packaging method Download PDF

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Publication number
CN1068710C
CN1068710C CN97118217A CN97118217A CN1068710C CN 1068710 C CN1068710 C CN 1068710C CN 97118217 A CN97118217 A CN 97118217A CN 97118217 A CN97118217 A CN 97118217A CN 1068710 C CN1068710 C CN 1068710C
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dry film
base material
thin copper
hole
copper
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CN1210368A (en
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蔡维人
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Huatong Computer Co ltd
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Huatong Computer Co ltd
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    • H10W72/5522
    • H10W72/884

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Abstract

The invention relates to a packaging method for a rolling belt automatic welding ball array type integrated circuit, which forms a first dry film on a polyimide film pressed with double-sided thin copper, electroplates copper/nickel/gold/nickel (or nickel/gold, copper/nickel), removes the first dry film, etches the lower layer thin copper of the polyimide film through a second dry film to form a plurality of gaps, uses the lower layer thin copper as a mask to form holes on the laser drilling hole of the polyimide film, and forms an outward protruding joint point by hole electrolytic plating, etches the thin copper and peels nickel, and forms a chip mounting hole and a peripheral through hole by laser drilling, thereby enabling the external joint point to be finer, and welding a chip by a single spot welding mode to reduce the packaging area.

Description

卷带自动焊接球阵式集成电路封装方法Tape and reel automatic soldering ball array integrated circuit packaging method

本发明涉及一种集成电路封装方法,尤其是一种卷带自动焊接球阵式集成电路封装方法。The invention relates to an integrated circuit packaging method, in particular to a tape and roll automatic welding ball array integrated circuit packaging method.

现今TAB-BGA型集成电路封装电路板的制法而论,基本如图4A~I所示,图中所示为3M公司典型的制程,首先是在图4A的聚酰亚胺膜90(POLYIMIDE)基材上方通过溅镀方式(PVD或CVD)形成薄厚度的溅镀铜91,以形成一含薄铜层的聚酰亚胺膜,然后为如图4B所示,表面以电镀方式覆盖一薄厚度的电镀铜92,之后,为如图4C所示,于顶底面处压合干膜以及通过曝光和显影的步骤,而形成位于顶底面呈多个具缺口的块状干膜93,其次,则为如图4D所示,于顶部位置进行电镀铜的步骤,以形成位于各干膜93之间的较厚电镀铜94,其次,则为如图4E所示,对聚酰亚胺膜90进行蚀刻的步骤,而形成供后续进行植入锡球的锥度孔97,而后,为如图4F所示,进行电解电镀镍及电解电镀铬的步骤,令位于上表面的较厚电镀铜94以及底部的锥度孔97处形成电解电镀镍和电镀铬层96,之后,为去除顶底层的干膜93而形成如图4G的型式,并经蚀刻铜层的步骤,对图4G内部夹层位置的电镀铜92以及溅镀铜91蚀刻,而转变为如图4H的型态,最后,则为对底部的各锥度孔97位置进行植入锡球的步骤,而在图4I所示的相关部位形成供外接的锡球98,至于位于表面适当位置的外突的电镀镍和电镀铬层96,其一处供粘着芯片40,并同时将芯片40各引脚通过互连机(BONDER)以金属线41跨接至相关位置处。但上述现有的TAB-BGA集成电路封装电路板的制法有如下缺点:首先,于聚酰亚胺膜90上方为溅镀(SPUTTERING)方式形成的薄厚度的溅镀铜91,虽通过溅镀方式形成铜箔可达到较均匀且较薄的厚度,然这种溅镀制程不仅较为昂贵,且在聚酰亚胺膜表面进行大面积的溅镀作业时,成本更属高昂,无法符合经济性的要求。其次,外接接点为使用→植锡球→方式为之,由于锡球大小有一定限制,而相应供锡球植入的锥度孔亦必须设计适当的许用误差,故导致外接接点的大小及间隔距离无法大幅缩减,造成外接接点无法细微化的缺点,且植入锡球的方式是令锡球于电路板上滚动而落入各锥度孔中,然后再通过高温与锥度孔内部的金属结合,此举,更有着定位精确度不足的现象,亦即无法确保各锡球全部对准,故而欲达到更高精密度及更小接点的需求下,乃无法实现。再者,由于其供连接芯片的接点上形成铬金属,故而必须使用金线焊接方式(Au Wire Bonding)来与芯片接点之间进行跳线连接,此种通过跳线连接芯片的封装方式较占用电路板面积,导致整个封装电路板的尺寸较大,无法符合高密度的要求。In terms of the manufacturing method of the current TAB-BGA type integrated circuit package circuit board, it is basically shown in Figure 4A~I, shown in the figure is the typical manufacturing process of 3M Company, at first it is polyimide film 90 (POLYIMIDE) in Figure 4A ) above the substrate by sputtering (PVD or CVD) to form a thin thickness of sputtered copper 91 to form a polyimide film containing a thin copper layer, and then as shown in Figure 4B, the surface is covered by electroplating Thin thickness electroplated copper 92, after that, as shown in Figure 4C, press the dry film at the top and bottom surfaces and pass the steps of exposure and development to form a plurality of block dry films 93 with notches on the top and bottom surfaces, and then , as shown in Figure 4D, the step of electroplating copper at the top position to form a thicker electroplated copper 94 between the dry films 93, and secondly, as shown in Figure 4E, the polyimide film 90 is etched to form a tapered hole 97 for subsequent implantation of solder balls. Then, as shown in FIG. And the taper hole 97 place of the bottom forms electrolytic electroplating nickel and electrochrome plating layer 96, afterward, forms the pattern as Fig. 4G in order to remove the dry film 93 of top bottom layer, and through the step of etching copper layer, to the interlayer position of Fig. 4G Electroplated copper 92 and sputtered copper 91 are etched to transform into the pattern shown in Figure 4H, and finally, the step of implanting solder balls at the positions of the taper holes 97 at the bottom is formed at the relevant parts shown in Figure 4I For external solder balls 98, as for the protruding electroplating nickel and electrochrome plating layers 96 located at appropriate positions on the surface, one of them is used for bonding the chip 40, and at the same time, each pin of the chip 40 is connected with a metal wire through an interconnector (BONDER). 41 is connected to relevant positions. But the above-mentioned existing TAB-BGA integrated circuit packaging method has the following disadvantages: first, the sputtering copper 91 of thin thickness formed in the sputtering (SPUTTERING) mode on the top of the polyimide film 90, though sputtering Copper foil formed by plating can achieve a relatively uniform and thin thickness. However, this sputtering process is not only expensive, but also the cost is even higher when sputtering a large area on the surface of the polyimide film, which is not economical. sexual demands. Secondly, the external contact is used→solder ball planting→method. Since the size of the solder ball has a certain limit, and the corresponding taper hole for the solder ball implantation must also be designed with an appropriate allowable error, the size and spacing of the external contact The distance cannot be greatly reduced, resulting in the disadvantage that the external contact cannot be miniaturized, and the method of implanting solder balls is to make the solder balls roll on the circuit board and fall into each tapered hole, and then combine with the metal inside the tapered hole through high temperature. This method also has the phenomenon of insufficient positioning accuracy, that is, it is impossible to ensure that all the solder balls are aligned, so it cannot be realized under the demand for higher precision and smaller contacts. Furthermore, since chromium metal is formed on the contacts for connecting the chip, Au Wire Bonding must be used to connect the chip contacts with jumper wires. The area of the circuit board leads to a large size of the entire package circuit board, which cannot meet the requirements of high density.

本发明的目的在于提供一种可使各外接接点精密定位,形成更细小外接接点,并且可适当地缩小封装电路板面积的卷带自动焊接球阵式集成电路封装方法。The object of the present invention is to provide a tape-and-roll automatic soldering ball-array integrated circuit packaging method that can precisely position each external contact, form smaller external contacts, and appropriately reduce the area of the packaged circuit board.

本发明的目的是这样实现的,一种卷带自动焊接球阵式集成电路封装方法,其特征在于包括下列步骤:取用含有双面薄铜的聚酰亚胺膜作为基材;对基材双面进行第一干膜的压合、曝光和显影,而仅令上表面形成缺口;为在第一干膜未覆盖的上表面处依次进行电镀铜、电镀镍、电镀金以及电镀镍等多层电镀;去除第一干膜;对基材双面进行第二干膜的压合、曝光和显影,而仅令下表面形成缺口;运用第二干膜为掩模,以对下层薄铜进行蚀刻;运用下层薄铜作为掩模,对基材的聚酰亚胺膜部位进行激光蚀刻,藉薄铜的阻挡以及激光能量的控制,形成未贯通的孔洞图形;在基材上表面压合第三干膜,以保护上表面电镀层;在聚酰亚胺膜的各孔洞实施电解电镀而形成填满各孔洞及略外突的电解电镀接点;去除第三干膜;蚀刻介于各个多层电镀层之间呈外露的上层薄铜,而使相邻电镀层相互隔开,以及蚀刻去除位于多层电镀层表面的电镀镍层,而使电镀金层外露;及,对基材中央及需形成贯通的部位进行激光钻孔,以分别形成位于基材中央的芯片安装孔及外围的激光贯孔,以使芯片安装孔部位外围形成由多层电镀层所形成的接触悬臂,供焊接结合芯片。The object of the present invention is achieved like this, a kind of tape and reel automatic welding ball array type integrated circuit packaging method, it is characterized in that comprising the following steps: get and use the polyimide film that contains double-sided thin copper as base material; Carry out the lamination, exposure and development of the first dry film on both sides, and only make the upper surface form a gap; in order to carry out electroplating copper, electroplating nickel, electroplating gold and electroplating nickel etc. in sequence on the upper surface not covered by the first dry film layer electroplating; remove the first dry film; press, expose and develop the second dry film on both sides of the substrate, so that only the lower surface forms a gap; use the second dry film as a mask to carry out the thin copper on the lower layer Etching: use the lower layer of thin copper as a mask to perform laser etching on the polyimide film of the substrate, and use the blocking of thin copper and the control of laser energy to form a non-through hole pattern; press the upper surface of the substrate Three dry films to protect the electroplating layer on the upper surface; electrolytic plating is performed on each hole of the polyimide film to form electrolytic plating contacts that fill each hole and slightly protrude; remove the third dry film; etch between each multilayer There is an exposed upper layer of thin copper between the electroplating layers, so that the adjacent electroplating layers are separated from each other, and the electroplating nickel layer on the surface of the multi-layer electroplating layer is etched away, so that the electroplating gold layer is exposed; and, for the center of the substrate and the required Laser drilling is performed on the part where the through hole is formed to form the chip mounting hole in the center of the substrate and the laser through hole on the periphery, so that a contact cantilever formed by a multi-layer electroplating layer is formed on the periphery of the chip mounting hole for welding and bonding chips .

本发明的目的还可以通过下述方法来实现,一种卷带自动焊接球阵式集成电路封装方法,其特征在于包括下列步骤:取用含有双面薄铜的聚酰亚胺膜作为基材;对基材双面进行第一干膜的压合、曝光和显影,而仅令上表面形成缺口;在第一干膜未覆盖的上表面处依次进行电镀镍、及电镀金的双层电镀;去除第一干膜;对基材双面进行第二干膜的压合、曝光和显影,而仅令下表面形成缺口;运用第二干膜为掩模,对下层薄铜进行蚀刻;运用下层薄铜作为掩模,对基材的聚酰亚胺膜部位进行激光蚀刻,薄铜的阻挡以及对激光能量的控制,形成未贯通的孔洞图形;在基材上表面压合第三干膜,以保护上表面电镀层;在聚酰亚胺膜的各孔洞实施电解电镀而形成填满各孔洞及略外突的电解电镀接点;去除第三干膜;蚀刻介于各个多层电镀层之间呈外露的上层薄铜,而使相邻电镀层相互隔开;及,对基材中央及需形成贯通的部位进行激光钻孔,以分别形成位于基材中央的芯片安装孔及外围的激光贯孔,以使芯片安装孔部位外围形成由多层电镀层所形成的接触悬臂,供焊接结合芯片。The purpose of the present invention can also be achieved by the following method, a tape and reel automatic soldering ball array integrated circuit packaging method, which is characterized in that it includes the following steps: taking the polyimide film containing double-sided thin copper as the base material Carry out lamination, exposure and development of the first dry film on both sides of the substrate, and only make the upper surface form a gap; sequentially perform double-layer electroplating of electroplating nickel and electroplating gold on the upper surface not covered by the first dry film ; remove the first dry film; carry out lamination, exposure and development of the second dry film on both sides of the substrate, and only form a gap on the lower surface; use the second dry film as a mask to etch the lower layer of thin copper; use The lower layer of thin copper is used as a mask to perform laser etching on the polyimide film of the substrate, and the blocking of the thin copper and the control of the laser energy form a hole pattern that is not penetrated; the third dry film is laminated on the upper surface of the substrate , to protect the upper surface electroplating layer; implement electrolytic plating in each hole of the polyimide film to form electrolytic plating contacts that fill each hole and slightly protrude; remove the third dry film; etch between each multi-layer electroplating layer The exposed upper layer of thin copper between them separates the adjacent electroplating layers from each other; and, laser drilling is performed on the center of the substrate and the parts that need to be formed through to form the chip mounting hole in the center of the substrate and the laser holes on the periphery, respectively. Through holes, so that the periphery of the chip mounting hole is formed with a contact cantilever formed by a multi-layer electroplating layer for soldering and bonding of the chip.

本发明的目的还可以通过下述方法来实现,一种卷带自动焊接球阵式集成电路封装方法,其特征在于包括下列步骤:取用含有双面薄铜的聚酰亚胺膜作为基材;对基材双面进行第一干膜的压合、曝光和显影的步骤,而仅令上表面形成缺口;在第一干膜未覆盖的上表面处依次进行电镀铜、及电镀镍的双层电镀;去除第一干膜;对基材双面进行第二干膜的压合、曝光和显影,而仅令下表面形成缺口;运用第二干膜为掩模,对下层薄铜进行蚀刻;运用下层薄铜作为掩模,对基材的聚酰亚胺膜部位进行激光蚀刻,藉薄铜的阻挡以及对激光能量的控制,形成未贯通的孔洞图形;在基材上表面压合第三干膜,以保护上表面电镀层;在聚酰亚胺膜的各孔洞实施电解电镀而形成填满各孔洞及略外突的电解电镀接点;去除第三干膜;在基材顶底部盖合第四干膜,并经曝光和显影,而仅在顶部特定位置形成缺口;对顶部缺口进行镀金,而形成镀金凸点;蚀刻介于各个双层电镀层之间外露的上层薄铜,而使相邻电镀层相互隔开;对基材中央及需形成贯通的部位进行激光钻孔,以分别形成位于基材中央的芯片安装孔及外围的激光贯孔,以使芯片安装孔部位外围形成由双层电镀层以及镀金凸点所形成的接触悬臂,供焊接结合芯片。The purpose of the present invention can also be achieved by the following method, a tape and reel automatic soldering ball array integrated circuit packaging method, which is characterized in that it includes the following steps: taking the polyimide film containing double-sided thin copper as the base material Carry out the steps of pressing, exposing and developing the first dry film on both sides of the base material, and only make the upper surface form a gap; Carry out electroplating copper and electroplating nickel in sequence on the upper surface not covered by the first dry film. Layer electroplating; remove the first dry film; press, expose and develop the second dry film on both sides of the substrate, and only form a gap on the lower surface; use the second dry film as a mask to etch the lower layer of thin copper ;Using the lower layer of thin copper as a mask, laser etching is performed on the polyimide film of the substrate, and through the blocking of the thin copper and the control of the laser energy, an incomplete hole pattern is formed; the upper surface of the substrate is laminated Three dry films to protect the electroplating layer on the upper surface; electrolytic plating is performed on each hole of the polyimide film to form electrolytic plating contacts that fill the holes and slightly protrude; remove the third dry film; cover the top and bottom of the substrate Combine the fourth dry film, and after exposure and development, only a gap is formed at the top specific position; the top gap is gold-plated to form a gold-plated bump; the upper layer of thin copper exposed between each double-layer electroplating layer is etched, and Separate the adjacent electroplating layers from each other; perform laser drilling on the center of the substrate and the part that needs to be formed to form a chip mounting hole in the center of the substrate and a laser through hole on the periphery, so that the periphery of the chip mounting hole is formed The contact cantilever formed by double-layer electroplating and gold-plated bumps is used for soldering and bonding chips.

本发明与已有技术相比优点和积极效果非常明显。由以上的技术方案可知,在本发明的前段制程中,由于直接取用已预先压合或粘合有双面薄铜的聚酰亚胺膜作为基材,基材的成本显然可较前述传统方式进行溅镀薄铜的步骤低廉,有着降低成本的优点,而通过对聚酰亚胺膜10进行激光蚀刻形成孔洞12以及形成电解电镀接点17的步骤中,即使得各接点得以自动对准(SELF-ALIGN)于各孔洞12内,而不致产生偏移或过度误差,故而提供精确定位的优点外,且可使各接点17之间的间距可控制在相当窄小的程度(20μm),更可符合细微接点的特性,此外,对于图1R、图2R以及图3S的供接合芯片40处的芯片安装孔22位置所形成的多层电镀层或形成有镀金凸点20的悬臂构造,更为形成一种可直接通过单点焊接(SINGLE POINT BOND)方式予以接合芯片40,无需通过跳接金线方式连结,此举,亦使得TAB-BGA封装电路板整体尺寸缩小,诚为一较传统TAB-BGA制法更具高密度化效果及可使外接接点更趋精确及细小的制法,再者,经使用双面薄铜的聚酰亚胺膜,下层薄铜亦可用作激光钻孔的掩模,更使得激光钻孔更趋精确。Compared with the prior art, the present invention has obvious advantages and positive effects. It can be seen from the above technical solutions that in the front-end process of the present invention, since the polyimide film that has been pre-pressed or bonded with double-sided thin copper is directly used as the base material, the cost of the base material can obviously be compared with the aforementioned traditional ones. The step of sputtering thin copper in this way is cheap, and has the advantage of reducing cost, and in the step of forming the hole 12 and forming the electrolytic plating contact 17 by carrying out laser etching to the polyimide film 10, even each contact can be automatically aligned ( SELF-ALIGN) in each hole 12, without causing offset or excessive error, so it provides the advantages of precise positioning, and can control the distance between the contacts 17 at a very narrow level (20 μm), and more It can conform to the characteristics of fine contacts. In addition, for the multi-layer electroplating layer formed at the chip mounting hole 22 position at the bonding chip 40 in FIG. 1R, FIG. 2R and FIG. 3S or the cantilever structure with gold-plated bumps 20 is formed Form a chip 40 that can be bonded directly by single point welding (SINGLE POINT BOND), without the need to connect by jumping gold wires. This also reduces the overall size of the TAB-BGA package circuit board, which is a comparison with the traditional TAB -The BGA manufacturing method has a higher density effect and can make the external contacts more precise and smaller. Furthermore, the lower layer of thin copper can also be used for laser drilling by using a polyimide film with double-sided thin copper The mask makes the laser drilling more precise.

以下结合附图进一步说明本发明的具体结构特征及目的。The specific structural features and purposes of the present invention will be further described below in conjunction with the accompanying drawings.

图1是本发明的第一实施例制法剖视示意图。Fig. 1 is a schematic cross-sectional view of the manufacturing method of the first embodiment of the present invention.

图2是本发明的第二实施例制法剖视示意图。Fig. 2 is a schematic cross-sectional view of the manufacturing method of the second embodiment of the present invention.

图3是本发明的第三实施例制法剖视示意图。Fig. 3 is a schematic cross-sectional view of the manufacturing method of the third embodiment of the present invention.

图4是传统的TAB-BGA制程的剖视示意图。FIG. 4 is a schematic cross-sectional view of a traditional TAB-BGA manufacturing process.

本发明具有三种不同的实施例,而其间仅各制程的电镀层的材料不同而导致制程略有变动,以下即依次就本发明的各实施例说明之,首先如图1A~R所示,在图1A中,本发明为直接使用已压合或粘合有双面薄铜11、111的聚酰亚胺膜10作为本发明的基材,而无需如传统制程必须先对聚酰亚胺膜基材上附加溅镀铜的步骤,据以免除薄铜金属需进行溅镀所衍生的作业复杂性以及基材成本过于高昂的问题,而在图1B中,为于上、下层薄铜11、111进行压合第一干膜13、131以及进行曝光和显影的步骤,以在上表面形成多个块状干膜13,然后为如图1C所示,依次电镀形成电镀铜141、电镀镍142、电镀金143以及电镀镍144等多层式电镀层,经去除前述图1干膜13后,即如图1D所示,为形成朝上突起的电镀层,其后,为如图1E所示,实施第二干膜16、161的压合、曝光和显影的步骤,而仅在底部形成外露缺口,即经图1F对下层薄铜111蚀刻,而在去除第二干膜16、161后,即形成如图1G所示,令下层薄铜111蚀刻形成具有多个缺口112的型态,其后,为如图1H所示,运用该下层薄铜111作为掩模,以激光蚀刻方式对聚酰亚胺膜10底部进行蚀刻,通过对激光能量的控制,使聚酰亚胺膜10蚀刻形成多个未贯穿的孔洞12(此等孔洞供后续电解电镀形成向下延伸的接点),然后为如图1I所示对上表面压合第三干膜19)以使前述位于上表面的各图形受到保护之后,再图1J所示去除下层薄铜111,其次,则进行如图1K的对聚酰亚胺膜10的各孔洞12部位进行电解电镀的步骤(镀镍或镀铜),而在各孔洞处填满以及外端呈外突型式的电解电镀接点17(形成此封装电路板的外接接点),然后,为去除覆盖在上表面的第三干膜19(如图1L),之后,为如图1M、N所示,依次对底面进行覆盖一保护膜18、覆盖第4干膜51,然在图1O的步骤中,去除位于电镀层顶部的电镀镍144以及介于各电镀层之间的上层薄铜11,而使电镀层的电镀金143呈外露状态,并进行如图1P的去除前述第四干膜51以及保护膜18的步骤,最后,则为如图1Q所示,对中央位置以及其他位置实施激光钻孔的步骤,以形成位于中央及外围位置的芯片安装孔22以及激光贯孔21,至此即完成封装电路板的制程,而安装芯片的方式,为如图1R所示,由于位于芯片安装孔22位置侧边的多层电镀层基本形成一悬臂状,且该图1R最上方位置的电镀层的表层位置为电镀金143的材料,故即可直接经单点焊接技术,直接结合芯片40。The present invention has three different embodiments, and only the material of the electroplating layer in each process is different, resulting in a slight change in the process. The following will describe each embodiment of the present invention in turn. First, as shown in Figures 1A-R, In Fig. 1A, the present invention directly uses the polyimide film 10 that has been laminated or bonded with double-sided thin copper 11, 111 as the substrate of the present invention, without having to first process the polyimide as in the traditional process. The additional step of sputtering copper on the film substrate is to avoid the complexity of the operation and the high cost of the substrate caused by sputtering the thin copper metal. In Figure 1B, the upper and lower layers of thin copper 11 , 111 carry out the steps of laminating the first dry film 13, 131 and exposing and developing, to form a plurality of bulk dry films 13 on the upper surface, and then as shown in Figure 1C, electroplating forms electroplated copper 141, electroplated nickel successively 142, multi-layer electroplating layers such as electroplating gold 143 and electroplating nickel 144, after removing the aforementioned dry film 13 in FIG. 1, as shown in FIG. As shown, the steps of lamination, exposure and development of the second dry film 16, 161 are implemented, and only an exposed gap is formed at the bottom, that is, the lower layer of thin copper 111 is etched through Fig. 1F, and after removing the second dry film 16, 161 , that is, as shown in FIG. 1G, the lower layer of thin copper 111 is etched to form a pattern with a plurality of notches 112. Afterwards, as shown in FIG. 1H, using the lower layer of thin copper 111 as a mask, laser etching The bottom of the polyimide film 10 is etched, and by controlling the laser energy, the polyimide film 10 is etched to form a plurality of non-through holes 12 (these holes are used for subsequent electrolytic plating to form downwardly extending contacts), and then After pressing the third dry film 19) on the upper surface as shown in Figure 1I so that the aforementioned patterns on the upper surface are protected, then remove the lower layer of thin copper 111 as shown in Figure 1J, and then perform the alignment as shown in Figure 1K The steps of electrolytic plating (nickel plating or copper plating) are carried out at each hole 12 positions of the polyimide film 10, and the electrolytic plating contacts 17 (forming the packaging circuit board of this packaging circuit board) are filled in each hole and the outer end is a protruding type. external contact), then, for removing the third dry film 19 (as shown in Figure 1L) covering the upper surface, after that, as shown in Figure 1M and N, the bottom surface is covered with a protective film 18 and covered with the 4th dry film successively. 51. However, in the step of FIG. 1O, the electroplated nickel 144 at the top of the electroplated layer and the upper layer of thin copper 11 between the electroplated layers are removed, so that the electroplated gold 143 of the electroplated layer is in an exposed state, and proceed as shown in FIG. 1P The step of removing the aforementioned fourth dry film 51 and the protective film 18, and finally, as shown in FIG. And the laser through hole 21, so far the process of packaging the circuit board is completed, and the way of installing the chip is as shown in Figure 1R, because the multi-layer electroplating layer located on the side of the chip mounting hole 22 basically forms a cantilever shape, and the The surface layer of the electroplating layer at the uppermost position in FIG. 1R is the material of electroplating gold 143 , so it can be directly bonded to the chip 40 through single-point welding technology.

本发明的另一实施例如图2A~R所示,其间的差异处仅在于图2C的电镀层的材料仅为依次电镀形成电镀镍142以及电镀金143两项材料而已,而在图2O中为仅需蚀刻去除介于各电镀层之间的上层薄铜11即可,其余均相同,而上述两种制程均可达到相同的效果。Another embodiment of the present invention is shown in FIGS. 2A-R. The only difference is that the material of the electroplating layer in FIG. It is only necessary to etch and remove the upper layer of thin copper 11 between the electroplating layers, and the rest are the same, and the above two processes can achieve the same effect.

本发明的第三实施例如图3中的A~S图所示,其间的差异仍在于图3C中的电镀层材料为仅以一厚电镀铜14以及一电镀镍15构成的双层型式的电镀层,而在图3N的第四干膜的压合、曝光和显影的步骤中,为将上、下表面均同时形成上、下层第四干膜51、511,仅在上表面近中央位置形成缺口512,而在图3O的步骤中,对缺口512位置进行电镀形成镀金凸点20,而在图3P的剥离第四干膜51、511以及在最终步骤(图3S),该等形成于表层电镀镍15上方的镀金凸点20即可作为供单点焊接芯片40的焊接点。在第三实施例的细部制程方面,如图3A所示,本发明是直接使用已压合或粘合有双面薄铜11、111的聚酰亚胺膜10作为本发明的基材,而无需如传统制程必须先对聚酰亚胺膜基材上附加溅镀铜的步骤,据以免除薄铜金属需进行溅镀所衍生的作业复杂性以及基材成本过于高昂的问题,而在图3B中,为于上、下层薄铜11、111进行压合第一干膜13、131以及进行曝光和显影的步骤,以在上表面形成呈多个块状干膜13的型式,然后为如图3C所示,依次电镀形成一厚电镀铜14以及一电镀镍15的双层电镀层,经去除前述第一干膜13、131后,即如图3D所示,形成朝上突起的电镀层,其后,为如图3E所示,实施第二干膜16、161的压合、曝光和显影的步骤,而仅在底部形成外露缺口,即经图3F对下层薄铜111蚀刻,而去除第二干膜16、161后,即形成如图3G所示,令下层薄铜111蚀刻形成具有多个缺口112的型态,其后,为如图3H所示,运用该下层薄铜111作为掩模,以激光蚀刻方式对聚酰亚胺膜10底部进行蚀刻,通过对激光能量的控制,使聚酰亚胺膜10蚀刻形成多个未贯穿的孔洞12(此等孔洞供后续电解电镀形成向下延伸的接点),然后为如图3I所示对上表面压合第三干膜19以使前述位于上表面的各图形受到保护后,再如图3J所示去除下层薄铜111,其次,则进行如图3K的对聚酰亚胺膜10的各孔洞12部位进行电解电镀的步骤(镀镍或镀铜),而在各孔洞处填满以及外端呈外突型式的电解电镀接点17(形成此封装电路板的外接接点),然后,为去除覆盖在上表面的图3干膜19(如图3L),之后,为如图3M所示,对底面进行覆盖一保护膜18以及在图3N中进行第四干膜51、511的压合、曝光和显影的步骤,而仅在上方特定位置形成缺口512,然后在图3O的步骤中,对前述缺口512进行金材料电镀的步骤,以形成镀金凸点20,而经图3P去除顶底部的第四干膜51、511及保护膜18后,即在该顶面近中央位置的厚电镀镍15上表面形成可供焊接芯片的镀金凸点20,更如图3Q所示,蚀刻去除介于相邻厚电镀铜14之间的上层薄铜11,最后,则为如图3R所示,对中央位置以及其他位置实施激光钻孔的步骤,以形成位于中央及外围位置的芯片安装孔22以及激光贯孔21,至此即完成封装电路板的制程,而安装芯片的方式,为如图3S所示,由于位于芯片安装孔22位置侧边的厚电镀铜14及电镀镍15基本形成一悬臂状,且该最上方位置的镀金凸点20,可直接经单点焊接技术,直接结合芯片40。The third embodiment of the present invention is shown in Figures A to S in Figure 3, and the difference between them is that the material of the electroplating layer in Figure 3C is a double-layer electroplating that only consists of a thick electroplated copper 14 and an electroplated nickel 15. layer, and in the steps of lamination, exposure and development of the fourth dry film in FIG. gap 512, and in the step of FIG. 3O, electroplating is performed on the position of the gap 512 to form a gold-plated bump 20, and in the peeling off of the fourth dry film 51, 511 in FIG. The gold-plated bumps 20 above the electroplated nickel 15 can be used as soldering points for single-point soldering of the chip 40 . In terms of the detailed manufacturing process of the third embodiment, as shown in FIG. 3A, the present invention directly uses the polyimide film 10 that has been laminated or bonded with double-sided thin copper 11, 111 as the substrate of the present invention, and There is no need to add copper sputtering on the polyimide film substrate as in the traditional process, so as to avoid the complexity of the operation and the high cost of the substrate caused by the sputtering of thin copper metal, and in the figure In 3B, the steps of laminating the first dry film 13, 131 and exposing and developing the upper and lower layers of thin copper 11, 111 are performed to form a plurality of block-shaped dry films 13 on the upper surface, and then as As shown in Figure 3C, a double-layer electroplating layer of a thick electroplated copper 14 and an electroplated nickel 15 is formed by sequential electroplating, and after removing the aforementioned first dry film 13, 131, as shown in Figure 3D, an upwardly protruding electroplating layer is formed , thereafter, as shown in FIG. 3E, implement the steps of pressing, exposing and developing the second dry film 16, 161, and only form an exposed gap at the bottom, that is, the lower layer of thin copper 111 is etched through FIG. 3F, and removed After the second dry film 16, 161 is formed as shown in Figure 3G, the lower layer of thin copper 111 is etched to form a pattern with a plurality of gaps 112, and thereafter, as shown in Figure 3H, the lower layer of thin copper 111 is used as Mask, etch the bottom of the polyimide film 10 by laser etching, by controlling the laser energy, the polyimide film 10 is etched to form a plurality of non-through holes 12 (these holes are formed by subsequent electrolytic plating Downwardly extending contacts), and then press the third dry film 19 on the upper surface as shown in Figure 3I so that the aforementioned patterns on the upper surface are protected, then remove the lower layer of thin copper 111 as shown in Figure 3J, and then , then carry out the step of carrying out electrolytic plating (nickel plating or copper plating) to each hole 12 positions of polyimide film 10 as shown in Fig. 3K, and fill in each hole place and the outer end is the electrolytic plating contact of protruding type 17 (forming the external contact of this encapsulation circuit board), then, for removing the Figure 3 dry film 19 (as Figure 3L) covering the upper surface, afterwards, as shown in Figure 3M, the bottom surface is covered with a protective film 18 and In FIG. 3N, the steps of lamination, exposure and development of the fourth dry film 51, 511 are carried out, and the gap 512 is only formed at a specific position above, and then in the step of FIG. 3O, the step of electroplating the aforementioned gap 512 with gold material , to form gold-plated bumps 20, and after the fourth dry film 51, 511 and protective film 18 on the top and bottom are removed through FIG. Gold-plated bumps 20, as shown in FIG. 3Q, are etched to remove the upper layer of thin copper 11 between adjacent thick electroplated copper 14. Finally, as shown in FIG. 3R, laser drilling is performed on the central position and other positions Steps to form chip mounting holes 22 and laser through holes 21 located in the center and peripheral positions, so far the process of packaging circuit boards is completed, and the way of mounting chips is as shown in FIG. 3S. The thick electroplated copper 14 and electroplated nickel 15 on the side basically form a cantilever shape, and the gold-plated bump 20 at the uppermost position can be directly bonded to the chip 40 through single-point welding technology.

Claims (9)

1 one kinds of winding automatic-welding spherical-array type integrated circuit packing methods is characterized in that comprising the following steps:
Take contain two-sided thin copper polyimide film as base material;
To two-sided pressing, exposure and the development of carrying out first dry film of base material, and only make upper surface form breach;
For carrying out multilayer platings such as electro-coppering, electronickelling, electrogilding and electronickelling successively at the unlapped upper surface of first dry film place;
Remove first dry film;
To two-sided pressing, exposure and the development of carrying out second dry film of base material, and only make lower surface form breach;
Using second dry film is mask, so that the thin copper of lower floor is carried out etching;
The thin copper of utilization lower floor carries out laser-induced thermal etching as mask to the polyimide film position of base material, and mat approaches the control of stopping of copper and laser energy, forms non-through hole figure;
At base material upper surface pressing the 3rd dry film, with protection upper surface electrodeposited coating;
Implement metallide and form the metallide contact that fills up each hole and omit evagination at each hole of polyimide film;
Remove the 3rd dry film;
Etching is the thin copper in the upper strata of exposing between each multilayer plating layer, and adjacent electrodeposited coating is spaced from each other, and etching removes and be positioned at the electroless nickel layer of multilayer plating laminar surface, and the electrogilding layer is exposed; And
Laser drill is carried out at position central to base material and that need to form perforation, to form chip installing hole and the peripheral laser perforation that is positioned at base material central authorities respectively, form by the formed contact cantilever of multilayer plating layer so that chip installing hole position is peripheral, for the solder bond chip.
2 winding automatic-welding spherical-array type integrated circuit packing methods according to claim 1 is characterized in that: wherein being somebody's turn to do can single-point welding manner and chips incorporate by the formed contact cantilever of multilayer plating layer.
3 winding automatic-welding spherical-array type integrated circuit packing methods according to claim 1 is characterized in that: wherein this metallide contact is made of nickel or copper product.
4 one kinds of winding automatic-welding spherical-array type integrated circuit packing methods is characterized in that comprising the following steps:
Take contain two-sided thin copper polyimide film as base material;
To two-sided pressing, exposure and the development of carrying out first dry film of base material, and only make upper surface form breach;
Carry out successively at the unlapped upper surface of first dry film place electronickelling, and the bilayer of electrogilding electroplate;
Remove first dry film;
To two-sided pressing, exposure and the development of carrying out second dry film of base material, and only make lower surface form breach;
Using second dry film is mask, and the thin copper of lower floor is carried out etching;
The thin copper of utilization lower floor carries out laser-induced thermal etching as mask to the polyimide film position of base material, the stopping and to the control of laser energy, form non-through hole figure of thin copper;
At base material upper surface pressing the 3rd dry film, with protection upper surface electrodeposited coating;
Implement metallide and form the metallide contact that fills up each hole and omit evagination at each hole of polyimide film;
Remove the 3rd dry film;
Etching is the thin copper in the upper strata of exposing between each multilayer plating layer, and adjacent electrodeposited coating is spaced from each other; And
Laser drill is carried out at position central to base material and that need to form perforation, to form chip installing hole and the peripheral laser perforation that is positioned at base material central authorities respectively, form by the formed contact cantilever of multilayer plating layer so that chip installing hole position is peripheral, for the solder bond chip.
5 winding automatic-welding spherical-array type integrated circuit packing methods according to claim 4 is characterized in that: wherein being somebody's turn to do can single-point welding manner and chips incorporate by the formed contact cantilever of double-deck electrodeposited coating.
6 winding automatic-welding spherical-array type integrated circuit packing methods according to claim 4 is characterized in that: wherein this metallide contact is made of nickel or copper product.
7 one kinds of winding automatic-welding spherical-array type integrated circuit packing methods is characterized in that comprising the following steps:
Take contain two-sided thin copper polyimide film as base material;
To two-sided pressing, exposure and the step of developing of carrying out first dry film of base material, and only make upper surface form breach;
Carry out successively at the unlapped upper surface of first dry film place electro-coppering, and the bilayer of electronickelling electroplate;
Remove first dry film;
To two-sided pressing, exposure and the development of carrying out second dry film of base material, and only make lower surface form breach;
Using second dry film is mask, and the thin copper of lower floor is carried out etching;
The thin copper of utilization lower floor carries out laser-induced thermal etching as mask to the polyimide film position of base material, the stopping and to the control of laser energy, form non-through hole figure of the thin copper of mat;
At base material upper surface pressing the 3rd dry film, with protection upper surface electrodeposited coating;
Implement metallide and form the metallide contact that fills up each hole and omit evagination at each hole of polyimide film;
Remove the 3rd dry film;
Cover the 4th dry film at the base material top/bottom part, and through exposure and development, and only form breach at the top ad-hoc location;
The top breach is carried out gold-plated, and form gold-plated salient point;
The upper strata that etching exposes between each double-deck electrodeposited coating approaches copper, and adjacent electrodeposited coating is spaced from each other;
Laser drill is carried out at position central to base material and that need to form perforation, to form chip installing hole and the peripheral laser perforation that is positioned at base material central authorities respectively, form by double-deck electrodeposited coating and the formed contact cantilever of gold-plated salient point so that chip installing hole position is peripheral, for the solder bond chip.
8 winding automatic-welding spherical-array type integrated circuit packing methods according to claim 7 is characterized in that: wherein being somebody's turn to do can single-point welding manner and chips incorporate by the formed contact cantilever of double-deck electrodeposited coating.
9 winding automatic-welding spherical-array type integrated circuit packing methods according to claim 7 is characterized in that: wherein this metallide contact is made of nickel or copper product.
CN97118217A 1997-09-04 1997-09-04 Tape and reel automatic soldering ball array integrated circuit packaging method Expired - Fee Related CN1068710C (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5244833A (en) * 1989-07-26 1993-09-14 International Business Machines Corporation Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5244833A (en) * 1989-07-26 1993-09-14 International Business Machines Corporation Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer

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