1352415 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種半導體裝置，特別係有關於— 種無外接腳式半導體封裝構造。 【先前技術】 無外接腳式半導體封裝構造是利用一晶片承座承載 晶片並以導線架之導腳電性連接晶片，以導腳之下表面 φ 作為對外電性連接’故不需要由封膠體側邊往外延伸之 外接腳，例如導腳排列在晶片承座四周邊之四方爲平無 外接腳封裝（Quad Flat Nonleaded，QFN)以及導腳排列 在晶片承座兩對應側邊之薄小外形無外接腳封裝（Thin Small Outline Nonleaded，TSON)。為了達到良好的散熱 效能，晶片承座應具有良好導熱性並使其尺寸遠大於晶 片。因此，整體半導體封裝構造無法縮小封襄尺寸。此 外，會有沖線與分層的問題。 •請參閱第1圖所示，習知無外接腳式半導體封裝構 造100包含一晶片承座110、複數個導腳120、一晶片 130、複數個金屬線140以及一封膠體丨50。該晶片承 座110係具有一黏晶表面111以及一散熱表面112，通 常該黏晶表面ill係等於或微大於該散熱表面112，用 以黏設該晶片130。該些導腳120係排列在該晶片承座 110之周邊，並每一導腳120具有一上表面m以及一 下表面122。該晶片丨30係具有複數個電極131 ’並利 用一黏晶膠1 6 〇之黏貼’使該晶片1 3 0設置在該晶片承 6 1352415 座110上。該些金屬線140係打線形成並電性連接該晶 片130之該些電極131至該些導腳12〇之該上表面 121。該封膠體150係密封該晶片13〇與該些金屬線 140，並顯露該晶片承座110之該散熱表面112以及該 些導腳120之該下表面122。請參閱第1圖所示，依散 熱需求的提咼’該晶片承座110必須更大於該晶片 120，造成該晶片130之該些電極131與該些導腳120 的距離增加，並且該無外接腳式半導體封裝構造1〇()之 尺寸無法縮小。當連接在該些電極131與該些導腳12〇 之間的金屬線140的長度越長，在該封膠體15〇之形成 過程中越容易產生沖線問題。又金屬線14〇係為昂貴的 高純度金線’其長度越長則封裝成本越高。此外，在熱 循環試驗中，在該晶片承座 110之黏晶表面111在該 片120之外的區域與該封膠體15〇之間的界面容易產生 分層。 【發明内容】1352415 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to an external pinless semiconductor package structure. [Prior Art] The external-footless semiconductor package structure uses a wafer carrier to carry the wafer and electrically connects the wafer with the lead legs of the lead frame, and the surface φ under the lead is electrically connected to the external portion. The outer side of the outer side of the wafer holder is arranged in a thin outer shape. Thin Small Outline Nonleaded (TSON). In order to achieve good heat dissipation, the wafer holder should have good thermal conductivity and be much larger than the wafer. Therefore, the overall semiconductor package structure cannot reduce the size of the package. In addition, there will be problems with rushing and stratification. • Referring to FIG. 1, a conventional pedestal-free semiconductor package structure 100 includes a wafer carrier 110, a plurality of leads 120, a wafer 130, a plurality of metal lines 140, and a colloid 丨50. The wafer holder 110 has a die attach surface 111 and a heat dissipating surface 112. Typically, the die attach surface ill is equal to or slightly larger than the heat dissipating surface 112 for bonding the wafer 130. The lead pins 120 are arranged around the wafer holder 110, and each of the lead pins 120 has an upper surface m and a lower surface 122. The wafer cassette 30 has a plurality of electrodes 131' and is attached to the wafer holder 16 1352415 by a paste of a glue adhesive. The metal wires 140 are formed by wires and electrically connected to the electrodes 131 of the wafer 130 to the upper surface 121 of the pins 12 . The encapsulant 150 seals the wafer 13 and the metal lines 140 and exposes the heat dissipating surface 112 of the wafer holder 110 and the lower surface 122 of the legs 120. Referring to FIG. 1 , according to the heat dissipation requirement, the wafer holder 110 must be larger than the wafer 120, causing the distance between the electrodes 131 of the wafer 130 and the guide pins 120 to increase, and the external connection is not required. The size of the foot semiconductor package structure 1〇() cannot be reduced. When the length of the metal wire 140 connected between the electrodes 131 and the guide pins 12A is longer, the problem of the punching line is more likely to occur during the formation of the sealant 15〇. Further, the metal wire 14 is an expensive high-purity gold wire. The longer the length, the higher the packaging cost. Further, in the heat cycle test, the interface between the region of the die pad surface 111 of the wafer holder 110 outside the sheet 120 and the sealant 15 is prone to delamination. [Summary of the Invention]
與電性接觸至晶片承座。Electrical contact to the wafer holder.
體封裝構造，以便於 目的係在於提供一種無外接腳式半導 以便於黏晶膠流入導腳之延長接指與晶片 7 1352415 , > . 承座之縫隙。 . 本發明之另—目的係在於提供一種無外接腳式半導 體封裝構造以阻擋黏晶膠流佈至延長接指之打線表 面。 本發明之另一目的係在於提供一種無外接腳式半導 體封裝構造，以阻擋黏晶膠流佈至晶片承座之顯露表 面。 本發明之另一目的係在於提供一種無外接腳式半導 _ 體封裝構造，避免B曰片承座在晶片周邊產生應力分層。 本發明之另一目的係在於提供一種無外接腳式半導 體封裝構造’避免黏晶膠外露。 本發明之另一目的係在於提供一種無外接腳式半導 體封裝構造’避免產生封穋氣泡。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明所揭示之一種無外接腳式半導 體封裝構造，主要包含一晶片承座、複數個導腳、一晶 籲 片、複數個金屬線以及一封膠體。該晶片承座係具有一 内層圖案與一外層圖案，其中該内層圖案係小於該外層 圖案，以致使該内層圖案之周邊形成複數個缺口。每一 導腳係具有一延長接指與一外接墊，其中該些延長接指 係延伸至該些缺口内並局部重疊於該外層圖案之周 邊。該晶片係設置於該晶片承座之該内層圖案上，該晶 片係具有複數個電極。該些金屬線係連接該晶片之該些 電極與該些導腳之該些延長接指。該封膠體係密封該晶 1352415 片與該些金屬線並電性絕緣地結合該些導腳與該晶片 承座，但顯露該些導聊之該些外接墊與該晶片承座之該 外層圖案。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述之無外接腳式半導體封裝構造中，可另包含一 黏晶膠，其係形成於該晶片與該内層圖案之間。 在前述之無外接腳式半導體封裝構造中，該黏晶膠係 可更形成於該些缺口内並黏著接觸該些延長接指。 在前述之無外接腳式半導體封裝構造中，該内層圖案 與該些缺口之間係可形成為倒斜角。 在前述之無外接腳式半導體封裝構造中，該些延長接 指係可具有位於該些缺口内之一第一截面銳角。 在前述之無外接腳式半導體封裝構造中，該晶片承座 之該外層圖案係可具有一位於該封膠體底面之第二截 面銳角。 在前述之無外接腳式半導體封裝構造中，該些金屬線 之材質係可包含金。 在前述之無外接腳式半導體封裝構造中，該些延長接 指之厚度係可小於該晶片承座之厚度之二分之一。 在前述之無外接腳式半導體封裝構造中’該晶片承座 之該内層圖案之厚度係可大於該外層圖案之厚度。 在前述之無外接腳式半導體封裝構造中，該晶片承座 之該内層圖案之面積係可大致與該晶片之設置表面相 9 1352415 等並且該内層圖案之周邊係為銘窗狀。 在前述之無外接腳式半導體封裝構造中，該封膠體係 可填滿該些外接墊與該外層圖案之間的縫隙。 在則述之無外接腳式半導體封裝構造中，該些外接墊 與該外層圖案之間的縫隙係可大於該些延長接指與該 外層圖案之縫隙。 在前述之無外接腳式半導體封裝構造中，該些導腳在該 些延長接指與該些外接墊之間係可形成有一内凹弧角。 【實施方式】 依據本發明之一具體實施例，請參閱第2圖所示， 具體揭示一種無外接腳式半導體封裝構造200,主要包 3日日片承座210、複數個導腳22〇、一晶片230、複 數個金屬線240以及一封膠體25〇。其中，該晶片承座 210與該些導腳22〇係可由一導線架取得並具有相同材 質，以降低製造成本。該晶片承座21〇與該些導腳22〇 之材質係可為易於蝕刻之金屬，例如銅、鐵或其合金。 晴參閱第2、3及4圖所示，該晶片承座21〇係具有 内層圖案211與一外層圖案212。其中，該内層圖案 1 1係小於該外層圖案2〗2 ’以致使該内層圖案2丨丨之 周邊形成複數個缺口 213 (如第5、6及7圖所示）。在本 實施例中’該内層圖案211之形狀如第3圖所示；該外 Q案212之形狀如第4圖所示。該晶片承座21〇係可 為倒τ形。該内層圖案2丨丨係作為與該晶片23〇黏貼之 内表面’其係可概呈矩形，以供該晶片23〇之設置。請 10 1352415 參閱第2及3圖所示，較佳地，該晶片承座210之 層圖案211之面積係可大致與該晶片230之設置表 等並且該内層圖案211之周邊係為鋸齒狀，可以減 内層圖案211在該晶片230之外的周邊面積，以避 晶片承座210在該晶片230周邊的區域與該封膠體 產生應力分層。在本實施例中，該晶片230之設置 即為該晶片230之背面，以黏貼至該内層圖案21 1 具體地，該晶片承座210之該内層圖案211之厚度 大於該外層圖案212之厚度。請參閱第5及6圖所 該些導腳220係排列在該晶片承座210之周邊。 請參閱第2圖所示，每一導腳2 20係具有一延 指221與一外接墊222。該外接墊222具有一外表 顯露於該封膠體25〇之底部’以供對外接合。該延 指22 1之厚度係小於該外接墊222之厚度》在本實 中，該延長接指221之厚度係可小於該外接墊222 度之二分之一。該延長接指221之長度係可大於該 墊222之長度。並且，如第6及7圖所示，該些延 指22 1係延伸至該些缺口 2 1 3内並局部重疊於該外 案212之周邊。因此’該些導腳220之截面係可呈 n形，即橫置L形（如第7圖所示），並往該内層圖案 之方向延伸（如第 2圖所示）而局部重疊在該外層 212之上。在本實施例中，該些延長接指221之厚 該外層圖案212之厚度以及由該些延長接指221至 層圖案2 1 2之垂直縫隙S2係可為相等，以使該些 該内 面相 少該 免該 250 表面 〇更 係可 示， 長接 面， 長接 施例 之厚 外接 長接 層圖 r或 211 圖案 度、 該外 延長 1352415 接指221之厚度概為該些導腳220之厚度的三 ’不與該外層圖案212電性接觸。 請參閱第2圖所示，該晶片230係設置於 座210之該内層圖案211上，該晶片230係具 電極231，例如銲墊，其係形成於主動面。該 係以該些電極231遠離該晶片承座210之方式 晶片承座2 10上，該些電極23 1係可位於該晶 主動面之周邊。在本實施例中，可利用一黏晶 _ 著該晶片230之一背面至該内層圖案211，以 為該晶片230之設置表面。 請參閱第2圖所示，該些金屬線2 4 0係連 230之該些電極231與該些導腳22〇之該些 2 2 1 ’以達到該晶片2 3 〇與該些導腳2 2 0之間 接。s玄些金屬線240係可為打線形成，其打線 形成方式係可以超音波接合、熱壓接合或熱超 • 等方式將該些金屬線之兩端連接在該晶片 導腳220以形成電性連接。在本實施例中，該 2 40係為金線。因此，利用該些延長接指221 金屬線240對該些導腳22〇的連接點，該些名 的長度可以有效縮短’以降低封裝成本以及种 請參閱第2圖所示，該封膠體25〇係密封寫 與該些金屬線240並電性絕緣地結合該些導胸 晶片承座210，但顯露該些導腳22〇之該些対 與該晶片承座210之該外層圖案212。該封膠 分之一且 該晶片承 有複數個 晶片230 設置於該 片230之 膠260黏 該背面作 接該晶片 延長接指 的電性連 接合點的 音波接合 230與該 些金屬線 改變該些 -屬線240 線風險。 :晶片230 220與該 接墊222 體250之 1352415 * 形成方式係可選自於模封（或稱轉移成形）與印刷等方 . 法之其中之一。由於該封膠體250係顯露該外層圖案 2 12,又該外層圖案212的面積能大幅擴大而與該些導 腳220局部重疊，故該外層圖案212能將該晶片2切所 產生的熱能傳遞至外界，以增加散熱效果。較佳地，該 些導腳220在該些延長接指221與該些外接墊222之間係 可形成有一内凹弧角223，用以導引該封膠體25〇以避免 _ 在空隙填充時產生孔隙與氣泡。 因此’藉由局部縮小該晶片承座2丨〇之設計（即該内 層圖案2 1 1小於該外層圖案2丨2)以及該些延長接指22 i 係延伸並重疊於該外層圖案2 i 2，能在維持一定的散熱 致能之條件下，有效縮短該些金屬線2 4 0之長度，以降 低元件成本與沖線風險並可避免該内層圖案211在該 晶片230周邊的區域產生應力分層，亦可縮小整體封裝 尺寸°該無外接腳式半導體封裝構造2〇〇可更適用於尺 籲 寸較小之晶片。並且’該外層圖案2 1 2係顯露於該封膠 體250’故可增進該晶片承座21〇之散熱效能。請同時 參閱第1與2圖’本發明之該晶片承座21〇之戴面係為 倒T形’習知晶片承座！ i 〇為τ形，本發明之晶片承座 210之外層圖案212之外露面積遠大於習知結構，故本 發明之無外接腳式半導體封裝構造2〇〇相較於習知無 外接腳式半導體封裝構造更具有較佳地散熱效果。 請參閱第2圖所示，在本實施例中，該黏晶膠260， 可形成於該晶片230與該内層圖案211之間。該黏晶膠 13 1352415 260係可利用網印或針筒點膠等方法塗佈在該晶片承座 210之該内廣圖案211上，用以黏貼該晶片23〇輿該内 層圖案2 11。該黏晶膠26〇係可選自於B階膠體與液感 膠之其中之一。較佳地，該黏晶膠2 6 〇係可更形成於該 些缺口 213内並黏著接觸該些延長接指221，利用固化 後之該黏晶膠2 6 0固定該些延長接指2 2 1，以避免打線 晃動並接觸該外層圖案212。光佳地，該内層圖案211 之周邊至該些缺口 2 1 3之間係可形成為倒斜角2 1 4 ’有 助於該黏晶膠260流入該些導腳220之該些延長接指 22 1與該晶片承座2 10之缝隙S2。請參閱第7圖所示’ 該些延長接指221係可具有位於該些缺口 213内之〆第 一截面銳角224，用以阻擋該黏晶膠260流佈至·該座延 長接指221之打線表面。請再參閱第7圖所示，該晶片 承座210之該外層圖案212係可具有一位於該射膠體 2 5〇底面之第二截面銳角215，用以阻擋該黏晶膠260 流佈至該外層圖案212之顯露表面。 請再參閱第7圖所示，較佳地，該些外接墊222與 該外層圖案2 1 2之間的縫隙S1係可大於該些延長接指 221與該外層圓案212之縫隙S2 ’以避免該黏晶膠26〇 流至上述縫隙S 1。該封膠體250係可填滿該些外接墊 222與該外層圖案2丨2之間的縫隙s卜以避免該黏晶膠 260外露（如第2圖所示）。 以上所述’僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，本發明技術方案範圍當依 14 工352415 所附申請專利範圍為準。任何熟悉本專業的技術人員可 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 容’依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】The body package is constructed so as to provide a gap between the extension of the die and the wafer 7 1352415, > Another object of the present invention is to provide an external legless semiconductor package construction to block the flow of adhesive to the wire surface of the extended fingers. Another object of the present invention is to provide an external pinless semiconductor package construction for blocking the flow of adhesive to the exposed surface of the wafer holder. Another object of the present invention is to provide a pedestal-free semiconductor package structure that avoids stress delamination at the periphery of the wafer by the B-plate holder. Another object of the present invention is to provide an external pinless semiconductor package construction that avoids the exposure of the adhesive. Another object of the present invention is to provide an external legless semiconductor package construction that avoids the generation of sealing bubbles. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, an external pinless semiconductor package structure mainly includes a wafer holder, a plurality of lead pins, a wafer, a plurality of metal wires, and a gel. The wafer holder has an inner layer pattern and an outer layer pattern, wherein the inner layer pattern is smaller than the outer layer pattern such that a plurality of notches are formed in the periphery of the inner layer pattern. Each of the legs has an extension finger and an outer pad, wherein the extension fingers extend into the notches and partially overlap the periphery of the outer pattern. The wafer is disposed on the inner layer pattern of the wafer holder, the wafer having a plurality of electrodes. The metal wires are connected to the electrodes of the wafer and the extension fingers of the leads. The encapsulation system seals the chip 1352415 with the metal wires and electrically insulatively bonds the leads and the wafer holder, but exposes the external pads of the guides and the outer pattern of the wafer holder . The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing external pinless semiconductor package structure, an adhesive may be further formed between the wafer and the inner layer pattern. In the foregoing external pin type semiconductor package structure, the adhesive layer may be formed in the notches and adhered to the extension fingers. In the above-described external pinless semiconductor package structure, the inner layer pattern and the notches may be formed as a chamfered angle. In the aforementioned external pinless semiconductor package construction, the extended fingers may have an acute angle of the first section located within the notches. In the foregoing external pinless semiconductor package construction, the outer pattern of the wafer holder may have a second cross-sectional acute angle on the bottom surface of the encapsulant. In the aforementioned external pin type semiconductor package structure, the material of the metal wires may comprise gold. In the pedestalless semiconductor package construction described above, the length of the extension fingers may be less than one-half the thickness of the wafer holder. In the foregoing external-footless semiconductor package construction, the thickness of the inner layer pattern of the wafer holder may be greater than the thickness of the outer layer pattern. In the above-described external pinless semiconductor package structure, the area of the inner layer pattern of the wafer holder may be substantially the same as the surface of the wafer, such as 9 1352415, and the periphery of the inner layer pattern is in the shape of a window. In the aforementioned external pinless semiconductor package construction, the encapsulation system can fill the gap between the outer pads and the outer layer pattern. In the outer-less semiconductor package structure described above, the gap between the outer pads and the outer layer pattern may be larger than the gap between the extended fingers and the outer layer pattern. In the external strapless semiconductor package structure described above, the lead pins may form a concave arc angle between the extension fingers and the external pads. [Embodiment] According to an embodiment of the present invention, as shown in FIG. 2, a pedestal-free semiconductor package structure 200 is disclosed, which mainly includes a 3-day Japanese wafer holder 210 and a plurality of guide pins 22, A wafer 230, a plurality of metal wires 240, and a colloid 25". The wafer holder 210 and the lead pins 22 can be obtained by a lead frame and have the same material to reduce the manufacturing cost. The material of the wafer holder 21 and the lead pins 22 can be a metal that is easy to etch, such as copper, iron or an alloy thereof. As shown in Figures 2, 3 and 4, the wafer holder 21 has an inner layer pattern 211 and an outer layer pattern 212. The inner layer pattern 1 1 is smaller than the outer layer pattern 2 ′ 2 ′ such that a plurality of notches 213 are formed around the inner layer pattern 2 ( (as shown in FIGS. 5 , 6 and 7 ). In the present embodiment, the shape of the inner layer pattern 211 is as shown in Fig. 3; the shape of the outer Q case 212 is as shown in Fig. 4. The wafer holder 21 can be inverted. The inner layer pattern 2 is an inner surface which is adhered to the wafer 23 and can be substantially rectangular for the wafer 23 to be disposed. 10 1352415, as shown in FIGS. 2 and 3, preferably, the area of the layer pattern 211 of the wafer holder 210 is substantially equal to the setting table of the wafer 230, and the periphery of the inner layer pattern 211 is serrated. The peripheral area of the inner layer pattern 211 outside the wafer 230 can be reduced to avoid stress delamination of the wafer holder 210 from the area around the wafer 230. In this embodiment, the wafer 230 is disposed on the back side of the wafer 230 to be adhered to the inner layer pattern 21 1 . Specifically, the thickness of the inner layer pattern 211 of the wafer holder 210 is greater than the thickness of the outer layer pattern 212 . Referring to Figures 5 and 6, the leads 220 are arranged around the wafer holder 210. Referring to Figure 2, each of the lead pins 20 has an extension 221 and an outer pad 222. The outer pad 222 has an outer surface that is exposed at the bottom of the encapsulant 25 to be externally joined. The thickness of the extension 22 1 is less than the thickness of the outer pad 222. In the present embodiment, the length of the extension finger 221 can be less than one-half of the thickness of the outer pad 222. The length of the extension finger 221 can be greater than the length of the pad 222. Further, as shown in Figs. 6 and 7, the extensions 22 1 extend into the notches 2 1 3 and partially overlap the periphery of the outer case 212. Therefore, the cross-sections of the guide pins 220 may be n-shaped, that is, transversely L-shaped (as shown in FIG. 7), and extend in the direction of the inner layer pattern (as shown in FIG. 2) to partially overlap the Above the outer layer 212. In this embodiment, the thickness of the outer layer pattern 212 of the extension fingers 221 and the vertical gap S2 of the extension fingers 221 to the layer pattern 2 1 2 may be equal, so that the inner surfaces are relatively small. The free surface of the 250 can be shown, the long joint, the thick outer joint length of the application example r or 211 pattern degree, the outer extension 1352415 the thickness of the joint 221 is the thickness of the guide legs 220 The three' does not electrically contact the outer layer pattern 212. Referring to Fig. 2, the wafer 230 is disposed on the inner layer pattern 211 of the holder 210. The wafer 230 is provided with an electrode 231, such as a pad, which is formed on the active surface. The electrodes 231 are located away from the wafer holder 210 on the wafer holder 2 10, and the electrodes 23 1 are located at the periphery of the crystal active surface. In this embodiment, a back surface of one of the wafers 230 may be utilized to the inner layer pattern 211 to provide a surface for the wafer 230. Referring to FIG. 2, the plurality of electrodes 231 of the metal wires 240 and 230 are connected to the pads 22 to reach the wafers 2 3 and the leads 2 2 0 is connected. The smectic metal wire 240 can be formed by wire bonding, and the wire forming method can connect the two ends of the metal wires to the wafer guiding pin 220 to form electrical properties by means of ultrasonic bonding, thermocompression bonding or thermal super-connection. connection. In this embodiment, the 420 is a gold wire. Therefore, by using the extension fingers 221 metal wires 240 to the connection points of the lead pins 22, the length of the names can be effectively shortened 'to reduce the packaging cost and the kind shown in FIG. 2, the encapsulant 25 The lanthanide seals are coupled to the plurality of metal wires 240 and electrically insulatively bonded to the pedestal wafer holders 210, but the ridges of the leads 22 and the outer pattern 212 of the wafer holder 210 are exposed. One of the sealants and the wafer carries a plurality of wafers 230. The glue 260 disposed on the sheet 230 adheres to the back side to form an acoustic bond 230 of the electrical connection point of the wafer extension finger, and the metal lines change the These - line 240 line risk. The way in which the wafer 230 220 and the pad 222 body 250 are formed may be selected from one of a method of molding (or transfer molding) and printing. Since the encapsulant 250 reveals the outer layer pattern 12, and the area of the outer layer pattern 212 can be greatly enlarged to partially overlap the lead pins 220, the outer layer pattern 212 can transfer the heat energy generated by the wafer 2 to the wafer 2 The outside world to increase the heat dissipation effect. Preferably, the guide pins 220 are formed with a concave arc angle 223 between the extension fingers 221 and the external pads 222 for guiding the sealant 25 to avoid _ when the gap is filled. Create pores and bubbles. Therefore, by locally reducing the design of the wafer holder 2 (ie, the inner layer pattern 21 is smaller than the outer pattern 2丨2) and the extension fingers 22 i extend and overlap the outer pattern 2 i 2 The length of the metal wires 240 can be effectively shortened under the condition of maintaining a certain heat dissipation capability, so as to reduce the component cost and the risk of punching and avoid the stress distribution of the inner layer pattern 211 in the region around the wafer 230. The layer can also reduce the overall package size. The external-footless semiconductor package structure 2 can be more suitable for wafers with smaller footprints. And the outer layer pattern 2 1 2 is exposed to the encapsulant 250 ′ to improve the heat dissipation performance of the wafer holder 21 . Please also refer to Figures 1 and 2. The wafer holder 21 of the present invention is an inverted T-shaped conventional wafer holder! i 〇 is τ-shaped, the exposed area of the outer layer pattern 212 of the wafer holder 210 of the present invention is much larger than the conventional structure, so the external-footless semiconductor package structure of the present invention is comparable to the conventional external-type semiconductor The package structure has a better heat dissipation effect. Referring to FIG. 2, in the embodiment, the adhesive 260 may be formed between the wafer 230 and the inner layer pattern 211. The adhesive 13 1352415 260 can be applied to the inner pattern 211 of the wafer holder 210 by screen printing or syringe dispensing to adhere the wafer 23 to the inner pattern 2 11 . The viscous gel 26 can be selected from one of a B-stage colloid and a liquid gutta-percha. Preferably, the adhesive layer of the adhesive is formed in the notches 213 and adheres to the extension fingers 221, and the extension contacts 2 2 are fixed by the cured adhesive 210. 1. Avoid line sloshing and contact the outer layer pattern 212. Preferably, the periphery of the inner layer pattern 211 to the notches 2 1 3 may be formed as a chamfer angle 2 1 4 ′ to facilitate the flow of the adhesive glue 260 into the extension fingers of the guide pins 220 . 22 1 is a gap S2 with the wafer holder 2 10 . Referring to FIG. 7 , the extension fingers 221 can have a first section acute angle 224 located in the notches 213 for blocking the flow of the adhesive 260 to the extension of the extension finger 221 . surface. Referring to FIG. 7, the outer layer pattern 212 of the wafer holder 210 can have a second acute angle 215 at the bottom surface of the adhesive body to block the adhesive 260 from flowing to the outer layer. The exposed surface of pattern 212. Please refer to FIG. 7 again. Preferably, the gap S1 between the outer pad 222 and the outer layer pattern 2 1 2 may be larger than the gap S2 ' between the extension fingers 221 and the outer circle 212. The adhesive glue 26 is prevented from flowing to the slit S1. The encapsulant 250 can fill the gap between the outer pad 222 and the outer layer pattern 2丨2 to prevent the adhesive 260 from being exposed (as shown in FIG. 2). The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art can make a few changes or modifications to the equivalent embodiments by using the technical content disclosed above, but the content without departing from the technical solution of the present invention is made according to the technical essence of the present invention. Any simple modifications, equivalent changes and modifications are still within the scope of the technical solutions of the present invention. [Simple description of the map]
第1圖：習知無外接腳式半導體封裝構造之截面示意圖。 第2圖：依據本發明之—具體實施例，一種無外接腳式 半導體封裝構造之戴面示意圖。 第3圖：依據本發明之一具體實施例，該無外接腳式半 導體封裝構造之晶片承座之内層圖案示意圖。 第4圖：依據本發明之一具體實施例，該無外接腳式半 導體封裝構造之晶片承座之外層圖案示意圖。 圖依據本發明之一具體實施例，該無外接腳式半 導體封裝構造在設置晶片之前所使用導線架之平 面示意圖。 第6 依據本發明之一具體實施例，該無外接腳式半 導體封裝構造在設置晶#之前之導線架局部示意 第 圖.依據本發明之一且魏眘始η '、體實施例，該無外接腳式半 導體封裝構造沿第6圖7_7剖 Γ ± ^ d切碌之截面不意圖。 1主要兀件符號說明】 園 ⑽半導體封裝構造 15 1352415 110 晶片承座 111黏晶表面 112 散熱表面 120 導腳 121上表面 122 下表面 130 晶片 131電極 140 金屬線 150封膠體 160 黏晶膠 200 無外接腳式半導體封裝構造 210 晶片承座 211内層圖案 212 外層圖案 213 缺口 214倒斜角 215 第二截面銳角 220 導腳 221延長接指 222 外接墊 223 内凹弧角 224第一截面銳角 230 晶片 231電極 240 金屬線 250封膠體 260 黏晶膠 SI 縫隙 S2 縫隙Figure 1: Schematic cross-sectional view of a conventional semiconductor package structure without external pins. Figure 2 is a schematic illustration of a wear surface without a pedestal-type semiconductor package construction in accordance with an embodiment of the present invention. Figure 3 is a schematic illustration of the inner layer pattern of the wafer carrier without the external leg semiconductor package construction in accordance with an embodiment of the present invention. Figure 4 is a schematic view showing the pattern of the outer layer of the wafer holder without the external-pin semiconductor package structure in accordance with an embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS In accordance with one embodiment of the present invention, the pedestalless semiconductor package is constructed as a plan view of a leadframe used prior to placement of the wafer. According to a specific embodiment of the present invention, the lead-free semiconductor package structure is partially illustrated in the lead frame before the setting of the crystal #. According to one of the inventions and the Wei Shenshi η ', the body embodiment, the The external pin type semiconductor package structure is not intended to be cut along the line of Fig. 6-7. 1 main element symbol description] garden (10) semiconductor package structure 15 1352415 110 wafer holder 111 adhesive surface 112 heat dissipation surface 120 lead 121 upper surface 122 lower surface 130 wafer 131 electrode 140 metal wire 150 sealant 160 adhesive plastic 200 External pin semiconductor package structure 210 wafer holder 211 inner layer pattern 212 outer layer pattern 213 notch 214 chamfer angle 215 second section acute angle 220 lead 221 extension finger 222 external pad 223 concave arc angle 224 first section acute angle 230 wafer 231 Electrode 240 metal wire 250 sealant 260 adhesive crystal SI slit S2 gap
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