[go: up one dir, main page]

TWI828198B - Lead frame sheet, lead frame and manufacturing method thereof, electronic component and manufacturing method thereof - Google Patents

Lead frame sheet, lead frame and manufacturing method thereof, electronic component and manufacturing method thereof Download PDF

Info

Publication number
TWI828198B
TWI828198B TW111122482A TW111122482A TWI828198B TW I828198 B TWI828198 B TW I828198B TW 111122482 A TW111122482 A TW 111122482A TW 111122482 A TW111122482 A TW 111122482A TW I828198 B TWI828198 B TW I828198B
Authority
TW
Taiwan
Prior art keywords
lead frame
frame
lead
manufacturing
chip
Prior art date
Application number
TW111122482A
Other languages
Chinese (zh)
Other versions
TW202401679A (en
Inventor
陳威辰
Original Assignee
福懋科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 福懋科技股份有限公司 filed Critical 福懋科技股份有限公司
Priority to TW111122482A priority Critical patent/TWI828198B/en
Application granted granted Critical
Publication of TWI828198B publication Critical patent/TWI828198B/en
Publication of TW202401679A publication Critical patent/TW202401679A/en

Links

Images

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

A lead frame sheet including a die seat, a frame and a plurality of leads is provided. The frame is adjacent to the die seat. The plurality of leads extend from the frame to the die seat adjacent to the frame respectively. The lead frame sheet has an upper surface and a lower surface that oppose to each other. The upper width of a first portion of the lead on the upper surface is smaller than the lower width of the first portion of the lead on the lower surface.

Description

導線架料片、導線架及其製造方法、電子元件及其製造方法Lead frame sheet, lead frame and manufacturing method thereof, electronic components and manufacturing method thereof

本發明是有關於一種導線架料片、導線架及其製造方法、電子元件及其製造方法。The invention relates to a lead frame piece, a lead frame and a manufacturing method thereof, electronic components and a manufacturing method thereof.

導線架一般是藉由導線架料片切割而成。隨著電子元件技術的發展,導線架產品的設計精密度上升及/或晶片輸出輸入(input/output,I/O)數增加,導腳設計的排列密度也需隨著增加。針對具有小間距(fine pitch)導腳的之產品,其切割精度的要求度也需更高。Lead frames are generally cut from lead frame sheets. With the development of electronic component technology, the design precision of lead frame products has increased and/or the number of chip input/output (I/O) has increased, and the arrangement density of pin design has also increased. For products with fine pitch leads, the requirements for cutting accuracy are also higher.

然而,在進行導線架料片切割的過程中,可能會因為切割時的金屬面延展而產生毛刺或拉伸的問題。這可能會造成切割後的導腳與導腳之間的空隙(space)不足,且/或可能會有電性短接(short)的風險。However, during the cutting process of the lead frame blanks, burrs or stretching problems may occur due to the extension of the metal surface during cutting. This may result in insufficient space between the cut leads and/or the risk of electrical shorts.

本發明提供一種導線架料片、導線架及其製造方法、電子元件及其製造方法。The invention provides a lead frame piece, a lead frame and a manufacturing method thereof, electronic components and a manufacturing method thereof.

本發明的導線架料片包括晶片座、框以及多個的導腳。框相鄰於晶片座。多個的導腳分別自框向相鄰於框的晶片座延伸。導線架料片具有彼此相對的上表面和下表面。導腳的第一部分在上表面上的上寬度小於在下表面上的下寬度。The lead frame piece of the present invention includes a chip holder, a frame and a plurality of lead pins. The frame is adjacent to the wafer mount. A plurality of lead pins respectively extend from the frame to the chip holder adjacent to the frame. The leadframe blank has upper and lower surfaces opposite each other. The first portion of the lead has an upper width on the upper surface that is smaller than a lower width on the lower surface.

在本發明的一實施例中,導腳的第一部分與框相連。In an embodiment of the invention, the first portion of the lead is connected to the frame.

在本發明的一實施例中,導腳更包括與第一部分相連的第二部分,且於俯視狀態下,第二部分的最大寬度大於第一部分的最大寬度。In an embodiment of the invention, the lead further includes a second part connected to the first part, and in a top view, the maximum width of the second part is greater than the maximum width of the first part.

在本發明的一實施例中,上寬度與下寬度的比基本上為3:4。In an embodiment of the invention, the ratio of the upper width to the lower width is substantially 3:4.

在本發明的一實施例中,導線架料片的材質為銅,且其中上寬度最小為100微米。In one embodiment of the present invention, the lead frame piece is made of copper, and its upper width is at least 100 microns.

本發明的導線架的製造方法包括以下步驟:提供前述實施例的導線架料片;以及至少移除導線架料片的框,以形成導線架。The manufacturing method of the lead frame of the present invention includes the following steps: providing the lead frame piece of the previous embodiment; and removing at least the frame of the lead frame piece to form the lead frame.

本發明的導線架,其包括由前述實施例的導線架料片移除框後所形成。The lead frame of the present invention is formed by removing the frame from the lead frame piece of the previous embodiment.

本發明的電子元件的製造方法包括以下步驟:提供前述實施例的導線架料片;配置晶片於晶片座上;使晶片電性連接於多個的導腳;以及至少移除導線架料片的框。The manufacturing method of electronic components of the present invention includes the following steps: providing the lead frame blank of the aforementioned embodiment; arranging the chip on the chip holder; electrically connecting the chip to a plurality of lead pins; and removing at least the lead frame blank frame.

本發明的電子元件包括:由前述實施例的導線架料片移除框後所形成的導線架以及晶片。晶片配置於晶片座上且電性連接於多個的導腳。The electronic component of the present invention includes: a lead frame and a chip formed by removing the frame from the lead frame piece of the previous embodiment. The chip is arranged on the chip holder and electrically connected to a plurality of pins.

基於上述,本發明的導線架料片在應用上(如:製造對應的導線架或電子元件)可以具有較佳的品質。Based on the above, the lead frame blank of the present invention can have better quality in applications (such as manufacturing corresponding lead frames or electronic components).

以下將參照本實施例之圖式以更全面地闡述本發明。然而,本發明亦可以各種不同的形式體現,而不應限於本文中所述之實施例。圖式中的層、區域或元件的尺寸可能會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件,以下段落將不再一一贅述。另外,實施例中所提到的方向用語,例如:上或下,僅是參考附加圖式的方向。因此,使用的方向用語是用來說明並非用來限制本發明。The present invention will be described more fully below with reference to the drawings of this embodiment. However, the present invention may also be embodied in various forms and should not be limited to the embodiments described herein. The dimensions of layers, regions or elements in the drawings may be exaggerated for clarity. The same or similar reference numbers indicate the same or similar components, and will not be repeated one by one in the following paragraphs. In addition, the directional terms mentioned in the embodiments, such as up or down, are only for reference to the directions in the attached drawings. Accordingly, the directional terms used are illustrative and not limiting of the invention.

圖1A是依照本發明的一實施例的一種導線架料片的俯視示意圖。圖1B是依照本發明的一實施例的一種導線架料片的部分俯視示意圖。圖1C是依照本發明的一實施例的一種導線架料片的部分剖視示意圖。舉例而言,圖1B可以是對應於圖1A中區域R1的放大圖,且/或圖1C可以是對應於圖1B中I-I’剖線上的剖視示意圖。1A is a schematic top view of a lead frame piece according to an embodiment of the present invention. 1B is a partial top view of a lead frame piece according to an embodiment of the present invention. 1C is a partial cross-sectional view of a lead frame piece according to an embodiment of the present invention. For example, FIG. 1B may be an enlarged view corresponding to the region R1 in FIG. 1A, and/or FIG. 1C may be a schematic cross-sectional view corresponding to the I-I' line in FIG. 1B.

請參照圖1A至圖1C,導線架料片100可以包括晶片座130、框110以及多個的導腳120。框110相鄰於晶片座130。多個的導腳120分別自框110向相鄰於框110的晶片座130延伸。導線架料片100具有彼此相對的上表面S1和下表面S2。導腳120的第一部分121在上表面S1上的上寬度WS1小於在下表面S2上的下寬度WS2。Referring to FIGS. 1A to 1C , the lead frame piece 100 may include a chip holder 130 , a frame 110 and a plurality of lead pins 120 . Frame 110 is adjacent to wafer mount 130 . The plurality of lead pins 120 respectively extend from the frame 110 to the wafer holder 130 adjacent to the frame 110 . The leadframe blank 100 has an upper surface S1 and a lower surface S2 opposite to each other. The upper width WS1 of the first portion 121 of the lead 120 on the upper surface S1 is smaller than the lower width WS2 on the lower surface S2.

在一實施例中,導線架料片100的材質可以為銅。In one embodiment, the lead frame piece 100 may be made of copper.

在一實施例中,導線架料片100可以先藉由沖壓、雷射切割或其他適當的製作方式而形成大致的形狀或圖案(後述可被稱為:初始導線架料片),然後,可以藉由蝕刻(如:濕蝕刻)的方式,以使導腳120的第一部分121在上表面S1上的上寬度WS1小於在下表面S2上的下寬度WS2。舉例而言,可以將初始導線架料片中不欲被蝕刻處以保護材料(如:保護膠)覆蓋;然後,將已被前述保護材料所部分覆蓋的初始導線架料片置於蝕刻劑中,以使導腳120的第一部分121在上表面S1上的上寬度小於在下表面S2上的下寬度;然後,移除前述的保護材料,以形成如圖1A至圖1C所示的導線架料片100。In one embodiment, the lead frame blank 100 may be first formed into a rough shape or pattern by stamping, laser cutting or other appropriate manufacturing methods (hereinafter referred to as: initial lead frame blank), and then, By etching (eg, wet etching), the upper width WS1 of the first portion 121 of the lead 120 on the upper surface S1 is smaller than the lower width WS2 on the lower surface S2. For example, the parts of the initial lead frame piece that are not to be etched can be covered with a protective material (such as protective glue); then, the initial lead frame piece that has been partially covered by the protective material is placed in the etchant. So that the upper width of the first part 121 of the lead 120 on the upper surface S1 is smaller than the lower width on the lower surface S2; then, the aforementioned protective material is removed to form a lead frame piece as shown in FIGS. 1A to 1C 100.

在一實施例中,導線架料片100可以包括外框111(框110的一部分)、內框112(框110的另一部分)、多個晶片座130、多個繫條(tie bar/support bar)140以及多個導腳120。外框111為導線架料片100最外圍的環狀框110。內框112在相鄰的兩個晶片座130之間。繫條140連接對應的晶片座130和框110的對應部分。各個導腳120分別自框110的對應處向相鄰於其的對應晶片座130延伸。另外,為求清楚表示,於對應或類似圖式中並未一一地標示所有的晶片座130、繫條140或導腳120。In one embodiment, the leadframe blank 100 may include an outer frame 111 (a part of the frame 110), an inner frame 112 (another part of the frame 110), a plurality of wafer holders 130, a plurality of tie bars/support bars. ) 140 and a plurality of lead pins 120. The outer frame 111 is the outermost annular frame 110 of the lead frame piece 100 . The inner frame 112 is between two adjacent wafer holders 130 . Ties 140 connect corresponding wafer holders 130 and corresponding portions of the frame 110 . Each lead 120 extends from a corresponding position of the frame 110 to a corresponding wafer base 130 adjacent thereto. In addition, for clarity of illustration, not all chip holders 130 , tie bars 140 or lead pins 120 are labeled one by one in corresponding or similar figures.

在一實施例中,導腳120可以包括第一部分121和第二部分122。於俯視狀態(即,在上表面S1或下表面S2的一法方向上看,如圖1B所示)下,第一部分121的相對兩端分別連接內框112和第二部分122。第二部分122的最大寬度W2大於第一部分121的最大寬度W1。在一示例性地應用中,具有較大寬度的第二部分122(相較於具有較小寬度的第一部分121)適宜被做為打線(wire bonding)的接合處。In an embodiment, the lead 120 may include a first portion 121 and a second portion 122 . In a top view (that is, viewed in a normal direction of the upper surface S1 or the lower surface S2, as shown in FIG. 1B ), the opposite ends of the first part 121 are respectively connected to the inner frame 112 and the second part 122 . The maximum width W2 of the second portion 122 is greater than the maximum width W1 of the first portion 121 . In an exemplary application, the second portion 122 with a larger width (compared to the first portion 121 with a smaller width) is suitable for being used as a wire bonding joint.

在一實施例中,導腳120由第一部分121和第二部分122組成。In one embodiment, the lead 120 is composed of a first part 121 and a second part 122 .

在一實施例中,導腳120由第一部分121和第二部分122組成,且第二部分122任意一區域(如:類似於圖1C所示,對第二部分122任意處進行垂直於上表面S1或下表面S2的剖面視之)在上表面S1上的對應寬度基本上相同於在下表面S2上的對應寬度。In one embodiment, the lead 120 is composed of a first part 121 and a second part 122, and any area of the second part 122 (for example, similar to that shown in FIG. 1C, any part of the second part 122 is perpendicular to the upper surface). The corresponding width on the upper surface S1 is substantially the same as the corresponding width on the lower surface S2 (viewed in cross section of S1 or lower surface S2).

在一實施例中,上寬度WS1與下寬度WS2的比基本上為3:4。值得注意的是,前述基本上為3:4的「基本上」用語可以包括製作上的可接受容許範圍(約為±15%),如3:4×(1-15%)~3:4×(1+15%)。舉例而言,上寬度WS1可以約為100微米(micrometer,µm),且下寬度WS2可以約為150微米。In one embodiment, the ratio of the upper width WS1 to the lower width WS2 is substantially 3:4. It is worth noting that the aforementioned "basically" term of basically 3:4 can include the acceptable allowable range in production (about ±15%), such as 3:4×(1-15%)~3:4 ×(1+15%). For example, the upper width WS1 may be approximately 100 micrometer (µm), and the lower width WS2 may be approximately 150 micrometer.

在一實施例中,由於第一部分121在上表面S1上的上寬度WS1小於在下表面S2上的下寬度WS2,因此,在藉由導線架料片100進行切割而製作導線架的過程中,可以降低因為金屬延展(如:銅延展)而造成相鄰的導腳120相接觸的可能。In one embodiment, since the upper width WS1 of the first portion 121 on the upper surface S1 is smaller than the lower width WS2 on the lower surface S2, during the process of manufacturing the lead frame by cutting the lead frame blank 100, This reduces the possibility that adjacent leads 120 may come into contact due to metal extension (such as copper extension).

在一實施例中,上寬度WS1最小為100微米。如此一來,可以降低以銅為材質的導線架料片100斷線的可能。In one embodiment, the upper width WS1 is at least 100 microns. In this way, the possibility of wire breakage of the lead frame piece 100 made of copper can be reduced.

在一實施例中,第一部分121的長度L1約為50微米至200微米。若長度小於50微米,則在進行切割過程中,可能會降低製程裕度(process window)。若長度大於200微米,則可能會降低第二部分122的施作空間。舉例而言,第一部分121的長度L1可以約為100微米。In one embodiment, the length L1 of the first portion 121 is approximately 50 microns to 200 microns. If the length is less than 50 microns, the process window may be reduced during cutting. If the length is greater than 200 microns, the application space of the second part 122 may be reduced. For example, the length L1 of the first portion 121 may be approximately 100 microns.

圖2A是依照本發明的一實施例的一種導線架的部分製造方法的俯視示意圖。圖2B是依照本發明的一實施例的一種導線架的俯視示意圖。圖2C是依照本發明的一實施例的一種導線架的部分俯視示意圖。圖2D是依照本發明的一實施例的一種導線架的部分剖視示意圖。FIG. 2A is a schematic top view of a partial manufacturing method of a lead frame according to an embodiment of the present invention. FIG. 2B is a schematic top view of a lead frame according to an embodiment of the present invention. FIG. 2C is a partial top view of a lead frame according to an embodiment of the present invention. FIG. 2D is a partial cross-sectional view of a lead frame according to an embodiment of the present invention.

請參照圖2A至圖2B,導線架200的製造方法可以包括以下步驟:提供前述實施例的導線架料片100;然後,至少移除導線架料片100的框110,以形成導線架。Referring to FIGS. 2A and 2B , the manufacturing method of the lead frame 200 may include the following steps: providing the lead frame piece 100 of the aforementioned embodiment; and then removing at least the frame 110 of the lead frame piece 100 to form the lead frame.

至少移除內框112的步驟可以相同或相似於一般由導線架料片進行切割而製作導線架的過程,差別在於:為使用本發明一實施例的導線架料片100;故,於此不加以詳述。簡單地舉例而言,可以將導線架料片100置於載板290上;然後,藉由切割刀沿著切割線CL進行切割。At least the step of removing the inner frame 112 may be the same or similar to the general process of cutting a lead frame sheet to make a lead frame. The difference is that the lead frame sheet 100 according to an embodiment of the present invention is used; therefore, no steps are performed here. Elaborate. For a simple example, the lead frame piece 100 can be placed on the carrier plate 290 and then cut along the cutting line CL with a cutting knife.

在一實施例中,於進行前述的切割過程中,部分的第一部分121也可能被移除。並且,由於第一部分121在上表面S1上的上寬度WS1小於在下表面S2上的下寬度WS2,因此,在藉由導線架料片100進行切割而製作導線架200的過程中,可以降低因為金屬延展(如:銅延展)而造成導腳120相接觸的可能。另外,為求簡單表示,縱使部分的第一部分121也可能被移除,但在部分的標示上仍可以援引原先的標示(如:導腳120或第一部分121)。繫條140亦可若是。In one embodiment, part of the first portion 121 may also be removed during the aforementioned cutting process. Furthermore, since the upper width WS1 of the first portion 121 on the upper surface S1 is smaller than the lower width WS2 on the lower surface S2, the metal due to metal can be reduced during the process of cutting the lead frame blank 100 to produce the lead frame 200. The lead pins 120 may be in contact due to extension (such as copper extension). In addition, for simplicity of representation, even though the first part 121 of the part may also be removed, the original identification (such as the lead 120 or the first part 121) can still be quoted on the part's identification. Tie 140 can also be used.

完成前述切割過程後所形成的導線架200可以如圖2B至圖2D所示。圖2C可以是類似或對應於圖1A中區域R1的放大圖,並且,為求對照(如:圖2A及圖2B間的比較),被切割移除的區域外圍在圖2C中以點線表示。圖2D可以是對應於圖2C中切割處的邊緣(如:II-II’面)上的側視示意圖。The lead frame 200 formed after completing the foregoing cutting process can be shown in FIGS. 2B to 2D . FIG. 2C may be an enlarged view similar to or corresponding to the area R1 in FIG. 1A , and for comparison purposes (such as comparison between FIG. 2A and FIG. 2B ), the periphery of the cut and removed area is represented by a dotted line in FIG. 2C . FIG. 2D may be a schematic side view corresponding to the edge of the cutting point in FIG. 2C (eg, II-II' plane).

如圖2B至圖2D,在進行切割而製作導線架200的過程之後,切割處的邊緣可能會具有因為金屬延展(如:銅延展)而形成的切割痕。舉例而言,如圖2C及2D所示,在第一部分121被切割處的邊緣,沿著切割方向D1上,於上表面S1上可以具有彼此相對的第一端點T1及第二端點T2,且於下表面S2上可以具有彼此相對的第三端點T3及第四端點T4。第一端點T1與第三端點T3的連線與一平行於上表面S1或下表面S2的虛擬面之間具有第一夾角(以所夾的銳角定義)θ1,第二端點T2與第四端點T4的連線與一平行於上表面S1或下表面S2的虛擬面之間具有第二夾角(以所夾的直角或銳角定義)θ2,且第二夾角θ2的角度大於第一夾角θ1的角度。並且,在第一部分121被切割處的邊緣,上表面S1上的上寬度WS3小於在下表面S2上的下寬度WS4。As shown in FIGS. 2B to 2D , after cutting to make the lead frame 200 , the edge of the cut may have cutting marks formed by metal extension (eg, copper extension). For example, as shown in FIGS. 2C and 2D , the edge of the first portion 121 where it is cut along the cutting direction D1 may have a first end point T1 and a second end point T2 opposite to each other on the upper surface S1 . , and may have a third endpoint T3 and a fourth endpoint T4 opposite to each other on the lower surface S2. The line connecting the first endpoint T1 and the third endpoint T3 has a first included angle (defined by the acute angle) θ1 between a virtual surface parallel to the upper surface S1 or the lower surface S2, and the second endpoint T2 is There is a second included angle (defined by the right angle or acute angle) θ2 between the line connecting the fourth endpoint T4 and a virtual surface parallel to the upper surface S1 or the lower surface S2, and the second included angle θ2 is greater than the first The angle between angle θ1. Also, at the edge where the first portion 121 is cut, the upper width WS3 on the upper surface S1 is smaller than the lower width WS4 on the lower surface S2.

圖3是依照本發明的一實施例的一種電子元件的部分製造方法的俯視示意圖。3 is a schematic top view of a partial manufacturing method of an electronic component according to an embodiment of the present invention.

請參照圖3,電子元件的製造方法可以不限順序地包括以下步驟:提供前述實施例的導線架料片100(標示於圖1A);配置晶片230於晶片座130上;使配置於晶片座130上的晶片230電性連接於多個的導腳120;以及至少移除導線架料片100的內框112(標示於圖1A)。值得注意的是,本發明並未限定將配置晶片230於晶片座130上的步驟以及移除導線架料片100的內框112的步驟的先後順序。Referring to FIG. 3 , the manufacturing method of electronic components may include the following steps in any order: providing the lead frame piece 100 of the aforementioned embodiment (marked in FIG. 1A ); arranging the chip 230 on the chip holder 130 ; The chip 230 on the chip 130 is electrically connected to the plurality of leads 120; and at least the inner frame 112 of the lead frame blank 100 is removed (marked in FIG. 1A). It is worth noting that the present invention does not limit the order of the steps of disposing the chip 230 on the chip holder 130 and removing the inner frame 112 of the lead frame blank 100 .

在一實施例中,配置晶片230於晶片座130上的步驟可以藉由一般晶片封裝製造中常用的方式(如:取放製程(pick up and place process))進行。In one embodiment, the step of disposing the chip 230 on the chip holder 130 can be performed by a method commonly used in general chip packaging manufacturing (such as a pick up and place process).

在一實施例中,使配置於晶片座130上的晶片230電性連接於多個的導腳120的步驟可以藉由一般晶片封裝製造中常用的方式(如:打線製程(wire bonding process))進行。舉例而言,配置晶片230於晶片座130上的晶片230可以藉由對應的導線320電性連接於對應的導腳120。另外,為求清楚表示,於對應圖式中並未一一地標示所有的晶片230或導線320。In one embodiment, the step of electrically connecting the chip 230 disposed on the chip holder 130 to the plurality of pins 120 can be performed by a method commonly used in general chip packaging manufacturing (such as a wire bonding process). conduct. For example, the chip 230 disposed on the chip holder 130 can be electrically connected to the corresponding lead 120 through the corresponding wire 320 . In addition, for clarity of illustration, not all chips 230 or wires 320 are labeled one by one in the corresponding figures.

在一實施例中,移除導線架料片100的內框112的步驟可以藉由前述的方式(如:對應於圖2A至圖2D中所敘及的方式)進行。In one embodiment, the step of removing the inner frame 112 of the lead frame piece 100 can be performed in the aforementioned manner (eg, corresponding to the manner described in FIGS. 2A to 2D ).

在一實施例中,於使配置於晶片座130上的晶片230電性連接於多個的導腳120之後,可以進行一般晶片封裝製造中常用的模塑製程(molding process)。舉例而言,可以藉由環氧樹脂(epoxy resin)或其他適宜的模塑料(molding compound)包封晶片230。In one embodiment, after the chip 230 disposed on the chip holder 130 is electrically connected to the plurality of pins 120 , a molding process commonly used in general chip packaging manufacturing may be performed. For example, the chip 230 may be encapsulated with epoxy resin or other suitable molding compound.

藉由上述步驟及使用前述實施例的導線架料片100,可以製造電子元件。在一實施例中,前述的電子元件可以被稱為四方平面無導腳封裝(Quad Flat No-Lead,QFN)或雙平面無導腳封裝(Dual Flat No-Lead,DFN)。前述的電子元件大致上的外觀可以相同或相似於常見的四方平面無導腳封裝或雙平面無導腳封裝,故於此不加以重覆繪示。Through the above steps and using the lead frame blank 100 of the above embodiment, electronic components can be manufactured. In one embodiment, the aforementioned electronic component may be called a Quad Flat No-Lead (QFN) package or a Dual Flat No-Lead (DFN) package. The general appearance of the aforementioned electronic components may be the same or similar to that of a common quadrilateral planar leadless package or a biplanar leadless package, and therefore will not be repeated here.

綜上所述,本發明的導線架料片在應用上(如:製造對應的導線架或電子元件)可以具有較佳的品質。To sum up, the lead frame blank of the present invention can have better quality in applications (such as manufacturing corresponding lead frames or electronic components).

100:導線架料片 110:框 111:外框 112:內框 120:導腳 121:第一部分 122:第二部分 130:晶片座 140:繫條 200:導線架 230:晶片 320:導線 CL:切割線 D1:切割方向 L1:長度 R1:區域 S1:上表面 S2:下表面 T1:第一端點 T2:第二端點 T3:第三端點 T4:第四端點 W1、W2:最大寬度 WS1、WS3:上寬度 WS2、WS4:下寬度 θ1:第一夾角 θ2:第二夾角 100: Lead frame blank 110:Box 111:Outer frame 112:Inner frame 120:Leader 121:Part One 122:Part 2 130:Chip holder 140:tie 200: Lead frame 230:Chip 320:Wire CL: cutting line D1: cutting direction L1:Length R1:Region S1: upper surface S2: Lower surface T1: first endpoint T2: second endpoint T3: third endpoint T4: The fourth endpoint W1, W2: maximum width WS1, WS3: upper width WS2, WS4: lower width θ1: the first included angle θ2: The second included angle

圖1A是依照本發明的一實施例的一種導線架料片的俯視示意圖。 圖1B是依照本發明的一實施例的一種導線架料片的部分俯視示意圖。 圖1C是依照本發明的一實施例的一種導線架料片的部分剖視示意圖。 圖2A是依照本發明的一實施例的一種導線架的部分製造方法的俯視示意圖。 圖2B是依照本發明的一實施例的一種導線架的俯視示意圖。 圖2C是依照本發明的一實施例的一種導線架的部分俯視示意圖。 圖2D是依照本發明的一實施例的一種導線架的部分側視示意圖。 圖3是依照本發明的一實施例的一種電子元件的部分製造方法的俯視示意圖。 1A is a schematic top view of a lead frame piece according to an embodiment of the present invention. 1B is a partial top view of a lead frame piece according to an embodiment of the present invention. 1C is a partial cross-sectional view of a lead frame piece according to an embodiment of the present invention. FIG. 2A is a schematic top view of a partial manufacturing method of a lead frame according to an embodiment of the present invention. FIG. 2B is a schematic top view of a lead frame according to an embodiment of the present invention. FIG. 2C is a partial top view of a lead frame according to an embodiment of the present invention. FIG. 2D is a partial side view of a lead frame according to an embodiment of the present invention. 3 is a schematic top view of a partial manufacturing method of an electronic component according to an embodiment of the present invention.

S1:上表面 S2:下表面 WS1:上寬度 WS2:下寬度 S1: upper surface S2: Lower surface WS1: Top width WS2: lower width

Claims (6)

一種導線架料片,包括:晶片座;框,相鄰於所述晶片座;以及多個的導腳,分別自所述框向相鄰於所述框的所述晶片座延伸,所述導腳包括相連的第一部分和第二部分,其中:所述導腳的所述第一部分與所述框相連;所述導線架料片具有彼此相對的上表面和下表面;所述第一部分在所述上表面上的上寬度小於在所述下表面上的下寬度所述導線架料片為全銅材質;所述上寬度最小為100微米;且所述第一部分的長度為50微米至200微米。 A lead frame piece includes: a chip holder; a frame adjacent to the wafer holder; and a plurality of lead pins extending from the frame to the wafer holder adjacent to the frame, the guide pins extending from the frame to the wafer holder adjacent to the frame. The foot includes a first portion and a second portion connected, wherein: the first portion of the lead pin is connected to the frame; the lead frame piece has an upper surface and a lower surface opposite to each other; the first portion is on the The upper width on the upper surface is smaller than the lower width on the lower surface. The lead frame piece is made of all copper; the upper width is at least 100 microns; and the length of the first part is 50 microns to 200 microns. . 如請求項1所述的導線架料片,其中所述上寬度與所述下寬度的比基本上為3:4。 The leadframe blank as claimed in claim 1, wherein the ratio of the upper width to the lower width is substantially 3:4. 一種導線架的製造方法,包括:提供如請求項1所述的導線架料片;以及至少移除所述導線架料片的所述框,以形成所述導線架。 A method of manufacturing a lead frame, including: providing the lead frame piece as claimed in claim 1; and removing at least the frame of the lead frame piece to form the lead frame. 一種導線架,包括:由如請求項1所述的導線架料片移除所述框後所形成。 A lead frame, comprising: a lead frame piece as described in claim 1, which is formed by removing the frame. 一種電子元件的製造方法,包括:提供如請求項1所述的導線架料片; 配置晶片於所述晶片座上;使所述晶片電性連接於多個的所述導腳;以及至少移除所述導線架料片的所述框。 A method of manufacturing electronic components, including: providing the lead frame sheet as described in claim 1; disposing a chip on the chip holder; electrically connecting the chip to a plurality of the lead pins; and removing at least the frame of the leadframe blank. 一種電子元件,包括:由如請求項1所述的導線架料片移除所述框後所形成的導線架;以及晶片,配置於所述晶片座上且電性連接於多個的所述導腳。 An electronic component, including: a lead frame formed by removing the frame from the lead frame piece as described in claim 1; and a chip arranged on the chip seat and electrically connected to a plurality of the Lead pin.
TW111122482A 2022-06-16 2022-06-16 Lead frame sheet, lead frame and manufacturing method thereof, electronic component and manufacturing method thereof TWI828198B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW111122482A TWI828198B (en) 2022-06-16 2022-06-16 Lead frame sheet, lead frame and manufacturing method thereof, electronic component and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW111122482A TWI828198B (en) 2022-06-16 2022-06-16 Lead frame sheet, lead frame and manufacturing method thereof, electronic component and manufacturing method thereof

Publications (2)

Publication Number Publication Date
TWI828198B true TWI828198B (en) 2024-01-01
TW202401679A TW202401679A (en) 2024-01-01

Family

ID=90457681

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111122482A TWI828198B (en) 2022-06-16 2022-06-16 Lead frame sheet, lead frame and manufacturing method thereof, electronic component and manufacturing method thereof

Country Status (1)

Country Link
TW (1) TWI828198B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200834856A (en) * 2007-02-07 2008-08-16 Advanced Semiconductor Eng Semiconductor chip package structure
TW200943515A (en) * 2008-04-11 2009-10-16 Powertech Technology Inc Semiconductor package without outer leads

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200834856A (en) * 2007-02-07 2008-08-16 Advanced Semiconductor Eng Semiconductor chip package structure
TW200943515A (en) * 2008-04-11 2009-10-16 Powertech Technology Inc Semiconductor package without outer leads

Also Published As

Publication number Publication date
TW202401679A (en) 2024-01-01

Similar Documents

Publication Publication Date Title
US7019388B2 (en) Semiconductor device
US20080283980A1 (en) Lead frame for semiconductor package
US8088650B2 (en) Method of fabricating chip package
TWI455213B (en) Outer lead package structure and manufacturing method thereof
CN105720034B (en) Lead frame, semiconductor device
JP2005026466A (en) Semiconductor device and lead frame
KR20190002931U (en) Preformed lead frame and lead frame package made from the same
TWM539698U (en) Lead frame preform with improved leads
TWM523189U (en) Lead frame preform and lead frame package structure
TWI828198B (en) Lead frame sheet, lead frame and manufacturing method thereof, electronic component and manufacturing method thereof
JP2011142337A (en) Method of manufacturing semiconductor device
JP2008113021A (en) Manufacturing method of semiconductor device
CN112956005B (en) Integrated circuit package including inwardly bent leads
US20230005827A1 (en) Lead frame, semiconductor device, and lead frame manufacturing method
TWI745213B (en) Semiconductor package structure and manufacturing method thereof
US20230005824A1 (en) Method of manufacturing substrates for semiconductor devices, corresponding substrate and semiconductor device
US20220270957A1 (en) Quad flat no-lead (qfn) manufacturing process
JP2003133262A (en) Manufacturing method of semiconductor package
CN119542138B (en) Method for manufacturing semiconductor structure
CN206497889U (en) Lead frame preform with modified leads
JP4455166B2 (en) Lead frame
KR102514564B1 (en) Lead frame including grooved lead
CN113838827A (en) Lead frame and package
CN220873575U (en) Lead frame and packaging structure
KR100493038B1 (en) Leadframe improving a inner lead performance and manufacturing method thereof