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TWI346955B - Non-volatile memory device and method of programming a multi level cell in the same - Google Patents

Non-volatile memory device and method of programming a multi level cell in the same

Info

Publication number
TWI346955B
TWI346955B TW096121639A TW96121639A TWI346955B TW I346955 B TWI346955 B TW I346955B TW 096121639 A TW096121639 A TW 096121639A TW 96121639 A TW96121639 A TW 96121639A TW I346955 B TWI346955 B TW I346955B
Authority
TW
Taiwan
Prior art keywords
programming
memory device
volatile memory
same
level cell
Prior art date
Application number
TW096121639A
Other languages
English (en)
Other versions
TW200828318A (en
Inventor
Jong Hyun Wang
Se Cheon Park
Seong Hun Park
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200828318A publication Critical patent/TW200828318A/zh
Application granted granted Critical
Publication of TWI346955B publication Critical patent/TWI346955B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
TW096121639A 2006-12-28 2007-06-15 Non-volatile memory device and method of programming a multi level cell in the same TWI346955B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060136356A KR100816155B1 (ko) 2006-12-28 2006-12-28 불휘발성 메모리 장치 및 불휘발성 메모리 장치의 멀티레벨 셀 프로그램 방법

Publications (2)

Publication Number Publication Date
TW200828318A TW200828318A (en) 2008-07-01
TWI346955B true TWI346955B (en) 2011-08-11

Family

ID=39411481

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096121639A TWI346955B (en) 2006-12-28 2007-06-15 Non-volatile memory device and method of programming a multi level cell in the same

Country Status (6)

Country Link
US (1) US7466587B2 (zh)
JP (1) JP2008165953A (zh)
KR (1) KR100816155B1 (zh)
CN (1) CN101211660B (zh)
DE (1) DE102007026856A1 (zh)
TW (1) TWI346955B (zh)

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KR100769770B1 (ko) * 2006-09-29 2007-10-23 주식회사 하이닉스반도체 메모리 장치의 페이지 버퍼 회로 및 프로그램 방법
KR101391881B1 (ko) * 2007-10-23 2014-05-07 삼성전자주식회사 멀티-비트 플래시 메모리 장치 및 그것의 프로그램 및 읽기방법
KR100965029B1 (ko) * 2008-05-13 2010-06-21 주식회사 하이닉스반도체 불휘발성 메모리 장치 및 그 프로그램 검증 방법
KR101024142B1 (ko) * 2009-02-02 2011-03-22 주식회사 하이닉스반도체 불휘발성 메모리 소자의 프로그램 방법
KR101074564B1 (ko) * 2009-02-04 2011-10-17 주식회사 하이닉스반도체 불휘발성 메모리 장치
US8355286B2 (en) * 2009-05-08 2013-01-15 Hynix Semiconductor Inc. Method of operating nonvolatile memory device controlled by controlling coupling resistance value between a bit line and a page buffer
KR101099911B1 (ko) * 2009-12-17 2011-12-28 주식회사 하이닉스반도체 반도체 메모리 장치 및 그 동작 방법
KR101391352B1 (ko) 2011-12-19 2014-05-07 삼성전자주식회사 메모리 시스템 및 그것의 프로그램 방법
ITUB20160956A1 (it) * 2016-02-22 2017-08-22 Sk Hynix Inc Memoria flash NAND comprendente un page buffer per il rilevamento di corrente
CN105976866B (zh) * 2016-04-21 2019-11-26 清华大学 二进制数据序列的编码方法、存储装置和电子设备
US9818476B1 (en) * 2016-07-25 2017-11-14 Samsung Electronics Co., Ltd. Reprogram without erase using capacity in multi-level NAND cells
US10162554B2 (en) * 2016-08-03 2018-12-25 Samsung Electronics Co., Ltd. System and method for controlling a programmable deduplication ratio for a memory system
JP7092915B1 (ja) 2021-04-06 2022-06-28 ウィンボンド エレクトロニクス コーポレーション 半導体装置
CN114512162A (zh) * 2022-01-27 2022-05-17 东芯半导体股份有限公司 一种预充电方法及使用该方法的存储器装置
KR20240129213A (ko) * 2022-03-14 2024-08-27 양쯔 메모리 테크놀로지스 씨오., 엘티디. 페이지 버퍼, 메모리 디바이스 및 그것의 프로그래밍 방법
CN114783488B (zh) * 2022-03-14 2024-10-11 长江存储科技有限责任公司 页缓冲器、编程方法、存储器装置及系统

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JP3476952B2 (ja) * 1994-03-15 2003-12-10 株式会社東芝 不揮発性半導体記憶装置
JP3153730B2 (ja) * 1995-05-16 2001-04-09 株式会社東芝 不揮発性半導体記憶装置
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JP3631463B2 (ja) * 2001-12-27 2005-03-23 株式会社東芝 不揮発性半導体記憶装置
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US6522580B2 (en) * 2001-06-27 2003-02-18 Sandisk Corporation Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states
KR100454119B1 (ko) * 2001-10-24 2004-10-26 삼성전자주식회사 캐쉬 기능을 갖는 불 휘발성 반도체 메모리 장치 및 그것의 프로그램, 읽기, 그리고 페이지 카피백 방법들
JP2004023044A (ja) * 2002-06-20 2004-01-22 Toshiba Corp 不揮発性半導体記憶装置
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KR100729350B1 (ko) * 2004-12-15 2007-06-15 삼성전자주식회사 시리얼 센싱 동작을 수행하는 노어 플래시 메모리 장치
KR100597788B1 (ko) * 2004-12-17 2006-07-06 삼성전자주식회사 프로그램 동작 속도를 개선하는 불휘발성 반도체 메모리장치의 페이지 버퍼와 이에 대한 구동방법
KR20060070734A (ko) * 2004-12-21 2006-06-26 주식회사 하이닉스반도체 불휘발성 메모리 장치 및 그것의 프로그램 검증 방법
KR100585628B1 (ko) * 2005-01-24 2006-06-07 삼성전자주식회사 불휘발성 반도체 메모리 장치의 프로그램 구동방법
KR100672148B1 (ko) * 2005-02-17 2007-01-19 주식회사 하이닉스반도체 불휘발성 메모리 장치 및 그것의 페이지 버퍼 동작 방법
KR100672147B1 (ko) * 2005-03-15 2007-01-19 주식회사 하이닉스반도체 불휘발성 메모리 장치의 체크 보드 프로그램 시에 프로그램페일을 방지하기 위한 페이지 버퍼
KR100723772B1 (ko) * 2005-03-28 2007-05-30 주식회사 하이닉스반도체 개선된 프로그램 동작 성능을 가지는 플래쉬 메모리 소자의페이지 버퍼 및 그것의 프로그램 동작 제어 방법
KR100600301B1 (ko) * 2005-05-25 2006-07-13 주식회사 하이닉스반도체 면적이 감소된 페이지 버퍼 회로와, 이를 포함하는 플래시메모리 장치 및 그 프로그램 동작 방법
KR100642892B1 (ko) * 2005-07-19 2006-11-03 주식회사 하이닉스반도체 면적이 감소된 페이지 버퍼 회로와 그 독출 및 프로그램동작 방법
US7366014B2 (en) * 2005-07-28 2008-04-29 Stmicroelectronics S.R.L. Double page programming system and method
US7336532B2 (en) * 2006-05-12 2008-02-26 Elite Semiconductor Memory Method for reading NAND memory device and memory cell array thereof

Also Published As

Publication number Publication date
JP2008165953A (ja) 2008-07-17
US20080158953A1 (en) 2008-07-03
US7466587B2 (en) 2008-12-16
CN101211660B (zh) 2010-09-29
TW200828318A (en) 2008-07-01
KR100816155B1 (ko) 2008-03-21
CN101211660A (zh) 2008-07-02
DE102007026856A1 (de) 2008-07-03

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees