1341942 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種顯示基板及包含此顯示基板之顯示面 板，具體而言，本發明係關於一種液晶顯示基板及包含此液晶 顯示基板之液晶顯示面板。 【先前技術】 隨著面板產業的發展，顯示面板已大量使用於各式電子裝 置上。特別是液晶顯示面板，由於技術上日趨成熟，因此可應 用之範圍也日益增加。舉凡電視、監視器等各式顯示裝置、行 動通訊裝置、筆記型電腦以及其他各式電子裝置等，均可見到 液晶顯示面板的身影。 目前各式電子產品之設計者均致力將產品之體積縮小，以 符合市場及消費者之需求。然而在整體體積縮小之狀況下，市 場及消費者仍希望顯示面積反向增加。此外，隨著影像處理技 術的進步及晝質及解析度之增加，顯示面板之顯示面積亦需配 合放大。因此如何在不增加整體體積的狀況下，卻能爭取到最 大的顯示面積，已成為此一領域的重要課題。 圖la所示為傳統液晶顯示面板之示意圖。如圖所示， 傳統液晶顯示面板包含薄膜電晶體基板10、顯示面基板2〇以 及封膠30。封膠30設置於薄膜電晶體基板1〇與顯示面基板 20之間，並設置於靠近邊緣之位置。薄膜電晶體基板1〇與顯 示面基板20之間另注入有液晶材料7〇，封膠3〇則限制液晶 5 1341942 材料不至流出賴電晶體基板10與顯示面基板2G之間。薄膜 電晶體基板10上位於_ 3G之下方設置有複數的訊號傳遞線 路50。-般而f ’在同-層並列設置之訊號傳遞線路5〇間需 保留距離，以避免相互干擾或短路的狀況發生。由 於面板邊緣及!懷30之見度需足以遮蔽訊號傳遞線路5〇，因 此面板邊緣及封膠30之寬度即受限無法進一步縮減。 在圖1 b所示之另一傳統液晶顯示面板中，訊號傳遞線路5〇 以間隔方式分層設置於介電層80及保護層90下方。由於不同 層之訊號傳遞線路50間夾設有介電層gQ，因此相鄰訊號傳遞 路50間之水平間距得以縮短。然而在此一設計中，由於位在 介電層80及保護層90間之訊號傳遞線路5〇高度往往高於鄰 近介電層80之高度’因此位於此位置上方之保護層9〇亦較其 他位置突出。當上方之封膠30因組裝或外力下壓時，保護層 90突出之部分較其他部分受力為大，因此下方之訊號傳遞線 路50亦承受較大之壓力。此外，由於此層之訊號傳遞線路50 設在介電層80上方，因此僅有保護層90之保護。在保護較少 且受力較大之狀況下’此層之訊號傳遞線路50較設於介電層 80下方之訊號傳遞線路50易受到損害。 【發明内容】 本發明之目的在於提供一種顯示基板及包含此顯示基板之 顯示面板，具有較窄之邊框寬度。 本發明之另一目的在於提供一種顯示基板及包含此顯示基 6 ^42 板之顯示面板’對設於基板邊框之導線提供較佳之保護。 本發明之另一目的在於提供一種顯示基板製造方法，具有 幸父向之生產良率及較長之產品壽命。The present invention relates to a display substrate and a display panel including the same, and more particularly to a liquid crystal display substrate and a liquid crystal display including the liquid crystal display substrate. panel. [Prior Art] With the development of the panel industry, display panels have been widely used in various electronic devices. In particular, liquid crystal display panels have become increasingly applicable due to their maturity in technology. The liquid crystal display panel can be seen in various display devices such as televisions, monitors, mobile communication devices, notebook computers, and various other electronic devices. At present, designers of various electronic products are committed to reducing the size of products to meet the needs of the market and consumers. However, in the overall volume reduction situation, the market and consumers still want to increase the display area in reverse. In addition, with the advancement of image processing technology and the increase in enamel and resolution, the display area of the display panel needs to be enlarged. Therefore, how to obtain the largest display area without increasing the overall volume has become an important issue in this field. Figure la shows a schematic view of a conventional liquid crystal display panel. As shown, the conventional liquid crystal display panel includes a thin film transistor substrate 10, a display surface substrate 2A, and a sealant 30. The sealant 30 is disposed between the thin film transistor substrate 1A and the display surface substrate 20, and is disposed at a position close to the edge. A liquid crystal material 7 is further implanted between the thin film transistor substrate 1 and the display surface substrate 20, and the sealant 3 限制 restricts the liquid crystal 5 1341942 material from flowing between the photovoltaic substrate 10 and the display surface substrate 2G. On the thin film transistor substrate 10, a plurality of signal transmission lines 50 are disposed under the _3G. In general, f ’ must be kept at a distance between the signal transmission lines 5 arranged side by side to avoid mutual interference or short circuit conditions. Since the edge of the panel and the visibility of the panel need to be sufficient to shield the signal transmission line 5, the width of the panel edge and the seal 30 is limited and cannot be further reduced. In another conventional liquid crystal display panel shown in FIG. 1b, the signal transmission lines 5 are layered under the dielectric layer 80 and the protective layer 90 in a spaced manner. Since the dielectric layer gQ is interposed between the signal transmission lines 50 of different layers, the horizontal spacing between adjacent signal transmission paths 50 is shortened. However, in this design, since the signal transmission line 5〇 located between the dielectric layer 80 and the protective layer 90 is often higher in height than the adjacent dielectric layer 80, the protective layer 9 located above the position is also higher than the other layers. The position is outstanding. When the upper sealant 30 is pressed by assembly or external force, the protruding portion of the protective layer 90 is more stressed than the other portions, so the underlying signal transmission line 50 is also subjected to a large pressure. In addition, since the signal transmission line 50 of this layer is disposed above the dielectric layer 80, only the protection of the protective layer 90 is provided. In the case of less protection and greater stress, the signal transmission line 50 of this layer is more susceptible to damage than the signal transmission line 50 disposed under the dielectric layer 80. SUMMARY OF THE INVENTION An object of the present invention is to provide a display substrate and a display panel including the same, which have a narrow bezel width. Another object of the present invention is to provide a display substrate and a display panel comprising the display substrate of the display substrate to provide better protection for the wires disposed on the substrate frame. Another object of the present invention is to provide a method of manufacturing a display substrate which has a good production yield and a long product life.
本發明之顯示基板包含第一基板、複數個第一導線、介電 層、複數個第二導線、複數個墊塊、保護層及封膠框。第一基 板上具有顯示區域及包圍顯示區域之邊緣區域。複數個第—導 線係設置於第一基板之邊緣區域上，並沿邊緣區域之延伸方向 刀佈’亚由介電層覆蓋其上。複數個第二導線係設置於介電層 上’並與第-導線間隔並列。墊塊係設置於介電層上並位於第 導線之上方；因此墊塊係與第二導線間隔並列。若以第一基 板為基準祕，魏之與高度係不低於第二導線頂端之高 度。The display substrate of the present invention comprises a first substrate, a plurality of first wires, a dielectric layer, a plurality of second wires, a plurality of pads, a protective layer and a sealing frame. The first substrate has a display area and an edge area surrounding the display area. A plurality of first-wire wires are disposed on the edge region of the first substrate, and the blade is sub-covered by the dielectric layer along the extending direction of the edge region. A plurality of second conductors are disposed on the dielectric layer and are juxtaposed with the first conductors. The spacer is disposed on the dielectric layer and above the first conductor; thus the spacer is spaced apart from the second conductor. If the first substrate is used as the reference, the height of the Wei and the height are not lower than the height of the top of the second wire.
保》蒦層ίτ、覆蓋於第二導線及塾塊上。保護層位於藝塊上方 之部分較位於第二導線上方之部分為突出。因此當承受外力 時’保護層位於墊塊上方之部分較位於第二導線上方之部分先 =力，以增加·二導線之保護。封職顧蓋於保護層上 方，並位於邊緣區域内。封膠框與第—導線及第二導線叠合， ^此·^^ —基板上邊緣區域之面積，並降低邊緣區域之寬 之设置，可塾高保護層位於塾塊上方之部分，以 =之==不受封膠框中粒子結構之破壞。 晶層。第省以及液 第二基板軸轉 7 與第二基板邊緣之間隙。液晶層位於第—基板與第二基板之 間，並位於封膠框内。 、本發明顯示基板之製造方法包含下列步驟。於第一基板之 邊緣區域上職複數㈣—導線，並使第—導線沿.邊緣區域分 饰。形成介電層覆蓋於第一導線上。形成複數個第二導線於介 電層上’第二導線並與第一導線間隔並列。形成複數個藝塊於 ，電層上位於第-導線上方之位置，並錄塊頂狀高度高於 第-導線頂端之高度。形成保護層覆蓋該些第二導線及墊塊。 形成封膠框覆蓋保護層並位於該邊緣區域上。 【實施方式】 本發明係提供-種顯減減包含賴示基板之顯示面 板，，’I示面板較佳包含液晶顯示面板；然而在不同實施例中， 亦可為其他不關式之平面顯示面板，例如有機發光二極體顯 丁面板此外’本發明亦提供上述顯示面板及顯示基板之製造 方法。 在圖2及@ 3所不之實施例中，顯示基板⑽包含第一基 板110、複數個第-導線21〇、介電層3〇〇、複數個第二導線 220、複數個塾塊23G、保護層_及封膠框·。第-基板 110較佳係為-咖基板’例如玻璃基板$翻㈣基板，以 2顯示基板⑽後方配置之f光模組(树示)人射光線。然而 不同實⑽巾’例如使用於有機發光二極體顯示面板時，第 -基板110亦可採用不透光之材質製成。 1341942 如^及圖3所示，第-基板邯上具有顯示區域⑴及 包圍顯不區域⑴之邊緣區域n3。顯示區域⑴上形成有複蒦 蒦 layer ίτ, covering the second wire and the block. The portion of the protective layer above the block is protruded from the portion above the second wire. Therefore, when the external force is applied, the portion of the protective layer above the spacer is first and the force is located above the second conductor to increase the protection of the two conductors. The cover is placed above the protective layer and is located in the edge area. The sealing frame is overlapped with the first wire and the second wire, and the area of the upper edge region of the substrate is reduced, and the width of the edge region is reduced, so that the portion of the protective layer above the block is raised to == is not damaged by the particle structure in the sealant frame. Crystal layer. The province and the liquid second substrate shaft 7 are separated from the edge of the second substrate. The liquid crystal layer is located between the first substrate and the second substrate and is located in the encapsulation frame. The method for manufacturing a display substrate of the present invention comprises the following steps. A plurality of (four) wires are placed on the edge region of the first substrate, and the first wires are decorated along the edge region. A dielectric layer is formed overlying the first wire. A plurality of second wires are formed on the dielectric layer and the second wires are juxtaposed with the first wires. A plurality of art blocks are formed on the electrical layer at a position above the first wire, and the height of the top of the recording block is higher than the height of the top end of the first wire. A protective layer is formed to cover the second wires and the spacers. A seal frame is formed to cover the protective layer and is located on the edge region. [Embodiment] The present invention provides a display panel including a display substrate, and the display panel preferably includes a liquid crystal display panel. However, in different embodiments, other non-closed planar displays may be provided. A panel, for example, an organic light-emitting diode display panel. Further, the present invention also provides a method of manufacturing the above display panel and display substrate. In the embodiment of FIG. 2 and FIG. 3, the display substrate (10) includes a first substrate 110, a plurality of first-conductors 21, a dielectric layer 3, a plurality of second wires 220, and a plurality of germanium blocks 23G. Protective layer _ and sealing frame. The first substrate 110 is preferably a coffee substrate, such as a glass substrate, and a (four) substrate, and the light-emitting module (tree) is disposed behind the substrate (10). However, when the actual (10) towel is used for, for example, an organic light emitting diode display panel, the first substrate 110 may be made of a material that is opaque. 1341942 As shown in Fig. 3, the first substrate has a display area (1) and an edge area n3 surrounding the display area (1). Formed on the display area (1)
=购咖之電晶體_。在本實施财，電晶體麵較 佳為_電晶體。複數個第—導線係設置於第一基板⑽ :邊^域⑽上’並沿邊緣區域⑴之延伸方向分伟。在此 實關中，第-導線21 〇係柄長之金屬導線，並平行於第一 基板110之端部。各個第一導線21〇之間較佳係相互平行，且 其間保持-定間距明免相互干擾之狀況發生。此外，第一導 係可以各式物理或化學⑽爾於第—基板則上，例 如=餘刻、沉積、蒸鑛，等方式均可視情況需要而採用。 圖2及圖3所示，介電層_係覆蓋於第一導線挪上。 =:=’介電層_係同時延伸至顯示區域m内，形 ΐ 部分° _層3(HM交佳由氣石夕化合物所製 果跡Μ第—導線21G之柳，並科可提供絕緣之效= Buy the crystal of the coffee _. In this implementation, the transistor surface is preferably a transistor. A plurality of first-conductor wires are disposed on the first substrate (10): the edge region (10) and extend along the extending direction of the edge region (1). In this practical case, the first wire 21 is a metal wire having a long handle and is parallel to the end of the first substrate 110. Preferably, each of the first wires 21 is parallel to each other, and a condition in which a predetermined interval is maintained to avoid mutual interference occurs. In addition, the first guiding system can be physically or chemically (10) on the first substrate, for example, = residual, deposition, steaming, and the like can be used as needed. As shown in FIG. 2 and FIG. 3, the dielectric layer _ covers the first wire. =:='Dielectric layer_ extends to the display area m at the same time, shape ° part ° _ layer 3 (HM 交佳 is made of gas stone compound compound Μ — - wire 21G willow, and Keke can provide insulation Effect
雜所示，介電層300較佳係具有波浪狀之截面 她於每—第—導線21G之上方形成波峰310; 並因此在相鄰第一導線210之間形成波谷33〇。 30(Th圖，2二圖3所不，複數個第二導線22〇係設置於介電層 亚。第—導線21G間隔並列。換言之，第二導線200 亦位於顯示區域lu之範圍 設置於介電層30。所形成 ㈤不，第二導線220係 一導線則分層設置。之波谷33G位置，並與第 之金屬導線，並平行4=1第二導線22G係為延長 、弟基板110之端部。各個第二導線 220之間較佳係相互平行，且相鄰之第二導線22〇間以及第二 導線2 2 0與第-導線210間均保持—定間距以避免相互干擾之 狀况發生。此外，第-導線21〇係'可以各式物理或化學製程形 成於第-基板110上’例如黃光颠刻、沉積、蒸鑛、麟等方 式均可視情況需要而採用。 如圖2及圖3所示，墊塊230係設置於介電層300上並位 於第一導線210之上方；因此墊塊23〇係與第二導線22Q間隔 並列。如圖3所示，墊塊230所在之位置係為介電層3〇〇所形 成之波峰310位置。在此實施例中，墊塊23〇係分別沿第二導 線220延伸，並與之平行。若以第一基板11〇為基準觀察，墊 塊230之頂端高度係不低於第二導線22〇頂端之高度。此外， 墊塊230之厚度較佳係不小於第一導線2丨〇與第二導線220的 冋度差，且較佳係不小於0.8微米（#m)。墊塊23〇較佳由第 導線210與第二導線220的中間層所構成，較佳係由矽層所 ’、且成，且其材貝可為非晶石夕、多晶石夕或其他之石夕聚合物。然而 在不同實把例中’墊塊230亦可由其他金屬或非金屬材質所形 成。 保護層500係覆蓋於第二導線220及墊塊23〇上。在此實 施例中，保護層500係同時延伸至顯示區域lu内，形成電晶 體600之一部分。保護層5〇〇較佳由氮矽化合物所製成，具有 保護第一導線210及第二導線220之功用。此外，如圖3所示， 保護層500較佳係具有波浪狀之截面形狀；其中保護層5〇〇位 於塾塊230上方之部分較位於第二導線22()上方之部分為突 1341942 出。因此當承受外力時，保護層500位於塾塊230上方之部八 導線220上方之部分先受力，以增加對第二^As shown, the dielectric layer 300 preferably has a wavy cross section. She forms a peak 310 above each of the first conductors 21G; and thus forms a valley 33 相邻 between adjacent first conductors 210. 30 (Th, 2, 2, 3), a plurality of second wires 22 are disposed in the dielectric layer. The first wires 21G are juxtaposed. In other words, the second wires 200 are also located in the display region lu. The electric layer 30 is formed. (5) No, the second wire 220 is a layer of a wire, and the trough 33G is located, and is parallel to the first metal wire, and 4=1, the second wire 22G is extended, and the substrate 110 is Preferably, each of the second wires 220 is parallel to each other, and the adjacent second wires 22 and the second wires 220 and the first wires 210 are spaced apart from each other to avoid mutual interference. In addition, the first wire 21 can be formed on the first substrate 110 by various physical or chemical processes, such as yellow light, deposition, steaming, and the like, which may be used as needed. 2 and FIG. 3, the spacer 230 is disposed on the dielectric layer 300 and above the first conductive line 210; therefore, the spacer 23 is spaced apart from the second conductive line 22Q. As shown in FIG. 3, the spacer 230 is provided. The position is the position of the peak 310 formed by the dielectric layer 3〇〇. In this embodiment The spacers 23 are respectively extended along and parallel to the second wires 220. If viewed from the first substrate 11 ,, the height of the top end of the spacers 230 is not lower than the height of the tips of the second wires 22 。. Preferably, the thickness of the spacer 230 is not less than the difference in twist between the first conductor 2 and the second conductor 220, and is preferably not less than 0.8 micrometer (#m). The spacer 23 is preferably provided by the first conductor 210. And the intermediate layer of the second wire 220 is formed, preferably by a layer of bismuth, and the material of the material may be amorphous, polycrystalline, or other stone polymer. In the example, the spacer 230 may also be formed of other metal or non-metal materials. The protective layer 500 covers the second wire 220 and the pad 23〇. In this embodiment, the protective layer 500 extends to the display area at the same time. In the lu, a part of the transistor 600 is formed. The protective layer 5 is preferably made of a nitrogen-niobium compound, and has the function of protecting the first wire 210 and the second wire 220. Further, as shown in FIG. 3, the protective layer 500 Preferably, it has a wavy cross-sectional shape; wherein the protective layer 5 is located on the block 230 The portion of wire 22 than in the second () is a portion above the projecting 1,341,942. Thus, when subjected to an external force, the protective layer 500 is located above the upper portion 230 of the wire 220 eight blocks Sook first force to a second increase ^
如圖2及圖3所示，封雜·係覆蓋於保護層5〇Q上方， 並位於邊緣區域113内。換言之，娜框係包圍於第一基 板11 〇顯示區域1U之外側。如圖3所示，封膠框7〇〇係與二 一導線210及第二導線220疊合，因此可減少第-基板11〇上 邊緣區域113之面積，並降低邊緣區域113之寬度。封膠框 中較佳係射-定比例之粒子簡，粒子結構之材質較佳 為金、矽、塑料等。因此触墊塊23〇之設置，可墊高保護芦 500位於墊塊230上方之部分，以保護相鄰墊塊23〇間之第: 導線220不受封膠框中粒子結構之破壞。As shown in FIGS. 2 and 3, the sealing layer covers the protective layer 5〇Q and is located in the edge region 113. In other words, the frame is surrounded by the outer side of the first substrate 11 〇 display area 1U. As shown in FIG. 3, the sealing frame 7 is overlapped with the two wires 210 and the second wires 220, so that the area of the upper edge region 113 of the first substrate 11 can be reduced, and the width of the edge region 113 can be reduced. In the sealing frame, it is preferred to singly-scale the particles, and the material of the particle structure is preferably gold, bismuth, plastic or the like. Therefore, the contact pad 23 is disposed to raise the portion of the protective reed 500 above the pad 230 to protect the first block between the adjacent blocks 23: the wire 220 is not damaged by the particle structure in the sealing frame.
如圖4a及圖4b所示，位於顯示區域⑴内之電晶體_ 包含有閘極層610、半導體層63Q及源沒極層咖。在此實施 例中，墊塊230係與半導體層630位於同一層；換言之，替 230與半導體層630會於同一製程步驟中形成，且具有相同材 質。然而在不同實施例中，塾塊23〇與半導體層63〇亦可於不 同製程步驟中形成，且具有不同材質。 在圖4a及圖4b所示之實施例中，第一導線21〇係组電曰 體剛之閘極層議同層，而第二導線刎則與騎極層; 同層。換言之’第-導線210與閘極層_會形成於同一製程 步驟中，而第二導線220與源沒極層65〇卿成於同—製程= 驟。在此實施射’ _層61G &含有複數相互平行之問= 1341942 611 ’ -部分之閘極線61卜例如奇數排序或偶數排序之閉極 線61卜於穿出顯示區域⑴並進入邊緣區域113後即彎折形 成第-導、線210。因此此部分之閘極線611係分別垂直連接於 第-導線210。而另-部分之閘極線6) i則在進入邊緣區域⑴ 後分別與垂直向且位於不同層之第二導線22{)以姻錫氧化物 ⑽)或其他導電材質搭接^於祕線611之方向係與第一 導線210及第二導線220垂直，第一導線21〇、第二導線刎 與閘極狀連接得以改變戰線路整體之傳遞方向，並沿邊緣 區域113將外部訊號輸入至閘極線611。 如圖5所示，顯示面板包含上述之顯示基板100、第二基; 120以及液晶層13〇。第二基板12()係覆蓋於顯示基板^ 上方並位於封膠框上。第二基板⑽藉由封膠框斑 -基板no組立’封勝框並密封第一基板11〇與第二知 120邊緣之_。第二基板⑽較佳為設有彩⑽光層之^ 面基板’具有光穿透性。液晶層位於第-基板11()與第: 基板120之間’並位於封膠框内。液晶層13〇係可藉由： 入或滴入方式設置於第-顧11G與第二基板⑽之間曰。 圖6為顯示基板製造方法之實關流_。如圖6所干 步驟⑽包含於第—基板之邊緣區域上形成複數個第 Ϊ之緣區域分佈。第-導線触係形成初 長之金屬導線’且被平触雜—定_ 目 狀況發生。此外疋邳兑干擾之 笛帛魏 各搞理献學餘形成於 第一基板上，例如普杏缸亡丨丨__ M、 /、先蝕刻、>儿積、鮝鍍、濺鍍等方式均可视 12 s :， 1341942 情況需要而採用。 步驟930包含形成介電層紐於第—導線上。介電層較佳 ，石夕化合物所製成’並可以各式物理或化學製程形成曰，例如 貫光姓刻、沉積、蒸鍍、顧等方式均可視情況需要而採用。 此外笔層較佳係與顯示區域内之電晶體介電層於同一製程 步驟中形成，以簡化製程。由於第—導線係突出於第一基板， 因此介電層較佳於每-第-導線之上方形成波谷；並因此在相 鄰第一導線之間形成波谷。 步驟950 &含形成複數個第二導線於介電層上，第二導線 並與第-導制隔剌。第二導_佳係形成於介電層所形成 之波谷位置。第二導線健係形成為延長之金屬導線，且與第 一導線平行聽持-定間距以避免相互干擾之狀況發生。此 外丄第二導線係可以各式物理或化學製程形成於介電層上，例 如黃光_、沉積、蒸鍍、賴等料均可視叙f要而採用。 步驟970包含形成複數個墊塊於介電層上位於第—導線上 ^之位置’並使魏頂敵高度高於第二導_端之高度。此 =較佳包含沿第二導線延伸分佈簡，並使墊塊與第二導線 ^並列。此外’墊塊較佳係設置於介電層所形成之波蜂位置 。在較佳實施例中’墊塊之厚度係不小於Q 8微米（m)。 甘塾塊較錄由料敝成，且其材質可為非祕、多晶石夕 辣合物。細在柯實補巾；鶴村由其他金 於〜^屬材f _成。鏡射以各式_姐學製程形成 、μ 曰上’例如結晶、黃光钱刻、沉積、蒸鑛、減錢等方式 1341942 均可視情況需要而採用。 層^Y別包含形成保護層覆蓋該些第二導線及塾塊。保護 二乂土由II魏合物所製成，並可以各式物理或化學製程形 '例如買光钱刻、沉積、蒸鍍、濺鑛等方式均可視情況需要 木用此外，保濩層較佳係與顯示區域内之電晶體保護 ^製程步财形成，明化製程。形成後之保護層位轉塊 =之部分較錄第二導線上方之部分為突出。因此當承受外 時’保護層位於墊塊上方之部分較位於第二導線上方之部八 先受力，以增加對第二導線之保護。 刀 步驟990包含形成_框覆蓋保護層並位於該邊緣區域 ^。封踢練健峨佈方式形成於保制± ;細在不同實 %例中，亦可直接以成形之封膠框組立於保護層上。 、 在圖7所示之實施例中，步驟911包含於第一導線形成時， 同時形成顯示區域内電晶體之閘極層。因此第一導線與開極層 會形成於同-製程步驟中。此外，此步驟更包含於閘極層形^ 複數相互平行之閘極線。-部分之閘極線，例如奇數排序或偶 數排序之閘極線，於穿出顯示區域並進入邊緣區域後即彎折形 成第一導線。因此此部分之閘極線係分別垂直連接於第一導 線。 步驟951包含於第二導線形成時’同時形成顯示區域内電 晶體之源汲極層。因此第二導線與源汲極層會形成於同一製程 步驟。此步驟更包含使未與第-導線連接之部分閘極線在進入 邊緣區域後分別與垂直向且位於不同層之第二導線以銦錫氧As shown in FIGS. 4a and 4b, the transistor _ located in the display region (1) includes a gate layer 610, a semiconductor layer 63Q, and a source layer. In this embodiment, the spacer 230 is in the same layer as the semiconductor layer 630; in other words, the replacement 230 and the semiconductor layer 630 are formed in the same process step and have the same material. However, in various embodiments, the germanium block 23 and the semiconductor layer 63 can be formed in different process steps and have different materials. In the embodiment shown in Figures 4a and 4b, the first wire 21 is the same as the gate layer of the gate layer, and the second wire is the same layer as the riding layer. In other words, the 'first-wire 210 and the gate layer _ are formed in the same process step, and the second wire 220 is formed in the same manner as the source-pole layer 65-process. Here, the emitter ' _ layer 61G & includes a plurality of mutually parallel questions = 1341942 611 ' - part of the gate line 61, such as an odd-ordered or even-ordered closed-pole line 61, which passes through the display area (1) and enters the edge area After 113, the first guide and the line 210 are formed. Therefore, the gate lines 611 of this portion are vertically connected to the first-wires 210, respectively. The other part of the gate line 6) i is connected to the second line 22{) of the vertical layer and located in different layers after entering the edge area (1), and is connected with the other conductive material. The direction of the 611 is perpendicular to the first wire 210 and the second wire 220. The first wire 21〇, the second wire 刎 and the gate connection are connected to change the overall transmission direction of the battle line, and the external signal is input to the edge region 113 to Gate line 611. As shown in FIG. 5, the display panel includes the above-described display substrate 100, second substrate 120, and liquid crystal layer 13A. The second substrate 12() is over the display substrate and located on the encapsulation frame. The second substrate (10) is assembled by the sealing frame-substrate no and seals the first substrate 11 and the edge of the second substrate 120. The second substrate (10) is preferably a light-transmissive substrate </ RTI> having a color (10) light layer. The liquid crystal layer is located between the first substrate 11 () and the first: substrate 120 and is located inside the encapsulation frame. The liquid crystal layer 13 can be disposed between the first electrode 11G and the second substrate (10) by means of: instillation or dripping. Fig. 6 is a view showing the actual flow of the substrate manufacturing method. Step (10) of FIG. 6 includes forming a plurality of edge regions of the first substrate on the edge region of the first substrate. The first-wire contact forms an initial metal wire' and is caused by a flat-to-dise condition. In addition, the whistle of the whistle of the whistle and the whistle of the martial arts are formed on the first substrate, for example, the 杏 普 丨丨 __ M, /, first etching, > erection, enamel plating, sputtering, etc. Both can be used as needed for 12 s :, 1341942. Step 930 includes forming a dielectric layer on the first conductor. The dielectric layer is preferably formed by the compound of Shixi compound and can be formed by various physical or chemical processes, for example, the lithography, deposition, evaporation, and the like can be used as needed. In addition, the pen layer is preferably formed in the same process step as the transistor dielectric layer in the display region to simplify the process. Since the first wire protrudes from the first substrate, the dielectric layer preferably forms a valley above each of the -th wires; and thus forms a valley between adjacent first wires. Step 950 & includes forming a plurality of second wires on the dielectric layer, and the second wires are isolated from the first conductive system. The second guide is formed at a valley position formed by the dielectric layer. The second wire is formed as an elongated metal wire and is held in parallel with the first wire to avoid mutual interference. The second wire can be formed on the dielectric layer by various physical or chemical processes, such as yellow light, deposition, evaporation, and the like. Step 970 includes forming a plurality of spacers on the dielectric layer at a position on the first conductor and making the height of the Weiding enemy higher than the height of the second conduction terminal. This = preferably comprises extending the distribution along the second conductor and aligning the spacer with the second conductor ^. Further, the spacer is preferably disposed at a position of a bee formed by the dielectric layer. In the preferred embodiment, the thickness of the spacer is not less than Q 8 micrometers (m). The sorghum block is recorded from the material, and its material can be non-secret, polycrystalline stone. Fine in the Keshi patch; Hecun by other gold in ~ ^ genus f _ into. Mirror shots are formed in various ways. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The layer ^Y includes forming a protective layer covering the second wires and the blocks. The protected bauxite is made of II Wei compound and can be used in various physical or chemical processes. For example, the method of buying money, depositing, evaporating, splashing, etc. can be used as needed. The crystal protection in the excellent system and the display area is formed by the process and the process is clear. After the formation of the protective layer turn block = the portion above the second wire is highlighted. Therefore, when the outer layer is received, the portion of the protective layer above the spacer is biased earlier than the portion above the second conductor to increase the protection of the second conductor. The knife step 990 includes forming a _ frame covering the protective layer and located in the edge region ^. The method of sealing and training is formed in the protection system. In the different cases, the formed sealing frame can be directly formed on the protective layer. In the embodiment shown in FIG. 7, step 911 includes forming a gate layer of a transistor in the display region while the first wire is being formed. Therefore, the first wire and the open layer are formed in the same-process step. In addition, this step is further included in the gate layer of the gate layer and the parallel gate lines. - A portion of the gate line, such as an odd-numbered or even-ordered gate line, is bent to form a first wire after it has passed through the display area and entered the edge area. Therefore, the gate lines of this portion are vertically connected to the first wires, respectively. Step 951 includes forming a source drain layer of the transistor in the display region while the second wire is being formed. Therefore, the second wire and the source drain layer are formed in the same process step. The step further comprises: placing a portion of the gate lines not connected to the first-conductor line into the edge region, respectively, and vertically and in the second layer of the different wires, indium tin oxide
14 (S 1341942 ’ 彳t物UTG)或其他導電材質搭接。 步驟971包含於墊塊形成時，同時於顯示區域内形成電晶 體之半‘體層。換言之，塾塊與半導體層會於同一製程步驟中 形成，且具有相同材質。半導體層之材質可為非晶矽、多晶矽 或其他之半導體金屬或非金屬。 本發明已由上述相關實施例加以描述，然而上述實施例僅 為實％本發明之範例。必需指出的是’已揭露之實施例並未限 • 制本發明之範圍。相反地’包含於申請專利範圍之精神及範圍 之修改及均等設置均包含於本發明之範圍内。 【圖式簡單說明】 圖la及圖比為傳統液晶顯示面板之示意圖； 圖2為顯示基板實施例之上視圖； 圖3為顯示基板實施例之剖視圖； 圖4a為顯示基板另一實施例之上視圖； 鲁 圖4b為圖4a所示實施例之刮視圖； 圖5為本發明顯示面板之實施例剖視圖； 圖δ為顯示基板製造方法之實施例流程圖； 圖7為顯示基板製造方法之另一實施例流程圖。 【主要元件符號說明】 100顯示基板 110第一基板14 (S 1341942 ’ UTt UTG) or other conductive material overlap. Step 971 includes forming a half "body layer" of the electromorph in the display region while the spacer is being formed. In other words, the germanium block and the semiconductor layer are formed in the same process step and have the same material. The material of the semiconductor layer may be amorphous germanium, polycrystalline germanium or other semiconductor metal or non-metal. The present invention has been described by the above related embodiments, but the above embodiments are merely examples of the present invention. It must be noted that the disclosed embodiments are not intended to limit the scope of the invention. Rather, modifications and equivalent arrangements are intended to be included within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a top view showing an embodiment of a substrate; FIG. 3 is a cross-sectional view showing an embodiment of a substrate; FIG. 4 is a view showing another embodiment of the substrate; 5 is a cross-sectional view of an embodiment of the display panel of the present invention; FIG. 5 is a cross-sectional view showing an embodiment of a display panel of the present invention; FIG. 7 is a flow chart showing an embodiment of a method for manufacturing a substrate; A flow chart of another embodiment. [Main component symbol description] 100 display substrate 110 first substrate
S 15 1341942 111顯不區域 113邊緣區域 210第一導線 300介電層 310波峰 330波谷 220第二導線 230墊塊 500保護層 600電晶體 610閘極層 611閘極線 630半導體層 650源汲極層 700封膠框S 15 1341942 111 display area 113 edge area 210 first wire 300 dielectric layer 310 wave 330 trough 220 second wire 230 pad 500 protection layer 600 transistor 610 gate layer 611 gate line 630 semiconductor layer 650 source bungee Layer 700 plastic frame