200905287 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種顯示基板及包含此顯示基板之顯示面 板；具體而言，本發明係關於一種液晶顯示基板及包含此液晶 顯示基板之液晶顯示面板。 【先前技術】 隨著面板產業的發展，顯示面板已大量使用於各式電子弟 置上。特別是液晶顯示面板，由於技術上日趨成熟，因此可肩 用之範圍也日益增加。舉凡電視、監視料各式顯示裝置、: 動通訊裝置、筆迅型電腦以及其他各式電子裝置等，均可見至， 液晶顯示面板的身影。 目前各式軒產品之設計者均致力職品之轉縮小，以 符合市場及_者之需求。然而在整體體雜小之狀況下， 場及消費者财魏示面積反㈣加。此外，隨著影像處 術的進步及晝質及解之增加，顯示面板之顯示面積 合放大。因此如何在不增加整體體積的狀況下，卻能爭田 大的顯示面積，已成為此—領域的重要課題。 取 圖1a所示為傳統液晶顯示面板之示意圖。如圖la所干 傳統液晶齡面板包含_電晶縣㈣、顯和加、二The present invention relates to a display substrate and a display panel including the display substrate. Specifically, the present invention relates to a liquid crystal display substrate and a liquid crystal display including the liquid crystal display substrate. panel. [Prior Art] With the development of the panel industry, display panels have been widely used in various electronic devices. In particular, liquid crystal display panels, due to the maturity of technology, are increasingly available. Various types of display devices such as televisions and monitoring materials, mobile communication devices, pen-speed computers, and various other electronic devices can be seen, and the liquid crystal display panels are visible. At present, the designers of all kinds of products are committed to the reduction of their products to meet the needs of the market and the market. However, in the overall situation of small and small, the field and consumer wealth show that the area is reversed (four) plus. In addition, as the image processing progresses and the enamel and solution increase, the display area of the display panel is enlarged. Therefore, how to expand the display area without increasing the overall volume has become an important issue in this field. Figure 1a shows a schematic view of a conventional liquid crystal display panel. As shown in Figure la, the traditional liquid crystal age panel contains _Dianjing County (four), Xianhe Plus, two
及封膠30。封膠3〇設置於薄膜恭日 土板⑼U 々、浔胰电晶體基板1〇與顯 20之間，並設置於靠近邊緣之位置曰、土板 示面基板20之間另注入有液 :基板10與顯 及曰曰材枓70，封膠3〇則限制液晶 200905287 電/晶體基晶體基板1G與齡面基板2()之間。薄膜 路50。二2位於封膠3Q之下方設置有複數的訊號傳遞線 保留—定二5 ’在同—層並列設置之訊號傳遞線路50間需 於面扣〜3 ""距離，以避免相互干擾或短路的狀況發生。由 此糾Γ及轉3Q之寬度蚊以雜訊號傳雜路50，因 mr及封膠3G之寬度即受限無法進—步縮減。 、Θ lb所示之另一傳統液晶顯示面板中，訊號傳遞線路卯 、隔方式刀層设置於介電層刖及保護層卯下方。由於不同 S訊號#遞線路5〇間夾設有介電層，因此相鄰訊號傳遞 一]之水干間距得以縮短。然而在此一設計中，由於位在 ;丨包層80及保護層90間之訊號傳遞線路50高度往往高於鄰 近介電層80之高度，因此位於此位置上方之保護層90亦較其 他位且犬出。當上方之封膠3〇因組裝或外力下壓時，保護層 90犬出之部分較其他部分受力為大，因此下方之訊號傳遞線 路50亦承受較大之壓力。此外，由於此層之訊號傳遞線路5〇 設在介電層80上方，因此僅有保護層90之保護。在保護較少 且受力較大之狀況下，此層之訊號傳遞線路50較設於介電層 80下方之訊號傳遞線路50易受到損害。 【發明内容】 本發明之目的在於提)共' —種顯不基板及包含此顯不基板之 顯示面板，具有較窄之邊框寬度。 本發明之另一目的在於提供一種顯示基板及包含此顯示基 200905287 板之’須示面板，對設於基板邊框之導線提供較佳之保護。 本發明之另一目的在於提供一種顯示基板製造方法，具有 較高之生產良率及較長之產品壽命。 本發明之顯示基板包含第一基板、複數個第一導線.、介電 層、複數個第二導線、複數個墊塊、保護層及封膠框。第—基 板上具有顯示區域及包圍顯示區域之邊緣區域。複數個第—導 線係設置於第一基板之邊緣區域上，並沿邊緣區域之延伸方向 分佈，並由介電層覆蓋其上。複數個第二導線係設置於介電層 上，並與第一導線間隔並列。墊塊係設置於介電層上並位於第 -导線之上方；因此麵係與第二導線間隔剌。若以第—基 板為基準觀察，墊塊之頂端高度係不低於第二導線頂端之高 度。 同 保羞層係覆蓋於第二導線及墊境上。保護層位於墊塊上方 之部分較位於第二導線上方之部分為突岀。因此#承受外力 時，鍵雜☆無上方之部分較纟於第H方之部分先 文力’以增加對第二導線之保護。封膠框係覆蓋於保護層上 方，並位於邊緣區域内。封膠框與第一導線及第二導線疊合， 因此可減少第-基板上邊緣區域之面積，並降低邊、^區^寬 度。藉由墊塊之設置，可墊高保護層位於墊塊上方之部分，以 保護相鄰墊制之第二導線不受封_巾料結構之破壞。 本發明之騎©板包含上狀_基板1二紐以及液. ί層。第t基板健蓋於顯示基板之上方，並位於導框上。 第二基板藉由娜框與第-基板組立，封麵I密封第一基板 200905287 與弟一基技邊緣之間隙。液晶層位於第一基板與第二具板之 間，並位於封膠框内。 本發明頒τρτ基板之製造方法包含下列步驟。於第一其板之 邊緣區域上形成複數個第一導線，並使第一導線沿.邊緣區域分 佈°形成介電層覆盍於第一導線上。形成複數個第二導線於介 包層上，第二導線並與第一導線間隔並列。形成複數個墊塊於 ，電層上赌第-導線上方植置，並錄_端之高度高於 第二導線顧之高度。形祕護層覆蓋該些第二轉及塾塊。 形成封膠框覆蓋保護層並位於該邊緣區域上。 【實施方式】 發縣提供—觀示基板及包含賴示基板之顯示面 /、‘項示面板較佳包含液晶顯示面板；然而在不同實施例中， 可為其他不_紅平面顯示面板，例如有機發光二極體顯 =板。此外’本發明雜供上述齡面減鮮基板之製造 在圖2及圖3所示之實施例中，顯示基板1〇〇包含第一基 ^ ι、ιο—、複數個第—導線21〇、介電層_、複數個第二導線 1101雜個塾壤23Q、保護層_及封膠框。第一基板 _ 為—基板，例如賴基板或透難料基板，以 在不後方崎之㈣模組(未繪句人射絲。然而 一其、 甲’例如使用於有機發光二極體顯示面板時，第 板11G亦可採财透光之材質製成。 200905287 如圖2及圖3所示，第—基板11〇上具有顯示區域⑴及 包圍顯示區域111之邊緣區域il3。顯示區域ηι上带成靜 數個呈柳陳電晶體咖。在本細种，電晶體 佳為薄膜電晶體。複數個第-導線21(H系設置於 之邊緣區域113上’並沿邊緣區域113之延伸方向料。在此 實施例中H線210係為延長之金屬導線，並平行於第一 基板110之端部。各個第-導線21〇之間較佳係相互平行，且 其間保持-定間距以避免相互干擾之狀況發生。此外，第一導 線210係可以各式物理或化學製程形成於第一基板咄上，例 如黃光_、沉積、驗，輯方式均可視情況需要而採用。 如圖2及圖3所示，介電層3〇〇係覆篕於第一導線训上。 在此實施例中，介電層·係同時延伸至齡區域ui内，形 成電晶體600之-部分。介電層·較佳域魏合物所製 成，具有保護導線2H)之_，並_可提供絕緣之交: 果。此外，如圖3所示’介電層較佳係具有波浪狀之截面 形狀。介電層3GG於每-第—導線咖之上方形成波举⑽； 亚因此在相鄰第一導線210之間形成波谷330。 如圖2及圖3所示，複數個第二導線22〇係設置於介電芦 300上，並與第-導線21Q㈤隔並列。換言之，第二導線^ 亦位於顯示區域ni之範圍内。如圖3所示，第二導線2 設置於介電層所形成波浪狀截面之波谷330位置，並與第 -導線210分層設置。在此實施例中，第二導線22q係為延 之金屬導線，並平行於第m之端部。各個第： 200905287 220之間較佳係相互平行，且相鄰之第二導線挪間以及第二 "導線22G與第-導線2_均保持—定間距以避免相互干擾之 、、、电生，此外，第一導線210係可以各式物理或化學製程形 成於第一基板11()上，例如黃光_、沉積、絲、減鐘等方 式均可視情況需要而採用。 、★如圖曾2及圖3所示’墊塊2紹系設置於介電層3〇〇上並位 於第-導線21G之上方；因此墊塊23G係與第二導線22〇間隔 並列。如圖3所示，墊塊23〇所在之位置係為介電層細所形 成之波峰310位置。在此實施例中，墊塊23〇係分別沿第二導 線咖延伸，並與之平行。若以第一基板11G為基準觀察，i 塊230之頂端高度係不低於第二導線22〇頂端之高度。此外， 墊塊230之厚度較佳係不小於第一導線21〇與第二導線挪的 高度差，且較佳係不小於〇. 8微米（卿）。墊塊230較佳由第 -導線21◦與第二導線220的中間層所構成，較佳係由石夕層所 組成’且其材質可為非㈣、多晶錢其他之料合物。然而 在不同實施例中’墊塊230亦可由其他金屬或非金屬材質所形 成。 保護層500係覆蓋於第二導線22〇及墊塊23〇上。在此實 施例中，保護層500係同時延伸至顯示區域m β，形成電晶 體600之-部分。保護層500較佳喊石夕化合物所製成，= 保護第-導線2U)及第二—22q之功用。此外，如圖3所示， 保護層500較佳係具有波浪狀之截面频；其中保護層5〇〇位 於塾塊’上方之部分較位於第二導線22〇上方之部分為突 200905287 出。因此當承受外力時，保護層5⑽位於塾塊23G上方之部八 較位於第二導線22〇上 刀 220之保護。.上方之I先劲，以增加對第二導線 、，如圖2及圖3所示’封膠框顧蓋於保護層500上方， 亚位於祕區域113内。換言之，封膠框 板110顯示區域11丄之外側。如^ ㈤瓦弟基 -料210Π道/ 封膠框係與第 ,、.泉及弟-導線220疊合，因此可減少第一基板则 邊緣_ 113之面積’並降低邊緣區域ιΐ3 中較佳輸-定比例之粒子結構，粒子結構 為金、石夕、塑料等。因此藉由塾塊23〇之設置 位於塾塊230上方之部分，以保護相轉塊230 ^;層 導線22Q不受封膠框中粒子結構之破壞。 弟一 如圖4a及圖4b所示，位於顯示區域lu内之電晶體 包含有閘極層_、半導體層咖及源汲極層咖。在 例中’垄塊230係與半導體層63〇位於同—声.押▲:也 聊與半導體層_會於同一製程步驟中形二二有相2 質。然而在不同實施例中，塾塊23〇與半導體層63〇亦 同製程步驟中形成，且具有不同材質。 在圖4a及圖4b所示之實施例中，第—導線21〇係心曰 體_之卩摘⑽_，㈣^ 同層。換言之，第-導線21〇與閑極層_會形成於同. 步驟中，而第二導線220與驗極層65〇則形成於同— 驟。在此實施例中，閘極層61〇包含有複數相互平行之閘^二 200905287 bll -部分之閘極線 , 邪可致排序或偶數排序之閘極 線611，於穿_示區域m並進入邊緣區域113後即彎折形 成第-導線21G。因此此部分之鬧極線611係分砸直連接於 第-導線21〇。而另-部分之閘極、線611則在進入邊緣區域ιΐ3 後分別與垂勤且位於不同層之第二導線咖喃錫氧化物 (ΙΤ0)或其他導電材質搭接。由於閑極線611之方向係盘第一 導線210及第二導線220垂直，第一導線21〇、第二導線挪 與閘極線之連接得贿變縣翁整體之傳遞额，^沿邊緣 區域113將外部訊號輸入至閘極線611。 如圖5所示，顯示面板包含上述之顯示基板1〇〇、第二基板 120以及液晶層130。第二基板12〇係覆蓋於顯示基板⑽之 上方並位於封膠框上，二基板12()藉由封雜盘第 一基板no組立’封膠框700並密封第一基板11〇與第二基板 120邊緣之間隙。第二基板12〇較佳為設有彩色遽光層之顯示 面基板，具有光穿透性。液晶層13〇位於第—基板ιι〇與第二 基板120之間，並位於封雜7〇〇内。液 葬 入或滴入方式設置於第一基板110舆第二基板12二执主 圖6為顯示基板製造方法之實施例流程圖。如圖6所示， 步驟_—包含於第-餘之邊縣域上形成絲個第;;導 線’並使第·y導線沿邊、賴域分佈。第—導線較佳係形成為延 長之金屬導線，且相互平行並鋪—定間距以避免相互干擾之 ，況發生。此外’第-導、_可以各式物理献學製程形^於 第-基板上’例如黃光蝴、峨、絲、續等方式均可視 12 200905287 情況需要而採用。 /步驟930包含形成介電層覆蓋於第一導線上。介電層較佳 由氮石夕化合物所製成，並可以各式物理或化學製程形成：如 黃光姓刻、沉積、蒸錢、賤鐘等方式均可視情況需要而採用。 此外’介電層較佳係麵示區勒之電晶體介電層於同一製程 步驟中形成，以簡化製程。由於第一導線係突出於第一基板， 因此介電層較佳於每-第—導線之上方形成波谷；並因此在相 鄰第一導線之間形成波谷。 步驟950包含形成複數個第二導線於介電層上，第二導線 並與第-導制隔並列。第二導線較佳伽彡成於介電層所:成 之波各位置。第二導線較佳係形成為延長之金屬導線，且舆第 一導線平行並保持-定間距以避免相互干擾之狀況發生。此 外’第二辱線係可以各式物理或化學製程形成於介電層上，例 如黃光侧、沉積、紐、聽等方式均可婦況需要而採用。 步驟970包含形成複數個墊塊於介電層上位於第一導線上 方之位置，並使墊塊頂端之高度高於第二導線頂端之高度。此 步騾較佳包含沿第二導線延伸分佈墊塊，並使墊塊與第二導線 間隔並列。此外，塾塊較佳係設置於介電層所形成之波峰^置 上。在較佳實施例中，墊境之厚度係不小於〇. 8微米（㈣。 墊境較佳係由_所組成，且其材質可為非轉、多晶石夕 或其他之縣合物。細在獨實施射：魏亦可由其他金 屬或非金屬㈣所形成。墊塊係可叫式物理或化學製程形成 於介電層上，例如結晶、黃光綱、積、蒸鍍、紐等方式 13 200905287 均可視情沉需要而採用。 步轉包含形絲護賴蓋_第二導線及墊塊。保護 層較佳由氮石夕化合物所製成，並可以各式物理或化學製程形 =例如黃細卜沉積、蒸鍍、顧等方式均可視情況需要 叩才不用此外保。蒦層較佳係與顯示區域内之電晶體保護層於 同一製程步驟中形成，以簡化製程。形成後之保護層位於墊塊 上方之#刀丁乂位於第—導線上方之部分為突出。因此當承受外 力時，保護層位於墊塊上方之部分較位於第二導線上方之部分 先受力，以增加對第二導線之保護。 步驟990包含形成封膠框覆蓋保護層並位於該邊緣區域 ^。封夥框較佳係以塗佈方式形成於保護層上；然而在不同實 %例中，亦可直接以成形之封膠框組立於保護層上。 _在圖7所不之實施例中，步驟911包含於第一導線形成時， 同夺也成顯示區域内電晶體之閘極層。因此第一導線與閉極層 曰形成於同一製程步驟中。此外，此步驟更包含於閘極層形成 複數相互平行之閘極線。一部分之閘極線，例如奇數排序或偶 數排序之閘極線，於穿出顯示區域並進入邊緣區域後即彎折形 成第一導線。因此此部分之閘極線係分別垂直連接於第一導 線。 . γ驟耶1包含於弟二導線形成時，同時形成顯示區域内電 晶體之源汲極層。因此第二導線與源汲極層會形成於同一製程 步驟。此步驟更包含使未與第一導線連接之部分閘極線在進入 邊線區域後分別與垂直向且位於不同層之第二導線以銦錫氧 14 200905287 化物（ΙΤ0)或其他導電材質搭接。 步爾971包含於墊塊形成日寺，同時於顯示區域… 肢之+雜層。換言之，墊塊與半導體層會糊—鄭步: 具有相同材f。半導體層之材質可為非㈣=晶石夕 或其他之半導體金屬或非金屬。 ^已由上述相除_以插述，然而上述實施例僅 本發明之侧。必咖的是，已揭露之實施例並未限 市设明之乾圍。相反地，包含於申請專利範圍之精神及範圍 之修改及均等設置均包含於本發明之範圍内。 【圖式簡單說明】 圖la及圖化為傳統液晶顯示面板之示意圖； 圖2為顯示基板實施例之上視圖； 圖3為顯示基板實施例之剖視圖； 圖4a為顯示基板另·一實施例之上視圖； 圖4b為圖4a所示實施例之剖視圖； 圖5為本發明顯示面板之實施例剖視圖； 圖6為顯示基板製造方法之實施例流程圖； 圖7為顯示基板製造方法之另一實施例流程圖。 【主要元件符號說明】 10 0顯不基板 110第一基板 200905287 111顯示區域 113邊緣區域 210第一導線 300介電層 310波峰 330波谷 220第二導線 230墊塊 500保護層 600電晶體 610閘極層 611閘極線 630半導體層 650源没極層 700封膠框And sealant 30. The sealant 3〇 is disposed between the film and the 土 土 土 ( ( 9 9 9 9 9 9 ( ( ( ( ( 9 9 , : : : : : : : : : : : : : 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜 薄膜10 and the display material 枓 70, the sealant 3 〇 limits the liquid crystal 200905287 between the electric / crystal-based crystal substrate 1G and the age-surface substrate 2 (). Film path 50. 2 2 is located below the sealant 3Q and has a plurality of signal transmission lines reserved - the fixed 2 5 'between the signal transmission lines 50 arranged side by side in the same layer, it is necessary to deduct the distance to 3 "" distance to avoid mutual interference or A short circuit condition occurs. Therefore, the width and frequency of the 3Q mosquitoes are transmitted by the noise signal 50, and the width of the mr and the sealant 3G is limited and cannot be reduced. In another conventional liquid crystal display panel shown by lb lb, the signal transmission line 卯 and the spacer mode are disposed under the dielectric layer 保护 and the protective layer 。. Since the dielectric layers are interposed between the different S signals and the 5 lines, the water-to-dry spacing of adjacent signals is shortened. However, in this design, since the height of the signal transmission line 50 between the enamel layer 80 and the protective layer 90 tends to be higher than the height of the adjacent dielectric layer 80, the protective layer 90 located above the position is also higher than other bits. And the dog is out. When the upper sealant 3 is pressed down due to assembly or external force, the part of the protective layer 90 is more stressed than the other parts, so the signal transmission line 50 below is also subjected to a large pressure. In addition, since the signal transmission line 5 of this layer is disposed above the dielectric layer 80, only the protection of the protective layer 90 is provided. In the case of less protection and greater force, the signal transmission line 50 of this layer is more susceptible to damage than the signal transmission line 50 disposed under the dielectric layer 80. SUMMARY OF THE INVENTION The object of the present invention is to provide a display panel having a narrow frame width and a display panel including the display substrate. Another object of the present invention is to provide a display substrate and a display panel including the display substrate 200905287, which provides better protection for the wires provided on the substrate frame. Another object of the present invention is to provide a method of manufacturing a display substrate which has a high production yield and a long product life. The display substrate of the present invention comprises a first substrate, a plurality of first wires, a dielectric layer, a plurality of second wires, a plurality of pads, a protective layer and a sealing frame. The first substrate has a display area and an edge area surrounding the display area. A plurality of first-wires are disposed on the edge region of the first substrate and distributed along the extending direction of the edge region and covered by the dielectric layer. A plurality of second conductors are disposed on the dielectric layer and are juxtaposed with the first conductors. The spacer is disposed on the dielectric layer and above the first conductor; thus the face is spaced apart from the second conductor. If viewed on the basis of the first substrate, the height of the top end of the spacer is not lower than the height of the top end of the second conductor. The same shame layer covers the second wire and the mat. The portion of the protective layer above the pad is more abrupt than the portion above the second wire. Therefore, when the external force is applied, the key is no more than the upper part of the H-th side to increase the protection of the second wire. The seal frame covers the top of the protective layer and is located in the edge area. The sealing frame is overlapped with the first wire and the second wire, so that the area of the upper edge region of the first substrate can be reduced, and the width of the edge and the area can be reduced. By the arrangement of the spacers, the portion of the protective layer above the spacer can be raised to protect the adjacent second printed conductor from being damaged by the sealing structure. The riding board of the present invention comprises a top layer _ substrate 1 nucleus and a liquid layer. The t-th substrate is covered above the display substrate and located on the lead frame. The second substrate is assembled with the first substrate by the nano frame, and the cover I seals the gap between the first substrate 200905287 and the edge of the base. The liquid crystal layer is located between the first substrate and the second plate and is located in the encapsulation frame. The manufacturing method of the τρτ substrate of the present invention comprises the following steps. A plurality of first wires are formed on the edge regions of the first plate, and the first wires are distributed along the edge regions to form a dielectric layer overlying the first wires. A plurality of second wires are formed on the via layer, and the second wires are juxtaposed with the first wires. A plurality of spacers are formed on the electrical layer to lie above the first conductor, and the height of the recorded end is higher than the height of the second conductor. The shape secret layer covers the second turn and the block. A seal frame is formed to cover the protective layer and is located on the edge region. [Embodiment] The present invention provides a display substrate and a display surface including a display substrate. The 'item display panel preferably includes a liquid crystal display panel; however, in different embodiments, other non-red plane display panels may be used, for example Organic light-emitting diode display = board. Further, in the embodiment shown in FIGS. 2 and 3, the display substrate 1 includes a first substrate, a plurality of first wires 21, and a plurality of first wires 21, The dielectric layer _, the plurality of second wires 1101 are mixed with the 23Q, the protective layer _ and the sealing frame. The first substrate _ is a substrate, for example, a slab substrate or a permeable substrate, so as to be in the rear of the (four) module (not drawn by a human ray. However, one, for example, for use in an organic light-emitting diode display panel The first plate 11G can also be made of a material that is rich in light. 200905287 As shown in Fig. 2 and Fig. 3, the first substrate 11 has a display area (1) and an edge area il3 surrounding the display area 111. The display area ηι In the present invention, the transistor is preferably a thin film transistor. A plurality of first-conductors 21 (H is disposed on the edge region 113) and extend along the edge region 113 In this embodiment, the H line 210 is an elongated metal wire and is parallel to the end of the first substrate 110. The respective first wire 21 turns are preferably parallel to each other with a spacing therebetween to avoid The mutual interference occurs. In addition, the first wire 210 can be formed on the first substrate by various physical or chemical processes, for example, the yellow light, the deposition, the inspection, and the mode can be used as needed. Figure 3 shows the dielectric layer 3 In this embodiment, the dielectric layer is simultaneously extended into the age region ui to form a portion of the transistor 600. The dielectric layer is preferably made of a composite layer having a protective wire. 2H) _, and _ can provide the intersection of insulation: fruit. In addition, as shown in Figure 3, the dielectric layer preferably has a wavy cross-sectional shape. The dielectric layer 3GG is formed above each of the --wire coffee Wave lifting (10); thus forming a valley 330 between adjacent first wires 210. As shown in Figures 2 and 3, a plurality of second wires 22 are disposed on the dielectric reed 300, and the first wire 21Q (five) In other words, the second wire ^ is also located in the range of the display area ni. As shown in FIG. 3, the second wire 2 is disposed at the position of the trough 330 of the wavy section formed by the dielectric layer, and is separated from the first wire 210. In this embodiment, the second wire 22q is a metal wire extending and parallel to the end of the mth. Each of the: 200905287 220 is preferably parallel to each other, and the adjacent second wire is moved. And the second "wire 22G and the first conductor 2_ are kept at a distance to avoid mutual interference, In addition, the first conductive line 210 can be formed on the first substrate 11 () by various physical or chemical processes, for example, yellow light, deposition, silk, and clock reduction can be adopted as needed. As shown in FIG. 2 and FIG. 3, the spacer 2 is disposed on the dielectric layer 3A and above the first conductor 21G; therefore, the spacer 23G is juxtaposed with the second conductor 22, as shown in FIG. As shown, the position of the spacer 23 is the position of the peak 310 formed by the thin dielectric layer. In this embodiment, the spacers 23 are respectively extended along the second conductive line and parallel thereto. When the substrate 11G is viewed as a reference, the height of the top end of the i-block 230 is not lower than the height of the top end of the second wire 22'. In addition, the thickness of the spacer 230 is preferably not less than the height difference between the first conductor 21 and the second conductor, and is preferably not less than 0.8 micron. Preferably, the spacer 230 is composed of an intermediate layer of the first wire 21 and the second wire 220, preferably composed of a layer of stone, and the material thereof may be a non-fourth or polycrystalline compound. However, in various embodiments, the spacer 230 can also be formed from other metallic or non-metallic materials. The protective layer 500 covers the second wire 22 and the pad 23〇. In this embodiment, the protective layer 500 is simultaneously extended to the display region mβ to form a portion of the electromorph 600. The protective layer 500 is preferably made of a compound of the stone, the protection of the first conductor 2U and the second 22q. In addition, as shown in FIG. 3, the protective layer 500 preferably has a wavy cross-sectional frequency; wherein the portion of the protective layer 5 that is positioned above the ’ block is located more than the portion above the second wire 22 为 200905287. Therefore, when subjected to an external force, the protective layer 5 (10) is located above the block 23G and is protected by the knife 220 located on the second wire 22 . The upper I force is added to the second wire, as shown in Figs. 2 and 3, and the sealing frame is placed over the protective layer 500, and is located in the secret area 113. In other words, the seal frame 110 shows the outer side of the area 11丄. For example, ^ (5) Vatican-material 210 channel/sealing frame is overlapped with the first, the spring and the younger-wire 220, so that the area of the edge _113 of the first substrate can be reduced and the edge area ι3 is preferably reduced. The particle structure of the transmission-constant ratio is composed of gold, stone eve, plastic, and the like. Therefore, the portion of the block 23 is disposed above the block 230 to protect the phase turn block 230^; the layer wire 22Q is not damaged by the particle structure in the seal frame. As shown in Fig. 4a and Fig. 4b, the transistor located in the display area lu includes a gate layer, a semiconductor layer, and a source layer. In the example, the ridge block 230 is located at the same level as the semiconductor layer 63. The ▲ is also associated with the semiconductor layer _ in the same process step. However, in various embodiments, the germanium block 23 and the semiconductor layer 63 are formed in the same process steps and have different materials. In the embodiment shown in Figs. 4a and 4b, the first conductor 21 is 曰 ( ( (10) _, (4) ^ the same layer. In other words, the first wire 21 and the idle layer _ are formed in the same step, and the second wire 220 and the gate layer 65 are formed in the same step. In this embodiment, the gate layer 61 includes a gate electrode of a plurality of gates 200905287 bll-parts, and a gate line 611 of a sorted or evenly ordered order, which enters the area m and enters The edge region 113 is bent to form the first wire 21G. Therefore, the portion of the pole line 611 is connected to the first wire 21〇. The other part of the gate and line 611, after entering the edge area ιΐ3, are respectively overlapped with the second wire of the tin-silicon oxide (ΙΤ0) or other conductive material on the different layers. Since the direction of the idle pole line 611 is perpendicular to the first wire 210 and the second wire 220, the connection of the first wire 21〇, the second wire and the gate line is the total transfer amount of the bribe county, and along the edge region. 113 inputs an external signal to the gate line 611. As shown in FIG. 5, the display panel includes the above-described display substrate 1A, second substrate 120, and liquid crystal layer 130. The second substrate 12 is covered on the display substrate (10) and located on the sealing frame. The two substrates 12 () are assembled by the first substrate no of the sealing disk and seal the first substrate 11 and the second substrate. The gap between the edges of the substrate 120. The second substrate 12A is preferably a display surface substrate provided with a color light-emitting layer and has light transmittance. The liquid crystal layer 13 is located between the first substrate ιι and the second substrate 120 and is located within the package 7〇〇. The liquid burial or dripping method is disposed on the first substrate 110 and the second substrate 12. FIG. 6 is a flow chart showing an embodiment of the substrate manufacturing method. As shown in Fig. 6, the step _- includes forming a silk number on the county side of the first and remaining sides; and guiding the wire and distributing the first y wire along the edge and the lagoon. Preferably, the first wire is formed as an elongated metal wire and is parallel to each other and laid to be spaced apart to avoid mutual interference. In addition, the 'first-guide, _ can be used in various physical learning processes on the first substrate, such as yellow light, enamel, silk, continuation, etc., can be used according to the needs of 12 200905287. /Step 930 includes forming a dielectric layer overlying the first wire. The dielectric layer is preferably made of Nitrogen compound and can be formed by various physical or chemical processes: such as Huang Guangming, deposition, steaming, and squaring, etc., may be used as needed. In addition, the dielectric layer of the dielectric layer is preferably formed in the same process step to simplify the process. Since the first conductor protrudes from the first substrate, the dielectric layer preferably forms a valley above each of the -first conductors; and thus forms a valley between adjacent first conductors. Step 950 includes forming a plurality of second conductors on the dielectric layer, the second conductors being juxtaposed with the first conductor. The second wire is preferably gamma formed in the dielectric layer: at various positions of the wave. The second wire is preferably formed as an elongated metal wire, and the first wire is parallel and held at a constant spacing to avoid mutual interference. In addition, the second insult line can be formed on the dielectric layer by various physical or chemical processes, such as yellow light side, deposition, New Zealand, and listening, etc., which can be used as needed. Step 970 includes forming a plurality of spacers on the dielectric layer above the first conductors such that the height of the top of the spacers is higher than the height of the top ends of the second conductors. Preferably, the step includes extending the spacer along the second wire and spacing the spacer from the second conductor. In addition, the germanium block is preferably disposed on the peak formed by the dielectric layer. In a preferred embodiment, the thickness of the mat is not less than 0.8 μm ((4). The mat is preferably composed of _, and the material thereof may be non-rotating, polycrystalline or other compound. Fine in the sole shot: Wei can also be formed by other metals or non-metals (4). The mats can be called physical or chemical processes formed on the dielectric layer, such as crystallization, yellow light, product, evaporation, New Zealand, etc. 13 200905287 It can be used according to the needs of the situation. The step consists of a wire-protecting cover _ second wire and a pad. The protective layer is preferably made of a Nitrogen compound and can be in various physical or chemical processes = for example, yellow Bu deposition, evaporation, and other methods may be used as needed. The germanium layer is preferably formed in the same process step as the transistor protective layer in the display region to simplify the process. The formed protective layer is located. The portion above the first block is protruded from the portion above the first wire. Therefore, when the external force is applied, the portion of the protective layer above the pad is more stressed than the portion above the second wire to increase the second wire. Protection. Steps 990 includes forming a seal frame covering the protective layer and located at the edge region. The truss frame is preferably formed on the protective layer by coating; however, in different real cases, the formed seal frame may be directly formed. On the protective layer, in the embodiment of Figure 7, step 911 is included in the formation of the first wire, and also forms the gate layer of the transistor in the display region. Therefore, the first wire and the closed layer are formed. In the same process step, in addition, this step further includes forming a plurality of gate lines parallel to each other in the gate layer. A part of the gate lines, such as odd-numbered or even-ordered gate lines, pass through the display area and enter the edge. After the region is bent, the first wire is bent. Therefore, the gate lines of the portion are vertically connected to the first wire. The γ 骤 1 1 is included in the formation of the second wire, and simultaneously forms the source bungee of the transistor in the display region. Therefore, the second wire and the source drain layer are formed in the same process step. This step further includes that a part of the gate lines not connected to the first wire are respectively perpendicular to the vertical direction and second in the different layers after entering the edge line region. The wire is overlapped with indium tin oxide 14 200905287 (ΙΤ0) or other conductive material. Step 971 is included in the pad to form the temple, and in the display area... limb + hetero layer. In other words, the pad and the semiconductor layer will paste - Zheng Bu: has the same material f. The material of the semiconductor layer may be non-four (s) = spar or other semiconductor metal or non-metal. ^ has been divided by the above - to interpret, however, the above embodiments are only the side of the present invention. It is to be understood that the disclosed embodiments are not limited to the scope of the invention. The modifications and equivalents of the spirit and scope of the invention are included in the scope of the invention. FIG. 2 is a top view showing an embodiment of a substrate; FIG. 3 is a cross-sectional view showing an embodiment of the substrate; FIG. 4a is a top view showing another embodiment of the substrate; 4b is a cross-sectional view of the embodiment shown in FIG. 4a; FIG. 5 is a cross-sectional view showing an embodiment of the display panel of the present invention; FIG. 6 is a flow chart showing an embodiment of a method for manufacturing a substrate; flow chart. [Main component symbol description] 10 0 display substrate 110 first substrate 200905287 111 display region 113 edge region 210 first wire 300 dielectric layer 310 wave 330 trough 220 second wire 230 pad 500 protective layer 600 transistor 610 gate Layer 611 gate line 630 semiconductor layer 650 source electrode layer 700 sealing frame