TWI237861B - Flip chip package structure and a method of the same - Google Patents

Abstract

A flip chip package structure comprising a substrate, a flip chip, a solder mask, a pre-solder layer, and an organic surface passivation (OSP) covered bump is provided. The solder mask is formed on an upper surface of the substrate and comprises a plurality of openings to define a plurality of connecting points on the substrate. The pre-solder layer fills each of the openings. The OSP covered bump is formed on a pad of the flip chip and extending downward to the opening. The pre-solder layer, which is squeezed by the bump, re-flows upward and covers at least 80% of the exposed surface of the bump, and the OSP on the bump disappears when the pre-solder layer is squeezed.

Description

1237861

V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a F Package Structure and its manufacturing method, earth, and p-lead of a lead-free bump. In particular, it is a method with and without. The flip chip encapsulation structure and its fabrication. Prior technology With the increasing number of semiconductor technologies, the number of contacts has increased, and the distribution method has changed. At the same time, (Pitch ^ 2 0 0 // m) mounted (W ire-Β ο nding) the flip chip connected to the mounting substrate at the same time, 'at the same time, the danger in the tin-lead bumps, so the use of European ship metal The exhibition has also received much attention. Basically, there are no elements such as tin, zinc, etc. Please develop rapidly, and meet the multi-functional communication and connection requirements of point (1/0) processors. Density; from low density. Degree of the Zhou helmet dedicated to one ~ Array Pad with 5 rounds of matrix connection points distribution, processor sealing technology also developed from the traditional wire sealing technology ' Through tin bump direct and Flip Chip Package technology. With the environmental protection concept being taken seriously, people began to realize that lead metal would pollute the land and even cause water resources. The United States and Japan have already legislated to restrict In terms of semiconductor packaging technology, the materials of the bumps of the lead-free bumps include gold, silver, copper, indium.

Page 7 1237861 V. Description of the invention (2)

A schematic diagram of a flip-chip packaging process for lead bumps. The lead-free bumps in this process use copper-containing materials. This flip chip packaging process is disclosed in U.S. Patent No. 6587754B1 " PILLAR CONNECTIONS FOR

SEMICONDUCTOR. First, as shown in FIG. 1A, a photosensitive layer 12 is fabricated on a surface of a wafer 10. Next, as shown in FIG. 1B, the photosensitive layer 12 is exposed according to a predetermined pattern, so that tooth holes 14 are formed in the photosensitive layer 12 to expose the wafer 10 under the photosensitive layer 12. Subsequently, as shown in FIG. 1C, a copper-containing material is filled in a portion below the perforation 14, that is, a portion close to the wafer 10, to form a copper pillar structure (Copper Pi 1 lar) 16a. Basically, this step can be achieved by using electroplating technology or copper bath technology (copper.) Then, as shown in the first D diagram, the vias 14 are filled with solder to complete the solder located above the copper pillar structure 16a. "Column structure" 4 or 8 'will be filled into the perforation by Yu Ke. Removal = 2 light layers 12 to complete the wafer part: made, and then the column structure 16a, 16b figure = inverted = sheet 10 together with the production On the surface r, two solder pillars are placed b: contact = pad 22. Next, as in the first and the connecting structure 16b on the surface of the clothing substrate 20, the solder is reflowed: do not 'moderately heat this solder pillar joint, In order to make the chip 10 be electrically connected to ΪΓ22 and fully connect 30 to the chip 10 and the package: the post structure is filled with insulating material 乂 ^ to ensure this columnar structure 1237861 V. Description of the invention (3) 16a, 16b ' And prevent the columnar structures 16a, 16b from breaking with the bonding surface of the wafer 10 or the package substrate 20. The aforementioned flip-chip package structure mainly has the following two disadvantages: Because copper is very easy to oxidize, therefore, Process towel of structure 1 6 b, divided into 4 monks < same as on copper pillar structure 1 6 The exposed surface of a is iw + .oxygen, Y. Due to the wet effect of the solder on the copper oxide layer = 1 2: far less than the wet effect on the copper metal, therefore, the copper connection is reliable: it leads to solder pillars Solder between the shape structure 16a and the copper pillar structure 16a: The weakest part of the shape crystal package structure is the joint main junction. Therefore, as η #, the force is slightly equivalent to the cross-sectional area of the copper pillar structure 16a. The cross-sectional area must also increase the density of the mesh connection points, and the joint strength of the copper pillar structure ... is relatively insignificant ^ ^ causing the 16c area of the joint surface to decrease, which leads to the lack of reliability ^ = to overcome the structure faced by traditional packaging structures Strength and essential issues. ,,,,,, and 'have become the mains to be overcome in the field of packaging technology today. [Summary of the invention The main purpose of the present invention is to improve the joint surface of solder and copper pillar structure: hair :: Another high joint strength and reliability At a glance, the traditional copper pillar structure is expected to be encapsulated

Page 91237861 V. Oxidation phenomenon faced in the description of the invention (4) 'Propose to solve the solder mask layer and pre-solder layer of the flip chip sealing / surface provided by the present invention, including the electric bumps produced on the package substrate . Among them, the solder mask layer 'position f: a lead-free conductive opening on the surface of the flip-chip to define the upper surface between the flip-chip and the substrate of the seal, and a layer is filled in this opening. The position of the connection point of the gold-free L-lane, and the pre-solder extends down into the opening, the same ;: the box bump is the wettability of the contact pad surface of the flip-chip surface ... the second electric bump

MateHd Layer). Fill in; ^^ 面. An insulating layer (Under-fill pre-solder layer and lead-free conductive bumps ^ between the substrate and the flip chip to protect the frost provided by the present invention. The sealed conductive bumps are formed by the wafer surface: then: two. Includes ... At least-no protective layer covers this lead-free conductive &# = outer extension, make a surface to protect the surface of the board to define the pre-solder layer between the chip and the package substrate in the opening of the solder mask, and this reflow temperature Above, pass the point f, and heat the pre-lead material layer to the above-mentioned lead-conducting bumps to place a solder resist; said ::: Place on the package substrate so that the pre-solder layer does not flow upward. ^: Sub-pressing the pre-solder layer and the lead-free conductive bumps. The edge-preserving pre-fresh layer can further understand the advantages and spirit of the present invention in the drawings. The following description banges on page 101237861

[Embodiment] ^ The second A to Η diagrams show a preferred embodiment of the flip-chip packaging method of the present invention.

Think chart. First, as shown in FIG. 2A, a photosensitive layer 12 is formed on a surface of a wafer 100 which has completed the previous process. Next, as shown in FIG. 2B, the photosensitive layer 120 is exposed according to a predetermined pattern to make perforations 140 to expose the surface of the wafer 100, especially the portion of the contact pad 50, under the photosensitive layer 120. Subsequently, as shown in FIG. 2C, a lead-free conductive material, such as a copper-containing material, is filled in the through hole 40 to form a lead-free conductive bump 16o above the contact pad 15o. Basically, this step can be achieved by electroplating technology or copper bath technology. It is worth noting that the shape of the lead-free conductive bump 160 is corresponding to the shape of the wafer 100 surface contact pad 150 to provide better bonding effect. Therefore, under the circumstance that the current contact pad 150 adopts a circular or polygonal design, for a preferred embodiment, the lead-free conductive bump 610 should be designed with a cylindrical shape. Next, as shown in FIG. 20, the unnecessary photosensitive layer 120 is removed. Then, an anti-oxidation surface protection layer 180 is formed, such as an organic surface protection layer (〇rganic Surface

Passivation (OSP) 'on the exposed surface of the oblique-free conductive bump 160 to prevent oxidation of the lead-free conductive bump 160. In addition, as shown in the second E diagram, a solder mask 240 is formed on the surface of a packaging substrate 2000, and the solder mask 24 has an opening 2 60 to expose the packaging substrate 2 Connection point on 0 0 2 2 0. Basically, the shape of the opening 260 is designed to correspond to the shape of the error-free conductive bump 160,

Page 11 1237861

5. Description of the invention (6) Second, for better joining effect. Therefore, in the case of the design of the lead-free conductive bump 160, the opening 26 () of the solder resist layer 240 should also be set in a circular shape. As shown in the second F figure, the pre-solder layer 280 is applied. If lead is recorded, = lead-free solder, within the opening 26 of the solder resist layer 24. It is worth noting that the reflow temperature of this pre-solder layer 28 () (Ref lowable " ¥ melting point of the bump 160). The core f 'heats the pre-solder layer 280 above its reflow temperature, Ran 1 # ΐ As shown in the second figure, the wafer 100 is then placed upside down on the gates of the package substrates 20, and 0, and the solder resist layer 240-2 is placed correspondingly to the lead-free conductive bump 160 series, and downwards. The pre-solder layer 2 8 0 ′ is pressed, so that the pre-solder layer automatically covers at least 80% of the exposed surface of the lead-free conductive bump 160 at the same time.;: System = = the surface protection layer 180 of the lead-free conductive bump 160 will be here 3 〇〇 于 \ ^ / 失. Finally, as shown in the second figure, filled with insulating materials: V; 2 ;: °; ί i :; Γ ° V ^ Af 1Λ 6〇 ^ I vanadium ϋ Π Π_ The surface of the road is protected to prevent lead-free conductive bumps 1 60 and prevent the joint surface of the block 16 ° from contacting 15 ° from breaking to improve the method. Chip package square solder mask # 24ί) The package structure includes a wafer chip, a package substrate 200, soldering two: bit: 28 ° material layer, and an error-free conductive bump 160. Among them, the resistance 240 is located on the surface of the sealing substrate 200, and the lead-free conductive bump 160 is contacted by the surface of the flip chip 100

Page 121237861 V. Description of the invention (7) 塾 150 extends downwards into the opening 26 °. At the same time, the pre-system is affected by the wetting of the surface of the error-free conductive bump 160, and the material flows upward. Uetting f〇rce). The joint surface of the lead-free cold-electrical bump 160 with at least 80% of the exposed surface area of the solder layer 280 'and the error-free conductive bump 160 has a significant increase in the bonding strength of the package structure. And this small joint area mainly depends on the size of the solder resist opening 26 and the lead cross section area. In terms of a preferred embodiment? ： In the case of a material with sufficient quality, in order to make the pre-solder layer ·, the material 2 flows at least 80% of the exposed surface of the error-free conductive bump 160, and is prevented from being produced in the layer opening 2 60 and lead-free. The diameter ratio of the conductive bumps 160 must be between 0.55. · 丄 · α ^ In order to prevent the components made on the surface of the wafer 1000 from being sealed in this dream, we will draw 'Before entering the second A picture' step, 'the two can be made in advance' and the passivation layer. 'Such as a silicon nitride layer or ρ, the surface of the f-chip 100 is covered to protect the circuits and components on the surface of the chip 100, and a part of the f-contact pad 150 is exposed through this protective layer. Compared with the traditional flip-chip package structure shown in the first F diagram, the following advantages are provided: First, the flip-chip package in the first F diagram: Japan's Silicone Co., Ltd. and copper pillar structure 16 & The area of the joint surface 16c is only...; ^ The cross-sectional area of the main structure 16b la. In the present invention, please refer to the same; structure: the solder layer 280 'covers at least 8 of the non-shipping conductive bump 160. Dagger surface 'to provide a larger joint area. Therefore, the flip-chip seal of the present invention

苐 Page 13 Ϊ237861 V. Ming Ming explained (8) The structure obviously has strong structural strength and reliability. 2. As shown in Figure 1E, the process of heating the solder pillar structure 丨 6b often produces a copper oxide layer on the exposed surface of the copper pillar structure 16a at the same time, and the wet effect of the solder on the copper pillar structure 16a. In the present invention, 'please refer to Figure 2E at the same time. The helmet makes the surface of the L track to be pre-washed. The right side & 3 kilograms of V electric bumps 1 60 are not exposed. The thickness of the surface is 1 η. This is the second G figure. From this surface protection layer 180 — until the b step, the pre-soldering sound, the lead conductive bump 16n_ ^ the material of the rod layer flows upward. There is no coverage; Therefore, the reliability of the copper oxide layer can be prevented. ,, dry ;, the joint between the layer 280 and the lead-free conductive bumps 160 制 ί ΐ Profit: The preferred embodiment describes the present invention in detail, but is not limited to making minor changes and knowing such skills Anyone can understand that it is appropriate to not deviate from the essence of the present invention ^ = 丄 will still not lose the essence of the present invention, but also the scope and scope.

Page 14 1237861 Brief description of the diagrams Brief explanation of the diagrams · The first A to F diagrams are schematic diagrams of the flow of the flip-chip packaging method in the invention of US Patent No. 6587754B1 CONNECTIONS FOR SEMICONDUCTOR CHIPS AND METHOD OF MANUACTURE " The second to A-th diagrams are schematic diagrams of a preferred embodiment of the flip-chip packaging method of the present invention. Description of drawing number: Wafer 1 0, 1 0 0 < Photosensitive layer 12, 120 Perforation 14, 140 Copper pillar structure 16a Solder pillar structure 16b, 16b 'Joint surface 1 6 c Package substrate 2 0, 2 0 0 Connection point 2 2, 2 2 0 Insulating material 30, 3 0 0 Contact pads 1 5 0 Lead-free conductive bumps 1 6 0 Surface protection layer 1 8 0 Fresh-prevention layer 2 4 0 Opening 26 0 Pre-solder layer 2 8 0, 2 8 0,

Claims (1)

1237861 VI. Application for patent scope I Application scope of patent: Type: “Package f” is used to package wafers, including: Define the upper surface of 2 boards at the connection points on the package substrate, and have openings to define-pre-solder layer, fill In the opening; at least one error-free conductive convex area extending down into the opening, and j), the pre-solder layer from the contact pad surface of the wafer surface, ^, and stomach Λ f ~ the lead-free conductive layer is subjected to the lead-free conductive The function of the bump (Uing force) flows upward to cover at least 80% of the exposed side of the Aluminium V-electric bump; and ..., an under-fill layer, which is filled in the wafer and the cloth soil board The delta-hai lead-free conductive bump and the exposed surface of the pre-solder layer are covered in between. 2. The flip-chip packaging structure according to item 1 of the patent application scope, wherein the lead-free conductive bumps are columnar (clumn). 3. The flip-chip packaging structure according to item 1 of the patent application scope, wherein the size ratio of the opening of the solder resist to the lead-free conductive bump is 0.5-1. 5. 4. The chip-on-chip packaging structure according to claim 1 further includes a protective layer on the surface of the wafer, and the protective layer has an opening to define the position of the contact pads on the surface of the chip. 5. The flip-chip packaging structure as described in the first item of the patent application, wherein the valley point of the error-free conductive bump material is still at a reflow temperature far from the pre-fresh layer. 6. The flip-chip packaging structure according to item 1 of the scope of patent application, wherein the helmet bump is made of copper. …. Conductive 7. The chip-on-package structure as described in item 1 of the patent application, wherein the pre-fresh layer Page 16 1237861 6. Scope of patent application It is made of faulty solder or lead-free solder. 8. If the frost of item 1 of the scope of the patent application is to completely cover the error-free conductive bumps, said structure 4 is the pre-solder layer. 9. A method for making a flip-chip package structure, including ... A wafer, the surface of the wafer has 1 丄, and the "plane f" has-the connection between the anti-oxidation layer ^ ^ 4 the substrate surface has ^ M layer to define the wafer and the substrate to form a pre-solder layer on the resistive recording The operating temperature is lower than the refining point Θ of the error-free conductive bump ^ 〃 1 re-solder layer of the dry material layer above its reflowable temperature; the wafer is placed upside down μ, μ, the opening of the solder layer Within t = p, the lead-conducting bump system is placed into the resistance flow to cover the no bump until the pre-solder layer is heated to the surface protection layer and disappears; and the side of the road, at the same time, the 1 η 4 A true & charge edge material is between the wafer and the substrate. • The 9th top of the patent scope of σ Shen Jing, Qu, Li Zhong, # y includes: the method of the 9th item, and the manufacturing steps of the said film ^ conductive pattern layer on the surface of the wafer; The exposed surface of the conductive pattern layer of the block is used to define the rough electric bump without filling in the conductive material; 于, in the opening of the photoresist pattern, to make the lead-free guide to remove the photoresist pattern; and «17 page 1237861 6. Scope of patent application An oxidation-resistant surface protection layer is made to cover the exposed surface of the lead-free conductive bump. 11. The method according to item 9 of the application, wherein the pre-solder layer completely covers the non-slanted conductive bump. 1 2. The method according to item 9 of the patent application scope, wherein the surface protection layer is an organic surface protection layer (Organic Surface Passivation, OSP). 1 3. The method according to item 9 of the scope of patent application, wherein the lead-free conductive bumps are columnar 〇1 4. The method according to item 9 of the patent scope, wherein the lead-free conductive bumps are made of copper . 1 5. The method according to item 9 of the patent application scope, wherein the pre-solder layer is composed of a lead solder or a lead-free solder. Page 18