TWI536474B - Unequal height columnar bump structure - Google Patents

Description

Unequal height columnar bump structure

The present invention relates to a bump structure for a semiconductor wafer, and more particularly to an unequal columnar bump structure for eliminating the coplanar difference of solder.

In today's semiconductor packaging technology, high-efficiency electronic components usually use solder balls or solder bumps to achieve electrical and mechanical connection between each other. The flip chip bonding is a joint of the wafer Array, so it can be applied to a very high density fabric wiring process. To put it simply, the concept of flip-chip bonding is to first form solder bumps on the pads of the IC chip, then place the IC wafer on the package substrate and complete the pad alignment, and reflow (Reflow). The heat treatment is combined with the surface tension effect of the solder to melt the balls into balls, thereby completing the bonding of the IC wafer and the substrate. At the requirement of bump micro-pitch, the flip-chip bonding of the early solder bumps has gradually turned into a flip chip bonding of the solder joints on the stud bumps, that is, the metal post soldering wafer connection structure (Metal Post Solder-Chip) Connection, MPS-C2).

However, in the conventional MPS-C2 flip-chip bonding process, if the columnar bumps are grown on the surface of the IC wafer of non-equal height, the height of the columnar bumps will be different during reflow and affect the flatness of the surface soldering. Bonding to the mounting substrate causes tilting, joint soldering or solder diffusion to adjacent columnar bumps In the case of a block, the reliability of flip chip bonding is caused.

As shown in FIG. 1 , it is a schematic cross-sectional view and a schematic plan view of a conventional columnar bump structure. The stud bump structure 100 includes a wafer 110, a first stud bump 120, a second stud bump 130, a first solder 140, and a second solder 150. The first stud bumps 120 are disposed on the pads 112 of the wafer 110, and the second stud bumps 130 are disposed on the protective layer 113 of the wafer 110, thereby causing the second stud bumps 130. The second soldering top surface 131 is higher than the first soldering top surface 121 of the first stud bump 120. The first solder 140 and the second solder 150 are respectively formed on the first soldering top surface 121 of the first stud bump 120 and the second solder top surface 131 of the second stud bump 130. After the reflow heat treatment is performed to melt the solder, a solder height difference H1 is generated. After soldering to the package substrate, the solder of the second solder 150 is diffused, and the first stud bump 120 is cooled. Welding defects such as welding, air welding or false welding, which in turn affect packaging reliability.

In order to solve the problem of the height of the columnar bumps, it has been proposed to use a plurality of electroplating methods to make the heights of the respective columnar bumps the same, for example, the national patent number No. I228814 "a solder bump structure and a manufacturing method for avoiding parasitic capacitance" After forming a metal pad on the lower height of the bump setting plane, an under bump metallurgy layer (UBM layer) is formed, and then the height is formed on the metal layer under each bump. The columnar bumps, but requiring a complicated number of plating steps, also take time to increase the manufacturing cost of the bumps.

In order to solve the above problems, the main object of the present invention is to provide an unequal columnar bump structure which eliminates the coplanar difference of solder, and can reduce the columnar bumps in the metal pillar soldered wafer connection (MPS-C2) structure. The process steps and achieve the purpose of coplanar bonding of the columnar bumps.

A second object of the present invention is to provide an unequal columnar bump structure in which the coplanar difference of the solder is eliminated, and the shape of the different stud bumps can be made in the same patterned photoresist, and the shape is after reflow. The special difference can be used for the storage and storage of the solder on the higher columnar bumps inside the columnar bumps, so that the different functions of the unequal columnar bumps (such as functional bumps and dummy bumps) can also be used as coplanar joints. The problem of solder diffusion and void soldering on the columnar bumps is avoided, and the effect of reducing the process steps and the wafer connection of good metal pillar soldering is achieved.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a unequal height stud bump structure for eliminating coplanar difference of solder, comprising a wafer, a first stud bump, a second stud bump, a first solder and a second solder. The active surface of the wafer has a pad and a protective layer exposed to one of the openings of the protective layer. The first stud bump is disposed on the solder pad and has a first solder top surface. The second stud bump is disposed on the protective layer and has a second soldering top surface, wherein the second soldering top surface is higher than the first soldering top surface from the protective layer. The first solder is formed on the first solder top surface. The second solder is formed on the second solder top surface. The second stud bump has a crack recessed inwardly from the second solder top surface to accommodate a portion of the second solder. The invention further discloses a method for manufacturing a unequal height stud bump structure which eliminates the coplanar difference of the solder.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the foregoing unequal columnar bump structure, the crack may be located at the center of the second soldering top surface and communicated inwardly to the protective layer such that the second stud bump is a hollow cylinder. Not only the shared process but also the same shape as the unequal columnar bumps.

In the foregoing unequal height stud bump structure, the first columnar shape The bump system can be a solid cylinder, and the bottom coverage area of the first columnar bump can be no more than the solder pad, that is, as a bumping micro-contact with electrical function.

In the foregoing unequal-column bump structure, the second soldering top surface can be formed by using the crack so that the area of the second soldering top surface is smaller than the area of the first soldering top surface, thereby reducing the retention The amount of solder on the second stud bump.

In the unequal columnar bump structure, the first stud bump can be a functional bump, and the second stud bump can be a dummy bump, so that it can be integrated into different uses. The stud bumps are on the same wafer.

In the foregoing unequal columnar bump structure, an interposer insulating layer may be further disposed between the protective layer and the active surface, and the pad is via a plurality of micro-guides penetrating the interposer insulating layer The holes are electrically connected to the active surface to prevent stress acting on the stud bumps from damaging the integrated circuit of the wafer.

In the foregoing unequal columnar bump structure, the first stud bump and the second stud bump may have the same metal material, column height and column shape.

In the foregoing unequal columnar bump structure, the second solder system may not completely fill the crack, so that the inside of the second columnar bump forms a gas trap with expansion/reduction variability, which is elastic. The second solder is housed.

In the unequal columnar bump structure, a solid under bump metal layer may be formed between the first stud bump and the solder pad, and the second stud bump and the protective layer The interlayer can be formed with a metal layer under the annular bump.

H1‧‧‧ height difference

100‧‧‧ Columnar bump structure

110‧‧‧ wafer

111‧‧‧Active surface

112‧‧‧ solder pads

113‧‧‧Protective layer

114‧‧‧Opening

120‧‧‧First columnar bump

121‧‧‧First welding top surface

130‧‧‧Second columnar bump

131‧‧‧Second welding top surface

140‧‧‧First solder

150‧‧‧second solder

200‧‧‧Unequal height stud bump structure

210‧‧‧ wafer

211‧‧‧ active face

212‧‧‧ solder pads

213‧‧‧Protective layer

214‧‧‧ opening

215‧‧‧Intermediate insulation

216‧‧‧Micro-conducting holes

220‧‧‧First columnar bump

221‧‧‧First welding top

230‧‧‧Second columnar bump

231‧‧‧Second welding top

232‧‧‧ crack

233‧‧‧ gas trap

240‧‧‧First solder

250‧‧‧second solder

260‧‧‧ under bump metal layer

261‧‧‧Solid under bump metal layer

262‧‧‧Under the metal layer of the annular bump

270‧‧‧Light resistance

271‧‧‧First bump hollow pattern

272‧‧‧Second bump hollow pattern

273‧‧‧ straight column

Fig. 1 is a schematic cross-sectional view (A) and a plan view (B) of a conventional columnar bump structure.

2 is a cross-sectional view (A) and a top view (B) of a unequal height stud bump structure in which the coplanar difference of the solder is reduced according to an embodiment of the present invention.

3 to 7 are schematic cross-sectional views (A) and a plan view (B) of each intermediate stage in the process of fabricating the unequal-high columnar bump structure according to an embodiment of the present invention.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

According to an embodiment of the present invention, an unequal height stud bump structure of a co-planar difference of the anti-smear solder is illustrated in a cross-sectional view (A) and a top view (B) of FIG. 2 . The unequal columnar bump structure 200 includes a wafer 210, a first stud bump 220, a second stud bump 230, a first solder 240, and a second solder 250.

The active surface 211 of the wafer 210 has a solder pad 212 and a protective layer 213. The solder pad 212 is exposed to one of the openings 214 of the protective layer 213. Specifically, the wafer 210 may be a semiconductor device formed with an integrated circuit (IC), such as a memory chip, a logic chip, a special application chip, or the like, which may be divided by a wafer. The active surface 211 is provided with integrated circuit components such as a microcontroller, a microprocessor, a memory, a logic circuit, a special application integrated circuit (such as a display driving circuit), or the like, or a combination thereof. The solder pad 212 can be an aluminum pad or a copper pad. Electrically connected to the integrated circuit components. The pads 212 are actually a plurality of pads. The pad 212 is disposed on a single side, two corresponding sides, a peripheral side, a center position, or a matrix array type of the active surface 211 of the wafer 210. The protective layer 213 (for example, a dielectric material such as PI) may be formed on the active surface 211 to protect the underlying film layers from environmental pollutants. The protective layer 213 is patterned to form an opening 214 of the protective layer 213 to expose the pad 212.

As shown in FIG. 2(A), in the embodiment, the unequal stud bump structure 200 may further include an interposer insulating layer 215. The dielectric insulating layer 215 is disposed between the protective layer 213 and the active surface 211 , and the solder pad 212 is electrically connected to the active surface 211 via a plurality of microvias 216 extending through the dielectric insulating layer 215 . Specifically, the microvias 216 are formed in the interposer 215 and penetrate therethrough to provide an electrical conduction path of the pad 212. The microvias 216 may be formed using techniques such as optical lithography and electroplating. A photoresist material is deposited on the interposer 215 and patterned to expose a portion of the interposer 215 to the microvias 216. An opening may be formed in the microvia 216 of the dielectric insulating layer 215 using an etching process such as an anisotropic dry etching process. The opening may be a liner using a diffusion barrier layer and/or an adhesive layer (not shown) and filled with a conductive material to form the microvias 216.

In detail, as shown in FIG. 2 , the first stud bump 220 is disposed on the solder pad 212 and has a first solder top surface 221 . The second stud bump 230 is disposed on the protective layer 213 and has a second soldering top surface 231, wherein the second soldering top surface 231 is higher than the first soldering top surface 221 The protective layer 213. In other words, the first stud bump 220 and the second stud bump 230 have different heights of the solder top surface and have different functions. In more detail, the first stud bump 220 can be a functional bump, for example, as an integrated circuit inside the wafer 210. The second columnar bump 230 can be a dummy bump, that is, the second pillar bump 230 can be electrically inductive. The bumps are not electrically connected to the integrated circuit inside the wafer 210, but are provided for other uses, such as support bumps and micro-spaced sustain bumps.

Preferably, the first stud bump 220 and the second stud bump 230 can have the same metal material, column height and column shape, and can be formed simultaneously in a one-time process, thereby saving cost. In detail, the first stud bumps 220 and the second stud bumps 230 are non-reflow bumps, such as gold bumps, copper bumps, aluminum bumps or A polymer conductive bump in which a copper pillar is preferred. The shape of the first stud bump 220 and the second stud bump 230 may be a square shape, a column shape or a thin column shape. Preferably, the first stud bump 220 and the second stud bump 230 are columnar conductors having high temperature resistance, good thermal conductivity and no deformation characteristics, such as copper pillars. The first stud bump 220 and the second stud bump 230 play a good interval maintaining role, and do not cause excessive collapse of the bump during the flip chip bonding process, and the copper post can be formed by low-cost plating. .

Further, as shown in FIG. 2(A), the first solder 240 is formed on the first bonding top surface 221. The second solder 250 is formed on the second solder top surface 231. The second stud bump 230 has a crack 232 recessed inwardly from the second solder top surface 231 to accommodate a portion of the second solder 250. It should be noted that the crack 232 can be located at the center of the second soldering top surface 231 and communicated to the protective layer 213 inwardly so that the second stud bump 230 is a hollow cylinder. In particular, when performing a reflow step, since the second solder top surface 231 has a crack 232 recessed inward, when the second solder 250 reaches a reflow temperature (about 217 degrees Celsius) or more Producing fluidity, causing a portion of the second solder 250 to collapse In the crack 232, the height of the second solder 250 is further lowered, so that the solder height difference between the first stud bump 220 and the second stud bump 230 is reduced, and the columnar bump structure can be optimally obtained. The bumps of the bumps of 200 reach an equal height state. In addition, the present invention can omit the conventional multiple plating steps to achieve the purpose of unequal height bumps in a one-time step (described in detail later).

As shown in FIG. 2(A), in the embodiment, the second solder 250 may not completely fill the crack 232, so that the inside of the second stud bump 230 is formed with an expansion/reduction. The variability gas trap 233 can adjust the welding amount of the second solder 250 during thermal expansion and contraction, and does not diffuse to other adjacent columnar bumps. When the temperature rises, the second solder 250 contained in the crack 232 is reduced, the amount of soldering of the second solder 250 on the second solder top surface 231 is increased; when the temperature is lowered and still above the melting point At this time, the second solder 250 is gradually accommodated in the crack 232 to prevent solder from spreading.

Figures 3 through 7 show various intermediate stages for fabricating structures having unequal height stud bumps in accordance with an embodiment of the present invention.

Referring first to Figure 3, a wafer 210, shown in part in accordance with an embodiment of the present invention, may be formed in a wafer. The active surface 211 of the wafer 210 has a pad 212 and a protective layer 213. The pad 212 is exposed to one of the openings 214 of the protective layer 213. The protective layer 213 may be a polyimide layer. Preferably, an intermediate insulating layer 215 may be formed between the active surface 211 and the protective layer 213, and the solder pad 212 is The micro-via 216 is electrically connected to the integrated circuit layer 215 and electrically connected to the integrated circuit region of the active surface 211. A fully covered under bump metal layer 260 is formed on the protective layer 213 of the wafer 210 and can be formed by chemical vapor deposition or physical vapor deposition. The under bump metal layer 260 is composed of a conductive material. A sub-seed layer that helps to form a thicker layer of electroplated film during subsequent processing steps. In an embodiment, the under bump metal layer 260 may be formed by depositing one or more thin conductive layers, such as one or more layers of copper, titanium, tantalum, titanium nitride, tantalum nitride, combinations of the foregoing, or the like. A thin layer of composition. For example, in one embodiment, a titanium layer is deposited by a physical vapor deposition process to form a diffusion barrier film, and a copper layer is deposited by a physical vapor deposition process to form a copper seed layer. The under bump metal layer 260 is simultaneously connected to the pad 212 via the opening 214.

Thereafter, as shown in FIG. 4, a photoresist 270 is formed on the under bump metal layer 260 in accordance with an embodiment of the present invention. The photoresist 270 is used to define the shape of the stud bumps, and the shape of the stud bumps will be described in more detail later. The photoresist 270 can be a patterned photoresist mask, a hard mask, combinations of the foregoing, or the like. Specifically, the photoresist 270 is patterned after exposure and development. As shown in FIG. 4(A), the photoresist 270 has a first bump hollow pattern 271 and a second bump hollow pattern 272. The shapes correspond to the first stud bumps 120 and the second stud bumps 130, respectively. Referring to FIGS. 2(A) and 4(A), the first bump hollow pattern 271 is a lateral boundary of the first stud bump 220. The lateral diameter of the first bump hollow pattern 271 and the second bump hollow pattern 272 may be the same, but the middle of the second bump hollow pattern 272 is formed with a straight column 273 to be reserved for the second The crack 232 of the stud bump 230.

Figure 5 shows a first stud bump 220 and a second stud bump 230 formed in accordance with an embodiment of the present invention. Performing a first bump plating step by patterning the photoresist 270 to form the first stud bump 220 and the second stud bump 230, wherein the first stud bump 220 and the first The two stud bumps 230 may be of the same metal material, such as copper (Cu). The first stud bump 220 is disposed on the solder pad 212 and has the first soldering top surface 221. The second stud bump 230 is disposed on the protective layer 213 and has the second soldering top surface. 231, wherein the length of the column is the same at the same plating time The degree should be the same. Since the protective layer 213 is at a higher level than the pad 212, the second soldering top surface 231 is higher than the first soldering top surface 221 for protection. The layer 213, and the second stud bump 230 has a crack 232 recessed inwardly from the second solder top surface 231, which is defined by the straight post 273.

In detail, the first stud bump 220 and the second stud bump 230 may also be formed of any other suitable conductive material, including copper, nickel, platinum, aluminum, a combination of the foregoing, or the like. And can be formed by appropriate plating techniques. In one embodiment, the thickness of the first stud bumps 220 and the second stud bumps 230 is about 30 to 60 μm. Preferably, the first stud bump 220 can be a solid cylinder, and the bottom cover area of the first stud bump 220 can not exceed the solder pad 212 to achieve miniaturization of the stud bumps. The shape of the solder pad 212 may be a rectangle. The shape of the first stud bump 220 may be a cylindrical shape, and the upright wall surface without the blocking colloid flow is favorable for the underfill filling of the flip chip gap.

As shown in FIG. 5, the second bump plating step is performed along the patterned photoresist 270 to form the first solder 240 and the second solder 250, wherein the first solder 240 is formed on the first On the solder top surface 221, the second solder 250 is formed on the second solder top surface 231. The first solder 240 and the second solder 250 have the same thickness at the same plating time, and are formed on the first stud bump 220 and the second stud bump 230, respectively. Usually, the solders 240 and 250 may be lead-free solders such as tin-silver (Sn/Ag).

Thereafter, as shown in FIGS. 5 and 6, the photoresist 270 is removed to expose the first stud bump 220 and the second stud bump 230 and most of the under bump metal layer 260. . It should be noted that, as shown in FIG. 6(A), the crack 232 may be located at the center of the second soldering top surface 231 and communicated inwardly to the under bump metal layer 260 to make the second pillar convex. Piece 230 is a hollow cylinder. The second soldering top surface 231 can be formed by using the crack 232 such that the area of the second soldering top surface 231 is smaller than the area of the first soldering top surface 221 .

Thereafter, as shown in FIGS. 6 and 7, the under bump metal layer 260 is removed. The exposed portion of the under bump metal layer 260 and any contaminants on the surface of the protective layer 213 may be removed using an anisotropic dry etch process or a wet etch process. Therefore, the remaining portion of the under bump metal layer 260 is a solid under bump metal layer 261 formed between the first stud bump 220 and the pad 212, and the second stud bump An annular under bump metal layer 262 is formed between the 230 and the protective layer 213. The second stud bump 230 will not be connected to the integrated circuit region of the wafer 210, but is a dummy bump, and the first stud bump 220 can be a functional bump ( Active bump). The second stud bump 230 does not have an electrical transfer function, and functions mainly as a buffer for the easily breakable bump region, mechanically maintaining the flip-chip bonding gap, positioning during flip chip bonding, or making the primer flow more. One of the non-electrical connection functions such as homogenization or the combination of the above functions.

Finally, as shown in FIG. 2(A), a reflow step is performed to accommodate a portion of the second solder 250 in the crack 232, thereby lowering the height of the second solder 250 to cause the stud bump The block structure 200 reaches an equal height state. Therefore, the present invention enables the unequal columnar bumps to achieve coplanar solder joints, and simplifies the bump process steps and achieves good bump soldering. Specifically, the size of the opening of the crack 232 can be adjusted by using the straight column 273 of the second hollow pattern 272 of the photoresist, which is appropriately adjusted for the height difference between the protective layer 213 and the pad 212. After the reflow step, a wafer dicing process can be performed to separate into individual wafers for flip chip bonding or wafer stacking processes.

Therefore, the present invention provides a coplanar difference in the anti-squeeze solder The unequal columnar bump structure is designed with different columnar bump shapes, and the solder collapses due to the shape difference after reflow, so that the unequal columnar bumps reach the coplanar solder joint and the bump process can be simplified. Steps and get good bump soldering effect.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

200‧‧‧Unequal height stud bump structure

210‧‧‧ wafer

211‧‧‧ active face

212‧‧‧ solder pads

213‧‧‧Protective layer

214‧‧‧ opening

215‧‧‧Intermediate insulation

216‧‧‧Micro-conducting holes

220‧‧‧First columnar bump

221‧‧‧First welding top

230‧‧‧Second columnar bump

231‧‧‧Second welding top

232‧‧‧ crack

233‧‧‧ gas trap

240‧‧‧First solder

250‧‧‧second solder

261‧‧‧Solid under bump metal layer

262‧‧‧Under the metal layer of the annular bump

Claims (10)

An unequal columnar bump structure for eliminating coplanar difference of solder, comprising: a wafer having an active surface having a pad and a protective layer, the pad being exposed to one of the openings of the protective layer; a columnar bump is disposed on the solder pad and has a first soldering top surface; a second stud bump is disposed on the protective layer and has a second soldering top surface, wherein the second soldering surface The top surface is higher than the first solder top surface by the protective layer; a first solder is formed on the first solder top surface; and a second solder is formed on the second solder a top surface; wherein the second stud bump has a crack recessed inwardly from the second solder top surface to receive a portion of the second solder; wherein the first stud bump and the solder A solid under bump metal layer is formed between the pads, and an annular under bump metal layer is formed between the second stud bump and the protective layer. An unequal height stud bump structure according to claim 1, wherein the crack is located at a center of the second solder top surface and communicates inwardly to the protective layer to enable the The second columnar bump is a hollow cylinder. The unequal height stud bump structure according to the second aspect of the patent application scope, wherein the first stud bump is a solid cylinder, and the bottom of the first stud bump is covered The area is not more than the pad. The unequal height stud bump structure according to claim 1, wherein the second solder top surface is formed by using the crack so that the area of the second solder top surface is smaller than the the first The area of the top surface of the weld. The unequal height stud bump structure according to claim 1, wherein the first stud bump is a functional bump, and the second stud bump is a Dummy bumps. The unequal height stud bump structure according to the fifth aspect of the patent application scope, further comprising an intervening insulating layer disposed between the protective layer and the active surface, and the solder pad The active surface is electrically connected via a plurality of microvias extending through the dielectric insulating layer. The unequal height stud bump structure of the dissipative solder coplanar difference according to claim 1, wherein the first stud bump and the second stud bump have the same metal material and column height With a column profile. The unequal height stud bump structure according to claim 1, wherein the second solder system does not completely fill the crack to form an inner portion of the second stud bump There is a gas trap that expands/reduces variability. An unequal columnar bump structure for eliminating coplanar difference of solder, comprising: a wafer having an active surface having a pad and a protective layer, the pad being exposed to one of the openings of the protective layer; a columnar bump is disposed on the solder pad and has a first soldering top surface; a second stud bump is disposed on the protective layer and has a second soldering top surface, wherein the second soldering surface The top surface is higher than the first solder top surface by the protective layer; a first solder is formed on the first solder top surface; and a second solder is formed on the second solder a top surface; wherein the second columnar bump has a top surface of the second soldering surface a concave crack to accommodate a portion of the second solder; wherein the first stud bump is a functional bump and the second stud bump is a dummy bump; the unequal height The columnar bump structure further includes an interposer insulating layer disposed between the protective layer and the active surface, and the pad is electrically connected to the active surface via a plurality of microvias extending through the interposing insulating layer . An unequal columnar bump structure for eliminating coplanar difference of solder, comprising: a wafer having an active surface having a pad and a protective layer, the pad being exposed to one of the openings of the protective layer; a columnar bump is disposed on the solder pad and has a first soldering top surface; a second stud bump is disposed on the protective layer and has a second soldering top surface, wherein the second soldering surface The top surface is higher than the first solder top surface by the protective layer; a first solder is formed on the first solder top surface; and a second solder is formed on the second solder a top surface; wherein the second stud bump has a crack recessed inwardly from the second solder top surface to receive a portion of the second solder; wherein the second solder trace is not completely filled The crack is such that a gas trap having expansion/reduction variability is formed inside the second columnar bump.