TWI220075B - Floating gate memory cell and manufacturing method thereof - Google Patents

Abstract

A floating gate memory cell is disclosed, which comprises a substrate, the substrate has a drain and source isolated with a channel; a floating gate located above the channel and isolated with the first insulation layer; a control gate located on the floating gate and isolated with a second insulation layer. By choosing proper deposition condition, at least one part of the floating gate is made of the polysilicon material with micro-crystalline particles, the particle diameter size ranges between 50 to 500 Å.

Description

1220075 Case No. 92106847 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a floating gate memory cell (〇〇 & 1: 111 § ^ memory ceH) and a manufacturing method thereof, and In particular, the invention relates to a floating gate memory cell capable of reducing the erasure frequency of the electric aa body and its manufacturing method. [Prior technology] One type of integrated circuit memory (IC memory) that can store non-volatile information is called erasable programmable read-only memory (erasaMe programmable ROM 'EPROM). This type of memory allows The user can write the program or erase the program and then repeat the program. One type of eprom is called N-channel MOSFET (N-channel MOSFET), as shown in Figures 1 and 2. The floating gate transistor 10 has two gates 12 and 14 made of polycrystalline silicon (polysilicon). Generally, polycrystalline silicon is deposited at about 520 ~ 700 C at high temperature by low pressure chemical vapor deposition (LPCVD), and the silane (si 1 ane, SiH4) or disiloxane di si Lane (Si2H6) is pyrolyzed. If polycrystalline silicon is at low temperature, for example 520. 〇 Deposition, the polycrystalline silicon formed is amorphous. The amorphous polycrystalline silicon is subjected to a subsequent τ% temperature process, such as an annealing step up to 900-1000 ° C. crystallization. Gate 14 is a floating gate (f 1 〇atinggate), and gate 12 is a selection or control gate (sei ec t or control gate) ° In transistor 10, substrate 16 has a source (source ) 1 8 and a drain 20 ′ and the two are separated by a channel 22. As for floating

TW0709 (040414) CRF.ptc Page 5 1220075 Case No. 92106847 Revised 5th, Sun and Moon Description (2) A first insulation layer 2 4 is used between the gate 1 4 and the channel 2 2, also known as the gate The gate oxide layer (gate ο X ide) is used for isolation; the control gate electrode 12 and the floating gate electrode 14 are separated by a second insulating layer 26. FIG. 1 shows an electric crystal in a programming mode. The arrow in FIG. 1 represents that the channel hot electrons are injected into the floating gate 14 from the channel 22 near the electrode 20, pass through the first insulating layer 24, and finally sink into the floating gate 14. The existence of negative charge in the floating gate 14 will increase the threshold voltage when the transistor is read. Even after the power is turned off, the read transistor will still maintain the read state. It is generally estimated that this state of maintaining reads can be as long as 1,000 years. Figure 2 shows a transistor in erase mode. The arrow in Figure 2 indicates that the Fowler-Nordheim (FN) electron tunneling current passes through the first insulating layer 24 and returns to the source 18 (or along the channel 22). When the transistor 10 is read, a voltage is applied to the control gate 12 and its voltage value is between a high threshold voltage and a low threshold voltage. If the transistor is read, the stored signal is equal to the '' 0 '' transistor is not conducting. If the transistor is not read, the stored signal is equal to '' Γ ', and the transistor can be turned on freely. For a single floating gate transistor in integrated circuit memory, one of the most common types of failure is called errat i c erase. This kind of floating gate is unstable. When the erase operation is performed, the unstable and unexpected behavior will occur. For example, 'this kind of indefinite erasure will cause the over erase of the transistor, and the memory cell will be trapped in the state of' '1 " and cannot be read.

1220075 ____ Case No. 92106847 V. Description of the invention (3) Birthday month amendment

[Summary of the Invention] In view of this, the object of the present invention is to provide a floating gate electrode cell and a method for manufacturing the same, by reducing the particle size of the polycrystalline silicon that constitutes the floating gate, and reducing the occurrence of erratic element erasure. erase) frequency.

According to a first object of the present invention, a floating gate memory cell is provided, including: a substrate, and the substrate has a drain and a source and a channel. ) Isolated, a floating gate located above the channel and isolated with a first insulating layer; and a control gate (contr0l gate) located above the floating gate and isolated with a second insulating layer. The floating gate is at least partially made of a polycrystalline silicon material with a micro grain, and has a particle size range of about 50 to 500 A. In addition, the particle size range may be approximately 50 to 300 A, or 200 to 50 GA.

According to a second object of the present invention, a method for forming a polysilicon floating gate is proposed, which is formed by a deposition process when manufacturing a floating gate memory cell. First, select a reaction gas 'and optionally a second gas Z, and apply them during the deposition process. The reaction gas is mainly SiX, SiY or a mixture of the two in an appropriate ratio' and X, γ, Z At least one of them includes a gas (deuterium 'D); then, a reactive gas / second gas is used to form a polycrystalline silicon floating gate with a micro-grain structure. Among them, X includes at least one of h4, h2C12, HC13, D4, D2C12, and D3C1. Y includes at least one of 116, H4C12, h2ci4, D6, D4C12, and D2C14. z includes at least D2, h2, D3

TW0709 (04 0414) CRF. P t c Page 7 1220075 Case No. 92106847 Month Revision V. Description of the Invention (4) First, it is mainly used to reduce particle size. In addition, during the deposition process, a polycrystalline silicon floating gate having a microcrystalline structure can be deposited at a time. Alternatively, an amorphous stone (a m 〇 r p h 〇 s s i 1 i c ο η) can be deposited as the floating gate first, and then the amorphous silicon is processed to form a desired microcrystalline grain structure. According to a third object of the present invention, a method for forming a polycrystalline silicon floating gate by using a deposition process when manufacturing a floating gate memory cell is proposed. First, select a reactive gas, and optionally a second gas, and-apply during the deposition process to form a floating gate, the reactive gas is Si X, and the second gas is Y; let X include at least H4, H2C12, HC13, D4, D2C12, D3C1, Y includes at least one of D2, H2, D3 to implement this selection step; then, the reaction gas / second gas is used to form a microcrystalline structure Polycrystalline silicon floating gate. Among them, the forming step may further include: depositing amorphous silicon as a floating gate; and processing the amorphous silicon to form a desired micro-grain structure, the particle size range of which is about 200 ~ 50 Between 0A. According to a fourth object of the present invention, a method for forming a polycrystalline silicon floating gate by using a deposition process when manufacturing a floating gate memory cell is proposed. First, a reactive gas is selected, and a second gas is selectively used during the deposition process to form a floating gate. The reactive gas is S i2 X, and the second gas is Y. Let X include at least H6, H4C12. , H2C14, D6, D4C12, D2C14, Y includes at least one of D2, H2, D3 to implement this selection step; then, a reactive gas / second gas is used to form a polycrystalline silicon with a microcrystalline structure Floating gate. Among them, the formation steps may be more inclusive

TW0709 (04-0414) CRF.ptc Page 8 1220075 Case No. 92106847 Revised gate; and for amorphous silicon, the particle size range is approximately one manufacturing a floating gate, a polycrystalline silicon floating The square plate of the gate, the substrate has a drain and a source, is located above the channel and first above the floating gate, and the steps are as follows: First, a sink gas flow is selected, and a deposition is at least partially micro. The size of the grain structure is about 50 ~ 50 0A. Another structure is polysilicon floating gate. The difference in shape lies in about 50 ~ 3 00A or a mixture of Z in an appropriate ratio, and X, Υ, and Z have at least one, X includes at least Η4, H2C12, and Y includes at least Za, H4C12,. Z includes at least D2, H2, and D3. Its characteristics and advantages can be more clearly and easily matched with the attached drawings, and will be described in detail. V. Description of the invention (5) Including depositing an amorphous silicon as a floating treatment to form an office The required micro-grain structure is between 200 and 50 0A. According to a fifth object of the present invention, when a cell is recalled, a deposition process is used to form it. The floating gate memory cell includes: a base and a channel isolation; a floating gate and an insulation layer isolation; and a control gate and a second insulation layer isolation. This method includes a step-by-step environment, including selecting a reactive gas, pressure, and a deposition time; then, a polycrystalline silicon floating gate is formed with a particle size, and the particle size may also be formed as a whole formed by microcrystals. Due to the deposition environment. The reaction gas is mainly SiX, SiY, or optionally a second gas including H (deuterium, D). Among them HC13, D4, D2C12, D3C1. One of H2C14, D6, D4C12, and D2C14. ^ _--Ο In order to make the above-mentioned object of the present invention more understandable, a preferred embodiment is exemplified below and explained as follows.

IH1

TW0709 (040414) CRF.ptc Page 9 1220075-plug mile · ^ year month date _ V. Description of the invention (6) [Embodiment] The floating transistor will cause a transistor when it is erased indefinitely The situation of over-erasing has caused a memry 11 to be in a state of 1, 1, and cannot be renewed. The present invention is directed to this problem to further solve and improve. The invention uses a microcrystalline pole as a floating gate electrode, and the microcrystalline grains above the first insulating layer are made of polycrystalline silicon and are controlled within a certain particle size range. This design not only eliminates the inconsistent erasing of the transistor, but also allows it to have a consistent erasing speed. Fig. 3 is a partially enlarged schematic diagram of the transistor of Fig. 1. Polycrystalline silicon particles 28 having a relatively large particle size are arranged above the first insulating layer 24 to form a floating gate electrode 1 4. The polycrystalline silicon formed by the conventional deposition method has a particle size range of about 60 to 300 A. At the parent boundary of the first insulating layer 24 and the two polycrystalline silicon particles 28, a so-called oxide valley (30) is formed. FIG. 4 is a partial schematic diagram of a floating gate transistor manufactured according to a known embodiment of the present invention. Generally speaking, the transistor manufactured according to the present invention is mainly the same as the traditional floating gate transistor, but the floating gate 1 4 A of the present invention is composed of polycrystalline silicon particles with a smaller particle size 2 8 A Composed of, and has a car parent small oxidation 30A. The oxide valley is a high-density phosphorous oxide region. The floating gate electrode 14A is composed of a plurality of polycrystalline silicon micro-grains 28A, and its particle size range is about 50 ~ 500a, and preferably about 50 ~ 300A. Compared to Figure 3, smaller micro-grains 28A can result in smaller oxide valleys 30A. The small particle size 28A can reduce the possibility of indefinite erasing of the transistor and make the transistor have the same erasing speed. In addition, smaller oxide valleys can reduce the barrier layer height or reduce electricity

TW0709 (040414) CRF.ptc Page 10 1220075 ___J Tiger 92106847 Date: Rev. _ V. Description of the invention (7) Probability that the sub crystal is trapped at the polycrystalline silicon / silicon dioxide interface. The microcrystalline particles 2 8 A shown in FIG. 4 are not so regular in particle size, so the hot electron impingement can be used to help the transistor 10 to resist electron trapping. In the present invention, polycrystalline silicon is deposited by a low pressure chemical vapor deposition method (1 ow pressure chemi cal vapor depositon, LPCVD). One type of LPCVD is called a furnace process, and is performed at a temperature of 500 to 700 ° C and a pressure of 0.1 mtorr to 5 torr. Another type of LPCVD is called a single wafer process, which is performed at a temperature of 5800 ~ 800 ° C 'and a pressure of 100 ~ 500. Floating gates can be deposited according to the required polycrystalline stone particle structure. However, if the deposition is performed at a temperature lower than 580 ° C, the formed floating gate electrode may become amorphous and require reprocessing, such as tempering (annea 1 ing), to obtain the required polycrystalline silicon particles. Structure; in this case, the resulting particle size range is about 200 ~ 500A. The present invention is not limited to LPCVD, and other deposition methods, such as plasma enhanced chemical vapor deposition (PE 1 a sma enhance chemical vapor deposition, PECVD), can be used to obtain the required gate electrode particle structure. In the integrated circuit memory device, the steps of forming the floating gate electrode of the present invention are too similar to the conventional method. However, the technical feature of the present invention is that a reactive gas is introduced when the floating gate electrode 14 A of polycrystalline stone is formed, and a second gas can also be selectively introduced during the deposition period. The reaction gas is mainly Si X, Si Y, or the two are mixed in an appropriate ratio; the second gas is z. Among them, at least one of 'X'γ and Z contains deuterium (D). X at least package

TW0709 (04〇414) CRF.ptc 1220075 __Case No. 92106847_Year Month Day Amendment _ V. Description of the invention (8) Including: h4, H2C12, hci3, d4, d2ci2, d3ci One of them includes at least H6, H4C12, H2C14, D6, D4C12, D2C14. z includes at least one of D2'H2'D3. After selecting the reaction gas (/ second gas), compare the results of using SiH4, Sin / H, Sil / D2, SiD ^ H2, and SiD "D2. The test conditions are: 2 temperature 640 ~ 77 (TC, pressure 20 0 ~ 400 torr, SiH4 gas flow control range; 10 ~ 1000 seem 〇 Floating gate produced by using Si 1 *-(1) 丨 48 does not have the required polycrystalline stone particle structure, and (2) The floating gate 1 4 A cannot be countered by electronic lightning;… i + the floating gate lu produced by the punch has the required granular structure, and (2) the floating produced The gate 14A cannot resist the situation of electronic card trapping ... The polysilicon required by the electric scale has a floating electron generated by the use of S i Η * / D2 — (1). The particles, structure 'And (2) the floating gate 14A generated can resist the situation of electronic card trapping. Use the floating gate 14 particle structure generated by sa / i at once, and (2) the floating generated by: The shape of Xijing Silicon's anti-electron entrapment. The open electrode 14A can be damaged by the impact of hot electrons.

Use of SiD4 / D2-(1) microparticles, structures' and (2) floating anti-electric + stagnation. The floating gate 14A has the required polycrystalline silicon. The idler 1 4 A can be paired by thermal electron shock. In the above case, the best results are obtained with H 2 gas flow based on the experimental results with S i. The effect on polycrystalline silicon particles is:

1220075 The case said on the date of 92106847 Amended 5. Description of the invention (9)

The larger the incoming H2 gas flow, the smaller the particle size. For example, under the test conditions of a temperature of 72 ° C and a pressure of 250t0rr ', the deposition is performed in a single wafer reaction chamber (singie-wafer POLYgen chamber) with Si H4 / H2 for 24 seconds, and the deposition is floated. The gate thickness is 1 0 0 0A. When the SiH4 / H2 gas flow ratio is 100/0 seem, the particle size of the polycrystalline silicon particles ranges from about 600 to 800 lids. When the ratio of Si 1 / Η 比 gas flow rate is 100/1 00 s c cm, the particle diameter range of the polycrystalline fine particles is about 200 ~ 40 0A. When the Si H4 / H2 gas flow ratio is 100/2000 seem, the particle size range of the polycrystalline silicon particles is about 50-200a. Another example of the test conditions is: at a temperature of 64 (TC, pressure 275t〇rr, in a single circle reaction to Si I /% for 3 8 seconds, and the thickness of the deposited floating gate It is 100 A. It is then subjected to a rapid thermal process (1 ^?) For 30 seconds at a temperature of 95 ° C and nitrogen. When 8 丨 114 / {12 gas flow ratio is 2000 / 〇3 (: 0: 111 ', the particle size range of polycrystalline silicon particles is about 800 ～ 〜οοοΑ. When 8 丨} 14/112 gas flow ratio is 2 0 0/1 0 0 0 sccm, the diameter 2 of polycrystalline silicon particles is formed. The range is reduced to about 40 0 to 600 A. When the SiH4 / H2 gas flow ratio is 200/200 00 sccm, the particle size range of the polycrystalline silicon particles is further reduced to about 200 to 300 A.

In addition, it is worth noting that the memory erasing method as described above is not limited to the source erasing method erase shown in the example), this process can also be applied to the channel erasing method (channei Eras e) Polysilicon floating gate for memory erasing method. It is combined with the above. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention to anyone skilled in the art. Without departing from this

1220075 Case No. 92106847 JF: _Ά Amendment V. Description of the invention (10) Within the spirit and scope of the invention, various modifications and retouching can be made, so the scope of protection of the present invention shall be defined as the scope of the attached patent quasi. TW0709 (040414) CRF.ptc Page 14 1220075 _Case No. 92106847_ Year Month Revised _ Simple Description [Schematic Description] Figure 1 shows a transistor in programming mode; Section 2 The figure shows a transistor in the erasing state (erasem ode); FIG. 3 is a partially enlarged schematic diagram of the transistor of FIG. 1; and FIG. 4 is a diagram of a transistor manufactured according to a preferred embodiment of the present invention Partial schematic of floating gate transistor. Explanation of reference numerals 10: transistor 12: control gate 14, 14A · floating gate 16: substrate 18: source 2 0: drain 22: channel 24: first insulating layer 2 6: second insulating layer 2 8: Polycrystalline silicon particles 2 8 APolycrystalline microcrystals 3 0, 3 0 A: Oxidized valley

TW0709 (040414) CRF.ptc Page 15

Claims (1)

1220075-Installation date: 92106847 June 6th, patent application scope 1 · A floating gate memory cell (f 1 oat ing gate memory cell) includes a substrate, the substrate has a drain and a source (source) and isolated by a channel (channei); a floating gate located above the channel and isolated by a first insulating layer; and a control gate (con trol gate) 'located above the floating gate and The improvement of the memory cell by a second insulating layer is that the floating gate above the first insulating layer is at least partly a microcrystalline polycrystalline silicon material and has a particle size range of about 50. 501, the floating gate memory cell as described in item 1 of the scope of patent application, wherein "the entire gate is made of a microcrystalline polycrystalline silicon material, and the particle size range Between 50 ~ 500A. 3. As described in the floating interrogation memory cell described in the first item of the scope of patent application, the particle size range is about 500 ~ 300A. Its 4 / such as In the floating idler memory cell described in item i of the patent application, The size range is between 2000 ~ 500A. 5 · As mentioned in the first patent application scope, the microcrystalline polycrystalline silicon material is _ A gate silicon cell Material: The material is undoped and undoped. 6. In the floating as described in item 1 of the patent application scope, the microcrystalline polycrystalline silicon material is placed in the gate electrode. 丨 Cell-in-situ doped- proces s Η Η polycrystalline silicon yiocess doped materi, which is an impurity introduced into the country, as described in item 1 of the scope of the patent application ~ the gate memory cell, which TW0709 (040414) CRF.ptc Page 16 1220075 Case No. 92106847_Amended on June 6, 2006. In the scope of the patent application, the 'polycrystalline broken material of this microcrystal is an undeployed polycrystalline TW0709 with ion implantation ( 040414) CRF.ptc Page 17 1220075 _ Case No. 92106847_ Ambiguity Day Amendment _ 6. Application for Patent Scope Undoed process with implant 〇8 · — A polysilicon floating gate forming polysilicon floating gate ) Method, including the following steps: selecting a reactive gas, and optionally selecting a second gas Z, and applying it to a deposition process, the reactive gas is mainly s, χ, S i Υ, or both Mix in an appropriate ratio, and at least one of χ, γ, and ζ includes a deuterium (Duterium); and use the reaction gas / the second gas to form a polycrystalline broken floating gate with a microcrystalline structure. 9. The method for forming a polycrystalline silicon floating gate as described in item 8 of the scope of the patent application, wherein the step of selecting a gas χ includes at least HC13, D4, D2C12, D3C1-. 22 10. Pole method H2C14, d6 11. Pole method one of the polycrystalline silicon floating gates includes h6, h4ci2 polycrystalline silicon floating gates including d2, h2, d3 as described in item 8 In the step of selecting gas in Γ1, 'Y to' D4C12, D2Cl4 Among them, such as the patent application JU g one. , Of which C. In the step of the pill, 2 to 1 2. Method, in which the polysilicon floating gate gas described in item 2 and item 8 is SiD4 / D2. -In the step, the reaction rolling body / the second 13. The method for forming a polycrystalline stone floating gate as described in item 8 of Shen Ziqing's patent m π 沾 古 土 甘 士 ⑦, wherein Weng Bei is selected In the step of 1 rAJ prosthesis' the reaction gas / the second TW0709 (040414) CRF.ptc Page 18 1220075 Saiwei 92106847 Birth month Correction — ««-VI. Patent application " " The gas is Si2D6 / D2. 14. The method for forming a polycrystalline silicon floating gate as described in item 8 of the scope of the patent application, wherein in the step of selecting a gas, the reaction gas / the second gas is at least SiD4 / D2, SiD4 / H2, SiH4 / P2, among which one. 15. The method for forming a polycrystalline silicon floating gate as described in item 8 of the scope of the patent application, wherein in the step of selecting a gas, the reaction gas / the second gas is at least SiA / D2, Si2D6 / H2: Si2H6 / D2, among which one. 16. Forming a polycrystalline silicon floating gate as described in item 8 of the scope of patent application, wherein the forming step includes: depositing an amorphous silicon (amorph〇us si 丨 icon) as the floating gate ; And processing the amorphous rock to form a desired microcrystalline structure. 17. The method for forming a polycrystalline silicon floating gate as described in item 16 of the scope of the patent application, wherein after performing the processing step, the microcrystalline polycrystalline silicon floating gate has a particle size range It is between 2000 and 500A. 18. The method for forming a polycrystalline silicon floating gate as described in item 16 of the scope of patent application, wherein the processing step is to heat the amorphous silicon floating gate to a temperature exceeding about 60 ° C. Xin 19. The method for forming a polycrystalline silicon floating gate as described in item 8 of the scope of the patent application, wherein a polycrystalline silicon particle structure is also formed at the same time when the polycrystalline silicon material is deposited. 2 0. Forming a polycrystalline silicon floating gate as described in item 8 of the scope of patent application TW0709 (040414) CRF.ptc Page 19 1220075 Case No. 92106847_ Amendment VI. Method for claiming patent scope, where the gas selection step and formation step are in a low pressure chemistry ΪΗΪ TW0709 (040414) CRF.ptc Chapter 20 pages of 1220075 _ case number 92106847_ year ^ a ^ g_ amendment _ 6, the scope of patent application for low pressure chemical vapor deposition (LPCVD) process. 21. The method for forming a polycrystalline silicon floating gate as described in item 20 of the scope of patent application, wherein the low-pressure chemical vapor deposition process can be performed in a furnace control process or a single wafer process. 2 2. The method for forming a polycrystalline silicon floating gate as described in item 8 of the scope of the patent application, wherein the operating pressure of the low-pressure chemical vapor deposition process applied to a furnace process is about 0. · 1 milliTorr ~ 5 Torr, operating temperature is about 500 ~ 700 ° C. 2 3. The method for forming a polycrystalline silicon floating gate as described in item 8 of the scope of the patent application, wherein the operating pressure of the low pressure chemical vapor deposition process applied to a single wafer process is about It is 10 Torr ~ 500 Torr, and the operating temperature is about 580 ~ 800 ° C. 24. The method of forming a polycrystalline silicon floating gate as described in item 8 of the scope of the patent application, wherein the polycrystalline polycrystalline silicon floating gate after the forming step has a particle size range of about Between 50 and 500A. 25. The method for forming a polycrystalline silicon floating gate as described in item 8 of the scope of the patent application, wherein the microcrystalline polycrystalline silicon floating gate after the forming step has a particle size range of about 50 to 30 〇A. 26 · A method for forming a polycrystalline silicon floating gate (p〇1ysi 丨 ic〇n floating ga te), including the following steps: TW0709 (040414) CRF.ptc Page 21 1220075 __ Case No. 92106847_ Month J --- 6. Application for patent scope. Tt 〆 * 第 — " Gas selective reaction gas, and optionally (ly) Select two bodies and apply them during a deposition process to form the floating gate. The anti-center gas is SiX, and the second gas is γ; X now includes at least Zr, H2C12, HC13, D4, D2C12, D3C1 First, Y includes at least one of D2, h2, and D3 to implement the selection step and use the reaction gas / the second gas to form a polycrystalline silicon floating gate with a micro-grain structure. 27. The method for forming a polycrystalline silicon floating gate as described in item 26 of the scope of application for a patent, wherein the forming step includes: ... / youji amorphous stone eve (am〇rph〇us si 1 i con) to As a "floating interrogator; and processing the amorphous rock to form a desired micro-aa particle structure. 0 2 8 · forming a polycrystalline rock float as described in item 27 of the scope of patent application The method of the polar electrode, wherein, after the processing step, the microcrystalline polycrystalline stone floating gate has a particle size range of about 2000˜500 A. 2 9. The method for forming a polysilicon floating gate as described in item 26 of the scope of the patent application, wherein the microcrystalline polycrystalline polysilicon floating gate after the forming step has a The particle size range is about 50 ~ 300A. 30. The method for forming a polycrystalline stone floating gate as described in item 26 of the scope of the application for patent, wherein χ and γ are, and one of them includes a rat (deuterium) 1220075 _Case No. 92106847_Amended in January / August 6, Application scope 31.-A method for forming a polycrystalline stone floating gate (ρ 〇1 ysi 1 ic η floating gate), including the following steps ·· A reactive gas, and optionally a second gas, which is applied during a deposition process to form the floating gate, the reactive gas is Si2X, and the second gas is Y; let X include at least One of H6, H4C12, H2C14, D6, D4C12, D2C14, and Y includes at least one of D2, H2, and D3 to implement the selection step; and using the reaction gas / the second gas to form a micro-grain Structure of polycrystalline stone floating gate. 3 2. The method for forming a polycrystalline silicon floating gate as described in item 31 of the scope of the patent application, wherein the forming step includes: depositing an amorphous crystalline stone (am or phous si 1 i con) as the floating A gate; and processing the amorphous silicon to form a desired micrograin structure. 33. The method for forming a polycrystalline silicon floating gate as described in item 32 of the scope of the patent application, wherein the microcrystalline polycrystalline silicon floating gate after the processing step has a particle size range of about 200 to 50 Between 0A. 34. The method for forming a polycrystalline silicon floating gate as described in item 31 of the scope of the patent application, wherein the microcrystalline polycrystalline silicon floating gate after the forming step has a particle size range of about 50 Between ~ 3 0 0 A. TW0709 (040414) CRF.ptc Page 23 1220075 SS—92106847 VI. Application scope 3 5. The method for forming a polycrystalline silicon floating gate as described in item 31 of the scope of patent application 'wherein' is at least one of X and γ Contains atmosphere view, D) ° 36 · A method for forming a polysilicon floating gate, which is used to manufacture a floating gate memory cell, wherein the floating gate memory cell includes a A substrate, which has a drain and a source and is isolated by a channel; a floating gate located above the channel and isolated by a first insulating layer; and a control gate A control gate is located above the floating gate and is isolated by a second insulating layer. The method includes the following steps: selecting a deposition environment, including: selecting a reactive gas; selecting a reactive gas flow rate; selecting a deposition pressure ; And selecting a deposition time; forming a polycrystalline silicon floating interrogator with a microcrystalline structure; and forming the floating gate, which is at least partly a microcrystalline structure, above the first insulating layer, and having one Park size range between about 5 0 〇A 0~5. 37. The method for forming a polycrystalline stone floating gate as described in item 36 of the scope of application for a patent, wherein the size range of the particle size range is between about 50 and 300A. 38. The method for forming a polycrystalline stone floating gate as described in item 36 of the scope of patent application, wherein the step of selecting the reactive gas includes: TW0709 (040414) CRF.ptc Page 24 1220075 _Case No. 92106847_Year Month_Charm_ VI. The scope of patent application selects a reactive gas, and optionally a second gas Z, and applies During the deposition process, the reaction gas is mainly SiX, Si Y, or the two are mixed in an appropriate ratio, and at least one of X, Y, and Z includes a gas (deuterium, D). 〇3. The method for forming a polysilicon floating gate according to the item, wherein X includes at least one of H4, H2C 12, HC 13, D4, D2C 12, and D3 C1. 40. The method for forming a polycrystalline silicon floating gate as described in item 38 of the scope of the patent application, wherein in the step of selecting a gas, Y includes at least one of H6, H4C 12, H2C14, D6, D4C12, and D2C14. 41. The method for forming a polycrystalline silicon floating gate as described in item 41 of the scope of patent application, wherein in the step of selecting a gas, Z includes at least one of D2, H2, and D3. TW0709 (040414) CRF.ptc Page 25