TWI245375B - Nonvolatile flash memory of hafnium silicate nanocrystal - Google Patents
Nonvolatile flash memory of hafnium silicate nanocrystal Download PDFInfo
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1245375 九、發明說明: 【發明所屬之技術領域】 本發明係提供一利用矽酸铪奈米微粒備製之非揮發 性快閃記憶體,特別是本發明係利用快速升溫退火製程 ^ Rapidly Temperature Annea丨丨ng ’ RTA)成長一具有奈 米晶體(nanocrystal)之矽酸铪(Hfs丨.a)薄膜層,^ 應用於快閃記憶體(Flash memory )、非揮發性記憶體 (nonvo丨atMememory)等相關記憶體及半導體產業;。 【先前技術】 隨著高科技時代的來臨,以矽(s丨丨丨·c〇n)為主的半 導體材料及技術便影響著大眾生活。而隨著半導體產業 的發展,各類電子產品料、、記憶體,,的材料與技術也 越重視’尤須具有輕、冑、短、小’及可攜帶(如:手 機、智慧型手機(smartph〇ne)、隨身碟、pDA……等等) 等特性。記憶體(memory)依所存入的資料是否會受、、供 電(P〇wer)〃的影響,可分為、、揮發性(v〇|at^)〃及 、、非揮發性(Non-volati丨e),,等兩大類。而非揮發性記憶 體(.Non-volatue memory)最早的產品是唯讀式記憶體 (ROM,Read-Only-Memory )’雖價格便宜又高密度 (high density)’但是因為非揮發性記憶體會因不同^ 戶而而用不同的光罩(mask ),因此無法標準化、大量生 產,且其成本與功能不夠強大。為解決上述之問題,隨 1245375 後出現一種稱為可程式化ROM (又稱PR〇m),可不隨 特另丨各戶而須用特定的光罩,亦即可在生產完記憶體晶 片後再將所需要的資料寫入,因此有可以快速生產的優 勢。但是由於可程式化ROM雖可依照客戶需求來程式化 5己憶體,但其程式化方式不甚方便,因此為因應需要又 再度改進成另一種可在生產完晶片後再用加電壓的方式 編程(program)的電子可程式化R〇M (e|ectr丨·ca丨丨y1245375 IX. Description of the invention: [Technical field to which the invention belongs] The present invention provides a non-volatile flash memory prepared by using nanometer silicate particles, especially the present invention uses a rapid temperature annealing process ^ Rapidly Temperature Annea丨 丨 ng 'RTA) Grow a HfS..a thin film layer with nanocrystals, ^ applied to Flash memory, nonvo 丨 atMememory And other related memory and semiconductor industries ;. [Previous Technology] With the advent of the high-tech era, semiconductor materials and technologies based on silicon (s 丨 丨 丨 · con) have influenced the lives of the general public. With the development of the semiconductor industry, more and more emphasis is placed on the materials and technologies of various electronic products, memory, and materials, which must be lightweight, compact, short, small, and portable (such as mobile phones, smart phones ( smartph〇ne), pen drive, pDA ... etc.). Memory (memory) can be divided into,, volatile (v〇 | at ^), and, non-volatile (Non- volati 丨 e), and so on. Non-volatile memory (.Non-volatue memory) is the earliest product is read-only memory (ROM, Read-Only-Memory) 'Although cheap and high density (high density)' Different masks are used for different users, so it cannot be standardized and mass-produced, and its cost and function are not powerful enough. In order to solve the above problems, a programmable ROM (also known as PRm) appeared after 1245375. It is not necessary to use a special photomask for each household. It can also be used after the production of memory chips. The required information is written in, so there is an advantage of rapid production. However, although the programmable ROM can be programmed according to the customer's needs, the programming method is not very convenient. Therefore, it can be improved to another method that can be applied after the wafer is produced. Programmable electronically programmable ROM (e | ectr 丨 · ca 丨 丨 y
Programmable R〇M),又稱為EPROM (如第丄8 A〜Programmable R〇M), also known as EPROM (such as 丄 8 A ~
18B圖所示),但是因為EPR〇M在抹除(erase)資 料時需用紫外光(UV,ht),故在包裝上需較貴的材料 3 土為解決上述之問題,覆又提出另一種不用紫外光而 疋罪加電壓予以編程或抹除之電子可抹除可程式化r〇M ( Electrically Erasable Programmable Read-Only-Memory,EEPR〇M )(如第 1 9 a 圖所示), 係在閘極(gate)加電壓將電子(e|ectr〇n)或電洞(h〇|e) 移出净閘(floating gate),如:在198〇年英特爾(丨nte丨) 提出的洋閉穿透氧化層(FLOTOX,floating-gate tun^lWde)記憶體,其係、將#近汲極端上方的氧化層 做得很薄由於6亥元件的程式編輯(programming )不是 罪熱電子(hot electron )式,而是靠電子穿透(e|ectr〇n tunneling )式的方法,利用加高壓使跨在薄氧化層的電 場很高,因而發生富勒-諾得漢穿透(F〇w|e「_N〇rdheim tunneNng,FNtUnneling),使電子可以進入浮閘,將汲 1245375 心⑴跟源極(source)接地,使間 =:黏而要清除時則相反,將閉極 極端電壓加+2〇V (如第1 9B圖所示)。 由於上述方法需要製作很薄的穿透氧化 〇她)’且品質(q_ty)要好,使其製程困難;且其 :斤制的工作電壓太高了 (+2〇v)’而其佈 Γ/Λ’儲存每個u(bit)均需要㈣單元㈤|) 1 2 0圖所不)’且操作的速度較慢(使用Μ 麵ehng)。因此’隨後又提出另—強調速度且 較小的快閃記憶體,同時縮小面積,即 =:〇「)僅需一個單元(1轉 而二程式編輯時是利用熱電子,不過該熱電子之 ,靠㈣極端產生的’但在清除時則是用fn t咖^ “進行的’係在閘極端上加電壓將電子從浮閘移 =❹低電壓(丨。”。丨_),即在進行程式編輯時在 沒極知只加到+5V,因此,稱為快閃(Flash),其 f夬且在進行清除時是採用一次一個區段($⑽、 ::广Ck)的型式;但是由於仍需要製作很心 透虱化層,故製程困難。 在上述浮閘結構的記憶體提出之時,亦同時提出一 示),又稱為金屬一氮化物一氧化物一半導瓶^ I Nitride-Oxide Semiconductor,MNOS),係在矽 以矽虱化合物為結構的非揮發記憶體(如 二、一 "·· . 一 V d 圖所 (Meta a曰 1245375 (sihcon wafer)上先長一層很薄的氧化層,再成長一層 品質很好的氣化層(nitride),再加上一金屬層(_3|); 但由於上述方法仍需要一層很薄的氧化層(約幾十埃 和品質很好的氮化層,使其製程技術困難而未被採用, 且該MNOS具有一個從上方往閘電極(gatee|ectr〇de) 方向的漏電,使記憶體單元的保存時間(retent丨〇nt丨me) 降低,因此,另再提出一石夕氧化氮氧化石夕(s丨·丨丨·ε〇η 〇力扣 Nitride Oxide Silicon,S0N〇S)結構之快閃記憶體(如 第2 3圖所示),係比上述之_os多了一層阻擔氧化層 (blocking oxide),再利用 FN tunne丨ing 電流(如第 2Figure 18B), but because EPROM needs to use ultraviolet light (UV, ht) when erasing (erase) data, more expensive materials are needed on the package. 3 In order to solve the above problems, I have proposed another An electronically erasable Programmable Read-Only-Memory (EEPROM) that can be programmed or erased without applying UV light and applying a voltage (see Figure 19a). The voltage is applied to the gate to remove the electron (e | ectr〇n) or hole (h〇 | e) from the floating gate. For example, in 1980, Intel (丨 nte 丨) proposed the A closed-through oxide layer (FLOTOX, floating-gate tun ^ lWde) memory, which is made of a thin oxide layer above the #next terminal, because the programming of the 6H device is not a hot electron. electron) type, but relying on the method of electron tunneling (e | ectrón tunneling), using an applied high voltage to make the electric field across the thin oxide layer high, so Fuller-Nordhan penetration (F0w e "_N〇rdheim tunneNng, FNtUnneling), so that electrons can enter the floating gate, which will draw 1245375 heart beat and source (s ource) Ground, make the interval =: sticky, but the opposite is to be removed, add + 20V to the extreme voltage of the closed electrode (as shown in Figure 19B). Because the above method needs to make a very thin penetrating oxide) 'And the quality (q_ty) is better, which makes the process difficult; and: the working voltage of the kilogram is too high (+ 2〇v)', and its layout Γ / Λ 'requires each unit of u to store 储存|) 1 2 0 (not shown in the figure) 'and the operation speed is slower (using the M-plane ehng). Therefore,' Another-emphasis on speed and smaller flash memory, while reducing the area at the same time, == 〇 「 ) Only one unit is needed (1 to 2 programs are edited using hot electrons, but the hot electrons are generated by the extremes, but when cleared, they are performed by fn tca ^ "on the gates". Applying voltage to move electrons from the floating gate = ❹ low voltage (丨. ". 丨 _), that is, only + 5V is added when the program is edited. Therefore, it is called flash, and its f 夬And in the removal, one segment at a time ($ ⑽, :: 广 Ck) is used; however, because it is still necessary to make a very transparent layer, the process is difficult. When the memory of the above floating gate structure is proposed, it is also shown at the same time), also known as metal-nitride-oxide half-conductor bottle ^ I Nitride-Oxide Semiconductor (MNOS), which is based on silicon with silicon lice compounds as the structure Non-volatile memory (such as two, one " .... A V d map (Meta a 1245375 (sihcon wafer) first grows a thin oxide layer, and then grows a good quality gasification layer ( nitride), plus a metal layer (_3 |); but because the above method still requires a very thin oxide layer (about tens of angstroms and a good quality nitride layer, making its process technology difficult and not used, And the MNOS has a leakage current from the top to the gate electrode (gatee | ectrode) direction, which reduces the retention time (retent 丨 〇nt 丨 me) of the memory cell. Therefore, another stone oxide nitrogen oxide oxide (S 丨 · 丨 丨 · ε〇η 〇 force buckle Nitride Oxide Silicon (S0NOS)) structure flash memory (as shown in Figure 23), there is an additional layer of oxide layer than the _os (blocking oxide), and then use the FN tunne 丨 ing current (such as the second
4 A圖所示),將電荷(charge)儲存於氮化矽(3丨3心, Nitride)層之能階中,當電荷(電子或電洞)經由薄穿 透氧化層被入射或跳出至該氮化矽層之能階中,其臨界 電壓(threshold voltage )便會因入射電荷的種類、數量、 及分布不同而改變,進而被區分為高電位(寫入,Pr〇gram State)及低電位(清除,Erase state)(如第2 4 B 圖所示)。上述之氮化矽層之能階由於是屬於分離式陷阱 (discrete trap),因此儲存的電荷間不會互相作用,而 该牙透氧化層的局部缺陷也不會造成全部電荷的流失, 且儲存在該氮化矽層之能階中的電荷也不會隨外在電源 的消失而流失,故稱為非揮發性記憶體。但由於其仍需 要一薄穿透氧化層,故製程不易。 1245375 【發明内容】 =,本發明之主要目的係在於提供一製程簡單、 Z速寫人或清除之利用㈣給奈米微粒備製 發 性快閃記憶體。 平& 為達上述之目的,本發明係提供—利用㈣給 備製之非揮發性快閃記憶體,其係在充滿氬氣(叫加, A「)及氧氣(0xygen ’ 〇2)之環境下,將給(細_, 听)及♦ (sme〇n,Sj)之兩㈣材以共焦錢渡法 (c〇-S_e_)錢上-厚度為3G埃之㈣給薄膜層, 再放置於高真空(highVacuum) τ通人氧氣,經過_ C 60秒之快速升溫退火製程,使該矽酸铪薄膜層產生高 密度及微粒小之奈米晶體,且該矽酸铪薄膜層可利用該 奈米晶體來補抓(trap)電荷,使其製造一具儲存方式為 區域性(localized )之特點的記憶體,且其一個單元(ce丨丨) 可儲存2個位元(2 bit/ce丨丨),而可用於[EPROM、快閃 記憶體、SONOS記憶體等相關記憶體及半導體產業中。 【實施方式】 本發明係提供一利用矽酸姶奈米微粒備製之非揮發 性快閃記憶體,係在充滿氬氣及氧氣之環境下,將銓及 矽兩種靶材以共焦濺鍍法鍍上一厚度為3 〇埃之矽酸铪薄 膜層,再放置於高真空下通入氧氣,經過9〇〇°C 60秒之 快速升溫退火製程,使該矽酸铪薄膜層產生奈米晶體, 該奈米晶體之密度範圍為〇·9〜1·9 X 1〇12 cm-2,其微粒 1245375 大小為小於10奈米(_),且該石夕酸給薄膜層可利用-顆顆的奈米晶體來補抓電荷,使儲存方式很區域性,可 利用上述之特點來製造記憶體,使其一個單元可儲存2個 位兀(2 bit/cell),且其製程簡單,可用於巧叩⑽、 快閃記憶體、S〇NOS記憶體等相關記憶體及半導體產業· 〇 為進-步說明本發明,本發明係進—步以數個較佳 實施例說明如後: [實施例1]利用矽酸铪奈米微粒備製之非揮發性快閃記 憶體 叫芩閱『第1〜2 B圖』所示,係本發明之利用矽、 酸铪奈米微粒備製之非揮發性快閃記憶體之製造流程示 意圖、本發明之矽酸铪薄膜層之剖面示意圖、本發明之 矽s欠铪4膜層之平面示意圖。如圖所示:係將一為p型矽籲 晶圓(p-type silicon wafer)之基板1置於真空環境(2 x1(T6torr)中,並通氬氣及氧氣(流量為24 seem / 8 seem )’利用給及石夕兩種乾材以共焦藏渡法鑛上一厚度為3q 埃之石夕酸給薄膜層3,再置於高真空下通入氧氣,經過 900 C 60秒之快速升溫退火製程,使該矽酸铪薄膜層3 產生奈米晶體’隶後再利用熱蒸鑛法(Thermal coater )於該矽酸铪薄膜層3上鍍上一控制閘極層5,該控制 1245375 間極層5之材料可為銘(a I u m i n u m,a丨),可作為問電 極(gateelectrode)。上述之矽酸給薄膜層3係利用穿 透式電子顯微鏡(Transition Electron Microscopy,ΤΕΜ )了觀察έ亥奈米晶體的形成,且該奈米晶體之密度範圍 為〇.9〜1·9 X 1〇12 cm·2 ’其微粒大小為小於1〇奈米。 請參閱『第3A〜5圖及表i』所示,係本發明之 矽醆铪薄膜層圖之不同晶態、χ射線光電子能譜儀結果、 電丨生里測及能量擴散結果示意圖。如圖所示:本發明之 矽酸铪薄膜層係經由900。〇之快速升溫退火製程改變該 石夕酸給_層之元素成分比例及結構,該結構由非晶態 (am〇rph〇us)變成多晶態(P〇lycrysta丨Hne),且量測 該石夕酸給薄膜層之電荷·電壓(Charge_v。丨响,c v) 電性,係加入3伏特(V0|tage’ v)到_3伏特之電壓,如 第5圖所示,係可看出在c-v開了 1V左右的記憶視窗( emory wmdc)w) ’亦即代表該石夕酸給薄膜層之奈米晶 、有補抓電荷的能力,係可應用在記憶體上。 [實施例2] S〇N〇s之利用魏給奈米微粒備製 性快閃記憶體 υ ”固』所不,係本發明之利 ^給奈米微粒備Μ之非揮發性快閃記憶體之s〇n〇As shown in Figure 4A), the charge is stored in the energy level of the silicon nitride (3 丨 3 core, Nitride) layer. When the charge (electron or hole) is incident or jumped out through the thin penetrating oxide layer, In the energy level of the silicon nitride layer, its threshold voltage will change due to the type, quantity, and distribution of incident charges, and then it can be divided into high potential (Prgram State) and low. Potential (clear, Erase state) (as shown in Figure 2 4 B). Since the energy level of the silicon nitride layer is a discrete trap, the stored charges will not interact with each other, and the local defects of the dental oxide layer will not cause the loss of all charges, and the stored The charge in the energy level of the silicon nitride layer will not be lost with the disappearance of the external power source, so it is called non-volatile memory. But because it still needs a thin penetrating oxide layer, the process is not easy. 1245375 [Summary of the invention] =, The main purpose of the present invention is to provide a nanometer particle to prepare a hair-saving flash memory by using a simple process, Z sketching or erasing. Ping & In order to achieve the above-mentioned object, the present invention provides a non-volatile flash memory prepared by using tritium, which is filled with argon (called Canada, A ") and oxygen (0xygen '〇2) Under the environment, the two layers of (fine, listening) and ♦ (sme〇n, Sj) will be confocal Qiandu method (c0-S_e_) money-the thickness of 3G Angstroms to the film layer, and then Placed in a high vacuum (highVacuum) τ through human oxygen, _ C 60 seconds of rapid heating annealing process, so that the samarium silicate film layer to produce high density and small particles of nanocrystalline, and the samarium silicate film layer can be used The nano crystal traps charges, making it a memory with localized storage mode, and one unit (ce 丨 丨) can store 2 bits (2 bit / ce 丨 丨), and can be used in [EPROM, flash memory, SONOS memory and other related memory and semiconductor industry. [Embodiment] The present invention provides a non-volatile prepared by using nanometer silicate nanoparticles Flash memory is used to confocal thoron and silicon targets in an environment full of argon and oxygen. A 30 angstrom erbium silicate thin film layer is plated by plating, and then placed under high vacuum to pass in oxygen. After a rapid temperature annealing process at 900 ° C for 60 seconds, the erbium silicate thin film layer is generated. Rice crystal, the density range of this nano crystal is 0.9 ~ 1.9 × 1012 cm-2, the size of its particles 1245375 is less than 10 nanometers (_), and the oxalic acid can be used for the film layer- Nanometer crystals make up for the charge, making the storage method very regional. The above characteristics can be used to make memory, so that a unit can store 2 bits / cell, and its process is simple. Can be used for related memory such as Qiaoshuang, flash memory, SONOS memory, and semiconductor industry. 〇 is a step-by-step description of the present invention, and the invention is a step-by-step description of several preferred embodiments as follows: [Example 1] The non-volatile flash memory prepared by using nano-silicate silicate particles is called "see Figure 1 ~ 2 B", which is prepared by using silicon and nano-silicate particles of the present invention. Schematic diagram of the manufacturing process of non-volatile flash memory, cross-sectional diagram of the rhenium silicate film layer of the present invention, The schematic diagram of the silicon s under 4 film layer of the present invention. As shown in the figure: a substrate 1 of a p-type silicon wafer is placed in a vacuum environment (2 x 1 (T6torr)) , And pass argon and oxygen (flow rate 24 seem / 8 seem) 'using two dry materials to Shixi to coniferous Tibetan Mine method to deposit a layer of 3q angstromian acid to the film layer 3, and then set Oxygen was introduced under high vacuum, and after a rapid heating and annealing process at 900 C for 60 seconds, the nanocrystalline silicon silicate film layer 3 was formed into nanocrystalline crystals, and then the thermal coating method was used on the rhenium silicate film. A control gate layer 5 is plated on the layer 3, and the material of the control 1245375 interlayer 5 can be a uminum (a), which can be used as a gate electrode. The above-mentioned silicic acid-imparting thin film layer 3 was observed with a transmission electron microscope (Transition Electron Microscopy, TEM) to observe the formation of crystalline nano crystals, and the density of the nano crystals ranged from 0.9 to 1.9 X 1 〇12 cm · 2 'has a particle size of less than 10 nm. Please refer to "Figures 3A to 5 and Table i", which are schematic diagrams of different crystal states, X-ray photoelectron spectroscopy results, electrophysical measurements, and energy diffusion results of the silicon rhenium film layers of the present invention. As shown in the figure: the samarium silicate film layer of the present invention passes through 900. The rapid heating annealing process of 〇 changes the proportion and structure of the elemental composition of the oxalic acid to the layer, the structure changes from amorphous (am〇rph〇us) to polycrystalline (P〇lycrysta 丨 Hne), and measures the The charge and voltage (Charge_v. Ring, cv) of the shixi acid to the thin film layer is a voltage of 3 volts (V0 | tage 'v) to _3 volts, as shown in Figure 5, which can be seen In cv, a memory window (emory wmdc) w) of about 1V is opened, which means that the shixi acid has nano-crystals for the thin film layer and has the ability to capture electric charges, which can be applied to the memory. [Example 2] The use of S0N0s to prepare nano-micro particles for flash memory υ "solid" is the advantage of the present invention ^ non-volatile flash memory for nano particles体 之 〇〇〇〇
圖。如圖所示··係、利用垂直爐管將-穿透!U 1245375 層2成長於一為p型石夕(p_typesi|ic〇n)之基板工的一端 面中央上’該穿透氧化層2之厚度為2〇埃,可為高介電 常數㈣化學氣相沉積氧化層,且該基板之兩側可形成 η源極或11汲極,再將兩種不同之乾材以物理化學 合成法〔如:原子層化學氣相沉積(at〇mjc |aye「chem丨ca| - vapor deposition,ALCVD)、高密度電聚化學氣相沈 積(High-Density Plasma Chemica| Vap〇r Dep〇s⑴〇n ,HDPCVD)、賤鑛法(Sputterjng)或電子餘真空蒸鍍 法(E-GUn)〕於該穿透氧化層2上鍍上一厚度為3〇埃· 之石夕酸給薄膜層3,該崎可為梦與鍅(料錯)、於 與石夕(料給)或給與紹(銘酸給),並置於在高真』 下通入氧軋,經過9〇(rc 6〇秒之快速升溫退火製程,使. 該石夕酸給薄膜層3產生奈米晶體,該奈米晶體之密度範 圍為0.9〜1.9 X 1〇 2 cm 2,而其微粒大小為小於1〇奈米 ’該石夕酸給_層3亦可切祕賴層(料為石夕與 錯)或!S酸給薄膜層(㈣為給與|g),再利用電 鲁 助化學氣相沉積(Pl咖a Enhance Chemica| _〇「Illustration. As shown in the figure ..., use the vertical furnace tube to penetrate- U 1245375 Layer 2 grows on the center of an end face of a substrate of p-type si (p_typesi | ic〇n) 'The thickness of the penetrating oxide layer 2 is 20 angstroms, which can be a high dielectric constant ㈣ chemical gas An oxide layer is deposited on both sides of the substrate, and an n-source electrode or an 11-drain electrode can be formed on both sides of the substrate. Then, two different dry materials are synthesized by a physical chemical method [such as: atomic layer chemical vapor deposition (at〇mjc | aye “ chem 丨 ca |-vapor deposition (ALCVD), high-density plasma chemical vapor deposition (High-Density Plasma Chemica | Vap〇r Dep〇s⑴〇n, HDPCVD), base ore method (Sputterjng) or electronic residual vacuum evaporation Method (E-GUn)] plating the penetrating oxide layer 2 with a thickness of 30 angstroms of oxalic acid to the thin film layer 3, the qi may be dream and sorrow (wrong material), Yu and Shi Xi ( Feed) or give Shao (Ming acid give), and put in oxygen rolling under high true, through a rapid heating annealing process of 90 (rc 60 seconds), so that the oxalic acid to the film layer 3 produces Nano crystals, the density of the nano crystals ranges from 0.9 to 1.9 x 10 cm 2 and the particle size is less than 10 nanometers. Lai secret layer (Xi stone material is wrong) or S acid to the thin film layer (iv given as | g)!, Recycling co-chemical vapor deposition electric Lu (Pl is coffee a Enhance Chemica | _〇 "
DeP〇s山on ’ PECVD)於該石夕酸給薄膜層3上成長一厚 j40埃之阻擔氧化層4 (bl〇Cking〇Xide),該阻擋氧 ^層之材料可為氧化物(〇她)、氮化物(N_e)、 2 — (Hf〇2)、氧化錯(Zr〇2)、氧化紹(〜so〗)或 =化鑭(La2〇3),最後再利用熱蒸鑛法於該阻擋氧化層 上鍍上—材料為鋁、多晶矽、多晶矽鍺或金屬之控: 13 1245375 閘極層5藉此开> 成一結構為§〇n〇s之利用石夕酸給奈米 U粒備衣之非揮發性快閃記憶體。上述之s〇n〇s之結構 的電何-電壓電性’係加入3伏特到_3伏特之電壓,請參閱 『第7圖』所示,係可看出㈢開了1VA右的記憶視窗 ’且施加不同電壓所對應形成的記憶視窗大小也不同, 如:由最小施加6V(3V掃到_3V) 一直到最大2〇ν(ι〇ν 掃到-10V)(如第8圖所示)。 本發明之利用矽酸铪奈米微粒備製之非揮發性快閃 記憶體係利用物理氣相沉積(PVD,Phys^wDeP0son'PECVD) grows a thick j40 angstrom barrier oxide layer 4 (blOCking〇Xide) on the thin film layer 3, and the material of the oxygen blocking layer may be an oxide (〇 (She), nitride (N_e), 2- (Hf〇2), oxidized oxide (Zr〇2), oxidized oxide (~ so〗) or lanthanum (La2〇3), and finally use the thermal distillation method to The barrier oxide layer is plated—the material is aluminum, polycrystalline silicon, polycrystalline silicon germanium, or metal. Control: 13 1245375 Gate layer 5 is used to create a structure of §〇n〇s using oxalic acid to give nano-U particles Non-volatile flash memory for clothing. The above-mentioned snos structure's electric-voltage electrical property 'is a voltage of 3 volts to _3 volts. Please refer to "Figure 7", it can be seen that the memory window opened to the right of 1VA 'And the size of the memory window corresponding to the application of different voltages is also different, such as: from a minimum of 6V (3V to _3V) to a maximum of 2〇ν (ι〇ν to -10V) (as shown in Figure 8) ). The non-volatile flash memory prepared by using nanometer silicate particles of the present invention uses physical vapor deposition (PVD, Phys ^ w
Deposition )沉積石夕酸給薄膜層,該㈣給薄膜層可應用 在任一基板上。上述之矽酸铪薄膜層係將電荷儲存在分 離式(discrete)的儲存點巾,因此儲存的電荷之間不會 互相作用彳吏4穿透氧化層的局部缺陷也不會造成全部 電荷的/爪失,且由於該矽酸铪薄膜層利用一顆顆的奈米 晶體來補抓電荷’因此儲存方式可以很區域性,可利用 上述之特縣製造記憶體,使其_個單元儲存2個位元( 2blt/CeM) ’亚具有高密度之優點(如第9 A〜1 〇圖及 表2所示)。 α及 月多閱第1 1〜1 5圖』所示,係利用矽酸铪奈 米,粒備製之非揮發性快閃記憶體記憶視窗、保持特性 不思圖。如圖所示:本發明之利用石夕酸給奈米微粒備製 非揮t f生决閃兄憶體之記憶視窗會因問極電壓(Vg ) 之極限越大而增大,在寫人或清除時不容易受到干擾, 14 1245375 不w在寫入或清除時,由於電荷入射或引出的速度合 魏化層的厚度,而本發明之穿透氧化層的^ 又馬'、'、丨矢,且本發明之矽酸銓薄膜層為30埃,使其可 、、”.、或π除,且其保持特性可以容納大量的資料並 可保存很久’其週期數值可㈣6。 、 [貫施例3】單位元記憶體(Single Dot Me,)之利用 夕酉文給不米微'粒備製之非揮發性快閃記憶體Deposition) deposits oxalic acid to the thin film layer, and the thin film can be applied to any substrate. The above-mentioned rhenium silicate thin film layer stores electric charges in a discrete storage point towel, so the stored electric charges do not interact with each other. 4 Local defects penetrating the oxide layer do not cause all electric charges. Claw loss, and because the samarium silicate thin film layer uses nano crystals to make up for the charge, so the storage method can be very regional. The above-mentioned special county can be used to make memory to store 2 units per unit. Bit (2blt / CeM) 'sub has the advantage of high density (as shown in Figure 9 and Figure 10 and Table 2). Alpha and Month are shown in Figures 11 to 15 below. It is a non-volatile flash memory memory window prepared by using nanometer silicate and grains. As shown in the figure: the memory window of the present invention for preparing non-volatile tf biodegradation memory for nanoparticle using oxalic acid will increase due to the larger limit of the interrogation voltage (Vg). It is not easy to be disturbed during erasing. 14 1245375 When writing or erasing, the speed of the incident or extraction of electric charge is consistent with the thickness of the chemical layer. However, the oxide penetrating layer of the present invention can be used as a substrate. Moreover, the samarium silicate film layer of the present invention is 30 angstroms, so that it can be divided by ","., Or π, and its retention characteristics can hold a large amount of data and can be stored for a long time. Its cycle value can be ㈣6. Example 3] Unit Dot Memories (Single Dot Me,) using non-volatile flash memory prepared by Budweiser's grains
it:制第ΐ 6圖』所示’係本發明之利用矽酸铪奈j t I之非揮發性快閃記憶體m記憶體結構7 :圖二如圖所示:係將一穿透氧化層2成長於一為絕· 曰復矽(S山con_〇n_lnsu丨ator,S0丨)結構之基板1白It is shown in Figure 6: "It is the non-volatile flash memory m memory structure of the present invention using cyanide jt I. 7: Figure 2 is as shown in the figure: a penetrating oxide layer 2Grows on the substrate of a complex structure called S-con_〇n_lnsu 丨 ator (S0 丨) 1 white
一端面中央上’再將給及歡材以共线渡法方 這穿透氧化層2上訂-厚度為3Q埃之㈣給薄心 3,亚置於在高A空下通入氧氣,經過9〇〇γ6〇秒之七 速.升溫退火製程,使該賴铪_層3產生奈米晶體 ,奈米晶體之密度範圍為而其韻 粒大小為小於10奈米’於該矽酸铪薄膜層3上成長1 擋氧化層4 ’再將-多晶⑦層6成長於該阻擋氧^層l 上’且在該穿透氧化層2、财酸給薄膜層3、該㈣ 氧化層4及該多晶矽層6之兩側分別成長一間隔層7 藉此形成-結構為單位元記憶體之利_㈣^ 15 1245375 備製之非揮發性快閃記憶體。 [貫施例4】多位元記憶體(Multi-bits Single DotOn the center of one end face, the material will be given to Huancai in a collinear way. This penetrates the oxide layer 2-the thickness is 3Q angstroms to the thin core 3, and the sublayer is put in oxygen at a high A altitude, passing through Seven speeds of 900 × 60 seconds. The annealing process is heated to generate nanocrystals in the lysate_layer 3. The density of the nanocrystals is in the range of 10nm and the size of the rhyme particles is less than 10nm. Layer 3 grows on the oxide barrier layer 4 and then 'polycrystalline rhenium layer 6 is grown on the oxygen barrier layer l' and on the penetrating oxide layer 2, the acid gives the thin film layer 3, the rhenium oxide layer 4 and A spacer layer 7 is grown on each of the two sides of the polycrystalline silicon layer 6 to form a structure of the unit cell memory. ㈣ ^ 15 1245375 Prepared non-volatile flash memory. [贯 例 4] Multi-bits Single Dot
Memory)之利用矽酸铪奈米微粒備製之非揮發性快閃記 憶體 ° μ參閱『第1 7 A〜1 7 B圖』所示,係本發明之Memory) Non-volatile flash memory prepared by using nano-silicate silicate particles ° μ Refer to "Figures 7 A to 17 B", which is the
矛J用石夕酸給奈米微粒備製之非揮發性快閃記憶體之多位 凡記憶體結構示意圖。如圖所示··係包含一結構為絕緣 層上覆矽之基板1,該基板係由一第一矽層丄丄上形成 -二氧化矽層1 2上,一第二矽層! 3成長於該二氧化 矽層1 f之一端面中央組成,再將一穿透氧化層2形成 於4 —氧化矽層1 2之一端面兩側及該第二矽層丄3上 矽酸铪薄膜層3再形成於該穿透氧化層 ^ - ^給薄膜層3係由給切之兩餘材以共㈣渡法於1' 牙透氧化層2上鍍上’其厚度為3〇埃’再置於在高直 下通入氧氣,經過90(rc 6〇秒之快速升溫退火製程:、 層3產生奈米晶體,上述之奈米晶體之 :二〇太:1·9 X 1〇12⑽·2’該奈米晶體之微粒大 =門之’而在該穿透氧化層2及該石夕酸給薄膜 3:間之…上形成一材料為氮切 hard mask )8,再將一阳私斤 恭增 膜層3上,且於該阻μ =化層4形成於騎酸給 、 ▲羊 θ上形成一控制閘極層5 16 1245375 口弟17A圖所示)’並將該阻擔氧化層4之一端面刺 用化學機械研磨法(chemiea| Mechanica|叫丨训^, CMP) 4 1去除該控制閘極層5形成控制閘極η (如 第17B圖所示)’使其形成—結構為多位元記憶體之 利用石夕酸給奈米微粒備製之非揮發性快閃記情體。 上所述,本發明 / %扣付肤厲」作為The spear J is a schematic diagram of the structure of non-volatile flash memory prepared by nano-particles with oxalic acid. As shown in the figure ..... It includes a substrate 1 with a structure that is covered with silicon on an insulating layer. The substrate is formed on a first silicon layer 丄 丄-on the silicon dioxide layer 12 and a second silicon layer! 3 grows in the middle of one end face of the silicon dioxide layer 1 f, and then forms a penetrating oxide layer 2 on both sides of one end face of the silicon oxide layer 12 and the second silicon layer 丄 3 The thin film layer 3 is further formed on the penetrating oxide layer ^-^ The thin film layer 3 is plated on the 1 'dental permeation layer 2 by a coexistence method of two cut materials, and its thickness is 30 angstroms. Then put in oxygen under high temperature and go through a 90 ° rc 60 second rapid heating annealing process :, layer 3 generates nano crystals, the nano crystals mentioned above: 20 too: 1 × 9 × 1012⑽ · 2 'The nano crystal particles are large = the door' and a material is formed by nitrogen cutting hard mask on the penetrating oxide layer 2 and the oxalic acid to the thin film 3: 8, and then Gong Gong increased the film layer 3, and the resistance μ = chemical layer 4 was formed on the acid supply layer, and a control gate layer 5 16 1245375 (shown in Figure 17A) was formed on the sheep θ) and the resistance was oxidized. One of the end faces of layer 4 is chemically mechanically polished (chemiea | Mechanica | called 丨 training ^, CMP) 4 1 The control gate layer 5 is removed to form a control gate η (as shown in FIG. 17B) 'to form— Structure for Stone memory element using an acid Xi nm to non-volatile flash situation in mind of preparing an microparticles. As mentioned above, the present invention /%
要朿略’可有效改善習狀種種缺點,使其製 記憶體可快速寫人或清除,且具有高密度、保存特性 =久特性佳等優點,進而使本發明之産生能更進步、 貫用、更符合❹者之所需,確已符合發明專利 ^件、,妥依法提出專利申請,尚請貴審查委員撥^ ,亚盼早日准予專利以勵創作,實感德便。 惟以上所述者,僅為本發明之較佳實施例而已,去 =此限定本發明實施之範圍;故,凡依本發明^專= =圍及發明說明書内容所作之簡單的等效變化與:飾, 皆應仍屬本發明專利涵蓋之範圍内。It's important to improve the shortcomings of the habit, make the memory can be written or erased quickly, and it has the advantages of high density, good storage characteristics and good long-term characteristics, etc., so that the production of the present invention can be more progressive and consistent. It is more in line with the needs of those who have already met the patents for inventions, and has applied for patents in accordance with the law. Your review committee is still requested to dial ^, and we hope to grant patents as soon as possible to encourage creativity. However, the above are only the preferred embodiments of the present invention, and are intended to limit the scope of implementation of the present invention; therefore, any simple equivalent changes made according to the present invention and the content of the description of the invention and : Decorations should still fall within the scope of the invention patent.
17 1245375 【圖式簡單說明】 第1圖,係本發明之利用矽酸铪奈米微粒備製之非揮發 性快閃記憶體之製造流程示意圖。 第2 A圖,係本發明之矽酸铪薄膜層之剖面示意圖。 / 第2 B圖,係本發明之矽酸姶薄膜層之平面示意圖。 · 第3 A圖,係本發明之矽酸铪薄膜層之非晶態示意圖。 第3 B圖,係本發明之石夕酸給薄膜層之多晶態示意圖。 第4 A〜4 B圖,係本發明之矽酸铪薄膜層之X射線光 電子能譜儀(X-ray Photoelectron Spectrum )結修 果示意圖。 第5圖,係本發明之矽酸铪薄膜層之電性量測結果示意 圖。 - 第6 A〜6 B圖,係本發明之利用矽酸铪奈米微粒備製 、 之非揮發性快閃記憶體之S0N0S結構示意圖。 第7圖,係本發明之S〇N〇S結構之電性量測結果示意 圖。 φ 第8圖,係本發明之SONOS結構之記憶視窗曲線示意 圖。 第9 A〜9 B圖,係本發明之SONOS結構之儲存電荷 曲線示意圖。 第1 0圖,係本發明之SONOS結構之工作狀態曲線示 意圖。 第1 1圖,係本發明之SONOS結構之記憶視窗曲線示 意圖。 18 124537517 1245375 [Brief description of the drawings] Figure 1 is a schematic diagram of the manufacturing process of the non-volatile flash memory prepared by using nanometer silicate particles of the present invention. FIG. 2A is a schematic cross-sectional view of the samarium silicate film layer of the present invention. / Figure 2B is a schematic plan view of the samarium silicate film layer of the present invention. Figure 3A is a schematic diagram of the amorphous state of the samarium silicate film layer of the present invention. FIG. 3B is a schematic diagram of the polycrystalline state of the oxalic acid to the thin film layer of the present invention. Figures 4A to 4B are schematic diagrams of the results of repair of an X-ray Photoelectron Spectrum (X-ray Photoelectron Spectrum) of the samarium silicate film layer of the present invention. Fig. 5 is a schematic diagram showing the electrical measurement results of the rhenium silicate film layer of the present invention. -Figures 6A ~ 6B are schematic diagrams of the structure of the SONOS of the non-volatile flash memory prepared by using nanometer silicate particles of the present invention. Fig. 7 is a schematic diagram of the electrical measurement results of the SONOS structure of the present invention. φ Figure 8 is a schematic diagram of a memory window curve of the SONOS structure of the present invention. Figures 9A ~ 9B are schematic diagrams of the stored charge curve of the SONOS structure of the present invention. Fig. 10 is a schematic diagram showing the working state curve of the SONOS structure of the present invention. Fig. 11 is a schematic view of a memory window curve of the SONOS structure of the present invention. 18 1245375
結構之抹除特性曲線Erase characteristic curve of structure
SONOS 第1 2 A圖,係本發明之 示意圖。 第1 2 B圖,係本發明之 示意圖。 1 3 C圖,係本發明之s〇N〇s 第1 3A〜1 3C圖,後 結構之寫入 及抹除干擾特性曲線示意圖。 第1 4 =,係本發明之s咖s結構之保存特性曲線示 意圖。 第1 5圖,係本發明之s〇N〇s結構之耐久測試曲線示 意圖。 第1 6圖’係本發明之利时·奈米微粒備製之非揮 ★ 發性快閃記憶體之單位it記憶體結構示意圖。 第1 7Αϋ ’係本發明之完成化學機械研磨法前之多位 元記憶體結構示意圖。 第1 7 Β圖’係本發明之完成化學機械研磨法後之多位 元記憶體結構示意圖。 第1 8 Α〜1 8 Β圖,係習用之epr〇m示意圖。 第19A〜19B圖,係習用之EEPROM示意圖。 第2 0圖,係習用之fl〇t〇x電路示意圖。 第2 1圖’係習用之快閃記憶體示意圖。 第2 2圖,係習用之MN〇s記憶體示意圖。 第2 3圖’係習用之s〇n〇S記憶體示意圖。 第2 4 A圖,係習用之s〇N〇s記憶體FN tunneling能 1245375 帶示意圖。 第2 4 B圖,係習用之S0N0S記憶體寫入/清除特性曲 線不意圖。 表1,係本發明之矽酸铪薄膜層之能量擴散光譜儀 (Energy Dispersive Spectrograph,EDS)、择果 表。 表2 ’係本發明之SONOS結構之工作狀態數據表。 【主要元件符號說明】 基板 1 第一石夕層 11 二氧化矽層 12 第二矽層 13 π源極/沒極 14 穿透氧化層 2 石夕酸铪薄膜層 3 阻擋氧化層 4 化學機械研磨法 41 控制閘極層 5 多晶矽層 6 間11¾層 7 硬照幕層 8Figure 1 2A of SONOS is a schematic diagram of the present invention. Figure 1 2B is a schematic diagram of the present invention. The 13 C diagram is the sonos 13th to 13C diagrams of the present invention, and the schematic diagram of the writing and erasing interference characteristics of the rear structure. The 14th = indicates the preservation characteristic curve of the s coffee structure of the present invention. Figure 15 shows the durability test curve of the sonos structure of the present invention. Fig. 16 'is a schematic diagram showing the structure of a unit it memory of non-volatile ★ flash memory prepared by Nissan Nanoparticles of the present invention. The first 17A ′ is a schematic diagram of a multi-bit memory structure before the completion of the chemical mechanical polishing method of the present invention. Figure 17B is a schematic diagram of the structure of the multi-bit memory after the completion of the chemical mechanical polishing method of the present invention. Figures 1 8 Α ~ 1 8 Β are schematic diagrams of epr0m used in the past. Figures 19A ~ 19B are schematic diagrams of a conventional EEPROM. Figure 20 is a schematic diagram of the conventional flot circuit. Figure 21 is a schematic diagram of a conventional flash memory. Figure 22 is a schematic diagram of the conventional MNOs memory. Figure 23 is a schematic diagram of a conventional SONOS memory. Fig. 24A is a schematic diagram of a conventional SN tunneling energy FN tunneling capacity of 1245375. Figure 2 4B is the intentional writing / erasing characteristic curve of S0N0S memory. Table 1 is an Energy Dispersive Spectrograph (EDS) and fruit selection table of the gadolinium silicate thin film layer of the present invention. Table 2 'is a working state data table of the SONOS structure of the present invention. [Description of Symbols of Main Components] Substrate 1 First stone layer 11 Silicon dioxide layer 12 Second silicon layer 13 π source / inferior layer 14 Penetrating oxide layer 2 Rhenium acid film layer 3 Barrier oxide layer 4 Chemical mechanical polishing Method 41 control gate layer 5 polycrystalline silicon layer 6 11 ¾ layer 7 hard photo curtain layer 8
20 1245375 β Ο 交〇 ^ η° ^ o° 辞 i Μ φ ΛΑ # 5 私 OS K) # OH f ^ %P OJ to |〇 os Ul # ^〇 y^N Ul φ Ul • ON 00 ps ^s Lh ㈣ Os • s 1245375 位元 2 位元 1 < m oL € < m oL o <J 〇 < 寫入 10V I U% < % 10V 1 U% < 清除 < >L6V 23V 1_ >L6V o < 23V 讀取20 1245375 β 〇 cross 〇 ^ η ° ^ o ° ii Μ φ ΛΑ # 5 Private OS K) # OH f ^% P OJ to | 〇os Ul # ^ 〇y ^ N Ul φ Ul • ON 00 ps ^ s Lh ㈣ Os • s 1245375 bit 2 bit 1 < m oL € < m oL o < J 〇 < write 10V IU% <% 10V 1 U% < clear < > L6V 23V 1_ > L6V o < 23V read
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