TWI220042B - Non-temporal memory reference control mechanism - Google Patents

Abstract

An apparatus and method are provided for extending a microprocessor instruction set to specify non-temporal memory references at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into a micro instruction sequence. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies a non-temporal access for a memory reference prescribed by the extended instruction, where the non-temporal access cannot be specified by an existing instruction from an existing instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the micro instruction sequence, and executes the non-temporal access to perform the memory reference.

Description

1220042 A7 V Description of the Invention (/) Contrast with related applications [0001] This case claims the priority of the following US applications ... Case No. 10/227583, application dated August 22, 2002. [0002] This application is related to the following U.S. patent applications, which are also in the same application, and have the same applicant and inventor.员工 Printed the Taiwan application number by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs DOCKET NUMBER 91116957 7/30/02 CNTR: 2176 Device and method for extending the microprocessor instruction set 91116958 7/30/02 CNTR: 2186 Implementation conditions Device and method for instruction 91124008 10/18/02 CNTR: 2187 Device and method for selectively controlling memory attributes 91116956 7/30/02 CNTR: 2188 Device and method for selectively controlling condition code writeback · 91116959 7/30 / 02 CNTR: 2189 Mechanism for increasing the number of registers in the microprocessor911124005 10/18/02 CNTR: 2190 Device and method for extending the microprocessor data mode911124006 10/18/02 CNTR: 2191 Extended microprocessor address Mode Z Device and method CNTR: 2192 Prohibition of storage inspection CNTR: 2193 Prohibition of selective interruption 91116672 7/26/02 CNTR: 2198 Apparatus and method for selectively controlling the result write-back (Please read the precautions on the back before filling (This page) P-Pack I 1 1 n One OJf eMmm tmf MmmB mMmm ϋ ϋ *

This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 1220042 A7 ______B7 —___ _ V. Description of the invention (Q) (1) Field of invention: [0003] The present invention is related to the field of microelectronics In particular, a technology capable of incorporating non-temporary (non_temporal) memory attribute control at the instruction level into an existing microprocessor instruction set architecture. (II) Technical background of the invention: [0004] Since its introduction in the early 1970s, the use of microprocessors has grown exponentially. From the earliest applications in science and technology to consumer areas that have introduced business from those special areas, such as desktop and laptop computers, video game controllers, and many other common home and business devices And other products. [0005] Explosive growth in use has also experienced a corresponding improvement in technology, which is characterized by increasing requirements for the following items: faster speed, stronger addressing ability, faster memory Access, larger operands, more general-purpose types of operations (such as floating-point operations, single instruction multiple lean (SIMD), conditional moves, etc.) and additional special-purpose operations (such as digital signal processing functions and others Multimedia computing). This has created amazing technological progress in the field, and has been applied to the design of microprocessors, such as extensive pipelining, ultra-scalar architecture, cache structure, and out-of-order processing ( 〇ut_〇f_〇rder pr〇㈣ 丨 叩), burst access (burst access) mechanism, branch prediction (branch predicati) and speculative execution. To put it bluntly, today's microprocessors are surprisingly complex and powerful compared to when they first appeared in 30 years. (Please read the notes on the back before filling out this page) Order -------- #-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 3

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5. Description of the Invention (f) These special blankets. If the existing instruction set architecture does not have redundant opcode states, some existing opcode states must be redefined to provide new features. Therefore, in order to provide new features, it is necessary to sacrifice legacy software compatibility. [0009] An area of concern for microprocessor designers today is how applications can efficiently use cache memory structures. As cache technology has evolved, more and more features have been provided that allow system programmers to control when and how cache memory in a system is used. Early cache control features only provided on / off capabilities. By setting one of the internal registers of the microprocessor, or by setting an external signal pin on its package to true, the designer can enable the cache of the memory or the entire memory The body space is set to uncacheable. For non-cacheable memory references (load / read and store / write), they are all sent to the system memory bus, resulting in the same latency (latency) as the external bus architecture ). In contrast, memory references or accesses to a cache memory only occur when a cache miss occurs (ie, a memory reference target is not valid in the internal cache memory) ., Is sent to the system memory bus. The cached feature makes the application run faster at the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, especially when the application repeatedly references the same data structure in memory. [0010] Recent improvements in microprocessor architecture have enabled system designers to more precisely control how cache features are used. These improvements allow the designer to set a pro-address range on the microprocessor's interface, with a mix of _ paragraphs, and how to perform a reference to the address range according to the cachehierarchy on the microprocessor. Nature. Generally speaking, for the address range

X 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1220042 A7 ---------- B7 _ V. References to the invention description (疒) can be set for silk and composite writers (writeeGmbining) , Writethrough, writeback, or write protection (such as protected). These properties are called memory attributes, or memory attributes. Therefore, the storage reference of the address with the write-back attribute is sent to the cache memory M, and is speeulatively assigned to the storage location therein. The storage reference of the address with the non-cacheable attribute is sent to the system bus and will not be speculativdy executed. [0011] However, providing a deep explanation of the memory state by its cache memory is not included in the first group of this application. To understand the current technical field, the designer is required to assign a memory area to a memory area, and all subsequent memory references to the addresses in the area will be based on the specified memory properties. Cachepolicy, which is sufficient. [0012] Although modern microprocessor designs allow different regions of memory to be endowed with different memory characteristics, they are still limited in design in two important respects. First, the microprocessor instruction set architecture limits the execution of instructions that define / change memory characteristics to a level that is not accessible to user-level applications. Therefore, when a desktop / laptop microprocessor is activated, its operating system establishes the memory characteristics of the virtual memory space before any user-level application is launched. Therefore, user-level applications cannot change the characteristics of the host system. Second, in modern microprocessors, the optimal processing level used to establish memory characteristics is the blade level. In ‘white use of paging memory paging (mem〇ry paging) 6 This paper size applies Chinese National Standard (CNS) A4 specifications (210 χ 297 public love)

2. Description of the invention (z) Deletion property of each memory page is set by the operating system in the items of the page, page, and table. Therefore, for the reference of a specific ribbed address, the fetch operation will be performed on the _xuanzhiji mixed. [0013] For the well multi-application program, although the above-mentioned control characteristics can be equal to the level of the program's day _ to speed up its execution speed, but the invention of this case ^ Note ... to 'the effect on other Gu programs Still limited. In addition to this, at the user level, there is no way to control the characteristics of modern keys. It is also because the memory attributes can only be established based on the paging level (the unit of Ke Mingzhi⑴). For example, a one-to-one first data structure For the user's private access of repeated accesses-when making reference to the-second data structure-occasional reference, if the first data, the cache items must be cleared to free up the space of the cache memory for the two-two data structure Use, the execution efficiency of professional user programs will be affected. Because the operating system does not predict the reference frequency of user-level applications to the data structure, the heterogeneous data space is generally given a write-back feature, so Contributed to the aforementioned conflict condition. The programmer does not have the tools to change the characteristics of the data space to force the occasional reference to be transferred to the memory bus (for example, to give the second data structure an uncacheable property), and Eliminate the conflict. [0014] In this technical field, the data repeatedly accessed by the application program is called temporary data, and accidentally accessed Data is called non-temporal data. Those skilled in the art will find that if a cache memory is filled with non-temporal data (that is, cache pollution), it will be Very unfavorable. Therefore, the latest technology has been introduced into A7 " " ^ _BZ ____ V. Invention Description (^!) It can be added to the existing instruction set to add a limited set of non-temporary storage instructions to it applications Designers move data from internal registers to memory without contaminating cache memory. However, there is no applicable tool now: let% s to use an existing instruction (for example, to specify one to use one Or more instructions that run different noses or logic operations) The memory reference specified is executed in a non-temporary manner, thus skipping the access of the cache memory completely. [0015] Therefore, what we need is A device and method capable of incorporating instruction-level non-temporary memory reference control features into an existing microprocessor instruction set architecture, wherein the instruction set architecture is completely occupied by a defined operation code and is included in the memory reference control Features allow a microprocessor that meets the old specifications to retain the ability to execute legacy applications, while also providing programmers with the ability to specify non-temporary memory access. (3) Brief description of the invention: [0016] The present invention is like The aforementioned other applications are aimed at overcoming the problems and disadvantages of the above-mentioned and other conventional technologies. The present invention provides a better technology for expanding the instruction set of a microprocessor to exceed the existing capabilities and provide instruction-level information. Non-temporary memory reference control. In a specific embodiment, a device that can perform instruction-level memory reference only control in a microprocessor is provided. The device includes a translation logic and— Extended execution logic. The translation logic translates an extended instruction into a micro instruction sequence (micro instruction sequenee). The extended instruction has an extended prefix and an extended prefix tag. The extended preamble is applicable to the extended paper size 8 Chinese paper standard (CNS) A4 (210 X 297 mm). Please read the note on the back first.

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A7 —- _____ B7 V. Description of the invention (/) The execution logic is coupled to the translation logic, and the memory reference is performed by the non-temporary access. [0019] Another object of the present invention is to provide a method for expanding an existing instruction set architecture to provide non-temporary memory reference control at the instruction level. The method includes providing an extended instruction, the extended instruction includes an extended mark and an extended preamble, wherein the extended mark is a different code item in the existing instruction set structure; specifying the required through the extended prefix Apply to a non-temporary access to a corresponding memory reference, where the memory reference is specified by the rest of the extended instruction; and apply the non-temporary access to execute the memory reference, which should be executed Perform a cache operation that excludes related data referenced by the memory. (IV) Illustrative illustration of the invention: γ〇〇２〇 The foregoing and other objects, features, and advantages of the present invention will be better understood after cooperating with the following description and accompanying drawings: [0021] It is a block diagram of a related-art microprocessor instruction format. [0022] FIG. 1 is a table describing the instruction of a consumer ’s cooperative printing order issued by the Intellectual Property Bureau of the Intellectual Property Bureau of the Ministry of Economic Affairs. The bit logic state of an 8-bit opcode byte in the instruction format; [0023] Figure 2 is a block diagram of the age division of the present invention; ⑽1 ° 〇24] Figure 4 is a table, which Shows how the extended architecture corresponds to the 8-bit extended preamble embodiment according to the present invention. 1220042

[0025] FIG. 5 illustrates the application of non-temporary memory reference control in the present invention.

Block diagram of a pipelined microprocessor; I

[0026] FIG. 6 shows the invention in a microprocessor for designating a spear. One of the extended preambles of the non-temporary access referenced by the self-memory format is specifically implemented in your block diagram; ^ [0027] ® 7 is a detailed block diagram of the logic in the translation stage of the microprocessor in Figure 5. [0028] FIG. 5 is a block diagram of the extended execution stage logic in the microprocessor of FIG. 5, and [0029] The headline 9 is a description of the non-temporary memory reference used to control the microprocessor in the present invention. Method flow chart. C Please read the precautions on the back before filling in this page) 0 Install the printed number description of the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs: 100 instruction format 102 operation code 200 8-bit operation code figure 202 operation code F1H 300 extended instruction format 302 opcode 304 extended instruction mark 400 8-bit prefix code diagram 500 pipelined microprocessor 1101 prefix code 103 address designator 201 opcode value 3301 prefix code 303 address designator 401 Architecture Ted 501 extracts logical words 502 instructions cache memory / external memory 503 5 04 translation logic order --------- 11 1220042 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs //) 505 extended translation logic 507 execution logic 600 extended preamble 602 purpose stop 700 translation stage logic 702 machine specific register 704 instruction buffer 706 translation controller 708 escape instruction detector 710 instruction decoder 712 micro Instruction buffer 714 Micro operation code block 716 Source block 800 Extended execution stage logic 802 Address buffer 804 Purpose operand buffer 806 Memory characteristic description 808 Bus unit 810 Store logic 812 Bus 814 Micro-instruction temporary register 816 Non-temporary load buffer 900 ~ 932 Controls the microprocessor's process 506 Micro-instruction 彳 Column 508 Extended execution logic 601 Source stop 603 Stand-by stand 701 Start status signal 703 Extended feature stop 705 translation logic 707 disabling signal 709 extended preamble decoder 711 control read-only memory 713 operation code extension field field 715 purpose stop 717 displacement stop 801 microinstruction buffer 803 address buffer 805 extended access logic 807 cache memory 809 access controller 811 load logic 813 bus 815 source operand buffer 817 composite write buffer non-temporary memory reference method operation I .— ^^ L— 装(Please read the notes on the back before filling this page)

ϋ mamam nn ^ -eJI ϋ an mmm— nl ^ i II # 12 1220042 Α7 Β7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (A) (5) Detailed description of the invention. [0030] The following description It is provided in the context of a specific embodiment and its necessary conditions, so that those skilled in the art can utilize the present invention. However, various modifications made to the preferred embodiment will be apparent to those skilled in the art, and the general principles discussed herein can also be applied to other embodiments. Therefore, the present invention is not limited to the specific embodiments shown and described herein, but has the widest scope consistent with the principles and novel features disclosed herein. [0031] The foregoing has discussed the background of today's microprocessors on how to expand their architectural features to surpass the capabilities of related instruction sets. In view of this, an example of related technology will be discussed in Figs. 1 and 2. The discussion here highlights the dilemma that microprocessor designers have been facing. On the one hand, they want to incorporate the newly developed architecture features into the design of the microprocessor, but on the other hand, they must keep the old implementation. Application capabilities. In the examples in Figures 2 to 2, a completely occupied opcode diagram has added a new opcode to the Fanny system, but it is compulsory for designers to incorporate new features into 'Qianzai to some extent' Wealth is mixed, otherwise we will change the architecture, new position-and give up, and read to maintain the compatibility of micro-processing H and old applications. After a discussion of the related art, a discussion of the present invention will be provided in Figs. Borrowing_existing—existing but unspecified operations ;; extending the light code mark of instructions, the present invention allows the designer to overcome the barrier of instruction set transfers that have been used, in addition to providing programs at the instruction level. Ability to determine the access of non-temporary memory referenced by a specific memory, and also (please read the precautions on the back before filling this page) FI equipment 1_ | I 1 1111 Order-— I! —! 13 A7 V. DESCRIPTION OF THE INVENTION (/ 9) All the features of Yu Yingcong are reserved for execution. [0032] Please refer to the figure, love 1 · 10 negative heads 101-103, the mother and one item are all micro-processed-the specific command touch value, together-the toilet organ executes a specific operation, f 100 orders The micro-processing item element is moved from the memory ship to a temporary 'or will-operation memory. -As usual, "= :, or moved from the internal register to the special operation to be executed, and select (〇pti〇nal) address to specify the meta project · Intellectual Property Bureau, Ministry of Economic Affairs, Consumer Consumption Cooperative Printed and read, 1 hinder_Xiao Xian said to add information, like = how to perform the calculation, Yuan recorded bribes. The age format is just, Yunjing Chengbei added _code item 101 before-operation code 102. When a specific operation specified by code 102 is executed, the preamble ⑼ is used to indicate whether it is a special wooden structure feature. In general, these architectural features can be applied to most of the operations specified by any operation code 1G2 in the set. For example, today Kechi Shima 101 exists in some micro-processing $ that can perform operations using virtual addresses of different sizes (such as 8-bit, I6-bit 70, 32-bit). And when many of these processors are programmed as -When the preset button size (such as 32-bit), set the code to 1 (n before it is provided in another instruction set, which can still enable the programmer to selectively override the preset according to each instruction. Address size (such as to generate a 16-bit it virtual address). The selectable address size is only Examples of architectural features. In modern microprocessors, these architectural features can be applied to many operations (such as addition, subtraction, multiplication, Bollinger logic, etc.) that can be specified by opcode 102. 14 Printed in accordance with National Standard A4 (CNS) A4 (21 × 297 mm), printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1220042 A7 ---------— B7 _ V. Description of the invention (/ 〆 ) ~-The instruction format shown in Figure 1 is a well-known example of the industry. This is the full instruction format, which is used by all modern Qin compatible micro. More specifically, the x86 instruction format ( Also known as Nacai's 々 Technical Architecture Discussion) uses 8-bit preambles 101, 8-bit opcodes ι02, and 8-bit addressing champion 架构 ..architecture 丨 ⑻ also has several preambles Two of 〇1 replaced the preset address / data size (namely, the opcode states 66 码 and ㈣) of the Na microprocessor, and the other instructed the microprocessor to interpret the subsequent ones according to different translation rules. Opcode byte 1 () 2 (i.e. the preamble value OFH 'which makes the translation action based on the so-called two bits The operation code rules are used), and the other preambles 101 cause special operations to be repeated until the repetition conditions are satisfied (ie, the REP operation codes: F〇h, F2H, and F3H). [〇〇34] Please Refer to FIG. 2, which shows a table 200, which is used to describe how the instruction 201 of an instruction set architecture corresponds to the bit value of an 8-bit opcode byte 102 in the instruction format of FIG. 1. The table 200 is presented. An example of an 8-bit opcode map 200, which associates a maximum of 256 values of an 8-bit opcode item 102 with the corresponding microprocessor opcode instruction 201. Table 200 calculates A specific value of the code item 102, such as 02H, is mapped to a corresponding different code instruction 201 (ie, instruction 102 201). In the example of the χ86 opcode diagram, it is well known in the art that the opcode value 14 is mapped to the x86 Add With Carry (ADC) instruction. This instruction is an 8-bit immediate (immediate ) Operand is added to the embedded value of the architecture register AL. Those skilled in this field will also find that the above-mentioned x86 preamble 101 (that is, 66H, 67H, OFH, F0H, F2H, and F3H) is the actual operation code value 201. In different contexts, the specified Extending the specific architecture by 15 paper sizes Applicable to China National Standard (CNS) A4 specifications (210 X 297 mm)

1220042 A7 V. Description of the invention (//) is applied to the operation specified by the subsequent operation code item 102. For example, under normal circumstances, 'the above-mentioned ADc opcodes' before the preamble makes the x86 processor perform a "decompress and insert low compression early, and stain value" (Unpack and Interleave bw p this ked gle_PredsiGn FlGating_pGint) operation '㈣ 县 的 就 =. According to the characteristics described in this example, the microprocessor in the Wei dynasty is able to process the instruction translation / decoding logic in the microprocessor in order. Therefore, in the past, using the special operation code value as the preamble 1 (Π in the instruction set architecture can allow processor designers, not: >, advanced * constructors to be compatible with the old software microprocessing Without the negative impact on t, which does not use those specific opcode states. For example, the old program that does not use χ86 opcodes can still be processed by today's χ86 microprocessors. A newer application 'by using the full operation code short as the preamble 101, can use many of the newly incorporated χ86 architecture features, such as single order (S thin) operation, conditional movement operation, etc. "Xi Zhongbeikedui [〇〇35] Although in the past by specifying the available / excessive opcode value plus as the set code 101 (also known as the architecture feature flag / indicator 101 or escape instruction 101) ' To provide architectural features', but many instruction set architectures 100 have been enhanced in the provision of function 2 I ^ 'will still be hindered by — very direct reasons': all available / excessive opcode values have been used End, that is, the Wang ^ ununique code value in the opcode graph has been structured When all available values are assigned as opcode entry 102 or preamble entry 101, there are no remaining opcode values available for inclusion in the new feature. This serious problem exists in current annotations Order t «: I___ 16 This paper size is applicable to the Zhongguanjia Standard (CNS) A4 specification (210 X 297 mm_y 1220042 V. Description of the invention (4) Many microprocessor architectures have forced designers to add [0036] It is worth noting that the instruction 201 shown in Figure 2 is expressed in a general way (ie, 124, off), It does not specifically refer to the actual operation (such as bit accumulation, subtraction, mutual exclusion, or). This is because in some different microprocessor architectures, the fully occupied operation code map 200 is architecturally included in the comparison. New, the possibility of exhibition is excluded. Although the example in Figure 2 mentioned above is an 8-bit operation code item 102, those skilled in the art will still find that the specific size of the operation ma 102, except as a-special case Let's discuss the fully occupied operation. Except for the problems caused by 200, other aspects are not related to the problem itself. F This,-6-bit opcodes on the full side _ have 64 opcodes / preambles that can be architecturally specified, and will not be available [0037] Another alternative is not to completely abandon the original instruction set and replace it with a new format 100 and opcode figure 200, but only for two Part of the existing operation code 201 is replaced by a new instruction meaning, as shown in the second code 40H to 4FH. With this mixed technology, the microprocessor can operate in one of the following two modes independently · Among them, the old mode uses operation codes 40H-4FH, which still has rules to interpret, or operates in another improved mode. At this time, operation codes 40Η_4ΡΉ are interpreted according to the enhanced architecture rules. This technology does allow designers to incorporate new features into their designs. However, when a microprocessor that conforms to the old specifications operates in enhanced mode, the disadvantages still exist because the microprocessor cannot execute any application that uses the opcode 40H_4FH. jg, standing at the standpoint of maintaining the compatibility of the old software. The 17 MM scale is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). Read the notes on the back side first.

I install page IIIIII order printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1220042 A7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention description (//) field, compatible with the old software / enhanced technology Accepted. [0038] However, for the case where the instruction code space 200 'has been fully occupied and the space covers all applications that are executed on micro-locations that meet the old specifications, the inventor of this case has noticed that the operation code The use of 201, and they also observed that although some instructions 202 are structured, they are not used in applications executed by microprocessors. The instruction IF1 202 described in Fig. 2 is an example of this phenomenon. In fact, the same opcode value 202 (ie F1H) is mapped to a valid instruction 202 that is not used in the x86 instruction set architecture. Although the unused χ86 instruction 200 is a valid instruction 6202, which instructs to perform a structurally specified operation on an x86 microprocessor, it is not used in any modern x86 microprocessor. Applications running on the processor. This special x86 instruction 202 is called the In Circuit Emulation Breakpoint (ie, ICE BKPT, and the opcode value is F1H). It was previously used exclusively for a microprocessor that no longer exists. Device. ICE BKPT 202 has never been used in applications other than in-circuit simulators, and in-circuit simulation devices that previously used ICE BKPT 202 no longer exist. Therefore, in the case of X86, the inventor of the present case has found a tool within the instruction set structure 2000 occupied by the King. By using an effective but unused operation code 202, the design of the microprocessor is allowed. Incorporates advanced architectural features without sacrificing compatibility with legacy software. In a fully occupied instruction set architecture 200, the present invention uses a structured but unused operation code 202 as an index mark to indicate the next n-bit preamble, thus allowing the microprocessor Designers can incorporate up to 2η of the latest development architecture features into the design of the microprocessor while retaining all the old software (please read the precautions on the back before filling this page).

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18 1220042 A7 B7 V Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the invention description (//) is fully compatible. [0039] The present invention provides an n-bit extended non-temporary access to the designated meta-preamble to use the concept of preamble marking / extended preamble, thus allowing programmers to perform micro-processing Device towel, specified according to each health order-non-temporary memory f fetch-corresponding memory reference operation. When the corresponding memory parameter is executed differently, the non-temporary memory access is used to replace the access to the base access memory (eaehe_based) according to a preset attribute. Designated as a memory table / mechanism previously created by the system. The invention will now be discussed with reference to Figs. [0040] Please refer to the third part, which is a block diagram of the extended instruction format of the present invention. It is very similar to the format discussed in the figure. The extended instruction format 300 has a variable number of instruction items 3G1_3G5. Each _ item is set to ^ one, and the value is set to form a specific instruction of the microprocessor. The specific instruction indicates Microlocation_execute—specific operations, such as adding two operations 疋 or '-operating element' from Temporary Nuina to Microlocation_'s temporary storage: inside. In general, the operation code item 3202 of instruction 300 specifies the specific operation of ^ ^, and the selected address designation meta-item 3G3 is located in the operation code, and f is used to determine additional information about the 4-key operation. , Such as how to "the Yun Yi, Yun Yi 7L where the temporary H, threat computing secret / end result of the emotional body address direct access to the fund solution, etc .. Command format 3⑻ also ^ using existing her 1 project 3G1 Does Meiss make _1] — 'this issue_extended instruction is the figure above_instruction grid please item # μ Qian scale applies to 19 X 297 mm) 1220042 A7 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs (//) Zhao set (superset) of formula 100, which has two additional items tear off and 3G5, can be selectively used as instruction extensions and placed before all the remaining items 301_303 in a formatted extension instruction 300. These two The additional item outline and 305 allow programmers to designate non-temporary memory access to the memory reference specified by the extended instruction, where the non-temporary memory access corresponding to the memory reference cannot be matched by the old Existing instructions with a specification microprocessor To specify it. Select items 304 and 305 as an extended instruction mark 304 and-extended non-temporary designated meta-prefix 305. The extended instruction mark system-micro-processing H instruction set-according to the architecture The specified operation ma. In a full embodiment, the extended instruction flag 304, or escape flag 304, uses the operation code state F1H, which is the ICE ΒΚρτ instruction used earlier. The escape flag 304 is processed to the micro processor. The device logic means that the extended prefix code 305, or 1 extended feature designator 305, follows, and the extended prefix code 305 corresponds to a designated memory reference (that is, a load Input operation, a store operation, or both) one of the non-temporary accesses. In a specific embodiment, the escape tag 304 indicates' an accompanying part 3001_3 and 3 of a corresponding extended instruction 300. 5 specifies the memory reference to be executed by the microprocessor. The non-temporary access designation element 3j05, or extended preamble 3505, specifies that a source operand is loaded to load the destination. In the operation or both, the non-temporary storage access is required. The extension execution logic executes the memory reference by performing the non-temporary memory access to replace the default cache attribute of caeheable that was originally referred to by other methods. These other methods include using Control register bits, memory type registers, paging tables, and other types of memory attribute descriptors in modern microprocessor architectures

(Please read the precautions on the back before filling out this page.) 装 • I 1_1 ϋ #. Description of the Invention (A) (descriptor) 〇 [0042] Here is an overview of the non-temporary reference control technology of the present invention. An extended instruction is configured to specify a non-temporary memory access to a memory reference of an existing microprocessor instruction set, wherein the non-temporary access to the memory reference cannot be replaced by the existing microprocessor. The instructions in the instruction set are specified. The extended instruction includes one of the operation code / instruction 304 of the existing instruction set and an n-bit extended preamble 305. The selected operation code / instruction is used as an index 304 'to indicate that the instruction 300 is an extended feature instruction 300 (that is, it specifies an extension of the microprocessor architecture), and the n-bit feature preamble 3 05 indicates that the non-transitory access is applied to a source operand, a destination operand, or both. In a specific embodiment, the extended preamble 305 has an octet size, and can specify a combination of non-temporary access control features and up to 64 other extended features. In the embodiment of the η-bit preamble, in addition to non-temporary access control features, a maximum of other 2η_2 extension features can be specified. [0043] Referring now to FIG. 4, a table 400 shows how a non-temporary access control feature referenced by a specified memory is mapped to the bit logic state of an 8-bit extended preamble embodiment according to the present invention. . Similar to the operation code diagram 2GG discussed in FIG. 2, the table 4GG in FIG. 4 shows an example of an 8-bit extended preamble map 400, which extends a maximum of 256 8-bit preamble entries 305. Values _to-microprocessing that conforms to the old specifications, corresponding to extended features 401 (such as Ε34, ·, etc.), two of which indicate non-temporary access. In the specific embodiment of the "man", the 8-bit extended feature preamble 305 of the present invention is provided for non-temporary memory access (that is, for instruction-level control). Remember that hiding 4G1 is the current x86 age. Set 1220042 A7 V. Explanation of the invention (〇? /) Which cannot be specified at the instruction level. _4] The extended features shown in Figure 4 are shown in a general way. The technology of the present invention can be applied to domain viewers and will find that there are many different architectural features. Among them, 'can be escaped according to the description of the escape tag 3ό4 / extended preamble 305-an existing instruction set. The four-bit 8-bit preamble embodiment provides 256 non-characteristic 4G1, and the η-bit preamble code embodiment has a stylized selection of 2 different features 4 0. ^ [0〇45] Now it is five, which explains the aspects of the present invention used to implement the non-temporary play-by-play game, the official line of the microprocessor 5⑻. The microprocessor chapter has three distinct types of stages: extraction, translation, and Execution. Fetch stage & has fetch logic 5G1, which can fetch instructions from the instruction cache memory 502 or external memory $ 502. The instruction is sent to the translator P and I through the instruction side $. The transmision section has a translator logic program that connects to a microinstruction queue. 06 translator logic 504 includes extended translator logic 505. During the execution phase, There is execution logic 507, which has extended execution logic 508. [0046] According to the present invention, during operation, the extraction logic 501 is cached from the instruction cache. The hidden / external brother memory 502 is used to extract the formatted instruction, And put these instructions into the instruction queue 503 in the order of execution. Then extract from the instruction queue 503 = two # 々, and send it to the transfer logic 504. The translation logic 504 sends each input The command translates / decodes into-corresponding micro-age phase, to refer to the thin processor 500 to perform the operations specified by these instructions. According to the present invention, the extended translation logic 505 detects Instructions for corresponding extended non-temporary • ί! Ί !! (please read the precautions on the back before filling this page)

I _1 n n One: OJ 羼 MM I I MB Ml · I _ #-Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

Size of this paper _TiiS ^ NSM4 ^ X 297 mm) 1220042 A7 V. Description of the invention (speaking) Save §self-thinking translation / decoding with reference to the 4th Yuan Yuan code. In "幼 6 杳:", the extended translation logic 505 is configured to detect the extended two mark whose value is ΠΗ, which is the ICE BKPT operation code. The microinstruction block is provided in the microinstruction side 506 'to allow specifying the source / destination non-temporary access of the relevant memory reference specified by the instruction accompanying section. [0047] The micro-instruction is sent from the micro-instruction queue 506 to the execution logic, where the extended execution logic 508 is configured to execute according to a preset memory characteristic (by an existing memory characteristic descriptor m_ 状 义). A designated memory reference, or configured to be executed at the user level through one of the non-transitory local memory accesses programmed through the extended frontend of the present invention, and designated by the extended microinstruction to replace 3 pre-hanks A memory feature and skips cache memory completely. In a specific embodiment, the processing method of the non-transitory storage operation < is the same as the storage operation of the address range using the input attribute. [0048] Those skilled in the art will find that the microprocessor 500 shown in FIG. 5 is a simplified result of a modern pipelined microprocessor 50. In fact, modern pipeline microprocessing H can contain at most 2 () to 3σ two identical pipeline stages. However, these stages can be broadly categorized into the three stages shown in the block diagram. Therefore, the block diagram 500 of FIG. 5 can be used to point out the above printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Real Economy of the present invention (please read the back first) (Notes on this page, please fill out this page) # The necessary 7L pieces required for the implementation. For brevity, extraneous components of the microprocessor 500 are not shown. [0049] Please refer to FIG. 6, which is a block diagram of a specific embodiment of an extended preamble of a non-temporary access referenced-programmed memory reference in a microprocessor according to the present invention. The non-temporary access designated meta-prefix 600 has an 8-bit size, and includes a source block 601, a field 602, and a backup 23. Private paper standards are applicable to China's national standards ^ CNS) A4 specification (21〇X 297 public reply) 1220042 A7 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs

---------- R7_ V. Description of the Invention (A) Use stop 603. Source Tone 601 specifies a non-temporary access to be applied to a related extension, so that the rest of the source operand memory accesses (ie, load, read) specified by the rest of the source, and the destination block specifies a Non-temporary accesses are applied to the destination operand memory accesses (ie, store, write) specified by the rest. Those skilled in the art will find that the source and destination non-temporary storage can be specified separately, and it will be particularly useful in the case of repeated string instructions such as the MOVS of the x86 architecture. . [0050] Please refer to FIG. 7, which is a detailed block diagram of the logic 700 of the translation stage in the microprocessor of FIG. 5. The translation stage logic 700 has an instruction buffer 704, which provides extended instructions to the translation logic 705 according to the present invention. The translation logic 705 is coupled to a machine specific register 702 having an extended Ted field 703. The translation logic 705 has a translation controller 706, which provides a disabling signal 707 to an escape command detector and an extended decoder 709. The escape instruction detector 708 is coupled to the extended decoder 709 and an instruction decoder 71. The extended decoder 709 and the instruction decoding logic 710 access a control read-only memory (ROM) 711, which stores a template micro instruction sequence corresponding to some extended instructions. The translation logic 705 also includes a micro-instruction buffer 712, which has an opcode extension slot 713, a microop address 714, a field 715, a source block 716, and a shift field 717. [0051] Operationally, during the start-up of the microprocessor, the state of the extended field 703 in the specific register of the machine is determined by the signal P_r-up state 701 to indicate the specific Whether the microprocessor can translate and execute the non-temporary register of instruction level of the present invention

This paper size applies to China National Standard (CNS) A4 specifications (210 X (please read the precautions on the back before filling this page) • I n --I I order ·!-# · 24 042 042

5. Description of the invention A temporary register is printed at the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (the number 701 is not shown in the picture from a feature control, and the feature control is stored in 11 reads-device-specific temporary storage.) Car (sea) (not shown). Machine cry 706. ^ The status of feature 703 is sent to the translation control II. 5 control logic 706 controls the extraction from the instruction buffer H 704 for: extended translation rules or custom translation rules. Interpretation. Provides control features like Ting, which can be used to allow the administrator to implement a green-type (such as BIOS) extended processor execution feature. If the extended feature is disabled, then == The instruction of the state of the opcode will be based on the translation rule 1 turn #. In the specific implementation of -x86, select the leg of the opcode state as your own. Under the conventional translation rules, it will be illegal to encounter a cut. Except l0n. If the extended translation is disabled, the instruction decoder 710 will translate / decode all the instructions given to you, and configure all the sheds 713 to 717 of the microinstruction 712. However, in the extended translation Under the rules, if you encounter a private person, you will be escaped Detected by the detector 708. The escape instruction detector 708 will instruct the extended preamble decoder 709 to translate / decode the extended preamble portion of the extended instruction according to the extended translation rule, and to the operation code Extension block 713 performs a group tragedy to indicate that the non-temporary memory access is to be applied to the memory reference specified by the rest of the extension instruction. The instruction decoder 710 will decode / translate the rest of the extension instruction, And configure the micro-transport different code block 714, source field 716, destination field 715, and displacement block 717 of the micro instruction 712. Certain specific instructions will cause access to the control ROM 711 'to obtain the corresponding Micro-instruction sequence template. The configured micro-instruction 712 is sent to a micro-instruction queue (not shown in the figure), which is processed by the processor for the subsequent 25 paper standards. Common Chinese National Standard (CNS) A4 specification (21 () χ 297 mm

1220042 A7 V. Description of Invention (J /) Implementation. [0052] Please refer to FIG. 8, which is a block diagram of the extended execution stage logic 800 in the microprocessor of FIG. The extended execution stage logic 8 includes an extended access logic 805, which is coupled to a cache memory 807 and a bus unit 808 via buses 812 and 813, respectively. The bus unit 808 is used to guide a memory transaction on a memory bus structure (not shown). According to the present invention, extended inventory

The page fetch logic 805 extends the microinstruction buffer 801 from one of the previous stages of the microprocessor. The receive command is' receive two address operands from the address buffers 802 and 803, and receive from the destination operand buffer 804. A destination operand. The extended access logic 805 is also coupled to a plurality of memory characteristic descriptors 806, which are conventionally configured according to the architecture of the host microprocessor. The extended access logic 805 includes an access controller 809, a storage logic 810, and a load logic 811. The load logic 811 includes a non-temporary load buffer 816 and outputs a source operand to a source operand buffer 815. The storage logic 810 has a composite write buffer 817.口 ”, Printed by the Intellectual Property Bureau ’s Employees’ Cooperatives of the Ministry of Economic Affairs 53 [G〇53] Operational 'Extended Execution Logic _ is the instruction of the micro instruction in the Saga extended micro instruction buffer 801 to perform memory access from Memory read operands and write operands to memory. When performing read / load operations, the access controller 809 receives one or more memory bits from the address buffers 802 and 803. Address, and read the memory characteristic descriptor to determine the memory attributes related to the load. In the _χ86 embodiment, the memory characteristic descriptor 806 contains the χ86 cache memory and the paging control temporary storage. Device, paging table of contents and paging table items, memory _ range register (_ Machika 26 M Zhang scale applicable to Chinese National Standard (CNS) A4 specifications (210 X 297 1 1220042 A7 B7 V. Description of the invention (W) (MTTR), paging attribute table (paging attribute orphan PAT), and external signal pins ID, Ding #, pcT, and pwT. The access controller 809 is based on the x86 level memory attribute conventions and uses 806 from these sources. Information obtained to determine The default memory attribute of the operation. For non-x86 embodiments, the access controller _ according to the specific frame corresponding to the host microprocessor II _ level memory performance, uses the information obtained from the memory characteristic descriptor 806 To determine the default memory attributes for human computing. The memory address, along with its corresponding access attributes, is sent to the load logic S1. Based on the provided attribute attributes, the load logic is retrieved from the cache via the bus 812 The memory or the source operand is obtained from the system memory (not shown) directly via the bus unit 808. The obtained source operand is synchronized with the answer clock signal (not shown) and sent to the source operand buffer 815 The extension microinstruction is also synchronized with the pipeline clock signal and is sent to the pipeline to the extension microinstruction register 814. In this way, the source operand is sent to the next stage of the microprocessor. [0054] Execution extension When a write / storage operation is instructed by a micro instruction, the access controller 809 receives the address data of the operation from the address buffer, 802 and 803, and receives the operand to be stored from the buffer 804. Save The controller 809 accesses the memory characteristic descriptor 806 as described above to determine the memory characteristics corresponding to the storage access operation. The memory characteristics, address data, and the purpose are different. Send to storage logic 810. According to the specific attributes provided, storage logic 810 writes the destination operand into cache memory 807 via bus 812, or directly into system memory via bus unit 808. [0055 ] The storage logic 810 and the load logic 811 of the present invention are configured as 27. The paper size is applicable to the Chinese National Standard (CNS) A4 regulation (21〇_x 297 public love) 1220042 Member 5 A7, invention description (J / ) Perform reference operations for storage and loading according to the processing requirements of the memory attribute model of the host processor, where the processing requirements include strong / weak ordering conventions (such as imaginary execution rules) and cache access principles. In a specific embodiment, the load and store operations are performed in different pipeline stages of the host microprocessor. [0056] For an extended instruction using a non-temporary memory reference preamble, the non-temporary transport heterogeneous element designator of the relevant memory reference (that is, load, store, or both load and store) extends the micro The extension code extension command block (not shown) in the instruction buffer 801 is sent to the access controller 809. The access controller 809 determines the default memory characteristics of the specified memory access by using the data obtained from the memory characteristic descriptor 806 as described above. If the corresponding default feature allows non-temporary access (ie, cacheable features, such as write-back feature), then the access controller _ sets the non-temporary designated element together with the aforementioned address and / or destination operand , And send it to the storage logic read and load the logic stream. If the corresponding preset feature does not allow non-temporary access (ie, a non-cacheable feature ^ ', then the access controller 8. 9 sends the preset feature with the address and / or destination transport element to storage Logic 810 / Load logic 811. A warrior enters the photos and g, load logic 811 first:,:;, _ mei memory miscellaneous ?. = :: ^ 疋 Exists and is valid (ie load hit) ). If the day ^ is loaded, that is, _memory execution is fine. Thin, silk pair 2 does not exist in the cache memory 807, then the manned logic ^ it. Early π _ fetch her domain person ilh fast from the domain Take ________ 28 paper size

--- Γ ”< Packing -------- Order --------- (Please read the precautions on the back before filling out this page} 1220042 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Invent the (d /) line, and keep the cache line in the non-temporary cache memory 807. So :, the king jump source operand buffer n 815. Manned transport non-temporary non-temporary cache The arrival of the ground M 'Π in terms of non-temporary_reference' storage logic 81G first asks ^ Huai Tisi, to determine in the cache memory,-through the purpose = metabuffer ϋ _ the storage operand provided No—corresponds to whether the cache line is present and valid (ie, storage hit (ehit)). If yes, the storage operation P is performed non-temporarily according to the pre-4 memory characteristics. Meaning, if the cache line does not exist In the cache memory_ (ie, store miss), the storage logic 810 does not configure the cache memory to the cache line L and sends the storage operand to the composite write buffer 817. The contents of the composite writing punch, 817 are then directly written into the memory through the bus unit 808 to meet the specific processor (pr〇cess r_specific) Hierarchical memory attribute processing routines, which are related to the memory specificity of composite writers. In an X86 embodiment, the composite write attribute allows delaying memory write operations " ^ And merge without requiring coherency. The storage operand is therefore sent to memory in a non-transitory manner. [0059] Now refer to FIG. Only the command level replaces the non-temporary memory referenced instructions in the microprocessor, and the flow chart of the method for translating and executing is 900. The flow starts at block 902, and one of them is configured with extended feature instructions. The program is sent to the microprocessor. The flow then proceeds to block 904. [0060] In block 904, the next instruction is fetched from the cache memory / external memory. The flow then proceeds to decision block 9o. 6. I ^ I 1 II — — — — — — — — ^ -11111111 ^ (Please read the notes on the back before filling this page)

1220042 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of Invention (γ) [0061] In decision block 906, the next instruction extracted in block 904 is checked to determine whether it contains an invention The extended escape code. In a η86 embodiment, the edge check is used to extract the operation code value fi (ice BKPT). If the extended escape code is detected, the flow proceeds to block 908. If the extended escape code is not detected, the flow proceeds to block 9 丨 2. [0062] In block 908, the extended preamble portion of the extended instruction is decoded / translated to determine whether to apply a non-temporary access, which is designated to replace the fetched instruction in block 904 The default memory attributes referenced by the specified related memory. The process then proceeds to block 910. [0063] In block 910, the related memory refers to a non-temporary storage to fetch the designated element in an extension of a corresponding microinstruction sequence for configuration. The flow then proceeds to block 912. [0064] In block 912, all the rest of the instruction is decoded / translated to determine the specified memory reference, the location of the register operand, the memory address designator, and the instructions based on the existing microprocessor Set, the use of an existing architectural feature specified by the preamble. Flow then proceeds to block 914. [0065] In block 914, a microinstruction sequence is configured to specify the specified memory reference and its corresponding opcode extension. The flow then proceeds to block 916. [0066] In block 916, the microinstruction sequence is sent to a microinstruction queue for execution by the microprocessor. Flow then proceeds to block 918. [0067] In block 918, the microinstruction sequence is extracted by an address logic of the present invention. The address logic generates an address referenced by the memory, and sends the address to the extended execution logic. The flow then proceeds to block 92. 30, this paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm)-^-J --- Ί · --------------- Order ----- ---- (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ---------------- —_B7 V. Description of Invention (Eg) [0068] In block 920, the memory characteristic description X of the logical structure is extended to determine the preset memory characteristics. The process then proceeds to decision block 922. [0069] An evaluation is performed in decision block 922 to determine whether the microprocessor's cache / memory model does not allow the non-temporary access to replace the default attribute. If non-temporary access is allowed, the flow proceeds to decision block 926. If non-temporary access is not allowed ', the flow proceeds to block 924. [0070] In block 924, the memory access is performed by using the preset memory attributes determined in block 920. The flow then proceeds to block 932. [0071] An evaluation is performed in decision block 926 to determine whether a cache line corresponding to the specified memory reference exists in the cache memory and is valid. If yes, the flow proceeds to block 928. If a cache miss is generated, the flow proceeds to block 930. [0072] In block 928, because in the cache memory, a cache line corresponding to the memory reference exists and is valid, even if it is used for the preset memory attribute determined by block 92, via the cache memory Perform the memory access. The process then proceeds to block 932. [0073] In block 930, the memory reference is performed using a non-transitory tool (such as a non-transitory load buffer or / and a composite write buffer). Flow then proceeds to block 932. [0074] In block 932, the method is completed. [0075] Although the present invention and its objects, features, and advantages have been described in detail, other embodiments may also be included within the scope of the present invention. For example, the present invention has been applied to 31 paper rulers & Chinese National Standards (CNS) A4 specifications (21〇X 297 male f ----- (Please read the precautions on the back before filling out this page) IIII — — — — — — — — — — 1220042 A7 V. Description of the Invention (W) The following technology is used to describe: Use a single, unused opcode state in the instruction set structure that has been fully occupied as a mark to indicate the following extended features Preamble. However, the scope of the present invention is not limited in any aspect to the fully occupied instruction set architecture, or unused instructions, or a single tag. On the contrary, the present invention covers incompletely mapped instruction sets. , An embodiment that has used an operation code, and an embodiment that uses more than one instruction tag. For example, consider one; there is an instruction set architecture that does not use a different code state. A specific embodiment of the present invention includes selecting one as The state of the operation code of the escape mark, where the selection criteria are determined according to market factors. Another specific embodiment includes the use of a special combination of operation codes as marks, such as operations State 7FH appears continuously. Therefore, the essence of the present invention is to use a tag sequence, followed by an 11-bit extended preamble, which allows the programmer to specify the memory attributes of memory access at the instruction level. These attributes cannot be provided by the existing instructions of the microprocessor instruction set. Μ [0076] In addition, although the above uses the microprocessor as an example to explain the present invention and its objectives, features, and advantages, familiarize yourself with this. Those skilled in the art can still perceive that the scope of the present invention is not limited to the architecture of the microprocessor, but can cover all forms of programmable devices, such as signal processors, industrial controllers, array processors, and other similar devices. . In short, the above is only a preferred embodiment of the present invention, and the limitation of b, is the scope of implementation of the present invention. Any equal change and modification applied for patenting according to the present invention should still fall within the scope of the patent under this judgment. I ask your reviewing committee to make a clear note and pray for your approval. (Please read the notes on the back before filling out this page> -ϋ · ϋ ϋ «ϋ ϋ ϋ · ϋ ^ r <» J_ 1 «ϋ n n n ϋ I # Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

297 mm)

Claims (1)

122004μ ^ ¥ ΈΈ 丨 Zhou Nianyueyue said printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 Β8 C8 D8 6. Scope of Patent Application (Case No. 091212407 Patent Application Amendment (1) A device capable of performing instruction-level memory reference control in a microprocessor, including: a translation logic for translating an extended instruction into a micro instruction sequence, wherein the extended instruction includes: A code for referring to a memory designated by the extended instruction, specifying a non-temporary access, wherein the non-temporary access cannot be specified by an existing instruction of an existing instruction set; and A code mark is used to indicate the extended preamble, wherein the extended preamble mark is originally an operation code specified by another architecture in the existing instruction set; and an extended execution logic is coupled to the translation logic To receive the micro-instruction sequence and use non-temporary storage access to perform the memory reference. 2. The device as described in item 1 of the patent application scope, wherein the extended instruction further includes an instruction item of the existing instruction set. 3. The device described in item 2 of the scope of patent application, wherein the instruction item specifies an operation to be performed by the microprocessor, and wherein the operation includes the memory reference. 4. If you apply for the device described in Section 1 Gu, refer to the title including-loading operation,-storage operation, or both the loading operation and the storage operation 5. As described in item i of the scope of patent application A device, wherein the non-temporary access instructs the microprocessor to exclude a cache action of the butterfly data referenced by the recorder. 6. The device as described in item i of the scope of patent application, where the non-temporary access means (please read the precautions on the back before filling this page) f7; r I λ Patent application scope The microprocessor should not exclude the cache operation of the related loading data referenced by the memory, and keep the loading data in a non-temporary buffer. 7. The device as described in item 1 of the scope of patent application, wherein the non-temporary access instructs the microprocessor to exclude the cache action of the related stored data referenced by the memory and to have a composite write memory attribute A way to store references' execute the memory reference. 8. The device according to item 1 of the scope of patent application, wherein the extended preamble contains 8 bits. 9. The device according to item 1 of the scope of patent application, wherein the extended preamble includes: a source block to specify that the non-temporary access is to be applied to one of the load references specified by the extended instruction; And a purpose stop to specify that the non-temporary access is to be applied to a storage reference specified by the extended instruction. 10. The device as described in item 1 of the scope of patent application, wherein the existing instruction set includes a x86 instruction set. 11. The device as described in item 1 of the scope of the patent application, wherein the extended preamble flag includes an operation code FI (ICE BKBT) of the χ86 instruction set. 12. The device as described in item 1 of the scope of patent application, wherein the translation logic includes an escape instruction detection logic for detecting the extended preamble flag; an instruction decoding logic for determining the execution to be performed One operation, wherein the operation includes the memory reference; and an extended decoding logic, coupled to the escape instruction detection logic and the instruction, the paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) F Pack-(Please read the precautions on the back before filling out this page). Ordered by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the consumer consumer cooperatives, and applied for patent range decoding logic to determine I transfer temporary storage access. The non-temporary access is specified in the instruction sequence. 13 • Kinds of expansion-a microprocessor device that has an existing instruction set to provide instruction-level non-temporary memory access control, including ... an extended instruction configured to specify a non-temporary memory reference Take, where the extended instruction includes one of the selected opcodes of the existing instruction set, followed by the -η bit extended preamble, the selected opcode indicates the extended instruction, and the n-bit extended The preamble indicates the non-temporary access, in which the non-temporary access referenced by the memory cannot be specified according to the instructions of the existing instruction set; and the translation is configured to receive the extended instruction and generate a A microinstruction sequence to instruct a microprocessor to perform the memory reference through the non-transitory access. & 14. The microprocessor device according to item 3 of the patent application scope, wherein the extended instruction further includes: the remaining instruction items are configured to specify the memory reference, wherein the memory reference includes a load reference , A stored reference, or both the loaded reference and the stored reference. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs15. The microprocessor device described in item 14 of the scope of patent application, wherein the eta bit before the code contains: a first non-temporary designated field, configuration To indicate that the non-temporary access is to be applied to the loading reference; and a first non-temporary designation field, configured to indicate that the non-temporary access is to be applied to the storage reference. This paper size applies to Chinese National Standard (CNS) A4 specification (210 × 297 mm) 1220042, with the name 'ey,', and the scope of patent application 16. The microprocessor set as described in item 13 of the patent application park, its temporary The memory access instruction instructs the microprocessor to exclude the cache operation of the memory table. 17. According to the microprocessor device described in item 13 of the scope of the patent application, a temporary storage instruction is issued to instruct the microprocessor to exclude cached non-data related cache operations, and send the loaded data to Into a non-minor planting. Non-temporary buffer 18. According to the microprocessor device described in item 13 of the scope of the patent application, a temporary storage access is issued to instruct the microprocessor to exclude the phase referenced by the memory. 4 Non-data cache action, and A composite write access method blocks memory references. $ 仃 此 记 19. The microprocessor device described in item 13 of the scope of patent application, wherein the ^ -bit extended preamble includes 8 bits. Λ n 20. The microprocessor device according to item 13 of the scope of the patent application, wherein the existing instruction set is the x86 microprocessor instruction set. ^ 21. The microprocessor device as described in item μ of the patent application scope, wherein the selected operation code includes the ICE ΒΚΡΤ operation code (that is, operation code F1) of the χ86 microprocessor instruction set. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 22 · The microprocessing miscellaneous as described in item 13 of the application scope, the translator contains: ^ 之 -escaping instruction detector 'is used in the extension instruction The selection opcode;-^ Let's depress' to decode the rest of the extended instruction to determine the memory reference; and M's Zhang scale suitable financial home ^ X 297 public meal an extended preamble The solution "_ to the escape instruction generator and the instruction decoder" is used to exhaust the 0-bit extended preamble and specify the non-temporary access in the micro instruction sequence. 23 · -A kind of module that adds instruction-level non-temporary access control features to the existing instruction set, including ···,-the escape flag is received by -translation logic, and refers to the accompanying part of the corresponding instruction is specified -Memory reference, where the escape tag is one of the first opcodes in the existing instruction set;-non-temporary access designator '_ is connected to the escape tag, and it is the accompanying ^ Among them, the rib designation—non-temporary access should take into account the memory reference; and—extend the execution logic, input to the translation logic, and execute the memory reference by the non-temporary access. 24. The module described in item 23 of the scope of patent application, wherein 25 = contains-a second operation code for designating the module described in item 23 of the two r range, wherein the non-temporary access is only required. Contains 8 bits. The Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the module described in item 23 of the H range, among which the module of the existing instruction set 2m Lifanyuan Item 23, where the -op code 3x86 The ICE βκρτ opcode in the instruction set == the module described in the item, its' = will be translated into the corresponding microinstruction with the accompanying part, and the corresponding 4々can shows that the extended execution logic is through the non-temporary storage access Dimensions of this paper 剌 ^^^ 7 ^ 7210X2 ^) Patent application scope , Shen = _ as described in item 23 ^ Not far away || Caching action to exclude relevant information referenced by this memory 0 If the scope of the patent application is 23rd rhyme, the translation logic includes: An escape mark _Logic, rib_The escape note, and instructs that the translation action of the accompanying part should be based on extended translation conventions; and a decoding logic, coupled to the escape mark detection logic, based on the existing There is a conventional instruction set, and a translation operation of the instruction is performed, and a translation of the corresponding instruction is performed according to the extended translation routine, to indicate that the memory reference is to be performed by the non-temporary access. 31. A method for expanding an existing instruction set architecture to provide control of non-temporary memory references at the instruction level, the method comprising: providing an extension instruction, the extension instruction including an extension tag and an extension preamble , Where the extended tag is one of the first opcode items of the existing instruction set architecture; the extended prefix is used to specify a non-temporary access to be applied to a corresponding memory reference, where the memory reference is Specified by the rest of the extended instruction; and applying the non-temporary access to execute the memory reference, wherein the application action pre-empts caching of corresponding data of the memory reference. 32. The method described in item 31 of the scope of patent application, in which the designated action spoon 12200 is being replaced to buy 丨 A8 Β8 C8 D8 Printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The memory reference is specified in the rest of the extended instruction, wherein the first specified action includes using a second opcode item in the existing instruction set architecture. 33. The method as described in item 31 of the scope of patent application, wherein the action of providing an extension finger includes using an 8-bit item to configure the extension preamble. 34. The method according to item 31 of the scope of patent application, wherein the action of providing an extended instruction includes selecting the first operation code item from an x86 microprocessor instruction set architecture. 35. The method described in item 31 of the stated patent scope, wherein the action of providing an extended instruction includes selecting an x86 ICE BKPT operation code (that is, operation code F1) as the extension mark. 36. The method according to item 31 of the scope of patent application, further comprising: translating the extended instruction into a micro instruction sequence, the micro instruction sequence instructs an extended execution logic to execute the memory by the non-temporary access ^ reference. " 37. The method as described in item 36 of the scope of patent application, wherein the actions of the order include:% detecting the extension mark within a translation logic; and decoding the extension preamble and the extension according to the extension translation rule The rest of the instructions generate the microinstruction sequence. 38 = The method described in item 31 of the scope of patent application, where the specified action package paper size is suitable for financial transfer (CNS) A4 specification (2lQx297) (please read the precautions on the back before filling this page) 1T U 1220042 A8 B8 C8 D8 6. The scope of the patent application specifies that the non-temporary access should be applied to a source operand, a destination operand, or both. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210X297 mm)