CN1308813C - Control mechanism referenced by non-temporary memory - Google Patents

Abstract

The invention relates to a control device, structure and method of non-temporary memory parameters, which are used to expand a microprocessor instruction set to specify non-temporary memory parameters at the instruction level. The device includes a translation logic device and an extended execution logic device. The translation logic device translates an extended instruction into a microinstruction sequence. The extended instruction has an extended preamble and an extended preamble flag. The extended preamble specifies a non-temporal access operation to a memory parameter specified by the extended instruction, wherein the non-transitory access operation cannot be specified by an existing instruction of an existing instruction set. The extended preamble flag identifies the extended preamble, which is another structurally specified opcode in the existing instruction set. The extended execution logic device is coupled to the translation logic device for receiving the microinstruction sequence, and applying the non-temporary access operation to execute the operation indicated by the memory parameter.

Description

Device, structure and method for controlling non-temporary memory parameters

Comparison with Related Applications

(0001) This application claims priority to the following US application: Case No. 10/227583, filed August 22, 2002.

(0002) This invention is related to the following co-pending US patent applications, all having the same applicant and inventor. Taiwan application number filing date DOCKET NUMBER patent name 91116957 7/30/02 CNTR: 2176 Device and method for extending microprocessor instruction set 91116958 7/30/02 CNTR: 2186 Device and method for executing conditional instructions 91124008 10/18/02 CNTR: 2187 Apparatus and method for selectively controlling memory attributes 91116956 7/30/02 CNTR: 2188 Device and method for selectively controlling condition code write-back 91116959 7/30/02 CNTR: 2189 Structure to increase the number of registers in a microprocessor 91124005 10/18/02 CNTR: 2190 Apparatus and method for extending microprocessor data mode 91124006 10/18/02 CNTR: 2191 Device and method for extending microprocessor address mode CNTR: 2192 Prohibition of storage inspection CNTR: 2193 Disabling of Selective Interrupts 91116672 7/26/02 CNTR: 2198 Apparatus and method for selectively controlling result write-back

technical field

(0003) The present invention relates to the field of microelectronics, especially a technology capable of incorporating instruction-level non-temporal memory attribute control into an existing microprocessor instruction set architecture.

Background technique

(0004) Since the early 1970s, the use of microprocessors has grown exponentially. From its earliest applications in the fields of science and technology, to the consumer field that has now been introduced into business from those specialized fields, such as desktop and laptop (lapiop) computers, video game controllers, and many other common home and business devices and other products.

(0005) With the explosive growth in use, there has also been a corresponding improvement in technology, characterized by increasing requirements for the following items: faster speed, stronger addressability, faster Memory access, larger operands, more general-purpose types of operations (such as floating-point operations, single instruction multiple data (SIMD), conditional moves, etc.), and additional special-purpose operations (such as digital signal processing functions and other multimedia computing). This has resulted in amazing technological advances in the field, and has been applied to the design of microprocessors, such as extended pipelining (extensive pipelining), super-scalar architecture (super-scalar architecture), cache structure, out-of-order processing ( out-of-order processing), burst access structures, branch prediction, and speculative execution. In short, today's microprocessors are astonishingly complex and powerful compared to when they first appeared 30 years ago.

(0006) But unlike many other products, there is another very important factor that has limited and continues to limit the evolution of microprocessor architectures. Much of the complexity of today's microprocessors is due to this factor, legacy software compatibility. Under market considerations, many manufacturers choose to incorporate new architectural features into the latest microprocessor designs, but at the same time, in these latest products, they retain all the features required to ensure compatibility with older, so-called "legacy" microprocessors. "(legacy) capabilities required by the application.

(0007) Nowhere is this burden of legacy software compatibility more apparent than in the history of x86-compatible microprocessors. Everyone knows that today's 32/16-bit virtual-mode x86 microprocessors can still execute 8-bit real-mode applications written in the 1980s. Those skilled in the art also admit that there is a lot of related architectural "baggage" piled up in the x86 architecture just to support compatibility with legacy applications and operating modes. While in the past developers could add newly developed architectural features to existing instruction set architectures, today the tools to use these features, ie, programmable instructions, are relatively rare. More simply, he said, in some important instruction sets, there are no "redundant" instructions that allow designers to incorporate newer features into an existing architecture.

(0008) For example, in the x86 ISA, there is no undefined one-byte opcode state that is unused. In the main one-byte x86 opcode map, all 256 opcode states are already occupied by existing instructions. As a result, designers of x86 microprocessors must now choose between providing new features and preserving legacy software compatibility. To provide new programmable features, opcode states must be assigned to those features. If the existing ISA does not have redundant opcode states, some existing opcode states must be redefined to accommodate new features. Therefore, compatibility with older software has to be sacrificed in order to provide new features.

(0009) A current problem area of interest to microprocessor designers is how efficiently applications use cache structures. As caching technology has evolved, more and more features have been provided that allow system programmers to control when and how caches are used in a system. Early cache control features only provided on/off capability. By setting an internal register of the microprocessor, or by setting an external signal pin on its package (package) to true, the designer can set The caching of the memory is enabled, or the entire memory space is set as uncacheable. For non-cacheable memory references (ie load/read and store/write), they are all sent to the system memory bus, resulting in the same latency as the external bus architecture. Conversely, memory references or accesses to a cache are sent to the system only when a cache miss occurs (i.e., the target of a memory parameter is not valid within the internal cache). memory bus. The caching feature allows applications to run much faster, especially when the application repeatedly references the same data structures in memory.

(0010) Recent improvements in microprocessor architecture have given system designers more precise control over how cache features are used. These improvements allow the designer to set the address range for a segment of the address range in the address space of a microprocessor on how the microprocessor executes references to the address range according to the cache hierarchy. nature. In general, references to the address range can be made non-cacheable. Combined with write combining, write through, write back or write protected. These properties are called memory attributes (attributes), or memory characteristics (traits). Therefore, the storage parameter for the address with the write-back attribute will be sent to the cache, and speculatively assigned to the storage location therein. The storage parameter of another address with non-cacheable attribute is sent to the system bus and will not be speculatively executed.

(0011) However, it is outside the scope of this application to provide an in-depth description of memory attributes and how specific attributes are handled by a microprocessor with its caches. Going to understand that the art currently enables designers to assign a memory attribute to a memory region, and all subsequent memory parameters for addresses in the region will be based on the ccache policy associated with the specified memory attribute deal with it, that's enough.

(0012) While modern microprocessor designs allow different regions of memory to be assigned different memory characteristics, the design is still limited in two important respects. First, the microprocessor instruction set architecture restricts the execution of instructions for defining/changing memory characteristics to a privileged level inaccessible to user-level applications. Thus, when a desktop/laptop microprocessor is activated, its operating system establishes the memory characteristics of the virtual memory space before any user-level applications are started. Therefore, user-level applications cannot change the memory characteristics of the host system. Second, in modern microprocessors, the best processing level for establishing memory characteristics is the paging level. In a commonly used architecture that allows memory paging (memory paging), the memory attributes of each memory page are set by the operating system in the entry of the page directory/table (page directory/tabie). Thus, all references to addresses within a particular page will use the memory attribute assigned when the associated memory access operation was performed.

(0013) For many application programs, although the above-mentioned control features can significantly speed up the execution speed of user-level application programs, the inventor of the present case noticed that the effect is still limited for other application programs. This is not only because modern memory property control features cannot be applied at the user level, but also because memory properties can only be established in page-level units. For example, if a user program that repeatedly accesses a first data structure makes an occasional reference to a second data structure, if the cache entry of the first data structure must be cleared to free up the cache If the space is used by the second data structure, the execution efficiency of the user program will be affected accordingly. Because the operating system does not predict the reference frequency of the user-level application program to the data structure, the data space of the application program is generally given a write-back feature, thus contributing to the aforementioned conflict. Programmers do not have tools for changing data space properties to force the infrequent references to be forwarded to the memory bus (eg, assigning non-cacheable properties to the second data structure), while prohibiting the conflict.

(0014) In this technical field, the data repeatedly accessed by the application program is called temporary data, while the data accessed occasionally is called non-temporal data. Those skilled in the art will realize that it is very disadvantageous for a cache to be filled with non-temporal data (ie, cache pollution). As a result, recent technology has advanced to the existing instruction set by adding a limited set of non-temporary store instructions to allow application designers to move data from internal caches to memory without polluting the cache , however, there are currently no available tools that allow programmers to execute in a non-temporal fashion memory parameters specified by an existing instruction (for example, an instruction specifying an arithmetic or logical operation using one or more operands), thus Skip cache access entirely.

(0015) What is needed, therefore, is an apparatus and method for incorporating instruction-level non-transitory memory parameter control features into existing microprocessor instruction set architectures, where the instruction set architecture is a defined opcode Full occupancy and the inclusion of the memory parameter control feature allows a microprocessor that conforms to legacy specifications to retain the ability to execute legacy applications while also providing the ability for the programmer to specify non-transitory memory accesses.

Contents of the invention

(0016) The present invention, like other aforementioned applications, is to overcome the problems and shortcomings of the above-mentioned and other known technologies. The present invention provides a better technique for extending the instruction set of a microprocessor beyond its current capabilities to provide instruction-level control of non-temporary memory parameters. In a specific embodiment, a device capable of controlling memory parameters at instruction level in a microprocessor is provided. The device includes a translation logic device (translation logic) and an extended execution logic device (extended execution logic). The translation logic device translates an extended instruction into a microinstruction sequence. The extended command has an extended prefix and an extended prefix tag. The extended preamble specifies a non-temporal access operation for a memory parameter specified by the extended instruction, wherein the non-temporal access operation cannot be specified by an existing instruction of an existing instruction set. The extended preamble tag identifies the extended preamble, wherein the extended preamble tag is another structurally specified opcode in the existing instruction set. The extended execution logic device is coupled to the translation logic device for receiving the microinstruction sequence and applying the non-temporary access operation to execute the operation indicated by the memory parameter.

(0017) It is an object of the present invention to propose a microprocessor architecture that extends the existing instruction set to provide instruction-level non-transitory memory access control. The microprocessor architecture stores an extended instruction and has a translator. The extended instruction specifies a non-temporary access operation of a memory parameter. The extended instruction includes a selected operation code in the existing instruction set, followed by an n-bit extended preamble. The selected opcode identifies the extended instruction, and the n-bit extended preamble identifies the non-transitory access operation. The non-transitory access operation of the memory parameter cannot be specified in addition to the instructions of the existing instruction set. The translator receives the extended instruction and generates a microinstruction sequence to instruct the microprocessor to execute the operation indicated by the memory parameter through the non-temporary access operation.

(0018) Another object of the present invention is to provide an apparatus for adding an instruction-level non-temporary access operation control feature to an existing instruction set. The device includes a translation logic device that receives an escape tag that identifies an accompanying portion of a corresponding instruction specifying a memory parameter, wherein the escape tag is an existing instruction set a first operation code, and wherein a non-temporal access specifier (non-temporal access specifier) is coupled to the escape flag, and is one of the accompanying parts, designated for performing the operation indicated by the memory parameter a non-transitory access operation; and an extended execution logic device. . The extended execution logic device is coupled to the translation logic device, and executes the operation indicated by the memory parameter through the non-temporary access operation.

(0019) Another object of the present invention is to provide a method for extending the existing instruction set architecture to provide control of non-temporary memory parameters at the instruction level. The method includes providing an extension instruction, the extension instruction includes an extension flag and an extension preamble, wherein the extension flag is a first operation code of the existing instruction set architecture; the extension preamble is specified to be applied to a non-transitory access operation corresponding to a memory parameter, wherein the memory parameter is specified by the rest of the extension instruction; and applying the non-transitory access operation to execute the parameter indicated by the memory parameter, wherein the apply action prohibits The caching action of the relevant data of the memory parameter.

Description of drawings

(0020) the aforementioned and other objects of the present invention. The features and advantages can be better understood with the following explanations and attached icons:

(0021) Fig. 1 is a block diagram of the microprocessor instruction format of a related art;

(0022) Fig. 2 is a table, which describes the instructions in an instruction set architecture, how to correspond to the bit logic state of an 8-bit operation code byte in the instruction format of Fig. 1;

(0023) Fig. 3 is a block diagram of the extended instruction format of the present invention;

(0024) FIG. 4 is a table showing how the extended architecture features map to the logic states of the bits in an 8-bit extended preamble embodiment in accordance with the present invention;

(0025) FIG. 5 is a block diagram describing a pipelined microprocessor controlled by non-temporary memory parameters of the present invention;

(0026) FIG. 6 is a block diagram of a specific embodiment of the extended preamble used for specifying a non-temporary access operation of a programmed memory parameter in a microprocessor according to the present invention;

(0027) Fig. 7 is the concrete block diagram of translation stage logic device in Fig. 5 microprocessor;

(0028) Fig. 8 is a block diagram of the extended execution stage logic device in the microprocessor of Fig. 5; and

(0029) FIG. 9 is a flowchart describing the operation of the method of the present invention for controlling non-transitory memory parameters in a microprocessor.

Icon description:

100 Instruction Format 101 Preamble

102 operation code 103 address designation code

2008-bit opcode diagram 201 opcode value

202 operation code F1H

300 extended instruction format 301 prefix

302 operation code 303 address designation code

304 Extended Instruction Mark

4008-bit preamble 401 architecture features

500 pipelined microprocessor 501 extraction logic device

502 instruction cache external memory

503 instruction queue 504 translation logic device

505 extended translation logic device 506 microinstruction queue

507 Execution logic device 508 Extended execution logic device

600 Extended Preamble 601 Source Field

602 purpose field 603 spare field

700 Translation stage logic device 701 Activation state signal

702 Machine specific register 703 Extended feature field

704 instruction buffer 705 translation logic device

706 translation controller 707 disable signal

708 Escaped Instruction Detector 709 Extended Preamble Decoder

710 Instruction Decoder 711 Control ROM

712 Microinstruction buffer 713 Operation code extension field

714 Micro operation code field 715 Purpose field

716 source field 717 displacement field

800 Extended Execution Stage Logic Device 801 Microinstruction Buffer

802 address buffer 803 address buffer

804 purpose operand buffer 805 extended access logic device

806 Memory Characteristic Descriptor 807 Cache

808 bus unit 809 access controller

810 store logic device 811 load logic device

812 bus 813 bus

814 extended micro instruction buffer 815 source operand buffer

816 non-temporary loading buffer 817 combined buffer with write function

900-932 Operation flow of the method for controlling non-temporary memory parameters in a microprocessor

Detailed ways

(0030) The following description is provided in the context of a specific embodiment and its prerequisites to enable those of ordinary skill in the art to utilize the present invention. However, various modifications to this preferred embodiment will be apparent to those skilled in the art, and the general principles discussed herein can be applied to other embodiments as well. Therefore, the present invention is not limited to the specific embodiments shown and described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

(0031) The previous article has discussed the background of how to expand its architectural features in today's microprocessors to exceed the capabilities of related instruction sets. In view of this, in FIG. 1 and FIG. 2 , an example of the related art will be discussed. The discussion here highlights the constant dilemma that microprocessor designers face when, on the one hand, they want to incorporate newly developed architectural features into their microprocessor designs, but on the other hand, they want to retain the implementation of application capabilities. In the example of Figures 1-2, a fully occupied opcode map has prohibited the possibility of adding new opcodes to the example architecture, thus forcing the designer to either choose to incorporate new features at the expense of some degree of Legacy software compatibility, or abandon the latest developments in the architecture, in order to maintain the compatibility of the microprocessor with legacy applications. Following the discussion of the related art, in Figures 3 through 9, a discussion of the present invention will be provided. By utilizing an existing but unused opcode as a preamble tag for an extended instruction, the present invention allows microprocessor designers to overcome the limitations of fully-used instruction set architectures, in addition to providing programmers with the ability to specify an The ability for non-temporal memory access of specific memory parameters while also retaining all the features required to execute legacy applications.

(0032) Please refer to FIG. 1, which is a block diagram of a related art microprocessor instruction format 100. The instruction 100 of the related art has a variable number of data items 101-103, each of which is set to a specific value, and together constitutes a specific instruction 100 of the microprocessor. The specific instruction 100 instructs the microprocessor to perform a specific operation, such as adding two operands, or moving an operand from memory to an internal register, or from the internal register to memory. In general, the operation code item 102 in the instruction 100 specifies the specific operation to be performed, and the optional (optional) address specification code item 103 is located after the operation code 102 to specify additional information about the specific operation, such as how to The operation is performed, where are the operands located, etc. The instruction format 100 also allows the programmer to add a preamble item 101 before an opcode 102 . When the specific operation specified by the operation code 102 is executed, the preamble 101 is used to indicate whether to use a specific architectural feature. In general, these architectural features apply to most of the operations specified by any opcode 102 in the instruction set. For example, preamble 101 exists today in some microprocessors that can perform operations using virtual addresses of different sizes (eg, 8-bit, 16-bit, 32-bit). And when many of these processors are programmed to a preset address size (such as 32 bits), the precode 101 provided in their individual instruction sets still enables programmers to selectively replace (override) the preset address size (for example, to generate a 16-bit virtual address). The selectable address size is just one example of an architectural feature that, in many modern microprocessors, can be applied to numerous operations (such as addition, subtraction, multiplication, Boolean logic, etc.) that can be specified by opcodes 102 .

(0033) The instruction format 100 shown in FIG. 1 has a well-known example in the industry, the x86 instruction format 100, which is adopted by all modern x86-compatible microprocessors. More specifically, he said that the x86 instruction format 100 (also known as the x86 instruction set architecture 100 ) uses an 8-bit preamble 101 , an 8-bit operation code 102 and an 8-bit address specification code 103 . The x86 architecture 100 also has several precodes 101, two of which replace the default address/data size of the x86 microprocessor (ie, opcode states 66H and 67H), and the other instructs the microprocessor to follow a different translation rule to interpret the subsequent operation code byte 102 (that is, the preamble value 0FH, which makes the translation action be performed according to the so-called two-byte operation code rule), and the other preamble code 101 makes the special operation repeated , until the repetition condition is satisfied (that is, the REP operation code: F0H, F2H and F3H).

(0034) Please refer to FIG. 2, which shows a table 200 for describing how an instruction 201 of an instruction set architecture corresponds to a bit value of an 8-bit opcode byte 102 in the instruction format of FIG. 1 . Table 200 presents an example of an 8-bit opcode map 200 that associates up to 256 values of an 8-bit opcode entry 102 to corresponding microprocessor opcode instructions 201 . The table 200 maps a specific value of the operation code item 102, such as 02H, to a corresponding operation code instruction 201 (ie, instruction I02 201). In the example of the x86 opcode diagram, it is well known to those skilled in the art that the opcode value 14H is mapped to the x86 Add With Carry (ADC) instruction, which converts an 8-bit immediate ) operand is added to the content of the architectural register AL. Those skilled in the art will also find that the x86 preamble 101 mentioned above (ie, 66H, 67H, 0FH, F0H, F2H, and F3H) is the actual opcode value 201, which, in a different context, specifies the desired The particular architectural extension term is applied to the operation specified by the opcode term 102 that follows. For example, adding the preamble 0FH before the operation code 14H (normally, it is the aforementioned ADC operation code) will cause the x86 processor to perform an "unpack and insert low-compression single-precision floating-point value" (Unpack and Interleave Low PackedSingle-precision Floating-Point Values) operation, not the original ADC operation. Features such as those described for the x86 example are partially enabled in modern microprocessors because instruction translation/decoding logic within the microprocessor interprets the items 101-103 of an instruction 100 in sequence. So in the past, using a specific opcode value as the preamble 101 in the instruction set architecture allowed microprocessor designers to incorporate many advanced architectural features into the design of a microprocessor compatible with legacy software without A negative impact on the execution of legacy programs that do not use those particular opcode states. For example, an old program that never used the x86 opcode 0FH can still execute on today's x86 microprocessors. And a newer application, by using the x86 opcode 0FH as the prefix 101, can use many newly incorporated x86 architecture features, such as single instruction multiple data (SIMD) operations, conditional move operations, and so on.

(0035) Although architectural features have been provided in the past by designating available/redundant opcode values 201 as preambles 101 (also known as architectural signatures/pointers 101 or escaped instructions 101), many instruction set architectures 100 in Providing functional enhancements is still hindered for a very straightforward reason: all available/redundant opcode values have been used up, i.e. all opcode values in opcode map 200 have been constructed specified. When all available values are assigned as opcode entry 102 or preamble entry 101, there are no remaining opcode values available for incorporating new features. This serious problem exists in many microprocessor architectures today, forcing designers to choose between adding architectural features and retaining compatibility with legacy programs.

(0036) It is worth noting that the instruction 201 shown in FIG. 2 is expressed in a general way (ie I24, I86), rather than specifically referring to actual operations (add carry accumulation, subtraction, XOR). This is because, in some different microprocessor architectures, the fully occupied opcode graph 200 has architecturally prohibited the possibility of incorporating newer advances. Although the example of FIG. 2 refers to an 8-bit opcode entry 102, those skilled in the art will recognize that the specific size of the opcode 102 results from the fully occupied opcode structure 200 being discussed except as a special case. In addition to the problem, other aspects are irrelevant to the problem itself. Thus, a fully occupied 6-bit opcode map would have 64 architecturally assignable opcodes/preambles 201 and would not provide usable/redundant opcode values for expansion.

(0037) Another alternative method is not to completely abolish the original instruction set, and replace it with a new format 100 and operation code map 200, but only for a part of the existing operation code 201, use the new instruction Means substitution, as shown in operation codes 40H to 4FH in Figure 2 . With this hybrid technique, the microprocessor can operate individually in one of two modes: the old mode, using opcodes 40H-4FH, which are still interpreted by the rules, or in another modified mode ( enhanced mode), at this time, the operation codes 40H-4FH are interpreted according to the enhanced architectural rules. This technology does allow designers to incorporate new features into their designs, however, when a microprocessor conforming to the legacy specification is run in enhanced mode, the disadvantage still exists because the microprocessor cannot execute any application using opcodes 40H-4FH program. Therefore, from the standpoint of retaining the compatibility of old software, it is still unacceptable to be compatible with old software/enhanced technology.

(0038) However, the inventors have noted the use of opcode 201 in the case of instruction set 200 where the opcode space is fully occupied and that space covers all applications executing on microprocessors conforming to legacy specifications. situation, and it is also observed that, although some instructions 202 are architecturally specified, they are not used in applications executable by the microprocessor. The instruction IF1 202 shown in FIG. 2 is an example of this phenomenon. In fact, the same opcode value 202 (ie, F1H) is mapped to an effective instruction 202 that is not used in the x86 instruction set architecture. Although the unused x86 instruction 202 is a valid x86 instruction 202 that instructs an architecturally specified operation to be performed on an x86 microprocessor, it is not used in any operation that can be performed on a modern x86 microprocessor. application. This special x86 instruction 202 is called In Circuit Emulation Breakpoint (also known as ICE BKPT, the operation code value is F1H), and was previously used exclusively for a now defunct microprocessor emulation in the device. ICE BKPT 202 has never been used in applications other than in-circuit simulators, and previous in-circuit simulation devices that used ICE BKPT 202 no longer exist. Thus, in the case of x86, the present inventors have discovered a tool within a fully occupied instruction set architecture 200, utilizing an efficient but unused opcode 202, to allow the incorporation of advanced architectures in the design of microprocessors features without sacrificing legacy software compatibility. In a fully occupied instruction set architecture 200, the present invention utilizes an architecturally specified but unused opcode 202 as a pointer marker to identify a subsequent n-bit preamble, thus allowing the microprocessor Designers can incorporate up to ²ⁿ of the latest developments in architectural features into microprocessor designs while retaining full compatibility with all legacy software.

(0039) The present invention specifies the code preamble by providing an n-bit extended non-temporary access operation, so as to use the concept of the preamble mark/extended preamble, thereby allowing the programmer to, in a microprocessor, according to Each instruction specifies a non-transitory memory access to a corresponding memory argument operation. When the corresponding memory parameter operation is performed, the non-transitory memory access is used in place of a cache-based access according to a predetermined attribute determined by the operating system program specified by a previously built Memory Characteristic Descriptor table/structure. The present invention will now be discussed with reference to FIGS. 3 to 9 .

(0040) Referring now to FIG. 3, it is a block diagram of an extended instruction format 300 of the present invention that is very similar to the format 100 discussed in FIG. An item is set to a specific value, and collectively constitutes a specific instruction 300 of the microprocessor. The specific instruction 300 instructs the microprocessor to perform a specific operation, such as adding two operands, or moving an operand from memory to a register of the microprocessor. Generally speaking, the operation code item 302 of the instruction 300 specifies the specific operation to be performed, and the optional address specification code item 303 is placed after the operation code 302 to specify additional information related to the specific operation, such as how to perform the operation , the buffer where the operand is located, the direct and indirect data used to calculate the memory address of the source/result operand, and so on. The instruction format 300 also allows the programmer to prefix an opcode 302 with a prefix item 301 . When the specific operation specified by the opcode 302 is executed, the preamble item 301 is used to indicate whether to use the existing architectural features.

(0041) However, the extended instruction 300 of the present invention is a superset (superset) of the aforementioned instruction format 100 in FIG. before all remaining items 301-303 in the extension instruction 300. These two additional items 304 and 305 allow the programmer to specify a non-temporal memory access for the memory parameter specified by the extension instruction 300, wherein the non-temporal memory access corresponding to the memory parameter cannot otherwise be determined by conforming to the old Specified microprocessor's existing instruction set to be specified. Optional items 304 and 305 are an extended command flag 304 and an extended non-temporary designation code prefix 305 . The extended instruction flag 304 is another architecturally specified opcode within a microprocessor instruction set. In an x86 embodiment, the extended instruction flag 304, or escape flag 304, is in opcode state F1H, which is the ICE BKPT instruction used earlier. The escape flag 304 identifies to the microprocessor logic device that the extended preamble 305, or the extended feature designation code 305, is to follow, wherein the extended preamble 305 specifies a value corresponding to a specified memory parameter (i.e. A non-temporal access operation of a load operation, a store operation, or both). In one embodiment, the escape flag 304 identifies that the accompanying portions 301-303 and 305 of a corresponding extension instruction 300 specify memory parameters to be executed by the microprocessor. The non-temporary access operation specifying code 305, or the extension prefix 305, specifies that the non-temporary access operation needs to be performed in a source operand load operation, a destination operand store operation, or both. The extended execution logic device in the microprocessor performs the operation indicated by the memory parameter by performing the non-temporary memory access, replacing the cacheable default memory attribute originally specified by other means . These other approaches include the use of control register bits, memory type registers, page tables, and other types of memory attribute descriptors that are present in modern microprocessor architectures.

(0042) The non-temporary reference control technology of the present invention is summarized here. An extension instruction is used to specify a non-transitory memory access to a memory parameter of an existing microprocessor instruction set; wherein the non-transitory access operation of the memory parameter cannot be performed by another instruction of the existing microprocessor instruction set be specified. The extended instruction includes one of the opcode/instruction 304 of the existing instruction set and an n-bit extended preamble 305 . The selected opcode/instruction acts as a pointer 304 to identify that the instruction 300 is an extended feature instruction 300 (i.e., it specifies extensions to the microprocessor architecture), and the n-bit feature preamble 305 is Identifies whether the non-transitory access operation is applied to a source operand, a destination operand, or both. In one embodiment, the extended preamble 305 has a size of eight bits, and can specify a combination of the non-temporary access operation control feature and other extended features at most. In the embodiment of the n-bit preamble, in addition to the non-temporary access operation control feature, other 2n ^-2 extended features can be specified at most.

(0043) Referring now to FIG. 4, a table 400 shows how the non-temporary access operation control characteristics of a given memory parameter map to the bit logic states of an 8-bit extended preamble embodiment according to the present invention. Similar to the opcode map 200 discussed in FIG. 2, the table 400 of FIG. Corresponding extended features 401 (such as E34, E4D, etc.) of a microprocessor conforming to the old specifications, two of which indicate non-temporary access operations. In an x86 embodiment, the 8-bit extended feature preamble 305 of the present invention is used to provide instruction level control of non-transitory memory accesses 401 (i.e., E00-EFF), which memory features 401 are currently The x86 instruction set architecture is not specified at the instruction level.

(0044) The extended feature 401 shown in FIG. 4 is expressed in a general manner, rather than specifically referring to actual features. This solidifies that the technology of the present invention can be applied to various architectural extensions 401 and specific instruction sets. architecture. Those skilled in the art will recognize that many different architectural features 401, some of which were mentioned above, can be incorporated into an existing instruction according to the escape marker 304/extended preamble 305 technique described herein. set. 4, the 8-bit preamble embodiment provides a maximum of 256 different features 401, while an n-bit preamble embodiment has a programmed selection of up to ²ⁿ different features 401.

(0045) Please refer to FIG. 5, which is a block diagram illustrating a pipelined microprocessor 500 for performing non-temporary memory parameter operations according to the present invention. Microprocessor 500 has three distinct phase types: fetch, translate, and execute. The fetch stage has a fetch logic 501 that can fetch instructions from an instruction cache 502 or external memory 502 . The fetched instructions are sent to the translation stage via the instruction queue 503 . The translation stage has translation logic 504 coupled to a microinstruction queue 506 . Translation logic 504 includes extended translation logic 505 . The execution phase has an execution logic device 507 with an extended execution logic device 508 therein.

(0046) According to the present invention, during operation, the fetch logic device 501 fetches formatted instructions from the instruction cache/external memory 502 and puts these instructions into the instruction queue 503 according to their execution order. These instructions are then extracted from the instruction queue 503 and sent to the translation logic device 504 . The translation logic device 504 translates/decodes each incoming instruction into a corresponding microinstruction sequence to instruct the microprocessor 500 to perform operations specified by these instructions. According to the present invention, the extended translation logic device 505 detects those instructions marked with the extended preamble to perform translation/decoding corresponding to the extended non-temporary memory parameter specification code preamble. In an x86 embodiment, the extended translation logic device 505 is used to detect the extended preamble flag whose value is F1H, which is the ICE BKPT opcode of x86. A microinstruction field is provided in the microinstruction queue 506 to allow specifying the source/destination non-transitory access operations of the associated memory parameters specified by the accompanying portion of the instruction.

(0047) The microinstruction is sent from the microinstruction queue 506 to the execution logic device 507, wherein the expansion execution logic device 508 is used to execute a specified memory parameter according to a preset memory characteristic (defined by the existing memory characteristic descriptor means), Or for performing a non-transitory memory access programmed at the user level by the extended preamble of the present invention, as specified by the extended microinstruction field, overriding the default memory characteristics and skipping the cache entirely. In one embodiment, non-transitory store operations are handled in the same manner as store operations using address ranges with attributes associated with write functionality.

(0048) Those skilled in the art will recognize that the microprocessor 500 shown in FIG. 5 is a simplified result of the modern pipelined microprocessor 50 . In fact, a modern pipelined microprocessor 500 may include up to 20 to 30 different pipeline stages. However, these stages can be broadly categorized into three stages shown in the block diagram. Therefore, the block diagram 500 of FIG. 5 can be used to point out the necessary components required by the foregoing embodiments of the present invention. For the sake of clarity, unrelated components of microprocessor 500 are not shown.

(0049) Please refer to FIG. 6 , which is a block diagram of an embodiment of an extended preamble 600 for specifying a non-temporary access operation of a programmed memory parameter in a microprocessor according to the present invention. The non-temporary access operation specific code preamble 600 has a size of 8 bits and includes a source field 601 , a destination field 602 and a spare field 603 . The source field 601 specifies that a non-temporal access operation is to be applied to the source operand memory access (i.e., load, read) specified by the remainder of an associated extension instruction, while the destination field 602 specifies a non-temporal access operation To be applied to the destination operand memory access (ie store, write) specified by the remainder. Those skilled in the art will recognize that the source and destination non-transitory access operations can be specified separately, which is particularly useful in conjunction with repeating string instructions such as REP MOVS on the x86 architecture.

(0050) Please refer to FIG. 7 , which is a specific block diagram of the logic device 700 of the translation stage in the microprocessor of FIG. 5 . The translation stage logic device 700 has an instruction buffer 704 that provides extended instructions to the translation logic device 705 in accordance with the present invention. The translation logic 705 is coupled to a machine specific register 702 having an extended feature field 703 . The translation logic device 705 has a translation controller 706 that provides a disable signal 707 to an escape command detector 708 and an extension decoder 709 . The escape instruction detector 708 is coupled to the extension decoder 709 and an instruction decoder 710 . The extension decoder 709 and the instruction decoding logic device 710 access a control read-only memory (ROM) 711, which stores template microinstruction sequences corresponding to certain extension instructions, and the translation logic device 705 also includes a microinstruction The instruction buffer 712 has an opcode extension field 713 , a micro opcode field 714 , a destination field 715 , a source field 716 and a displacement field 717 .

(0051) In operation, during power-up of the microprocessor, the state of the extension field 703 in the machine-specific register 702 is determined by the signal power-up state 701 to identify whether the particular microprocessor is Extended instructions for implementing instruction-level non-temporary memory parameters capable of translating and executing the present invention. In one embodiment, signal 701 is derived from a feature control register (not shown) that reads a fuse array (fuse array) (not shown) configured at the time of manufacture. ). The machine specific register 702 sends the status of the extended features field 703 to the translation controller 706 . The translation control logic device 706 controls the instructions extracted from the instruction buffer 704 to be interpreted according to the extended translation rules or common translation rules. Providing such a control feature may allow a supervisory application (eg, BIOS) to enable/disable the extended execution features of the microprocessor. If extended features are disabled, instructions with opcode states selected as extended feature flags will be translated according to common translation rules. In a specific embodiment of x86, if the operation code state F1H is selected as a flag, under common translation rules, encountering F1H will cause an illegal instruction exception (exception). If extended translation is disabled, instruction decoder 710 will translate/decode all incoming instructions and configure all fields 713 to 717 of microinstruction 712 . However, under extended translation rules, if a token is encountered, it will be detected by the escaped instruction detector 708 . The escaped instruction detector 708 will instruct the extended preamble decoder 709 to translate/decode the extended preamble part of the extended instruction according to the extended translation rules, and configure the operation code extension field 713 to indicate the Non-temporary memory accesses are to be applied to the memory parameters specified by the rest of the extended instruction. The instruction decoder 710 will decode/translate the rest of the extended instruction and configure the micro-opcode field 714 , source field 716 , destination field 715 and displacement field 717 of the microinstruction 712 . Certain specific instructions will result in access to the control ROM 711 to obtain the corresponding microinstruction sequence template. The configured microinstructions 712 are sent to a microinstruction queue (not shown in the figure) for subsequent execution by the processor.

(0052) Please refer to FIG. 8 , which is a block diagram of an extended execution stage logic device 800 in the microprocessor of FIG. 5 . The extended runtime logic device 800 has an extended access logic device (extended access logic) 805, which is coupled to a cache memory 807 and a bus unit 808 via buses 812 and 813, respectively. The bus unit 808 is used to direct memory transactions on a memory bus (not shown). According to the present invention, the extended access logic device 805 receives microinstructions from an extended microinstruction buffer 801 in the previous stage of the microprocessor, receives two address operands from address buffers 802 and 803, and receives two address operands from the destination operand buffer. 804 receives a destination operand. The extended access logic device 805 is also coupled to a number of memory property descriptors 806 configured according to the architectural protocol of the host microprocessor. The extended access logic device 805 includes an access controller 809 , a store logic device 810 and a load logic device 811 . The load logic device 811 includes a non-transitory load buffer 816 and outputs a source operand to a source operand buffer 815 . The storage logic device 810 has a buffer 817 combined with a write function.

(0053) In operation, the extended execution logic device 800 performs memory access, reads operands from the memory, and writes operands to the memory according to instructions of the microinstructions in the extended microinstruction buffer 801 . When performing a load/load operation, the access controller 809 receives one or more memory addresses from the address buffers 802 and 803, and reads the memory property descriptor 806 to determine memory properties associated with the load operation, in a In an x86 embodiment, the memory characteristic descriptor 806 includes an x86 cache and paging control register, a paging directory and a paging table entry, a memory type range register (memory toe range register, MTTR), and a paging attribute table (paging attribute table, PAT ) and external signal pins KEN#, WB/WT#, PCT and PWT. The access controller 809 uses the information obtained from these sources 806 to determine the default memory attributes for the load operation according to the x86 hierarchical memory attribute protocol. For non-x86 embodiments, the access controller 809 uses information obtained from the memory property descriptor 806 to determine the default memory for the load operation according to the hierarchical memory attribute protocol corresponding to the specific architecture of the host microprocessor. Attributes. The memory address, along with its corresponding access attribute, is sent to load logic 811 . Load logic 811 obtains source operands from cache memory via bus 812 or directly from system memory (not shown) via bus unit 808, depending on the provided property attributes. The obtained source operands are sent to the source operand buffer 815 synchronously with a pipeline clock signal (not shown), and the extended microinstructions are also sent into the pipeline to the extended microinstruction register 814 synchronously with the pipeline clock signal. In this way the source operand is sent to the next stage of the microprocessor.

(0054) When executing the write/store operation indicated by the extended microinstruction, the access controller 809 receives the address data of the operation from the address buffers 802 and 803, and receives the operand to be stored from the buffer 804. The access controller 809 accesses the memory property descriptor 806 as described above to determine the memory property corresponding to the storage access operation. The memory characteristics. The address data and the destination operand are sent to the storage logic device 810 . Depending on the specific attributes provided, storage logic device 810 writes the destination operand into cache 807 via bus 812 , or directly into system memory via bus unit 808 .

(0055) The storage logic device 810 and the load logic device 811 of the present invention are used to perform storage and load reference operations according to the relevant processing requirements of the memory attribute model of the host processor, wherein the processing requirements include strong/weak sorting Protocols (such as hypothetical execution rules) and cache access principles. In one embodiment, the load and store operations are performed in separate pipeline stages of the host microprocessor.

(0056) For extension instructions using non-temporary memory parameter preambles, the non-temporal operand specification code for the associated memory parameter (i.e. load. store or both load and store) is passed through the extended The opcode extension field (not shown) of the microinstruction is sent to the access controller 809 . The access controller 809, as described above, uses the information obtained from the memory property descriptor 806 to determine the default memory characteristics for the specified memory access. If the corresponding default feature allows non-temporary access operations (i.e. fast-fetching features, such as write-back features), the access controller 809 sends the non-temporary designation code together with the aforementioned address and/or destination operand to To store logic device 810/load logic device 811. If the corresponding default characteristic does not allow non-temporary access operations (i.e., non-cacheable characteristics), the access controller 809 sends the default characteristic together with the address and/or destination operand to the storage logic device 810/ The logic device 811 is loaded.

(0057) If the corresponding default feature allows non-temporary access operations, then with respect to non-temporary load parameters, the load logic device 811 first inquires the cache 807 through the bus 812 to determine in the cache 807, a corresponding Whether the load operand exists and is valid (i.e. load hit). If yes, the load operation is executed according to the default memory characteristic. However, if the corresponding load operand does not exist in cache 807, then load logic 811 fetches the cache line containing the load operand from memory via bus unit 808 and keeps the cache line in a non-temporary cache cache 816, thus skipping cache 807 entirely. Thus, the load operand is sent to the source operand buffer 815 non-temporarily.

(0058) For non-temporary storage parameters, storage logic device 810 first queries cache 807 to determine whether a corresponding cache line for a storage operand provided by destination operand buffer 804 is present in cache 807 exists and is valid (i.e. store hit). If yes, the storage operation is performed according to the default memory characteristics instead of non-temporarily. However, if the cache line does not exist in the cache 807 (i.e. a store miss), then the storage logic device 810 does not allocate the cache 807 space to the cache line, but the store operation The data is sent to the buffer 817 which incorporates a write function. The contents of the write-incorporated buffer 817 are then directly written into memory via the bus unit 808 to conform to the processor-specific level memory attribute processing protocol applied to the write-incorporated memory characteristics. In an x86 embodiment, the write-incorporated attribute allows memory write operations to be delayed and coalesced without requiring coherency. Store operands are thus sent to memory in a non-transitory manner.

(0059) Please refer to FIG. 9 , which is a flow chart 900 describing the operation of the method for translating and executing instructions that enable programmers to replace non-temporary memory parameters in the microprocessor at the instruction level. The flow begins at block 902, where a program configured with extended feature instructions is sent to the microprocessor. The flow then proceeds to block 904 .

(0060) In block 904, the next instruction is fetched from cache/external memory. The flow then proceeds to decision block 906 .

(0061) In decision block 906, check the next command extracted in block 904 to determine whether it includes an extended escape code of the present invention. In an x86 embodiment, the check is to detect opcode value F1(ICE BKPT). If the extended escape code is detected, the flow proceeds to block 908 . If the extended escape code is not detected, the flow proceeds to block 912 .

(0062) In block 908, decode/translate the extended preamble portion of the extended instruction to determine whether to apply a non-temporal access operation designated to replace the fetched instruction at block 904 Default memory attribute for the specified associated memory parameter. Flow then proceeds to block 910 .

(0063) In block 910, a non-temporary access operation designation code of the relevant memory parameter is configured in an extension field of a corresponding microinstruction sequence. Flow then proceeds to block 912 .

(0064) In block 912, all remaining parts of the instruction are decoded/translated to determine the specified memory parameters, register operand locations, memory address specification codes and according to the existing microprocessor instruction set, Use of existing architectural features specified by prefixes. Flow then proceeds to block 914 .

(0065) In block 914, a microinstruction sequence is used to specify the specified memory parameter and its corresponding opcode extension. Flow then proceeds to block 916 .

(0066) In block 916, the microinstruction sequence is sent to a microinstruction queue for execution by the microprocessor. Flow then proceeds to block 918 .

(0067) In block 918, the microinstruction sequence is fetched by an address logic device of the present invention. The address logic device generates the address of the memory parameter and sends the address to the extended execution logic device. The flow then proceeds to block 920 .

(0068) In block 920, the extended execution logic device uses the memory characterization tool of the microprocessor architecture to determine a predetermined memory characteristic. The flow then proceeds to decision block 922 .

(0069) An evaluation is performed in decision block 922 to determine whether the cache/memory model of the microprocessor architecture allows the non-temporal access operation to override the default attribute. If the non-temporary access operation is allowed, the flow proceeds to decision block 926 . If the non-temporary access operation is not allowed, the process proceeds to block 924 .

(0070) In block 924, the memory access is performed using the default memory attributes determined in block 920. Flow then proceeds to block 932 .

(0071) An evaluation is performed in decision block 926 to determine whether the cache line corresponding to the specified memory parameter exists and is valid in the cache. If so, the process proceeds to block 928 . If a cache miss occurs, the process proceeds to block 930 .

(0072) In block 928, since the cache line corresponding to the memory parameter exists and is valid in the cache, ie, for the default memory attribute determined in block 920, the memory access is performed via the cache. Flow then proceeds to block 932 .

(0073) In block 930, perform the operation indicated by the memory parameter using a non-temporal tool (such as a non-temporal load buffer or/and a buffer combined with a write function). Flow then proceeds to block 932 .

(0074) In block 932, the method is complete.

(0075) Although the present invention and its objects, features and advantages have been described in detail, other embodiments may also be included within the scope of the present invention. For example, the present invention has been described with respect to the technique of using a single, unused opcode state within a fully occupied instruction set architecture as a flag to identify a subsequent extended feature preamble. However, the scope of the present invention is not limited in any respect to a fully occupied ISA, or unused instructions, or a single flag. Rather, the invention covers instruction sets that are not fully mapped, embodiments with used opcodes, and embodiments that use more than one instruction flag. For example, consider an ISA without unused opcode states. An embodiment of the present invention includes selecting an opcode state as an escape flag, wherein the selection criteria are determined by market factors. Another embodiment includes using a particular combination of opcodes as a marker, such as successive occurrences of opcode state 7FH. Therefore, the essence of the present invention is that the use of a flag sequence followed by an n-bit extended preamble allows the programmer to specify at the instruction level memory attributes for memory accesses that cannot otherwise be determined by the microprocessor. Existing instructions of the processor instruction set are provided.

(0076) In addition, although the above uses the microprocessor as an example to illustrate the present invention and its purpose, features and advantages, those skilled in the art can still understand that the scope of the present invention is not limited to the architecture of the microprocessor, but Can cover all forms of programmable devices, such as signal processors, industrial controllers (industrial controllers), array processors and other similar devices.

In a word, the above descriptions are only preferred embodiments of the present invention, and should not be used to limit the implementation scope of the present invention. All equivalent changes and modifications made according to the claims of the present invention should still fall within the scope covered by the patent of the present invention.

Claims (25)

1. the device of the memory references control that can instruct level in a microprocessor is characterized in that, comprising:

One translation logic device, in order to an extended instruction is translated into a microinstruction sequence, wherein this extended instruction comprises:

One expansion preamble in order to the specified memory references of this extended instruction, is specified a non-interim accessing operation, and wherein this non-interim accessing operation can not be with existing an appointment of an existing instruction set; And

One expansion preamble mark, in order to identify this expansion preamble, wherein this expansion preamble mark is the former operation code that should have appointment on interior another structure of instruction set; And

One expansion actuating logic device is coupled to this translation logic device, in order to receiving this microinstruction sequence, and uses this non-interim accessing operation and carries out the indicated operation of this memory references.

2. device as claimed in claim 1 is characterized in that described extended instruction also comprises the instruction of this existing instruction set.

3. device as claimed in claim 2 it is characterized in that the computing that the instruction of the existing instruction set that described extended instruction is included specifies this microprocessor to carry out, and wherein this computing comprises this memory references computing.

4. device as claimed in claim 1 is characterized in that described memory references comprises the parameter of a load operation, a store operation or this load operation and this store operation.

5. device as claimed in claim 1, it is characterized in that described non-interim accessing operation indicate this microprocessor forbid this memory references related data get action soon.

6. device as claimed in claim 1, it is characterized in that comprising in the described expansion actuating logic device a non-interim access buffer, described non-interim accessing operation indicate this microprocessor forbid this memory references relevant loading data get action soon, and this loading data is remained in the described non-temporary buffer.

7. device as claimed in claim 1, it is characterized in that described non-interim accessing operation indicate this microprocessor forbid this memory references relevant storage data get action soon, and carry out as the indicated operation of memory references that stores parameter, this storage parameter has and is combined with the memory attribute of writing function.

8. device as claimed in claim 1 is characterized in that described expansion preamble comprises:

One source field will be applied to the specified loading parameter of this extended instruction in order to specify this non-interim accessing operation; And

One destination field will be applied to the specified storage parameter of this extended instruction in order to specify this non-interim accessing operation.

9. device as claimed in claim 1 is characterized in that described translation logic device comprises:

One escape instruction detects logical unit, is used to detect this expansion preamble mark;

One instruction decode logical unit, in order to the computing that decision will be carried out, wherein this computing comprises this memory references computing; And

One expansion decoding logic device is coupled to this escape instruction and detects logical unit and this instruction decode logical unit, in order to this non-interim accessing operation of decision, and specifies this non-interim accessing operation in this microinstruction sequence.

10. microprocessor architecture that expands an existing instruction set with non-temporary storage access control that the instruction level is provided is characterized in that:

This microprocessor architecture stores an extended instruction, be used to specify a non-interim accessing operation of a memory references, wherein this extended instruction comprises an operation code of choosing in the existing instruction set, after this operation code, then follow the expansion preamble of a n position, this operation code of choosing identifies this extended instruction, the expansion preamble of this n position then identifies this non-interim accessing operation, and wherein the non-interim accessing operation of this memory references can not be specified according to the instruction of this existing instruction set; And

This microprocessor architecture comprises a translater, be used to receive this extended instruction, and produce a microinstruction sequence, carry out the indicated operation of this memory references to indicate a microprocessor by this non-interim accessing operation, this microprocessor also comprises an expansion actuating logic device, it is coupled to this translation logic device, in order to receiving this microinstruction sequence, and uses this non-interim accessing operation and carries out the indicated operation of this memory references.

11. microprocessor architecture as claimed in claim 10 is characterized in that described extended instruction also comprises:

All the other instructions are used to specify this memory references, and wherein this memory references comprises that one loads parameter, a storage parameter maybe this loading parameter and this storage parameter.

12. microprocessor architecture as claimed in claim 11 is characterized in that the expansion preamble of described n position comprises:

One first non-interim specific field is used for this non-interim accessing operation of indication and will be applied to this loading parameter; And

One second non-interim specific field is used for this non-interim accessing operation of indication and will be applied to this storage parameter.

13. microprocessor architecture as claimed in claim 10, it is characterized in that described non-interim accessing operation indicate this microprocessor forbid this memory references related data get action soon.

14. microprocessor architecture as claimed in claim 10, it is characterized in that comprising in the described expansion actuating logic device a non-interim access buffer, described non-interim accessing operation indicate this microprocessor forbid this memory references relevant loading data get action soon, and this loading data is sent in the described non-temporary buffer.

15. microprocessor architecture as claimed in claim 10, it is characterized in that described non-interim accessing operation indicate this microprocessor forbid this memory references relevant storage data get action soon, and, carry out the indicated operation of this memory references to be combined with the access mode of writing function.

16. microprocessor architecture as claimed in claim 10 is characterized in that described translater comprises:

One escape instruction detecting device is in order to detect this operation code chosen in this extended instruction;

One command decoder is in order to decipher the part except the described operation code of choosing in this extended instruction, to determine this memory references; , and

One expansion preamble code translator is coupled to this escape instruction detecting device and this command decoder, in order to deciphering the expansion preamble of this n position, and specifies this non-interim accessing operation in this microinstruction sequence.

17. one kind is the device that an existing instruction set increases the non-interim accessing operation controlling features of instruction level, it is characterized in that, comprising:

One translation logic device, receive an effusion mark, this effusion mark identifies the subsidiary part of a corresponding instruction and has specified a memory references, wherein this effusion is labeled as one first operation code in this existing instruction set, a non-interim accessing operation designated code wherein, be coupled to this effusion mark, and for should subsidiary part one of them, to be applied to this memory references in order to specify a non-interim accessing operation; And

One expansion actuating logic device is coupled to this translation logic device, carries out the indicated operation of this memory references by this non-interim accessing operation.

18. device as claimed in claim 17 is characterized in that the remainder of described subsidiary part comprises one second operation code, in order to specify this memory references.

19. device as claimed in claim 17, it is characterized in that described translation logic device should the effusion mark with should subsidiary part translate into corresponding micro-order, this corresponding micro-order is to indicate this expansion actuating logic device to carry out the indicated operation of this memory references by this non-interim accessing operation.

20. device as claimed in claim 17 is characterized in that described translation logic device comprises:

One effusion marker detection logical unit in order to detecting this effusion mark, and indicates translation action of this subsidiary part to need according to the expansion translation protocol; And

One decoding logic device, be coupled to this effusion marker detection logical unit, should have the agreement of instruction set in order to foundation, the translation action of execution command, and carry out the translation of this correspondence instruction according to this expansion translation protocol, to pass through this non-interim accessing operation with indication, carry out the indicated operation of this memory references.

21. a method that expands an existing instruction set architecture so that the control of non-temporary storage parameter to be provided in the instruction level, is characterized in that this method comprises:

One extended instruction is provided, and this extended instruction comprises an extending marking and an expansion preamble, and wherein this extending marking is wherein one first operation code of this existing instruction set architecture;

Specify a non-interim accessing operation that will be applied to a corresponding memory references by this expansion preamble, wherein this memory references is specified by the remainder of this extended instruction; And

Use this non-interim accessing operation to carry out the indicated operation of this memory references, wherein this using action has forbidden getting soon the corresponding data of this memory references in advance.

22. method as claimed in claim 21 is characterized in that described required movement comprises:

At first in the remainder of this extended instruction, specify this memory references, wherein this at first the action of appointment comprise use should existing instruction set architecture in one second operation code.

23. method as claimed in claim 21 is characterized in that, it also comprises:

This extended instruction is translated into a microinstruction sequence, and this microinstruction sequence is that indication one expansion actuating logic device is carried out the indicated operation of this memory references by this non-interim accessing operation.

24. method as claimed in claim 23 is characterized in that the action of described translation extended instruction comprises:

In a translation logic device, detect this extending marking; And

Decipher the remainder of this expansion preamble and this extended instruction according to expanding translation rule, to produce this microinstruction sequence.

25. method as claimed in claim 21 is characterized in that described required movement comprises:

Specify this non-interim accessing operation to be applied to a source operand, a destination operand or above both.

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