TWI245221B - Apparatus and method for selective memory attribute control - Google Patents

Abstract

An apparatus and method are provided for extending a microprocessor instruction set to allow for selective override of memory traits at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into a micro instruction sequence. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies a memory trait for a memory reference prescribed by the extended instruction, where the memory trait for the memory reference cannot be specified by an existing instruction from an existing instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the micro instruction sequence, and employs the memory trait to execute the memory reference.

Description

1245221 Α7; ^ (Case No. 091124008 Specification Amendment; λ * η

V. Description of the Invention (Comparison with related applications Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs [0001] This application claims the following priority of the United States application and Meijia Minglei: Fortunately 10/227572, the application date is 2002 August 22, 2000. [0002] This application has the same applicants and inventors as the following U.S. patents that are also in the same application. 申请 Taiwan Application No. Application DOCKET NUMBER Set and Method 91116957 7 / 30/02 CNTR: 2176 91116958 7/30/02 CNTR: 2186 Device and method for executing conditional instructions 91116956 7/30/02 CNTR: 2188 Selectively control condition code writeback 91116959 7/30/02 CNTR: 2189 Add micro Mechanism of the number of registers of the processor 91124005 10/18/02 CNTR: 2190 Device and method for extending microprocessor data mode 91124006 10/18/02 CNTR: 2191 Device and method for extending microprocessor address mode CNTR: 2192 Prohibition of storage inspection CNTR: Prohibition of 2193 91124007 10/18/02 CNTR: 2195 I ----------- Non-temporary memory reference control mechanism 91116672 7/26/02 CNTR: 2198 --------- Control results selectively Apparatus and method for writing " ----- This paper scales applicable Chinese National Standard (CNS) A4 size (210 X 297 mm)

A7 | Fan Zheng Replacement Book Repair — i J Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1245221 (Case No. 5) Invention Description (X) (I) Field of Invention Technology: Mao Yue is a field related to microelectronics, especially Refers to a technology that can incorporate selective memory attribute control ship A ^ ^ control into an existing microprocessor instruction set architecture (II) Technical background of the invention ·· _4] since the early 1970s, microprocessing, The use of devices has grown exponentially. From the earliest applications in science and technology to consumer areas that have introduced business from those special areas, such as desktop and laptop computers, video game controllers And many other common household disk commercial devices and other products. [0050] Ik has grown explosively in use, and has also undergone a corresponding technical upgrade, which is characterized by increasing requirements for the following items: · Faster speed, stronger addressing capability, faster memory access, larger operands, more general-purpose types of operations (such as floating-point operations, single instruction multiple data (SIMD) Conditional movement, etc.) and additional special-purpose operations (such as digital machine number processing functions and other multimedia operations). This has created amazing technological progress in this field and has been applied to the design of microprocessors, such as expansion pipelines (extensive pipelining), super_scalar architecture, cache structure, out-factory processing, burst access mechanism, branch predication, and speculative In short, compared to when it first appeared 30 years ago, today's microprocessors have shown amazing complexity and powerful capabilities. _________2___ This paper standard applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) Order ------------ Line-[245221 A7 (Amendment to the Specification of Patent Case No. 091124〇08) B7

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention ([0006] But unlike many other products, there is another very important factor that has been limited and continues to limit the evolution of microprocessor architectures. Today Microprocessors can be so complicated 'due in large part to the compatibility of old software. In consideration of the market, many manufacturers choose to incorporate new architectural features into the latest microprocessor designs , But at the same time retains all the capabilities necessary to ensure compatibility with older, so-called "legacy" applications in these latest products. [0007] This legacy software compatibility The burden, nowhere else, will be more obvious than in the development history of x86-compatible microprocessors. Everyone knows that the current 32 / 16-bit virtual mode (virtuai_mode) x86 microprocessors, still It can execute 8-bit real-mode applications written in the 1980s. Those skilled in this field also acknowledge that there are many related architectures "packages" only stacked in the x86 architecture, just for the sake of Support compatibility with old applications and operating modes. Although in the past, developers can add newly developed features to existing age sets, but now they can be programmed using the tools that these features rely on However, in short, there are no "redundant" instructions in some important instruction sets, allowing designers to incorporate updated features into an existing architecture. — [0008 ] For example, in the x86 instruction set architecture, there is no state of an undefined -byte size opcode, and it is not yet used. In the main -bit byte size opcode diagram, all The MS opcode states have been occupied by existing instructions. As a result, designers of χ86 microprocessors must now choose between providing new software and retaining compatibility with old software. Right to provide For new programmable features, you must assign calculations to (210 X 297 mm) (please read the precautions on the back before filling this page) • -Li ------- Order --- ---- ·

I 245221 (Amendment to the specification of case No. 091 m008)

Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (4 ·) These characteristics. If the existing instruction set architecture does not have redundant opcode states, some existing opcode states must be rewired to provide new features: Therefore, in order to provide new features, the old software compatibility must be sacrificed Already. [0009] One area of interest to microprocessor designers today is how applications can use cache memory structures efficiently. As cache technology evolves, more and more features have been provided that allow system programmers to control when and how cache memory in the system is used. The early_cache control feature only provides on / off capability. By setting one of the internal registers of the microprocessor, or by setting an external signal pin on its package to true, the user can enable the cache of §memory body, or Make the entire memory space uncacheable. For non-cacheable memory references (load / read and store / write), they are all sent to the system memory bus, resulting in the same waiting time as the external bus structure ( latency). Conversely, §memory's reference or access to a cache memory occurs only when a cache miss occurs (that is, the target of a carcass reference is in the internal cache memory) (Not valid) before being sent to the system memory bus. The cache feature makes the application run faster, especially when the application repeatedly references the same data structure in memory. [0010] Recent improvements in microprocessor architecture have enabled system designers to more precisely control how cache features are used. These improvements allow the designer to define the nature of a range of addresses within the microprocessor's address space, where the definition is based on how the microprocessor references these addresses in accordance with its cache hierarchy ). Generally speaking, the Chinese national standard (CNS) A4 specifications (210 X 297 issued) are applicable to these paper sizes (please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1245221 A7 (Amendment of the Specification of Patent Case No. 091124〇08) B7 V. Description of Invention (r) Reference to the address can be defined as non-cacheable, composite writing Write combining, write through, writeback, or write protected. These properties are called memory attributes, or memory attributes (t) rait. Therefore, a storage reference for an address with a write-back attribute is sent to the cache memory and speculatively assigned to the storage location therein. A storage reference to another address that is not cacheable is sent to the system bus without the action of virtually assigning a storage location. [0011] However, it is beyond the scope of this application to provide an in-depth description of how memory attributes and specific attributes are processed by the microprocessor through its cache memory. Here to understand that the present technology enables designers to assign a memory attribute to a memory region, and all subsequent memory references to addresses in the region will be based on the cache associated with the specified memory attribute. Principle (cachepolicy) to deal with, this is sufficient. [0012] Although modern microprocessor designs allow different regions of the memory to be endowed with different memory characteristics, the design is still limited in two important respects. First, the microprocessor instruction set architecture limits the execution of instructions at a privilege level that are not accessible to applications that define / change memory characteristics to the user level. Therefore, when a desktop / laptop microprocessor is started, its operating system establishes the memory characteristics of the physical memory space before any user-level application is opened. Therefore, user-level applications cannot change the memory characteristics of the host system. Second, in modern micro-processing H, the optimal processing level for establishing memory characteristics is the paging level. Permissible memory paging in practice --------- 8___ This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) Order --------- n ϋ nn-A7 1245221 (Case No. g 〇9 丨 l24 〇 08 V. Description of the invention (△ architecture, the memory attributes of each memory page, by the operating system It is further defined in the page directory / table item. Therefore, 'all references to the addresses in a specific page will be used in the relevant memory to store the runtime slave properties. [0013 ] For many applications, although the above-mentioned control features allow «user-level_satoshi to be improved in execution speed, the inventors of this case have noticed that there are still restrictions on other systems. This is not only because at the level of the ambassador, it is not possible to control modern medullary characteristics, but also because the Zlt body can only be established in units of the page level (page_levei). For example, a pair of first data User program structure for repeated access When performing an incidental reference, if the cache item of the first data structure must be cleared to free up the space of the cache memory for the second data structure, the execution efficiency of the user program will be affected accordingly. = The operating system does not predict the frequency of multi-photographs of user-level programs to the material structure, and the data space of the application is generally given a write feature, which has contributed to the generation of pre-Sudden conditions. Programmers and financial resources To change the asset red flag, forcing _ with parameters to be transferred to the memory bus to give non-cacheable properties to the second data structure), and exclude _4] Therefore, what we need is a way to select The control characteristics of the memory attributes include the existing microprocessor instruction set method, in which the microprocessor instruction set is completely occupied by the defined opcodes. The birth control features are not affected except that they conform to the old specifications of "Riding" The ability to sell applications' also provides programmers to modify the memory ^ --------- (Please read the precautions on the back before filling this page)-This paper size applies to Chinese national standards (CN S) A4 specification (210: 297 mm) 245221 __Jie No. 091] Revised description of Patent No. 8 No. 8) ^

V. Description of the invention (9 Ability of attributes.) (3) Brief description of the invention: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs [0015] The present invention, like the other applications mentioned above, addresses the problems and disadvantages of the above and other conventional technologies. To overcome this, the present invention provides a better technology for expanding the microprocessor's instruction set to exceed the existing capabilities, and provides instruction-level memory characteristics control features. In a specific embodiment, a- A device capable of performing instruction level control of memory attributes in a microprocessor. The device includes a translation logic (gic) and an extended execution logic. The translation logic translates an extended instruction into a sequence of microinstructions (micro instmctin, etc.). The ^ extension instruction has an extended preflx and an extended prefix tag 圯. The extended preamble refers to the -key reference, designation -key specified by the extended instruction, although its memory characteristics cannot be specified by an existing instruction in an existing instruction set. The extended preamble tag indicates the extended preamble, wherein the extended preamble tag is an operation code specified by another architecture in the existing instruction set. The extended execution logic is reduced to translation, used to receive the microinstruction sequence, and apply the memory characteristics to perform the memory reference. [0016] An object of the present invention is to provide a microprocessor mechanism that extends an existing instruction set to provide selective control of memory characteristics. The microprocessor mechanism has an -extend instruction and -tfanslatw. The extended instruction specifies a memory attribute of the memory access, wherein the extended instruction includes one selected operation code of the existing microprocessor instruction set, followed by an n 10 paper standard applicable to the Chinese National Standard (CNS ) A4 specification (210 X 297 male f 1245221 A / (Amendment of the specification of patent case No. 0991124〇08) B7 five

The extended prefix of the (g) bit printed by the Consumers and Consumers Agency of the Intellectual Property Office of the Ministry of Economic Affairs and published by the Consumer Affairs Agency. The selected operation code indicates the extended instruction, and the n-bit extended preamble indicates that the memory belongs to the society. The read attribute of the memory access cannot be specified according to the instructions of the existing instruction set. The translator receives the extended instruction and generates a micro-instruction sequence to instruct the microprocessor to perform the play access, and the memory access will be performed according to the memory attribute. [0017] Another object of the present invention is to propose a memory-specific control feature that adds instruction levels to an existing instruction set-an escape flag (-),-a memory characteristic index unit (: two spmfier), and -Extend execution logic. The observation mark is received by the -translation logic 'and pointed out-the access to the county order has been touched-slimming access, where the escape mark is the observation operation code. The memory characteristic designates that the element consumption is connected to the escape mark, and it is one of the accompanying parts', which is used to confuse the faces of others with their towels—access to the ship. The extended execution logic is consumed by the translation logic, and the memory access is performed by using the specified memory characteristics, wherein the existing instruction set only provides the designation of the memory storage = of-the default memory, and the The memory characteristic specified by the extended execution logic application replaces the preset memory characteristic. Another object of the present invention is to provide a method for expanding an existing instruction set architecture so as to enable selective memory attribute control at the instruction level. The method includes providing an extension instruction. The extension instruction includes an extension tag and an extension tag, wherein the extension tag is one of the first operation code items of the existing instruction set architecture; and the extension prefix is used to specify an application code to be applied. One of the memory attributes in a corresponding memory access, where the memory access refers to the extension of the paper (applicable to Zhongguan Jiaxian (CNS) A4 specifications ⑽ 97 public love) (Please read the note on the back first) Please fill in this page again for the items) Order:-Line · A7 1245221 (Amendment of the specification of Case No. 091 丨 24008) B7 V. Designation of the rest of the invention description (γ) order; and application of the memory Memory to perform the memory (please read the precautions on the back before filling this page), and the application action replaces one of the default memory attributes of the memory access. (IV) Illustration of the invention ... [0019] The foregoing and other objects, features, and advantages of the present invention will be better understood after cooperating with the following description and accompanying drawings: [0020] FIG. A block diagram of a related art microprocessor instruction format; [0021] FIG. 2 is a table 'which describes how instructions in an instruction set architecture' correspond to an 8-bit operation code byte in the instruction format of FIG. Bit logic state; [0022] FIG. 3 is a block diagram of the extended instruction format of the present invention; [0023] FIG. 4 is a table showing extended architecture lines according to the present invention. How features correspond to an 8-bit [0024] FIG. 5 is a block diagram illustrating a pipelined microprocessor that is one of the selective memory attribute control applications of the present invention; employee consumption of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the cooperative [0025] FIG. 6 is a block diagram of a specific embodiment of an extended preamble for specifying extended memory characteristics in a microprocessor according to the present invention; [0026] FIG. 7 is the present invention Used to specify a microprocessor [0027] FIG. 8 is a table illustrating an encoding example of a typical memory characteristic in the extended preamble of FIG. 7; ^ Zhang scale is appropriate Γ Zhongguanjia Standard (CNS) ^ grid (21G xy97 public 6 " 1245221 _ month book revision) ba; V. Description of the invention

D Figure Nine is a block diagram of the details of the logic in the translation stage of the microprocessor in Figure 5. Figure 10 is a block diagram of the execution logic of the microprocessor in Figure 5; and # Figure 10-is a description The present _ in the replacement-the operation of the method of the memory characteristics of the microprocessor _ Figure. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, the drawing number description: 100 instruction format 102 operation code 208-bit operation Martu 202 operation code Flfi 300 extended instruction format 3202 operation code 3 04 extended instruction mark 4 〇8-bit preamble Figure 500 pipelined microprocessor 502 instruction cache memory / external balance 503 instruction 彳 ning column 505 extended translation logic 507 execution logic 600 extended prefix 602 purpose field 70 〇 Memory attribute preamble 101 103 201 301 303 305 401 501 504 506 506 508 601 Preamble address designation element code Nose code prefix stone horse address designation element extended preamble architecture feature extraction logic translation logic The micro-instruction is extended to execute the logical source characteristic block 701 attribute block the paper size Lai @ i ^^ (eNS) A4 [245221 A7 (case number 009] 丨 2408 patent specification amendment) ^ 94. 4.2 2 Five-member Intellectual Property Bureau of the Ministry of Economic Affairs printed a description of the invention (/ 1) 702 Source bit 704 Standby stop 800 Form 900 Translation stage logic 902 Machine-specific register 904 Instruction buffer 906 Translation controller 908 escape Instruction detector 910 instruction decoder 912 micro instruction buffer 914 micro operation code block 916 source block 1000 extended execution stage logic 1002 address buffer 1004 destination operand buffer 1006 memory characteristic description unit 1008 confluence Row unit 1010 storage buffer 1012 bus 1014 storage buffer 703 destination bit 901 activation status signal 903 extension characteristic stop 905 translation logic 907 disabling signal 909 extension preamble decoder 911 control read-only memory 913 operation code extension Entry block only 915 purpose block 917 displacement block 1001 extended microinstruction buffer 1003 address buffer 1005 extended access logic 1007 cache memory 1009 access controller 1011 cache memory 1013 bus 1015 source operand Buffers 1100 ~ 1128 Saki-chan-The H process of the second method of the micro-red red face noodles, jujube (five) invention detailed description ... [] The following description is based on the specific embodiment and the necessary conditions of this paper Dimension outline (please read the precautions on the back before filling this page) Medical Order --------- Slow ·········································· a economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau V. Invention Description (丨 II) Provided in the context of the invention, so that those skilled in the art can use the present invention. However, various modifications made to the preferred embodiment will be apparent to those skilled in the art, and the general principles discussed herein can also be applied to other embodiments. Therefore, the present invention is not limited to the specific embodiments shown and described herein, but has the widest scope consistent with the principles and novel features disclosed herein. '^ [0032] The previous discussion has been made on the background of today's microprocessors on how to expand their architectural features to surpass the capabilities of related instruction sets. In view of this, an example of related technology will be discussed in Figs. 1 and 2. The theory here emphasizes the dilemma that microprocessor designers have been facing. On the one hand, they want to incorporate the newly developed architecture features into the design of the microprocessor, but on the other hand, they have to keep the old Has application capabilities. In the example of Figures 1-2, a fully occupied opcode diagram has excluded the possibility of adding new opcodes to the example architecture, thus forcing the designer to choose to incorporate new features or sacrifice some Legacy software compatibility, or we must abandon the latest developments in architecture in order to maintain the compatibility of the microprocessor with legacy applications. Following a discussion of the related art, a discussion of the present invention will be provided in Figures 3-11. By using an existing but unused opcode as the pre-coded mark of two extended instructions, the present invention allows microprocessor designers to overcome the limitations of the instruction set architecture that has been fully used, while allowing them to provide programmers with instructions The ability of a level to refer to a specific memory while assigning memory characteristics, 9 preserves compatibility with legacy applications. [0033] Please refer to FIG.-, which is a block diagram of a related art microprocessor instruction format 100. The relevant technology directive encourages a variable amount of capital paper size to apply Chinese National Standard (CNS) A4 specifications (210 X 297 public love) (Please read the precautions on the back before filling this page) — — — — — — — · 111111 I · · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1245221 (Patent No. 091124〇08 Patent Case ^ No ^; V. Description of Invention (/ 4) Just 〇3, each _ item is set to _Specific value, grouped together for 100 1002 order-specific operation, such as adding two operations ^, or finding an operation to move from memory to-internal register, or from the internal The register moves the I memory.-In general, the operation code item in the instruction just specifies the read operation to be performed, and the optional address specifies the meta item just after the operation code 102. Specify additional information about the specific operation, such as 疋 how to perform the operation, where the operands are located, etc. The instruction format is 0 and allows the private operator to add the preamble item 101 before the -unique code 102. In When a specific operation specified by operation code 102 is performed, Code 101 is used to indicate yes = use specific architectural features. In general, these architectural features can be applied to most of the operations specified by any operation code 102 in the instruction set. For example, the current installation code 101 exists in some applications. Microprocessors that use different sizes of virtual addresses (such as 8-bit, 16-bit το, 32-bit) to perform operations. When many of these processors are programmed to a preset address size (such as 32 Bit), before setting it to 10 in its individual instruction set, can still allow the programmer to selectively override the preset address size (such as to generate 16-bit Virtual address). The selectable address size is only an example of architectural features. In many modern microprocessors, these architectural features can be applied to operations specified by the transport code 102 (such as adding , Subtraction, multiplication, Bollinger logic, etc.) [0034] The instruction format 100 shown in Figure 1 has a well-known example in the industry, this is the x86 instruction format 100, which is all modern χ86_ compatible microprocessors Used. More specifically, χ86 refers to Order format 100 (also known as χ86 This paper size applies to Chinese National Standard (CNS) A4 specifications (210 X 297 mm)) (Please read the precautions on the back before filling out this page) -------- Order- -------- Line 1245221 (Amendment to the Specification of Patent Case No. 09) No. 124008) & A7 V. Description of the Invention (./4) The order set architecture 100) uses 8 bits ago Set up a 10-bit 8-bit operation code 丨 〇2 and 8-bit address designation element 103. \ 86 architecture 100 also has several preambles, two of which replace the pre-programmed x86 microprocessor Set the address / data size (that is, the different code states 66H and 67H), and the other instructs the microprocessor to interpret the subsequent operation code byte 1102 (that is, the preamble value) according to different translation rules. 0FH, which makes the translation action based on the so-called two-byte opcode rules), and other preambles 101 repeat special operations until the repetition conditions are met (ie REP opcodes · F〇H, F2H and F3H). Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) --line How the structured instruction 201 corresponds to the bit value of an 8-bit operation code byte 102 in the instruction format of FIG. 1. Table 2000 shows an example of an 8-bit opcode map 200. It associates up to 256 values of an 8-bit opcode item 102 with the corresponding microprocessor opcode instruction 201. . The table 200 maps a specific value of the operation code item 102, such as 〇2H, to a corresponding operation code instruction 201 (ie, instruction 102201). In the example of the x86 opcode diagram, it is well known in the art that the opcode value 14H is mapped to the x86 Add With Carry (ADC) instruction. This instruction is an 8-bit direct (immecjiate ) Operands are added to each value in the architecture register. Those skilled in this field will also notice that the aforementioned setting codes 101 (ie, 66Η, 67Η, 0FH, F0H, F2H, and F3H) are actual operation code values 201. In different contexts, it is specified that Specific architectural extensions are applied to the operations specified by the subsequent opcode item 102. For example, adding the preamble 0FH before the opcode 14Η (normally, the aforementioned adc opcode) will cause the χ86 processor to perform a "decompression and insertion of low-compression code. The Zhang scale is applicable to China. Standard (CNS) A4 specification (210 X 297 mm) 1245221 A7 / (Amendment of the specification of patent case No. 09911124008) B7 V. Description of the invention (/ 丄) Single-precision floating-point value "(u 叩ack and Inter 丨 eave LQW paeked Single-precisi0n Floating-Point Values) operation instead of the original ADc operation. The features described in this example are partially enabled in modern microprocessors. This is because the instruction translation / decoding logic in the microprocessor is to sequentially interpret the item HH · of instruction 100. Therefore, in the past, the use of specific opcode values as preambles in the instruction set architecture allowed the microprocessor to incorporate many advanced architectural features into the design of microprocessors compatible with old software without affecting Legacy programs that do not use those particular opcode states have a negative impact on execution. For example, an old program that has not used the M6 opcode can still run on today's x86 microprocessors. And a newer application program, by using the X86 operation code ㈣ as the preamble 就能, can use many of the newcomer's χ86 architecture features, such as single-instruction multiple data (SIMD) operations, conditional movement operations, and so on. _6] Although architecture features have been provided in the past by specifying available / excessive opcode value 201 as a preamble (also known as architecture feature flag / indicator 101 or escape instruction 101), many instruction set architectures 1〇〇 When providing functional enhancements, there will still be obstacles for very direct reasons ... All available / excessive opcode values have been used up, that is, all 2 in opcode map 200 The opcode value has been speculatively specified. When the fiscal value is assigned as opcode item 102 or preamble item 101, there is no remaining opcode value available for incorporating new features. This serious problem exists in many microprocessor architectures today, forcing designers to choose between adding architecture feature disks and retaining compatibility with legacy programs. [0〇37] It is worth noting that the instructions shown in Figure 2 are expressed in general 1245221 (Amendment of the Specification of Patent Case No. 091124008) B7 V. Invention Description (//,) 124'186), rather than specifically referring to actual operations (such as carry accumulation, subtraction, mutual exclusion, or). This is because, in some different microprocessor architectures, the fully occupied operation code figure 200 has been architecturally excluded from the possibility of incorporating newer developments. Although the example in Figure 2 refers to the 8-bit opcode item ι〇2, those skilled in the art will still notice that the specific size of the opcode 102 is a special case to discuss the fully occupied operation. Apart from the problems caused by the code structure 200, other aspects have nothing to do with the problem itself. Therefore, a fully-occupied 6-bit opcode map will have 64 transportable code / preamble 2 (H) that can be architecturally specified, and will not provide usable / excessive opcode values for expansion. # Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs [0038] Another alternative is not to completely abandon the original instruction set and replace it with a new format 100 and operation code diagram 200, but only for two For some existing operation codes, the instruction implies substitution, as shown in Figure 2. The different codes are torn to the side. With various mixed technologies, the microprocessor can operate in one of the following two modes: The mode uses the operation code 40H-4FH 'to interpret the rules, or to operate in another enhanced mode. At this time, the operation code 40H_4FH is interpreted according to the enhanced construction rules. This technology Wei allows designers to incorporate new features into the design 'however' when a microprocessor that conforms to the old specifications operates in a thief-like manner, the disadvantages still exist because the microprocessor cannot perform any application that uses 4 ^ 4FH. Therefore, Stand to retain the old software phase ==%, compatible with old software / enhancement technology, it is still unacceptable. [0039] Of course, while the code space is completely occupied, it means 2000, and this space covers all Specifications of the ministry on duty 'paper scale_CNS Standard A4 (21 (^ 97mm 1245221, A7 /; * j 9 ο ^ (Case No. 009 like 〇〇08 patent case Revision of the description) B7 ·: "V. Invention description 0〇) The application, the inventors of this case have noticed the use of the operation code 201, and they have also observed that although some instructions 202 are architecture Specified, but not used in an application that can be executed by a microprocessor. The daily order IF1 202 described in Figure 2 is an example of this phenomenon. In fact, the same opcode value 202 (that is, F1H) Maps to a valid instruction 202 that is not used in the x86 instruction set architecture. Although the unused x86 instruction 202 is a valid x86 instruction 202, it indicates that an architectural designation is to be performed on the x86 microprocessor Operations, but it is not used in any modern x86 microprocessor Application type. This particular x86 instruction 202 is known as the breakpoint circuit simulation (In

Circuit Emulation Breakpoint) (ie, ICE BKPT, with an operating code value of F1H printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs), was previously used exclusively in a microprocessor simulation device that no longer exists. ICE BKPT 202 has never been used in applications other than in-circuit simulators ’and in-circuit simulation devices that previously used ICE BKPT 202 no longer exist. Therefore, in the case of x86, the inventor of this case has found a tool in a completely occupied instruction set architecture 200, by using an effective but unused operation code 202, to allow advanced microprocessors to be incorporated into the microprocessor design Without compromising the compatibility of legacy software. In a fully occupied instruction set architecture 200, the present invention uses a structured but unused operation code 202 as an index mark to indicate the next n-bit preamble, thus allowing the microprocessor Designers can incorporate up to y latest developments in architectural features into the design of the microprocessor, while retaining full compatibility with all legacy software. [0040] The present invention provides an n-bit extended memory characteristic designation elementary month, J coded to use the concept of preamble marking / extended preamble, thus allowing ^ 7 -------- _ —--_20_ This paper size is applicable to China National Standard (CNS) A4 (21〇X 297mm) n Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 245221 (Case No. 09 丨) No. 24〇08 Revision of the description of the patent case) Anti-fifth, the invention description (/ （programmer in-microprocessor, according to each instruction, assign a memory attribute to a corresponding memory access operation. Access in the corresponding memory When the operation is performed, the memory attribute is used to replace one of the default attributes specified by the memory property description metatable / mechanism previously established by the operating system program. The present invention will now be discussed with reference to FIGS. 0041] Please refer to FIG. 3, which is a block diagram of the extended instruction format 3㈨ of the present invention. It is very similar to the format 100 discussed in FIG. 1. The extended instruction format 300 has a variable number of instruction items 3001_3. 5, each _ item is set to a special threshold, Taken together, it forms a specific instruction 3 of the microprocessor. The specific instruction 300 instructs the microprocessor to perform a specific operation, such as adding two operations = elements, or moving an operation element from memory to the microprocessor. In general, the operation code item 3202 of instruction 300 specifies the specific operation to be performed, and the selected address designation meta-item 303 is located after operation data 3202 to specify the specific operation. Additional information about the operation, such as how to perform the operation, the register in which the operand is located, direct and indirect data of the memory address used to calculate the source / result operand, etc. The command format 300 also allows programmers A preamble item 301 is added before an operation code 302. When a specific operation specified by the operation code 302 is performed, the preamble item 301 is used to indicate whether to use an existing architectural feature. [0042] However, The extended instruction 300 of the present invention is a superset of one of the instruction format 100 of the foregoing figure. It has two additional items 304 and 305, which are selectively used as instruction extension items and placed in a format. Extension Order all remaining items 301-303 in 300. These two additional items 304 and 305 allow programmers to refer to the memory specified in the extended instruction 300. This paper size applies the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) (Please read the notes on the back before filling out this page) Order: i-line-1245221-Λ ... '>-(Case No. 091 丨 24〇08 patent case description (Revision) B7 V. Description of the invention (/,) Setting-memory characteristics, which corresponds to the memory by referring to the county law and by the existing instruction set of the microprocessor that conforms to the old specifications == 疋. Optional items 304 and 305 are an extended instruction mark 304. Prefix 3.5. The extended instruction mark 304 is on the :: operation code specified by another architecture in the set. In the -x86 embodiment, 'the extended instruction mark 304, or the escape tag 3〇 = === 咖 之 咖啡 聊 指令 —every time logical correction, the extended code 3G5, or extended feature refers to the heart疋 305 'is followed, in which the extended preamble 305 specifies the corresponding ^ -specified memory access-memory attribute. In the specific embodiment, 2304 indicates that the '-corresponding part of the extended age 3⑻3_3 = 005 specifies the memory access to be performed by the microprocessor. Memory characteristic 305, or extended preamble 305, specifies a plurality of memory characteristics. If—find memory access. The microprocessing 11 Qi Yanpei logic executes Guanlong access based on the specified face to hide, thus replacing the default memory attributes specified by the original = other methods, which include making the post office The control unit stores memory elements, memory types, page tables, and other types of memory attribute descriptors. The selective memory attribute control technology of the present invention is summarized here at first. -The extended instruction is configured to specify an existing microprocessor instruction set = physical access designation-slimming secret. The memory attribute accessed by the clock cannot be added to the instruction of the existing microprocessor instruction set. Specify it. The extended instruction includes one of the opcodes / instructions 304 of the existing instruction set at 1 x 297 mm. Page line 245221 A7 (Amendment of the specification of the case No. 091124008 patent) B7 treatment replacement 5. Description of the invention) And an n-bit extended preamble 305. The selected opcode / instruction is used as an indicator 304 to indicate that the instruction 300 is an extended feature instruction 300 (that is, it is said to have extended the extension of the micro-processing state architecture) 'the n-bit feature preamble The code 305 only states the attribute of the 5 memory. In a specific embodiment, the extended preamble 305 has an eight-bit size, and can specify a maximum of 256 different attributes or combinations of memory attributes and other extended features. The embodiment of the n-bit preamble can specify up to 211 different memory characteristics. [0044] Referring now to FIG. 4, a table 400 shows how a designated memory referenced memory attribute is mapped to the bit logic state of an 8-bit extended preamble embodiment according to the present invention. Similar to the operation code diagram 200 'discussed in FIG. 2, the table 400 in FIG. 4 presents an example of an 8-bit extended preamble figure 400, which extends an 8-bit extended preamble item 305 to a maximum of 256. Value, which is related to the corresponding memory characteristic 401 (such as E34, E4D, etc.) of a microprocessor conforming to the old specification. In a specific embodiment of χ86, the 8-bit extended feature preamble 305 of the present invention is provided for the instruction level control of the memory characteristics 401 (ie, E00-EFF). These memory characteristics 4 〇1 is not specified by the current x86 instruction set architecture at the instruction level. [0045] The extended feature 401 shown in FIG. 4 is expressed in a general way, and does not specifically refer to actual features. This is because the technology of the present invention can be applied to various different architectural extensions 401 and specific instructions. Hego. Those skilled in the art will find that there are many different architectural features 401, some of which have been mentioned above 'can be escaped according to the escape tag 3 04 / extended preamble 305 technology described here Inclusion-Existing instruction set. The embodiment of the 8-bit preamble in FIG. 4 provides a maximum of 256 different features. 40-bo-n-bit preamble embodiment The paper size is applicable to the Chinese National Standard (CNS) A4 specification (21〇> ^ 7 male f) (Please read the precautions on the back before filling this page) ·-丨 · Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

1245221 (Description of Patent No. 091124008, Repair TP, V. Invention Description (> Stylized selection with up to 2 «different features. [0_] Please refer to _5, which is to explain the invention Base execution selectivity = block diagram of pipelined microprocessor leaks of memory attribute control operations. Microprocessor 500 has three distinct types of stages: fetch, translate, and execute. The fetch stage has an extract logic plan that can be cached from instructions The instruction is fetched by the memory 502 or the external reading body 502. The fetched instruction is sent to the translation stage via the instruction sequence 503. The translation stage has the translation logic 5G4 and is connected to a micro instruction sequence 506. The translation logic 504 includes extended translation Logic 505. The execution phase includes execution logic 507, which contains extended execution logic. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs [0047] According to the present invention, during operation, logic 50 is extracted from the instruction cache. .Hidden body / foreign memory body 502 extracts formatting instructions, and puts these instructions in the order of Wei line into the instruction array 503. Then extract these instructions from the instruction array such as Send to translation logic 504. Translation logic 504 translates / decodes each incoming instruction into a corresponding micro-instruction sequence to instruct microprocessor 500 to perform the operations specified by these instructions. According to the present invention, Extended translation logic 505 detects those instructions with extended preamble marks to perform translation / decoding of meta-prefixes corresponding to extended memory characteristics. In an embodiment of χ86, extended translation logic 505 is configured as Detect the extended preamble tag whose value is F1H, which is the ICE BKPT operation code of x86. The extended microinstruction block is provided in the microinstruction queue 506 to allow specifying the correlation specified by the accompanying part of the instruction [0048] Micro-instructions are sent from the micro-instruction queue 506 to the execution logic 507, where the extended execution logic 508 is configured to follow a preset memory characteristic (described by an existing memory characteristic) (Defined by the meta tool) execute a designated memory parameter L ----- 2 ^-This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm)

1245221 A7 A7 __ (Amendment to the description of the patent case No. 丨 丨 24008) B7 I 1 I 丨 m 丨, — I .1 V. Description of the invention () Photo, or configured to be used at the user level through this book One of the memory characteristics programmed by the extended preamble of the invention is replaced by the designation of the extended microinstruction field. --- Please read the precautions on the back before filling in this page) Preset slimming characteristics. In a specific embodiment, the memory characteristics are given in units of a cache line. Those skilled in the art will find that the microprocessor 500 shown in FIG. 5 is a simplified result of the modern pipelined microprocessor 50. In fact: A modern pipelined microprocessor 500 can contain up to 20 to 30 different pipeline stages. However, these stages can be broadly classified into three stages as shown in the block diagram. Therefore, the block diagram 500 of FIG. 5 can be used to point out the necessary elements required for the aforementioned embodiment of the present invention. For the sake of brevity, no two components of the microprocessor 500 are shown. -丨 Line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs [0050] Please refer to FIG. 6, which is an extended preamble for specifying the memory attributes of a programmed memory access in a microprocessor according to the present invention 600bis block diagram of a specific embodiment. The memory property designation 600 has a meta-prefix of 8 bits in size, and includes a source trait field 601 and a destination trait field 602. The source property field 601 specifies a memory attribute for the source meta title access (ie load, read) of the rest of a related extended instruction, and the target property block 602 is the rest. Part of the specified destination memory access (ie, storage, write) refers to the memory properties of a brother. Therefore, the 8-bit preamble 60㈣ example can specify one of 16 different memory characteristics—both source and destination operands, and these I6 memory characteristics can be tested instead of side address ranges or memory. The paging has been set as the default feature. The embodiment shown in Figure 6 specifies a single source memory characteristic for all source operand addresses associated with the corresponding instruction. This paper standard applies to China's National Standard 1 (CNS) A4 specification-(21G x 22597 public meal)-- -——--- 1245221 (Amendment to the description of the patent case No. 091 丨 24008) A7 B7 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description () Designates a single unit for all purposes ( (May be different from the aforementioned). Those skilled in the art will find that the source and destination attributes can be specified separately, which is particularly useful in the case of repeated string instructions such as the x86 architecture. A variant of the above embodiment provides a corresponding destination characteristic stop 602 and source characteristic stop 601 for each destination / source operand referenced by the corresponding instruction, thus increasing the * / decrease of the preamble 600 by the same amount. Number of bits. [0050] Please refer to FIG. 7, which is an extended preamble 600 for designating memory attributes of a programmatic memory access in a microprocessor according to the present invention: a block diagram of a specific embodiment . The memory attribute preamble 700 has an 8-bit size, and includes an attribute block 701, a source bit 702, a destination bit 703, and a spare block 704. The 3-bit attribute block 701 specifies one of eight different memory characteristics for a memory access operation specified by a corresponding instruction. The source bit 702 enables memory access for all source operands, and enables the attribute specified by the attribute field 701, while the destination bit 703 enables the specified attribute for memory access of all destination operands. . Therefore, the first two 8-bit embodiments can specify one of eight different memory characteristics for memory access that may be applied to source reference, destination reference, or both, and these 8 memory characteristics can be used instead of The default characteristics assigned to the relevant address range or memory tab. 9 [0052] Please refer to the figure, which is a table for explaining an example of a typical memory characteristic of the extended preamble 700 of FIG. The table states that it has -attribute row ATTR and -attribute row TRAIT. The value of the attribute hold in the ATTR line is mapped to a corresponding memory characteristic in the TRAIT line. Here (please read the precautions on the back before filling this page) 1¾ Order ·--Line · This paper size is applicable to China National Standard (CNS) A4 (210 X 297 public love) 1245221 (Case No. 091124〇08 Amendments to the specifications of the patent case) A7 B7 V. Description of the invention (> < f) In the coding example, conventional memory characteristics are provided, such as uncacheable (value 000) and write-back (value 011), However, those skilled in the art will find that other characteristics applicable to a particular microprocessor architecture can also be encoded by the attribute blocks 601, 602, and 701 in Figures 6 and 7. [0053] Please refer to FIG. 9, which is a detailed block diagram of the logic 900 of the translation stage in the microprocessor of FIG. 5. The translation stage logic 900 has an instruction buffer 904 'which, in accordance with the present invention, provides extended instructions to the translation logic 905. The translation logic 905 is coupled to a machine specific register 902 having an extended characteristic stop 903. The translation logic 905 has a translation controller 906, which provides a disabling signal 907 to an escape instruction detector 908 and an extended decoder 909. The escape instruction detector 908 is connected to the extended decoder 909 and an instruction decoder 910. The extended decoder 009 and the instruction decoding logic 910 access a control read-only memory (ROM) 911, which stores a template micro-instruction sequence corresponding to certain extended instructions. The translation logic 905 also includes a microinstruction buffer 912, which has an opcode extension field 913, a microop code block 9M, a destination bit 915, a source block 916, and a displacement block 917. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). Line [0054] During operation, during the microprocessor power-up, the extended stop in the machine-specific register 902 The state of 903 is determined by the signal activation state (signal power state), which indicates whether the particular microprocessor can translate and execute the extension of the default memory attribute of the present invention to replace the microprocessor. instruction. In a specific embodiment, the signal 901 is derived from a feature control register (not shown in the figure), and the feature control register reads a fuse array (ftxsearray) that has been configured at the time of manufacture. (Not shown). Machine _______ 2Ί This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

m i i [

I

I line 1245221 | A7 (Amendment of the specification of case number 091124008) p7 V. Description of the invention (> 4) The rows 1012 and 1013 are coupled to a cache memory 107 and a bus unit 1008. The bus unit 1008 is used to guide the 5 memory access operations (memory transaction) performed on the memory bus (not shown in the figure). According to the present invention, the extended access logic 1005 receives microinstructions from the extended microinstruction buffer 1001, which is one of the previous stages of the microprocessor, and receives two address operations from the address buffers 1002 and 2003. And receives a destination operation 7L from the destination operand buffer 1004. The extended access logic 1005 is also coupled to a plurality of memory characteristic descriptors 1006 that are configured according to the architecture of the host microprocessor. The extended access logic 1005 includes an access controller 1009, a storage buffer 1010, and a load buffer 1011. The load buffer 1011 sends a source operand output to a source operand buffer 1015. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page)-Line · [0056] In operation, the extended execution logic 100 is used to perform memory access from memory The volume reads the operand and writes the operand to the memory, as indicated by the microinstruction in the extended microinstruction buffer 1001. When performing a read / load operation, the access controller 1009 receives one or more memory addresses from the address buffers 1002 and 2003, and reads the memory characteristic descriptor 1006, To determine the memory attributes related to the load operation. In a χ86 embodiment, the memory characteristic descriptor 1006 includes a χ86 cache memory and paging control register, paging directory and paging table entries, a memory type range register (m_ ^ type range register (MTTR), Paging attribute table (PAT) and external signal pins keN #, wb / wt #, pcT and PWT. The access controller 1009 uses the information obtained from these sources 1006 according to the x86-level memory attribute conventions to determine the preset memory attributes of the load operation. For non-x86 embodiments, the access controller 1009 & Zhang Jiji Standards (CNS) A4 specification (210 > ^ 97 public love) '" a-1245221 A7 ( Case No. 09] 丨 No. 24008 Patent Specification Amendment) ρ7 V. Description of the invention) According to the light-memory regularity of the specific _ specific _ of the county machine, use the memory characteristic descriptor 1006 Information to determine the predictive recall of the load operation. The memory address, its corresponding accessibility, is sent to the load buffer 1 (m. According to the characteristics provided, the load is slow. The device 1011 via the bus body from the cache memory or directly via the bus unit 1008 Obtain the source operand from the system memory (not shown). The obtained source operand is synchronized with a pipeline clock signal (not shown) and sent to the source operand buffer Jan 5. The extended microinstruction is also associated with This pipeline clock signal is synchronized and sent to the official line to the extended microinstruction register 1014. In this way, the source operand is sent to the next stage of the microprocessor. [0057] Execution of the extended microinstruction indicates When writing / storing an operation, the access controller 1009 receives the address data of the operation from the address buffer dirty and flipped, and receives the operand to be stored from the buffer H 1 '. The access controller ι〇09 is To access the memory characteristic descriptor 1006 as described above, to determine the memory characteristics corresponding to the ai storage operation. The memory characteristics, address information, and the destination operand are sent to the storage buffer 1 〇1〇. According to the specific Europe's storage buffer 1010 writes the destination operand into the cache " memory body 1007 via the bus 1012, or writes the system directly to the system through the bus unit 1008 to record the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economy Printed (please read the precautions on the back before filling this page) Reference memory. &Amp; [0058] The storage buffer 1010 and load buffer 1011 of the present invention are grouped based on the memory attributes of the host processor The relevant processing requirements of the model are to perform access operations of store and load, where the processing requirements include strong / weak ordering conventions (such as imaginary execution rules) and cache access principles. In a specific practical example 'Loading and storing operations are performed on different pipelines of the host microprocessor.

1245221 A7 _ (Amendment of the specification of patent case No. 091124008) B7 V. The invention description (· > (?) Is executed in the stage. [0059] The use of optional memory attributes instead of preamble extension instructions and In other words, the memory characteristics of the related memory access (that is, loading 'store or both loading and storing) are replaced by the extension code field of the extended micro instruction in the extended micro instruction buffer 1001 (not (Shown) and sent to the access controller 1009. The access controller 1009, as described earlier, determines the preset memory access preset by using the information obtained from the memory characteristic descriptor 1006. Memory characteristics. If the designated replacement characteristic is stronger than the corresponding preset characteristic, the access controller 1009 sends the replacement characteristic with the aforementioned address and / or destination operand to the storage buffer 1010 / load buffer 1011. If the designated replacement characteristic is weaker than the corresponding preset characteristic, the access controller 1009 sends the preset characteristic address and / or destination operand to the storage buffer 1010 / load buffer Device 10U. Therefore, the selective replacement of the button only depends on the For example, in the x86 architecture, the non-cacheable feature of a memory access cannot be weakened to write back. Conversely, the write back feature cannot be enhanced to be uncacheable. Memory access is based on the use of cache lines. In many modern desktop / laptop microprocessor architectures, the size of the cache line is 32 bytes. [0060] Please refer to FIG. 11, which describes the operation of the method for translating and executing a method that enables a programmer to process H-shaped preset records on the instruction level, and execute and execute the instructions. The process begins with the block magic, Sending a program with extended feature instructions sent to the microprocessor. The flow then proceeds to block 1104. [61] In block 1104, the next instruction is from cache memory / outside 1245221 A7 (Case No. 091124008 Patent Specification Amendment) π 丨 22 V. Description of the Invention (MP Part Memory Extraction. The process then proceeds to judgment block 1106. [0062] In judgment block 1106, The next instruction extracted in block 1104 is A check is performed to determine whether an extended escape code of the present invention is included. In an x86 embodiment, the check is used to detect an operation code value ρ (ICE BKPT). If the extended escape code is detected , The flow proceeds to block 1108. If the extended escape code is not detected, the flow proceeds to block 1112. [0063] In block 1108, decode / translate the extended preamble portion of the extended instruction to A memory attribute is determined, and the memory attribute is designated as a default memory attribute to replace the related memory access specified by the next command. The flow then proceeds to block 1110. [0064] In block mo, the The memory attributes of the related memory access are configured in an extension block corresponding to the micro instruction sequence. The flow then proceeds to block 1112. [0065] In block 1112, all the rest of the instruction is decoded / translated to determine the specified memory access, the location of the register operand, the memory address designator, and according to the existing microprocessor Instruction set, the use of existing architectural features specified by the preamble. The flow then proceeds to block 1114. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs [0066] In block 1114, a microinstruction sequence is configured to specify the specified memory reference and its corresponding opcode extension. Flow then proceeds to block 1116. [0067] In block 1116, the microinstruction sequence is sent to a microinstruction queue for execution by a microprocessor. Flow then proceeds to block 1118. [0068] In block 1118, the micro-instruction sequence is one of the paper sizes of the present invention and is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). [245221 a7 (Case No. 09) 124008 Amendment to the description of the patent case) B7 5. Description of the invention 0) Extraction of the address logic. The address logic generates an address for the memory access and sends the address to the extended execution logic. The flow then proceeds to block 112. [0069] In block 1120, the extended execution logic uses the memory characteristic description tool of the microprocessor architecture to determine-a predetermined memory characteristic. The process then proceeds to decision block 1122. [0070] An evaluation is performed in decision block 1122 to determine whether the cache / memory model of the microprocessor architecture allows the specified memory attribute to replace the preset attribute. If substitution is permitted, flow proceeds to block 1124. If the substitution is not allowed, the flow proceeds to block 1126. [0071] In block 1124, the memory access is performed by replacing the memory attribute specified by the extended preamble block used in block 1108. The process then proceeds to block 1128. [0072] In block 1126, the memory access is performed by using the default memory attributes determined in block 1120. The process then proceeds to block 1128. [0073] In block 1128, the method is completed. [0074] Although the present invention and its objects, features, and advantages have been described in detail, other embodiments may also be included within the scope of the present invention. For example, the present invention has been described in terms of the following techniques. A single, unused opcode state in the instruction set architecture that has been fully occupied is used as a flag to indicate the following extended feature preamble. However, the scope of the present invention is not limited to any aspect, and is not limited to a completely occupied instruction set architecture, an unused instruction, or a single mark. In contrast, the present invention encompasses incompletely mapped instruction sets, embodiments with used opcodes, and embodiments using more than one instruction tag. For example, consider 33 paper sizes that apply Chinese National Standard (CNS) A4 specifications (210 X 297 mm) (please read the notes on the back before filling out this page) # 线 · Printed by the Employees ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1245221 , — (Case No. 124008 Patent Case ^^ Five

Description of the invention (; 丨)-There are no unused opcodes and the state is less than eight. The embodiment includes a selection-operation method and an architecture. In the present invention, the specific reality is the final code status according to market factors. Among them, the subject-specific miscellaneous cooperation is selected as follows. The _ :: _ side contains the use of opcodes such as the different code status 7FH. It is an extended preamble of the sister-standard, yuan, and can be allowed to -3, !! is the η-bit W to specify the memory access in the instruction level to reduce the amount of miscellaneous errors. < Nine 7 results [^ 75] In addition, 'Although the above uses the microprocessor as an example to explain the present invention and its objects, features and advantages, those skilled in the art can still perceive the scope of the present invention In micro processing, it can cover all forms of programmable devices, such as signal processors, industrial controllers (Industry Controllers (Introduction), array processors and other similar devices. The above, "," are only the preferred embodiments of the present invention, and should not be used to limit the scope of the present invention. Any equal changes and modifications made in accordance with the scope of the patent application of the present invention should still be It is within the scope of the patent of the present invention, and I would like to ask your reviewers to make a clear reference and analyze the benefits. (Please read the precautions on the back before filling this page) Order. Online Printed by the cooperative 34 This paper size applies Chinese National Standard (CNS) A4 regulations C210 X 297 mm>

Claims (1)

1245221 __ (Case No. 1〗 24008 Patent Specification Amendment) ABCD Correction Years ml Day 26. Patent Application Scope-(Please read the notes on the back before filling this page) 1 · A device that provides instruction-level control of memory attributes in a microprocessor, including: a translation logic for Translate an extended instruction into a microinstruction sequence, wherein the extended instruction includes: an extended preamble for referencing a memory specified by the extended instruction, and designating a memory characteristic, wherein the memory referenced by the memory The characteristics cannot be specified by an existing instruction in an existing instruction set; and an extended preamble tag to indicate the extended preamble, where the extended preamble tag is originally another in the existing instruction set According to the operation code specified by the architecture; and an extended execution logic, coupled to the translation logic, for receiving the micro-finger 々 sequence and applying the memory characteristics to execute the memory reference. 2. The device according to item 1 of the scope of patent application, wherein the extended instruction further includes instruction items of the existing instruction set. 3. The device as described in item 2 of the scope of patent application, wherein the instruction item specifies that the consumer-cooperative society of the Intellectual Property Bureau of the Ministry of Economic Affairs prints the-operation to be performed by the microprocessor, and wherein the operation includes the memory reference. 4. The device as described in the patent application @ Item 丨, wherein the reference to the button contains -operator manned operation, -operator stored operation, or both. 5. The device described in item 1 of the scope of patent application, wherein the memory characteristics refer to how a cache memory is used when the memory is executed by reference. 6. The device as described in item i of the scope of patent application, wherein the memory characteristics refer to the Chinese paper standard (CNS) A4 specification (21 οχ297 public shame) of the paper size I ABCD, patent application scope. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 26_ Preface 2 Think 4 Photo For other memory refer to the device described in the implementation of 7., where the extended preamble refers to the characteristics. Carefully touch and correct, shout—the device described in item 8 of the preset memory 8 range, where the extended preamble package ^ declares the device described in patent item 丨, wherein the extended preemption package belongs to Europe A shelf is used to specify the memory characteristic, wherein the memory characteristic includes a plurality of clocks and sounds. Special 10., a plurality of memory J co-authors, write through, write back and write protection. 11. The device as described in item 丨 of the scope of application for profit conversion, wherein the existing instruction includes the X86 instruction set. [2] If applying for a special device, the extended preamble mark contains the operation code FI (ICEBKPT) of the x86 instruction set. 13. The device according to item 丨 of the applied patent, wherein the translation logic includes a escape instruction detection logic for detecting the extended preamble mark; an instruction decoding logic for determining the execution to be performed An operation, wherein the operation includes the memory reference; and an extended decoding logic coupled to the escape instruction detection logic and the instruction decoding logic to determine the characteristics of the memory and to the microinstruction sequence Paper size applies to Chinese National Standard (CNS) A4 ^ (210X297 meal) (Please read the precautions on the back before filling in this tile) I ABCD patent application column specifies the memory characteristics. M.-A kind of extension-the existing instructions provide a microprocessor device that provides food control of the miscellaneous dragon, including ...- extension instructions, configured to specify-remember the bribe access-the memory belongs to I. Health The KNθ · 7 contains the pre-selected opcode 4 in the existing microprocessor instruction set, followed by the _ η bit extended preamble. The selected op code indicates the extended instruction, and the η bit Extended Preface_ indicates the memory attribute, wherein the memory attribute of the memory access cannot be specified according to the instructions of the existing instruction set; and-the translator generates a micro-instruction sequence to receive the extended instruction. The instruction-microprocessor performs memory access, wherein the memory access is performed according to the memory attribute. 15. The device described in claim 14 of the patent application, wherein the extended instruction further includes: the remaining instruction items' configured to specify the memory access, wherein the memory attribute is used when the memory access is executed Replaces a default memory attribute. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 16. The microprocessor device described in item 14 of the scope of patent application, wherein the η-bit extension preamble includes:. Her hidden characteristics have been turned into a lack of memory attributes for memory access, where the memory attributes include one of a plurality of memory access characteristics. 17. The microprocessor device according to item 16 of the scope of patent application, wherein these (210X297 mm) ABCD 1245221 7T, patent application scope Memory access features include non-cacheable, composite, and write-protected. ", Write through, write back ο As described in item 14 of the scope of patent application, please read the precautions of backing δ before filling in the extended preamble of the bits on this page, including 8 bits. Record the n 19 The microprocessor device described in item M of the application of the kiss kiss patent has an instruction set of χ86 microprocessor instruction set. ° The microprocessor device described in the application item n, wherein the register operation code includes The x86 code in the x86 microprocessor instruction set (the operation code F1). ^ The micro-point device described in item 14 of the scope of interest, wherein the reordering escape command detects H, which is used to ga The selection operation code in the extended instruction; an instruction decoder for decoding the rest of the extended instruction to determine the memory access; and, an extended special code decoder connected to the escape instruction side device And it refers to the “T Decoder” printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to decode the η-bit extended preamble and specify the memory attribute in the micro-instruction sequence. Add instruction-like slimming features to the existing instruction set The feature device includes: an escape tag, which is received by a translation logic, and indicates that the accompanying part of a corresponding instruction specifies a memory access, wherein the escape tag is one of the existing instruction sets. An opcode; a memory property designator, coupled to the escape tag, and the accompanying A8 B8 C8 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 1245221 ~ No. 09〗 124008 Amendment to the specification of Dali Case) D8 VI. One of the parts of the scope of patent application, which is used to specify one of the multiple memory characteristics Giving the memory access; and an extended execution logic coupled to the translation logic to perform the memory access using the specified memory characteristics, wherein the existing instruction set only provides a pre-processing of the memory access The designation of the memory characteristics is set, and the preset memory characteristics are replaced by the memory characteristics specified by the extended execution logic application. 23. The device according to item 22 of the scope of patent application, wherein the rest of the accompanying part includes a second operation code for specifying the memory access. 24. The device according to item 22 of the scope of patent application, wherein the memory characteristic designating element includes 8 bits. 25. The device according to item 22 of the scope of patent application, wherein the existing instruction set is an x86 instruction set. 26. The device according to item 22 of the scope of patent application, wherein the first operation code includes the ICEBKPT operation code (ie operation code π) in the x86 instruction set. 27. The device according to item 22 of the scope of patent application, wherein the translation logic translates the escape mark and the accompanying part into corresponding micro instructions, and the corresponding micro instruction instructs the extension execution logic according to the specified Memory characteristics to perform the memory access. 28. The device according to item 22 of the scope of patent application, wherein the memory characteristics include non-cacheable, composite write, write through, write back, and write protection. 29. The device according to item 22 of the scope of patent application, wherein the translation logic includes: a detailed disclosure of the escape mark, which is used to refine the escape mark 'and refers to the A4 specification (210X297 public director) (please first (Read the notes on the back and fill out this tile) I ABCD A member of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by 245221 ^, the translation of the accompanying part of the patent application scope shall be based on extended translation conventions; and a decoding logic, coupled to the escape mark detection logic, uses According to the convention of the existing 'order set, the translation action of the instruction is executed, and the translation of the corresponding instruction is executed according to the extended translation convention, so as to enable the execution of the memory access according to the specified memory characteristics. 3〇 · —A method for expanding an existing instruction set architecture to provide instruction-level selective memory attribute control. The method includes ... providing an extension instruction, which includes an extension mark and an extension preamble. Code, where the extension tag is one of the first opcode items of the existing instruction set architecture; the extension prefix is used to specify a memory attribute to be applied to a corresponding memory access, where the memory access system Specified by the rest of the extended instruction; and applying the memory attribute to perform the memory access, wherein the application action replaces a preset memory attribute of the memory access. 31. The method according to item 30 of the scope of patent application, wherein the action of specifying the memory attribute to be applied includes: first specifying the memory access in the rest of the extended instruction, wherein the first specified action includes Use a second opcode item in the existing instruction set architecture. 32. The method as described in item 30 of the scope of patent application, wherein the action of providing an extended instruction includes using an 8-bit size item to configure the extended preamble. This paper rule i is applicable to ^^? ^ 准 （CNS） 八 4 胁 （210X ^ 97 公 董） " " (Please read the precautions on the back before filling this page) A8 B8 C8 D8 I24522l Amendment to Specification No. 24008), Patent Application Range 33. The method described in Item 30 of the Patent Application Range, wherein the action of providing an extension of the dagger includes selecting the gift code item from the x86 microprocessor instruction set architecture . w Please read the precautions on the back before you write this page. • As described in Item 30 of the patent scope, the action of providing extended instructions includes selecting the x86 ICE BKPT operation code (that is, the operation of the scorpion nj as the extension mark). 35. The method described in item 30 of the scope of patent application, further comprising: translating the extended instruction into a micro instruction sequence, the micro instruction sequence instructs an extended execution logic to execute the memory storage based on the memory attributes. 36. The method according to item 35 of the scope of patent application, wherein the action of the translation extension instruction includes: detecting the extension mark in a translation logic; and decoding the extension preamble and the extension according to the extension translation rule. Extend the rest of the instruction to generate the micro-instruction sequence. 37. The method described in claim 30 of the patent scope, wherein the action of specifying the memory attributes to be applied includes: the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Prints out-of the following memory characteristics as the memory property that replaces the default memory attribute · Can not be cached, composite write, write-through, write-back and write-protected. This paper suitable scale quasi-fiscal S ^^ (CNS) Α4 Specification (male 6