TWI286325B - Semiconductor memory device and method of arranging signal and power lines thereof - Google Patents

Abstract

Method and apparatus for use, e.g., with synchronous dynamic random access memory (SDRAM) circuits are disclosed. In one described embodiment, three metal layers are deposited and patterned in turn overlying a memory array portion of an SDRAM. Relatively wide power conductors are routed on a third metal layer, allowing power conductors to be reduced in size, or in some cases eliminated, on first and second metal layers. The relatively wide power conductors thus can provide a more stable power supply to the memory array, and also free some space on first and/or second metal for routing of additional and/or more widely spaced signal conductors. Other embodiments are described and claimed.

Description

1286325 17116pif.doc IX. Invention Description: This application claims Korean Patent Application No. P2004-40542 filed on June 3, 2004 with the Korea Intellectual Property Office and P2004-74730 on September 17, 2004. The benefit of the priority of the number is disclosed in this specification. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a dynamic random access memory (D RA Μ) semiconductor device, and more particularly to overlying the device, in a patterned metal layer, routing power and Method and apparatus for signal traces. [Prior Art] A DRAM device includes a memory array, a circuit for accessing the memory array, and peripheral circuits for controlling DRAM operation and communication together with external components. A conventional memory array consists of a repeating array of secondary memory cells interspersed in a portion of the circuit used to access the memory array, and the remaining access circuits are typically located at the edge of the memory array. Inside the decoder. 1 illustrates a conventional memory configuration that includes a memory array 10, a row decoder 20, and a column decoder 30. The memory array 10 is configured much like a checkerboard; the secondary memory cell arrays (SMCAs) are vertically separated by sub-word lines, actuators (SWDs) and are applied horizontally to sense amplifiers (SAs) of memory cells. Separate. Each sub-memory cell array includes a plurality of memory cells (MC), each of which is composed of a secondary word line (SWL)-driven access transistor and a capacitor for storing data. The SAs are vertically separated by the connected areas (CJs), which contain control signal generating circuits for the SAs. 7 1286325 17116pif.doc / The decoder 20 generates signals on the row select lines (CSLs) to select ___to the township line for reading and writing according to a provided row address (CA). The column decoder 30 reacts to a provided column address by selecting a -line and a word 7-line selection signal in a plurality of U main character lines (NWE) to initiate a column in the array. Memory cells. Other aspects of Figure 1 will be explained in conjunction with a more detailed illustration of a portion of memory array 10 illustrated in Figure 2. Two memory cells, M c丨 and M c 2 , were shown in SMCA1 and SMCA2, respectively. Each memory cell includes a capacitor C, which is connected to a cell plate voltage (Vp) and a source for accessing the transistor ν. Typically, Vp is half the supply voltage. The gate of each access transistor (N) is controlled by a corresponding sub-word line (sw L) with SW L1 controlling the access transistor of M C1 and SWL2 controlling the access transistor of MC2. . The drain of each access transistor is connected to a corresponding bit line (BL), such as BL1 to MCI and BL2 to MC2. Each bit line is also connected to other memory cells (not shown) in the respective SMCAs by means of access transistors (not shown) connected to the SWLs. One sense amplifier block is between Smcai and SMCA2. Referring to SMCA1, BL1 and BL1B are connected to a precharge circuit PRE1' in SA1 and connected to a pair of sense bit lines SBL and SBLB through a bit insulation gate iso1. As for SMCA2, BL2 and BL2B are connected to the precharge circuit PRE2 in SA1, and are connected to a pair of sense bit lines SBL and SBLB through a bit insulation gate IS02. A bit sense amplifier BLSA and a data output gate I0G are also connected to sense bit lines SBL and SBLB. 1286325 17116pif.doc The bit sense amplifier amplifies the voltage difference between BL1 and BL1B in memory cell MCI. For example, in the following sequence, memory cells represent two logical states (multiple state memory cells also exist and One of the more sophisticated sense amplifier circuits is known. The insulating gate IS01 is connected to BL1 to SBL, and is also connected to BL1B to SBLB. The precharge circuit PRE1 charges BL1 and BL1B to a voltage midway point, which is a voltage between a discharge capacitor c (say, logic 0) and a charge capacitor C (in the same example, representing logic 1). between. SWL1 is energized to couple the memory cell capacitor within the MCI to BL1. When the cell capacitor is discharged, the charge sharing effect causes the voltage on BL1 to decrease relative to BL1B. When the cell capacitor is charged, the charge sharing effect causes the voltage on BL1 to increase relative to BL1B. After the charge sharing effect is completed, the insulating gate 18〇1 starts to be effective, so that a slight voltage difference between the bit lines BL1/BL1B is transferred to the sensing bit lines SBL1/SBL1B. In either case, the bit sense amplifier BLSA is activated during the preset period to sense and amplify the small voltage difference between the bit lines BL1/BL1B. When the output IOG is started, SBL and SBLB are coupled to a pair of regional output lines LIO and LIOB, which are also connected to other output gates in other SA areas (not shown) above and below SA1. i〇G. Here, the output gate IOG is activated to react to the row selection line CSL (not shown). When LIO and LIOB are active, a region's overall output gate LGIOG servo selectively couples LIO and LIOB to a pair of integral output lines GI〇 and gi〇b. Thus the sensed memory cell state is coupled to a peripheral output-in circuit. 9 1286325 17116pif.doc It can be seen from Figures 1 and 2 that a large number of wires are routed through the memory array. The NWE line passes over the cell array and is vertically routed across the memory array, and the PX, LIO, and LIOB lines are routed vertically across the memory array via the connection region and the sense amplifier region. The CSL, GIO, and GIOB lines are routed vertically across the memory array via the secondary § cell array. The power line is not drawn, and the line must also be routed across the memory array to provide power I to the circuits in the SA, CJ, and SWD blocks. Figure 3 shows an area of the memory array 1 ,, which omits the detailed circuit below, and is explained by the metal traces overlying it. On the first metal layer, the LIO, PX, and NWE traces are separated from the first power line pi, which provides different equipotential voltages required by the memory array circuitry. Some of the first power lines P1 may include a ground voltage line (VSS) and a power line (VCC). The other first power line P1 may include a reference voltage line (Vref), a negative (VBB) ^ 〇cl and a GIO trace separated from the second power line P2, the power line providing different equal bits Voltage. Some of the second power lines P2 may also include a ground voltage line (vSS) and a power line (VCC). The other second power line P2 may include a reference voltage line (Vref), a negative power line (VBB), an enhanced voltage line (vpp), and the like. Where the P2 traces of the same bit voltage are overlaid, the two traces are connected together to create a gate. ! The > 2 trace is connected to a power supply located outside the memory array area of the dram element. '. Figure 4 shows a simplified block diagram of the column decoder 3 of Figure 1. The column decoder 30 includes a column address decoder region 3 (M and a column address predecoder region 1286325 17116pif.doc 30 2 in the column address decoder region 3〇_丨, each of which is depicted A decoder area RD1 generates a word line selection signal, and each of the second decoder areas RD2 is shown to generate a main word line signal: ^^¥]£, corresponding to the sequentially listed address. The column address ra and the pre-decoded address DRA generated by the decoder area 3〇-2. 舅5 shows a part of the area of the column decoder 3〇, which omits the detailed circuit below, but covers the metal traces above it. The line is explained. On the first metal layer, 'covering a first decoder region rD1, the signal line 81 (for example, ρχ line) is on the side of the first power lines PVINT1 and PVSS1. On the first metal layer, covering a first The second decoder area RD2, the signal line S1 (for example, the NWE line) is on the side of the additional first power lines PVINT1 and PVSS1. The second metal layer includes the signal line S2 (for example, the RA line and the DRA line) and the second power line. PVINT2 and PVSS2. PVINT2 is connected to PVINT1 and overlaps, and PVSS2 is connected to PVSS1 and overlaps. The PVINT2 and PVSS2 traces are connected to a power supply located outside the memory array area of the DRAM component. In this case, the power supply line cannot be designed as a wider line without increasing the chip area. When the ratio is reduced to a smaller cell size and or the number of cells in the memory array is increased, more signal lines per unit area are passed through the memory array and the column decoder; and this unit area is essentially the previous servo. The same area of a smaller number of signal lines. The width of the power line is therefore proportionally reduced to suit a denser memory array. However, reducing the width of the power line is not good; when reducing the width of the power line, Causes a large resistance to the current 11 1286325 17116pif.doc, a large voltage drop and power supply; Xiao consumption, counting - a:: == set U double θ to help her, will (four) enhance the message [implementation The following embodiment uses a three-layer metal layer on the memory array, column decoder, and or row decoder. In these embodiments, a wider power line is usually possible and can improve the power. The distribution and stability of the embodiments. The differences between the embodiments can be clearly seen from the following description of the illustrations. Figure 6 illustrates the first implementation of a memory array using a three-layer metal layer on the signal line and power line. For example, the first metal layer includes NWE, pχ, U0 signal lines, and P1 power lines, which is similar to the prior art. The second metal layer includes CSL and GIO 矾 lines, but no power lines. The third metal layer includes P3 power lines. The line is perpendicular to the P1 power line formed on the first metal layer. Since the CSL line and the GIO line do not compete with the metal layer 3 overlying the memory array, the P3 power line can be formed by using the prior art. The P2 power line on the two metal layers is wider. Although for clarity, Figure 6 does not show the characteristics of the P3 power line, some parts of the power line can even cover the CSL and GIO lines. At the same voltage, 12 1286325 17116pif.doc

P3 power, the line covers the P1 power line, the connection of the power line, there is a gap problem, the joint can be connected (the direct connection between the third metal layer and the first metal layer) or welded with a medium P2 Click to connect to metal layer 1. The p3 power line can therefore be routed with less resistance and improved power distribution. The spacing between CSL and GIO is also improved by the lack of p2 traces, reduced crosstalk, and enhanced signal transfer speed. Φ Figure 7 illustrates a second embodiment of a memory array using a three-layer metal layer over the signal line and power line. In this embodiment, the P1 power line is not on metal layer i, and the P2 power line is parallel to CSL and GIO on metal layer 2 and distributes power to the memory array circuitry. The P3 power cable is placed on the metal layer 3, perpendicular to the p2 power line, and connected to the P2 power line where the P3 power line and the power line have the same voltage crossing. The P2 power line can be kept relatively thin when the P3 power line can be made wider to effectively deliver current to the desired area. Figure 2 illustrates a third embodiment of a memory array using a three-layer metal layer over the signal line and power line. In this embodiment, the thin power cord is connected to the thin • power cord. The P1 and P2 power lines of the same voltage are connected at the intersection: the wide P3 power line is routed in parallel through the P2 power line, and is usually superimposed on the P2 power line of the equipotential voltage. When the P3 and P2 power lines are stacked along their length, the connection between the two lines can be made in an elongated pipe or in a small connecting column used by g. When P3/P2 shares the metal layer with CSL and GIO, but has very little space, the P3/P2 structure still has a low resistance per unit length. One 13

1286325 17116pif.doc Figure 9 illustrates a fourth embodiment of a memory array using a three-layer metal layer over the signal line and power line. In this embodiment, the metal layer 1 is fine? 1 power line, which is routed through the NWE line in parallel. Metal layer 2 contains a thin P2 power line that is routed vertically through the P1 power line and parallel to the CSL and GIO lines. Where the P2 power line of the same voltage crosses the Pi power line, the two lines are connected together. Metal layer 3 contains a relatively wide P3 power line, and with? 1 The power lines are parallel, and the preferred routes are overlapped together, and the Η power line with the same bit voltage is below. In the P3 power line with the same bit voltage? 2 The power lines cross each other and the two wires are connected together. Figure 10 illustrates a fifth embodiment of a memory array using a three-layer metal layer over a signal line and a power supply line. This embodiment is similar to the third embodiment (Fig. 8), but the GIO line is routed through the metal layer 3 instead of the metal layer 2. This is an attractive, generational approach because the overlapping P2 and p3 power lines can act as a single wire with low resistance to allow the P3 power line to be not too wide, and the work room, seven to the genus The nickname line on 3. Therefore, the line spacing between the csls lines can be larger to reduce the coupling noise. In order to route the signal line and the power line over the column decoder, it is preferred, but not necessary, to carry out the different types of embodiments in combination with the embodiments. ® 11 explains the realization of a column-column decoder. A relatively thin power supply line PVINT]^PVSS1, a 2-sided column decoder circuit is provided on the first metal layer. For example, the bay is operated from the top to the bottom, facing the outside of the calcite region, and leaves a section covering the RD1 to operate the signal line in the first metal. Its 1286325 17116pif.doc his column The decoder signal line S2 is formed on the second metal to operate perpendicular to the PVINT1, PVSS1, and S1 lines. On the third metal layer, relatively wide power supply lines PVINT3 and PVSS3 operate in parallel with the phantom line, each of which is overlapped with one or more signal lines S2. Where PVINT3 and PVSS3 overlap rather than overlap with the phantom, a connection point is formed between the two power lines. Similarly, where pvg;s3 and PVSS1 0 overlap rather than overlap with S2, a connection point is formed between the two power lines. In this embodiment, the connection may involve a via post partially filled with metal layer 2, but no power line of continuous metal layer 2 is present. The connection can be made directly between the metal layer 3 and the metal layer 1 (connecting a contact). The advantage of this configuration is that the Rong Luwu metal layer 2 has extra space to despread or increase the number of S2 lines, and also provides power distribution through the metal layer 3 of a larger cross section than the power line on the metal layer 2 of the prior art. . Figure 12 illustrates an embodiment of a second column decoder similar to that of Figure 11, except that additional power lines PVINT2 and PVSS2 are used on metal layer 2, which operates in parallel with the outer signal line S2. In the overlap of PVINT2 and PVINT1, a connection point is formed between the two power lines; a similar connection is made between pVSS2 and PVSS1. PVINT3 and PVINT2 overlap (and can also overlap with one or more signal lines S2) and are connected between the two power lines of pVINT3 and PVINT2. This connection can be a narrow channel or a series of small connected columns along the length of PVINT3 and PVINT2. The same configuration and connections also exist between PVSS3 and PVSS2. 15 1286325 17116pif.doc An embodiment of a third column decoder similar to that of FIG. 11 is explained. PVINT1 and PVSS1 are placed in the middle, but above the column decoder area RD1, the signal line si is located outside the pvinti and pvssi. Here, PVINT2 and PVSS2 are not present on the second metal layer. Figure 14 illustrates an embodiment of a fourth column decoder similar to that of Figure 12. PVINT1 and PVSS1 are placed in the middle, but above the column decoder area RD1, the signal line S1 is located outside of PVINT1 and PVSS1. Here, pviNT2 and PVSS2 are present along with the signal line S2 on the second metal layer. In order to route the signal and power lines over the row decoder, a different type of embodiment that is preferably, but not necessarily, combined with any of the previous embodiments is also presented herein. Figure 15 illustrates an embodiment of a first row decoder, for example, for use with the Figure 10 embodiment having a GIO line on metal layer 3. The row decoder 2 〇 uses the signal line S1, and the power lines PVINT1 and PVSS1 are located on the metal layer 1, and the bit line S2, the power lines PVINT2 and PVSS2 are located on the metal layer 2 above the metal layer 1. However, on the metal layer 3, the GIO lines of the metal layer 3 (and the power lines on the metal layer 3 that can be selected for Φ, not shown, providing power to the memory array) are overlaid on the memory array and continuously traversed directly The row decoder is an output-in circuit (not shown) that faces the periphery. Figure 16 illustrates an embodiment of a second row decoder similar to that of Figure 15 which causes the GIO line to pass through a row decoder on metal layer 3. However, just after passing through the row decoder, each GIO line is connected to a Gi〇 line through a connecting post and continuously traversed, for example, a memory array on metal layer 2 as depicted in Figures 6-9. 16 1286325 17116pif.doc Anyone skilled in the art will understand that the imagination is one of the described embodiments. Other routing arrangements can be separated by intervals, as these are within the structure. Absolute line width and number. Minor modifications and detailed functional requirements for processing and processing requirements are considered to be within the scope of this patent application. I3 In the embodiments of the present invention, the previous embodiments are merely examples. Although the script may quote "one", "one, and; in some places only, it means that this does not necessarily mean that every reference to Lt," or "some" is only applicable to the implementation of the single- example. H ° application example, the finger refers to this feature book = this book has been fed on the implementation of the knitting wire, the financial face is used to limit the inside \ can be familiar with this skill, without leaving the spirit and scope of the invention: Application === is the scope of protection of the present invention. [Simplified description of the drawing] A generalized memory array of the memory element and a part of the external memory array are enlarged and displayed in detail, and the detailed display of the figure 3 is also shown in the figure. A portion of the memory array is shown in an enlarged view. This figure specifically illustrates the signal of the double-layer metal layer on the array and the power trace. FIG. 4 shows a partial enlarged view of the m-column decoder, and the external circuit and the signal line. Λ 17 1286325 17116pif.doc Figure 5 also shows a partial enlarged view of the column decoder of Figure 1, which is specifically designed for the routing of signal and power traces over a two-layer metal layer over a column decoder. 6-10 illustrate various embodiments showing signal lines and power lines routed through a three-layer metal layer of a memory array. Figures 11-14 illustrate various embodiments showing the signal and power lines of a three-layer metal layer routing a column decoder. Figures 15-16 illustrate various embodiments showing the signal lines and power lines of the three-layer metal layer of the routing pass decoder. [Main component symbol description] 10 • Memory array 20: Row decoder 20': Row decoder 30-1: Column address decoder area 30-2: Column address predecoder area 30: Column decoder 100: Memory configuration BL (bit line): Bit line BL1B (bit line): Bit line BL2 (bit line): Bit line sense amplifier: Bit sense amplifier C (capacitor): Capacitor CA (cell array ): Cell array 1286325 17116pif.doc CA (column address): row address CJ (conjunction region): link area CSL (column select line) · • row select line DRA (pre-decoding row address): pre-decode address GIO (global input/output line): IOG (input/output gate): output isolation gate ISO (bit isolation gate): bit global isolation gate LGIOO (local global input / output gate): regional overall output gate LIO ( Local input/output line): local input/output line: local area input line MC (memory cell): memory transistor N (access transistor): access transistor NWE (main word line): main character Line PI (first power line): The first power line P2 (second power line) ·· Second power line P3 (precharge circuit): precharge circuit PVINT 1 (first power line): first power line PVINT2 (second power line): second power line PVINT3 (third Power line): third power line P VS SI (first power line) ··first power line PVSS2 (second power line): second power line 19 1286325 17116pif.doc P VS S3 (third power line): third power supply Line line select: RA (row address): RD1 (first decoder area): first decoder area RD2 (second decoder area): second decoder area 51 (signal line) Signal line (signal line): signal line SA (sensing bit line): sensing bit line SBLB (sensing bit line) · sensing bit line SMC A (sub memory cell array) · memory cell array SWD (sub word line driver): sub-word line driver SWL (sub word line): sub-word line

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Claims (1)

4 Repair (more) 13⁄43⁄43⁄4 page Revision date: December 11, 1995 The insulating layer is padded in the patterned metal layer except that the hole of the insulating layer is used to provide electrical contact with the trace, and the actual edge of the insulating layer; ' 1286325 is the Chinese patent range of No. 94118121 Line Correction 17116pif.doc X. Patent Application Range: 1. A semiconductor dynamic random access memory (DRAM) component, including: - Memory cells (4), including - repeating column/row format cell blocks, each cell block Including a memory-like fine-transfer, and a sense amplification II block and a sub-word line driver block combined with the secondary memory cell array; the first, second, and first configured above the memory cell array The three patterned metal layer 'each patterned metal layer includes a plurality of traces; and wherein the first patterned metal layer trace comprises ... a plurality of substantially parallel regions of the output line, each line and the cell block a plurality of sense amplifier sections arranged in a column are coupled, a plurality of first power lines to provide memory cell array power, and the power line actually runs in parallel with the regional output lines; Μ $number of main character lines, the line actually runs in parallel with the regional round-out line, and the parent line is connected with a plurality of sub-line driver blocks arranged in a column in the cell block; wherein the second patterned metal layer trace The line contains a plurality of strips that are actually parallel rows, each of which is connected to the output and the closed pole in the cell block; wherein the third patterned metal layer trace includes a plurality of third power lines for the sake of 5 Cell array power; and ' 21 1286325 17116pif.doc where at least the lines in the second and third patterned metal layers contain more of the total output line of the line', the line actually runs, and each line turns out the line Connected to a large number of cell blocks, selectively multi-transports a number of areas to output the human line to the overall output line. 2. If the application is as disclosed in (4), the transfer is returned to the machine (4) and the memory (DRAM) is read. The third power line is actually running with the line. 4 3. The semiconductor ItlKDRAM), as described in claim 2 of the patent scope, is provided with a number of first-power lines to provide parallel operation of the memory cell array in parallel with the line. 4. If the semiconductor memory (DRAM) component described in the third paragraph of the patent application is applied, J: Zhongyi Yitang, store _ ° line actually covers one of the corresponding one power cord, Connected together. "5. For example, the width of each of the third power lines is actually greater than the width of the second power line below." The semiconductor dynamic random access memory device of claim 4, wherein all of the overall output human lines are present on the third patterned metal layer. 7. The semiconductor dynamic randomness as described in the fourth patent scope Access memory (DRAM) component 'where the mth line actually runs perpendicular to the row select line. I286325 17116pif.doc 8·If you want to ask for the seventh item in the township, = the component 'where the second patterned metal layer trace is more than one 苐-power cord' to provide memory cells _ power and line Select lines to run in parallel. The electric line is 9. If you apply for the semi-conductive (four) state memory (DRAM) component of the eighth item of Weiwei, at least one of the third power lines, at least one of the first-power lines, Connect at the intersection between the third line and the bottom: ς source line. - Electricity 10. The semiconductor dynamics with memory (DRAM) component of claim 7 wherein at least one of the third power lines is overlaid on a corresponding one of the first power lines And connected. 11. The semiconductor dynamic memory (DRAM) component of claim 1, wherein at least one of the third power lines has a width that is substantially greater than a width of the first power line below. '', 12. The semiconductor dynamic random access memory (PRAM) component according to the scope of the patent application, further comprising a row decoder at the periphery of the memory cell array, and at least some of the row selection lines A line connection in which at least some of the integer rounds of incoming lines cross the row decoder and route through the third patterned metal layer trace as they pass the row decoder. A semiconductor dynamic random access memory (DRAM) device according to claim 12, wherein at least one of the overall output lines is routed past the memory cell array. Patterned metal layer traces. The semiconductor dynamic random access DRAM (DRAM) component of claim 12, wherein at least one of the overall output lines is crossed over the memory cell array. Place, routed through the second patterned 'genus layer trace. 15. A semiconductor dynamic random access DRAM (DRAM) component as described in claim 1 wherein all of the integral output lines are present on the second patterned metal layer. The semiconductor dynamic random access memory (DRAM) device of claim 15, wherein the second patterned metal layer trace further comprises a plurality of second power lines to provide memory cell array power, Most of the second power lines actually run in parallel with the row select lines. 17. The semiconductor dynamic random access memory (DRAM) component of claim 16, wherein the plurality of third power lines actually operate vertically with the row select lines. 18. The semiconductor dynamic random access memory (DRAM) component of claim π, wherein at least one of the third power lines is actually covered by a corresponding one of the first power lines A semiconductor dynamic random access memory (DRAM) device according to claim 18, wherein at least one of the third power lines is actually covered by a corresponding first power source One of the wires, the connection between the two exists in the communication column, the communication column allows at least one third power line to directly engage with one of the corresponding first power lines. 24 1286325 17116pif.doc 20 - A semiconductor dynamic random access memory (DRAM) component, comprising: a memory cell array comprising a repeating column/row format cell block, each cell block comprising a secondary memory cell array, And a sense amplifier block and a sub-word line driver block combined with the sub-memory cell array; the first, second, and third patterned metal layers disposed above the § memory cell array, each pattern The metal layer includes a plurality of traces; and an insulating layer surrounding the patterned metal layer, the insulating layer actually insulating the traces except that the holes of one of the insulating layers are used to provide electrical contact with the traces; The first patterned metal layer trace comprises: a plurality of consecutive parallel input and output lines, each line being coupled with a plurality of sense amplifier sections arranged in a column in the cell block, ^ number of main words a line that actually runs in parallel with the regional input and output lines, each line and a plurality of sub-word line driver blocks arranged in a column within the cell block Connecting; wherein the second patterned metal layer trace comprises: · a plurality of strips are actually parallel row select lines, each line is connected to an output gate arranged in the cell block; the second thread of the strip is called Memory cell array power, the second power line actually runs in parallel with the row select line; and 25 1286325 17116pif.doc The overall output is entered into the line, the line actually runs, and the total output line of each line is connected to a majority of the packages = 2 lines of multiplex transmission. Most ships take the whole round of the round wire to select which The third patterned metal layer trace comprises a plurality of memory cell array powers. The Wo-Wen source line is a semi-conductive memory (DRAM) component as described in the scope of the patent (4), wherein the third power line actually runs in parallel with the row =. " 22. For example, (4) a semiconductor dynamics with memory (DRAM) component, wherein each third power line actually covers one of the corresponding second power lines, and connection. 23. The semiconductor dynamic random access memory (DRAM) component of claim 22, wherein each third power line width is substantially greater than a width of the second power line below. The semiconductor dynamic random access memory (DRAM) component of claim 20, wherein the first patterned metal layer trace further comprises a plurality of first power lines to provide memory cell array power. The semiconductor dynamic random access memory (DRAM) component of claim 20, wherein the third power line actually runs vertically with the row select line. 26. The semiconductor dynamic random access memory (DRAM) component of claim 25, wherein at least one of the third power lines is actually covered by a corresponding one of the first power lines And connected. 26 A plurality of consecutive parallel regions are input and output lines, and each line is coupled with a plurality of sense amplifier segments arranged in a column in the cell block, and a plurality of first power lines are provided to provide memory cell array power. The line actually runs in parallel with the regional output line; and 1286325 I7ll6pif.doc 27. A semiconductor dynamic random access memory (DRAM) component, including: - a memory cell array, including - repeating column/row format cell blocks, Each cell block includes - one: Wei-_, and a sense amplification block and a sub-word line driver block combined with the secondary memory cell array; the first, second, and above the memory cell array And a third patterned metal layer, each patterned metal layer comprising a plurality of traces; and an insulating layer 'padded around the patterned metal layer except that one of the insulating layer holes is used to provide electrical contact with the trace In addition, the insulating layer actually insulates the trace; the first patterned metal layer trace of t includes: ^ y a plurality of main word lines, the line actually intersects with the area input line The translation block _ is set to - touch most of the sub-words where the second patterned metal layer trace contains ·· Configure the line at the fine === line select line 'per-green connection to the second power line array power' 1286325 17116pif.doc The majority of the overall output line 'this line actually runs in parallel with the row selection line, each integral input line is connected to a number of cell blocks, in order to selectively multiplex the majority of the area output line into the overall output line, The third patterned metal layer trace includes a plurality of third power lines to provide memory cell array power, each of the third power lines respectively overlapping one of a corresponding second power line, and the trace width Greater than the width of the second power cord below. 28. A semiconductor dynamic random access memory (DRAM) component, comprising: a memory cell array comprising a repeating column/row format of cell blocks, each cell block comprising a memory cell array and a sense amplifier a block and a sub-word line driver block are coupled to the secondary memory cell array; the first, second, and third patterned metal layers disposed above the memory cell array, each patterned metal layer including a plurality of traces And an insulating layer, the pad is around the patterned metal layer, except that the hole of one of the insulating layers is the wire providing contact with the trace t, the insulating layer actually insulating the trace; wherein the first patterned metal layer The traces include: Most of the parallel parallel regions output the human line, each line is in line with the majority of the sensing amplification area in the cell block = configured as a column, the power line actually field::: line recall : Array _ ^ 28 1286325 17116pif.doc Most of the main character lines, the line actually runs in parallel with the regional output line, each line is arranged in a column with a majority in the cell block Sub-character line driver block connections; wherein the second patterned metal layer trace comprises a plurality of second power lines to provide memory cell array power; and wherein the third patterned metal layer trace comprises: Parallel row selection lines, each line connected to a plurality of sense amplifier segments arranged in a row within a cell block; and a plurality of overall output lines that actually run in parallel with the row select lines, each overall output The incoming line is connected to a plurality of cell blocks to selectively multiplex the majority of the area output lines into the overall output line. 29. A semiconductor dynamic random access memory (DRAM) component, comprising: a column decoder that generates a signal on a plurality of main word lines and includes a plurality of control circuits; a first one disposed above the column decoder Second and third patterned metal layers, each patterned metal layer comprising a plurality of traces; and an insulating layer padding around the patterned metal layer except that one of the insulating layer holes is provided to provide trace creation In addition to the electrical contact, the insulating layer actually insulates the trace, wherein the first patterned metal layer trace comprises: a plurality of first signal lines, each line connected to one of the preset control circuits; and 29 1286325 17116pif .doc The power line is actually a plurality of first power lines to provide power in parallel with the first signal line; wherein the second patterned metal layer trace comprises a plurality of second signal lines on the solid bar, the line actually And the third patterned metal layer trace includes a plurality of third power lines to provide power; the third power line is actually configured to be connected to the first signal line; It is configured to line with the second signal and actually covers some of the at least second signal lines. 30. The semiconductor dynamic random access memory (DRAM) component of claim 29, further comprising a sensation cell array proximate to the column decoder, wherein at least some of the first power lines provide power To the memory cell array. 31. The semiconductor dynamic random access memory (DRAM) component of claim 29, further comprising a memory cell array proximate to the column decoder, wherein at least some of the third power lines provide power to Memory cell array. 32. The semiconductor dynamic random access memory (DRAM) device of claim 29, wherein the second patterned metal layer trace further comprises a plurality of second power lines to provide power; the second power line Running in parallel with the second signal line, the width of each second power line is on the width of the third power line. 33. The semiconductor dynamic random access memory (DRAM) component of claim 32, wherein at least one of the third power lines substantially covers at least the second one of the second power lines . The semiconductor singular random access memory (DRAM) component of claim 32, wherein at least one of the third power lines crosses the central half of each control circuit. . 35. The semiconductor dynamic stagnation random access memory (DRAM) component of claim 29, wherein at least one of the third power lines crosses the central half of each of the control circuits. 36. A semiconductor dynamic random access memory (DRAM) component, comprising: a column decoder comprising a column of decoder cells; first, second, and second patterned metal layers disposed above the column decoder 'Each patterned metal layer includes a plurality of traces; and an insulating layer, padded around the patterned metal layer, except that the holes of one of the insulating layers are used to provide electrical contact with the trace, the insulating layer is actually An insulated trace; wherein the first patterned metal layer trace comprises: ^ a plurality of signal lines, each signal line is connected to a corresponding decoder cell; and a plurality of first power lines are provided to provide power, The power line actually runs in parallel with the brother-signal line; wherein the second patterned metal layer trace comprises: a plurality of substantially parallel second signal lines, the line is actually configured to be perpendicular to the brother-signal line, and 31 1286325 I7l I6pif.doc I want to run the second power cord in parallel with the second signal line; and the line three map/chemical layer trace contains a number of third power supplies: The power line is actually configured to be the second signal The line is flat and overlaps at least the second signal line and the second power line. 37· Please ask for a special (4)% of the semiconductors to be dynamically stored. A dram component in which one line of the first power line provides an internal operating voltage above each decoder cell and the other line of the first power supply provides a ground voltage. '' 38. The semiconductor dynamic random access read (DRAM) component of claim 37, wherein the first power supply line providing internal operating voltage is provided above each decoder cell Another grounding voltage, the first power line, is configured to be in close proximity together, while at least nick line covers the decoder cell, and the outer side of the first power line provides an internal operating voltage; There is another first-signal line covering the decoder cell and the ground side of the first power line providing a ground voltage. 39. The semiconductor dynamic random access memory (DRAM) component of claim 37, wherein at least two first signal lines are placed immediately adjacent each decoder cell; the first signal line The internal operating voltage is supplied to the outside of those signal lines on one side, and the first signal line provides a ground voltage to the outside of those signal lines on the other side. 32 1286325 17116pif.doc 40. A method of powering a power line and a signal line. The method includes: providing a main power trace on a third metal layer on a DRAM array; connecting a main power trace to the first metal The layer-layer secondary power trace 'the secondary power trace has at least the trace width on the master layer; and the original trace has a smaller €. The region on the first metal layer provides the "line 41". For example, in the scope of application for patents, item 4, +, , , and supply line. You are happy to go to the level of 42. Please refer to the method of covering the DRAM array, and enter the msL money. The overall output is included in the line. It also includes the routing of 4" on the second metal layer. "The fourth line and the signal line are covered by the method package on the DRAM array-;f for the overall output line. The method further includes: on the second metal layer, a method for covering the power line and the signal line on the dram array, the method comprising: providing a main power trace on the third metal layer; a power trace to a secondary power trace of at least one of the first metal layer and the second metal layer, the secondary power trace having a smaller trace width than the primary power trace; and the first and second metal layers A signal line is provided. 33