DE102005026637A1 - Semiconductor dynamic random access memory device comprises power lines formed on respective metal layers arranged at row and column decoders, having different widths - Google Patents

Abstract

The device has power lines (P1,P2) formed on respective metal layers arranged at row decoder and column decoder, for supplying power to the memory array. The power line (P3) formed on the metal layer has larger width and the power line (P1) formed on the metal layer has smaller width. Signal lines (GIO,LIO) are routed such that the signal lines are isolated more broadly. An independent claim is also included for power and signal line routing method on the dynamic random access memory (DRAM) array.

Description

The The invention relates to a semiconductor device with a dynamic Random access memory (DRAM) and a method of arrangement of power and signal lines in structured metal layers, the above such a building block.

DRAM devices include a memory array, circuits to access the memory array access and peripheral circuitry to control DRAM operation and to communicate with external components. Typical memory fields are from a repeating pattern of sub memory cell fields Shaped, interspersed with a part of the circuits that uses to access the memory field. The rest of the access circuit is ordinary in a row decoder and a column decoder at the edges of the Memory array arranged.

1 shows a typical memory arrangement 100 comprising a memory array 10 , a column decoder 20 and a row decoder 30 , The memory field 10 is similar to a chessboard applied, with sub memory cell arrays SMCAs, vertically separated by sub-word line driver SWDs and horizontally separated by sense amplifier SAs for the memory cells. Each of the sub memory cell arrays includes a plurality of memory cells (MC), each of which is composed of an access transistor activated by a sub-word line SWL and a capacitor to store data. The SAs are vertically separated by connection areas CJ including control signal generation circuits for the SAs.

The column decoder 20 generates signals on column select lines (CSL) to select one or more columns of the field to read or write according to an applied column address (CA).

The row decoder 30 responds to an input row address to activate memory cells in a row of the array by selecting one of a plurality of main word line (NWE) and word line select (PX) signals.

Other aspects of 1 be related to 2 explains what another detail of a part of the field 10 shows. Two memory cells MC1 and MC2 are shown in SMCA1 and SMCA2, respectively. Each memory cell comprises a capacitor C which is connected between a cell plate voltage Vp and the source of an access transistor N. In general, Vp is equal to half the supply voltage. The gate of each access transistor N is controlled by a corresponding sub-word line (SWL), SWL1 controlling the MC1 access transistor and SWL2 controlling the MC2 access transistor.

The Drain of each access transistor is connected to a corresponding bit line BL connected, e.g. BL1 for MC1 and BL2 for MC2. Each bit line is also connected to other memory cells (not shown) in the corresponding SMCAs, with access transistors (not shown) are connected to other SWLs. A sense amplifier area SA1 is between SMCA1 and SMCA2. With respect to SMCA1, BL1 and BL1 are B connected to a precharge circuit PRE1 in SA1 and are with a pair of read bit lines SBL and SBLB through a bit isolation gate ISO1 connected. In terms of SMAC2 are BL2 and BL2B with a precharge circuit PRE2 in SA2 and connected to the pair of read bit lines SBL and SBLB Bit isolation gate ISO2 connected. A bit line sense amplifier BLSA and a data input / output gate IOG are also included connected to read bit lines SBL and SBLB.

Of the bitline reinforced the voltage difference between BL1 and BL1B of the MC1 memory cell for example, in the following sequence, wherein the memory cell has a of two logical states shows (multi-state memory cells exist as well and use typically a more complicated sense amplifier circuit). The isolation gate ISO1 connects BL1 to SBL and BL1B to SBLB. The precharge circuit PRE1 loads BL1 and BL1B to a voltage in the middle between the voltage a discharged capacitor C (which represents, for example, a logical 0) and the voltage of a charged capacitor C (which in the same example represents a logical 1). SWL1 is powered to the Pair MC1 memory cell capacitor with BL1. If the cell capacitor was discharged, causing a charge sharing that voltage BL1 decreases relative to BL1B. When the cell capacitor is charged Charge sharing causes the voltage at BL1 to be relative increases to BL1B. When the charge sharing is completed, will the isolation gate is activated ISO1, leaving a small voltage difference between the bit lines BL1 / BL1B to the read bit lines SBL1 / SBL1B is passed on. In any case, the sense amplifier is BLSA while a predetermined duration activated to the small voltage difference between the bit lines BL1 / BL1B and amplify.

The input / output gate IOG, when activated, couples SBL and SBLB to a pair of local input / output lines LIO and LIOB, which also operate with other 10-gates in others SA areas (not shown) are connected above and below SA1. Here, the input / output gate IOG is activated in response to the column select line CSL (not shown). A local global input / output gate LGIOG serves to selectively couple LIO and LIOB to a pair of global input / output lines GIO and GIOB when LIO and LIOB are active. Consequently, the read state of the memory cell is coupled to a peripheral input / output circuit.

From the 1 and 2 can be recognized that a large number of conductors over the memory field 10 are guided. NWE lines are routed vertically across the array over the sub memory cell arrays and PX, LIO and LIOB lines are routed vertically across the array via the connection areas and sense amplifier areas. CSL, GIO and GIOB lines are routed horizontally across the field via the sub memory cell arrays. Not shown are power lines that must also be routed across the field to provide power for the circuits in the SA, CJ, and SWD regions.

3 shows a region of the memory field 10 , with underlying circuit details omitted and overlying metal traces illustrated. On a first metal layer, the LIO, PX, and NWE traces are spaced apart with first power lines P1 which provide power at different voltage levels required by the field circuits. Some of the first power lines P1 may include ground voltage lines VSS and power supply lines VCC. Other lines of the first power lines P1 may include a reference voltage line Vref, a negative power line VBB, a boost voltage line VPP, etc. On a second metal layer, CSL and GIO traces are spaced with second power lines P2 which supply power at different voltage levels. Some of the second power lines P2 may also include voltage leads at ground potential VSS and power supply lines VCC. Other lines of the second power lines P2 may include a reference voltage line Vref, a negative power line VBB, and a boost voltage line VPP, etc. Where a P2 lane is above a P1 lane at the same level of tension, the two lanes are joined together to form a lattice. The P2 paths are connected to power supplies that are outside the memory array area of the DRAM device.

4 shows a simplified block diagram of the row decoder 30 out 1 , The row decoder 30 includes a row address decoder area 30-1 and a row address predecoder area 30-2 , Within the row decoder area 30-1 Each of the first decoder regions RD1 shown generates a word line selection signal PX, and each of the second decoder regions RD2 shown generates a main word line signal NWE in response to row addresses RA and predecode row addresses DRA, which are in turn addressed by row address predecoder 30-2 to be generated.

5 shows part of the row decoder 30 with the underlying circuit details omitted and overlying metal traces shown. Signal lines S1 (eg PX lines) are flanked by first power lines PVINT1 and PVSS1 above a first decoder area RD1 on a first metal layer. Signal lines S1 (eg NWE lines) are flanked by additional first power lines PVINT1 and PVSS1 via a second decoder area RD2 on a first metal layer.

A second metal layer includes signal lines S2 (e.g., RA and DRA lines) and second power lines PVINT2 and PVSS2. PVINT2 is connected to PVINT1, with the two overlapping, and PVSS2 is with PVSS1, the two overlap. The PVINT2 and PVSS2 tracks are connected to power supplies that are outside the memory area of the DRAM blocks are located. Under this condition, the Power lines can not be made wider without increasing the chip area.

There Scaling DRAM devices to smaller cell dimensions and / or the As the number of cells in a memory field increases, more signal lines are going through the Memory field and the row decoder per unit area essentially the same area, which previously served a smaller number of signal lines, guided. The width of the power lines is therefore reduced proportionally, to adapt to the denser field. The reduction of the width However, the power lines is undesirable because a reduced Width of the power lines to a greater resistance of the current flow, a higher one Voltage drop and power consumption and reduced stability of the power supply, when the power demand fluctuates leads. The various signal and power lines are also getting closer together packed when the building block scales to smaller dimensions, which to an unwanted crosstalk between leads adjacent lines.

The invention is based on the technical problem of providing a DRAM semiconductor device and a corresponding method for arranging power and / or signal lines, which be able to at least partially avoid the difficulties of the above-mentioned prior art.

The Invention solves this problem by providing a DRAM semiconductor device with the features of claim 1, 13 or 23 and a method with the features of claim 26 or 29.

advantageous embodiments The invention are set forth in the subclaims.

The Embodiments, which are described herein use a DRAM design with three Metal layers, which is the lead the signal and power lines considerably over one Improved arrangement with two metal layers. Although by others already different designs, about signals over proposed to lead a memory field using three metal layers It is believed that the present interpretation is the problem with particular attention to the point of view of the power supply and a group of new arrangements of metal layers which scale well to smaller cell sizes.

preferred Embodiments of the invention described in more detail below and the embodiment explained above for easier understanding of the invention The prior art are shown in the drawings, in FIG which:

1 shows a memory array and a column / row decoder arrangement of the general prior art for a DRAM memory module,

2 an enlarged view of a portion of the memory array 1 with additional circuit and signal line details,

3 also an enlarged view of a part of the memory array of 1 shows, with particular attention to the layout of the signal and power train management for the two metal layers, which are above the memory field,

4 an enlarged view of a portion of the row decoder 1 with additional circuit and signal line details,

5 also an enlarged view of a part of the row decoder 1 shows here, with particular attention to the layout of the routing of signal and power strands for the two metal layers overlying the row decoder,

6 to 10 illustrate various embodiments showing the routing of signal and power lines in three metal layers across a memory array,

11 to 14 illustrate various embodiments showing the routing of signal and power lines in three metal layers via a row decoder, and

15 and 16 Illustrate various embodiments showing routing of signal and power lines in three metal layers via a column decoder.

The following embodiments use three metal layers over a memory array, a row decoder and / or a column decoder. In these embodiments wider power lines are generally possible, which the power distribution and stability increased.

Various Advantages of the embodiments are given by the following description of the figures clear.

6 shows a first embodiment with signal and power lines, which are passed over a memory array, wherein three metal layers are used. The first metal layer includes NWE, PX, LIO signal lines and P1 power lines, similar to the prior art. The second metal layer includes CSL and GIO signal lines and no power lines. The third metal layer includes power lines P3 perpendicular to the P1 power lines formed of the first metal layer. The P3 power lines can be made wider than the prior art power lines P2 formed of the second metal layer because the CSL and GIO lines are not in competition with the metal 3 area overlying the memory array , Although for the sake of clarity this property is not in 6 As shown, portions of the P3 lines may even be directly over CSL and GIO lines. Connections to power lines P1 exist in free spaces where a P3 line is above a P1 line of the same voltage and may be a via (a direct connection between the third metal and the first metal) or an intermediate P2 pad (not shown) Use connection with the metal-1. The P3 lines can thus be guided with reduced resistance and improved power distribution. The distance between the CSL and GIO lines can also be improved as the P2 tracks are missing, causing the overflow speak reduced and the signal propagation speed improved.

7 shows a second embodiment with signal and power lines, which are passed over a memory array, wherein three metal layers are used. In this embodiment, there are no P1 lines in metal-1, and P2 lines parallel to CSL and GIO in metal-2 distribute power to the memory array circuits. P3 lines are located in the metal-3, perpendicular to the P2 lines, and are connected to the P2 lines at the points where a P3 line and a P2 line cross at the same voltage. The P2 lines can remain relatively thin while the P3 lines can be made relatively wide to effectively transport power to the environment where it is needed.

8th shows a third embodiment with signal and power lines, which are passed over a memory array, wherein three metal layers are used. In this embodiment, thin P1 power lines intersect with P2 thin power lines. P1 and P2 lines with the same voltage level are connected where they intersect. Wider P3 power lines are routed in parallel with the P2 lines and generally overlap the P2 lines which have the same voltage level. Since P3 and P2 lines overlap along their length, the connection between the two lines can be made with long channels or with more frequent, short-circuiting vias. The P3 / P2 arrays have less resistance per unit length, while requiring significantly less space on the metal layer that they share with CSL and GIO.

9 shows a fourth embodiment with signal and power lines, which are passed over a memory array, wherein three metal layers are used. In this embodiment, the metal-1 includes thin P1 power lines routed in parallel with NWE lines. Metal 2 contains thin P2 lines routed perpendicular to the P1 power lines and parallel to CSL and GIO lines. Where a P2 line crosses a P1 power line at the same voltage level, the two power lines are connected. Metal-3 includes relatively wide P3 power lines in parallel with the P1 power lines, which are preferably routed to overlap with an underlying P1 line having the same voltage level. Where a P3 power line crosses a P2 power line having the same voltage level, the two power lines are connected.

10 shows a fifth embodiment with signal and power lines, which are passed over a memory array, wherein three metal layers are used. This embodiment is similar to the third embodiment ( 8th ), but the GIO leads are routed to the metal 3 instead of the metal 2. This may be an attractive alternative, as overlapping P2 and P3 lines can act together as a single reduced-resistance conductor, allowing P3 to be made less wide and leaving more room for the signal lines on the Metal-3. Therefore, the line pitch between the CSLs can be larger, so that coupling noise can be reduced.

Preferably, but not necessarily, in connection with any of the foregoing embodiments, various embodiments are also provided to guide signal and power lines that overlay a row decoder. 11 shows a first row decoder embodiment. Relatively thin power lines PVINT1, PVSS1 are provided on a first metal layer to provide power to an underlying row decoder circuit. For example, PVINT1 and PVSS1 power lines are arranged to extend from top to bottom to an area outside a row decoder area RD1 with an inner portion overlying RD1 being left to lead signal lines S1 in the first metal. Other row decoder signal lines S2 are formed on the second metal and are perpendicular to the PVINT1, PVSS1 and S1 lines. On the third metal run relatively wide power lines PVINT3 and PVSS3 parallel to the S2 lines, wherein PVINT3 and PVSS3 each overlap with one or more of the signal lines S2. Where PVINT3 overlaps with PVINT1 but not with S2, a connection is made between the two power lines. Similarly, where PVSS3 overlaps PVSS1, but not S2, a connection is made between the two power lines. The connection may include a via partially filled with the metal 2, but there are no continuous metal 2 power lines in this embodiment. The connection can be made directly between metal-3 and metal-1 (by means of a contact). Advantageously, this arrangement allows extra space on the metal-2 to spread or increase the number of lines S2, and also provides power distribution through metal-3 power lines having a substantially larger cross-section than the power lines in the prior art metal-2 the technology ready.

12 FIG. 12 shows a second row decoder embodiment similar to FIG 11 but uses extra power lines PVINT2 and PVSS2 on the metal-2, which run parallel to and outside the signal lines S2. Where PVINT2 overlaps with PVINT1, a connection is established between the two power lines, and similar connections are made between PVSS2 and PVSS1. PVINT3 overlaps with PVINT2 (and may also overlap one or more signal lines S2), establishing a connection between PVINT3 and PVINT2 where the two lines overlap. This connection may be an elongate channel or a series of further shorting vias spaced over the longitudinal extent of PVINT3 and PVINT2. A similar arrangement and connection exists between PVSS3 and PVSS2.

13 FIG. 12 shows a third row decoder embodiment similar to FIG 11 , PVINT1 and PVSS1 are centrally located, but above the row decoder area RD1, with signal lines S1 outside of PVINT1 and PVSS1. Here, PVINT2 and PVSS2 do not exist on the second metal layer.

14 Figure 4 shows a fourth row decoder embodiment similarly 12 , PVINT1 and PVSS1 are located centrally, but above the row decoder area RD1, with signal lines S1 outside of PVINT1 and PVSS1. In this case, PVINT2 and PVSS2 exist on the second metal layer with the signal line S2.

Preferred, but not necessary, in connection with any of the previous embodiments, various embodiments are also provided to guide signal and power lines that are above a column decoder. 15 shows a first column decoder embodiment, for example, with the embodiment of the 10 can be used, which has GIO lines, which are arranged on the metal-3. A column decoder 20 ' uses signal lines S1 and power lines PVINT1 and PVSS1 located on the metal-1 and signal lines S2 and power lines PVINT2 and PVSS2 located on the metal-2 over the metal-1. However, on the metal-3, the metal 3-GIO lines (and, optionally, metal-3 power lines, not shown, to power the memory array) that overlay the memory array continue to move over the column decoder toward one peripheral I / O circuit (not shown).

16 shows a second column decoder design similar 15 in which the GIO leads pass over the column decoder on the metal-3. However, just after the column decoder, each GIO line is connected through a via to a GIO line that extends over the memory array on the metal 2, as in FIGS 6 to 9 shown.

Of the One skilled in the art recognizes that many other permutations of routing in Be considered that in the general context of the described embodiments fall. Absolute widths and distances of the lines were not as these are generally a function of the building block and of the process requirement. Such minor modifications and implementation details are through the embodiments of the invention includes and is intended to be within the scope of the claims.

Claims (29)

A dynamic random access memory (DRAM) semiconductor device comprising: a memory cell array having a repeated row / column pattern of cell blocks, each cell block comprising a sub memory cell array and a sense amplifier section and a sub-word line section associated with the sub memory cell array; second and third patterned metal layers disposed over the memory cell array, each structured metal layer comprising a plurality of traces, and insulating layers disposed about the patterned metal layers to substantially insulate the traces except where holes exist formed in one of the insulating layers to make electrical contact with a web; Wherein the tracks of the first patterned metal layer include a plurality of substantially parallel input / output (I / O) lines, each coupled to a plurality of sense amplifier sections in cell blocks arranged in a row, and a plurality of main word lines which are substantially parallel to the local I / O lines and each of which is connected to a plurality of the sub-word line driver sections in cell blocks arranged in a row, the paths of the second patterned metal layer being a plurality of substantially parallel ones Column select lines, each of which is connected to an input / output gate in a cell block, wherein the tracks of the third structured metal layer, a plurality of third power lines to provide power for the memory cell array, and / or a plurality of substantially parallel column selection leitleit each of which is connected to a plurality of sense amplifier sections in cell blocks arranged in a column, wherein the tracks in at least one of the second and third patterned metal layers further include a plurality of global I / O lines are substantially parallel to the column select lines and each of which is connected to a plurality of cell blocks to selectively multiplex a plurality of local I / O lines onto this global I / O line, and wherein a plurality of first power lines in the tracks of the first patterned metal layer are included to power the memory cell array which are substantially parallel to the local I / O lines and / or a plurality of second power lines are included in the tracks of the second patterned metal layer power the memory cell array. A DRAM semiconductor device according to claim 1, wherein at least one of the third power lines with at least one of the second Power lines at a crossing point between the third Power line and an underlying second power line connected is. A DRAM semiconductor device according to claim 1 or 2, wherein at least one of the third power lines substantially above one corresponding to the first power lines and connected to this is. A DRAM semiconductor device according to claim 3, wherein at least one of the third power lines has a width that is essential is larger than the width of the underlying first power line. DRAM semiconductor device according to one of claims 1 to 4, further comprising a column decoder located at the periphery the memory cell array arranged and with at least some of the Column selection lines is connected, wherein at least some of the global I / O lines cross the column decoder and on tracks the third structured metal layer are guided at least there, where they cross the column decoder. A DRAM semiconductor device according to claim 5, wherein at least some of the global I / O lines on the lanes of the second or the third structured metal layer are led, where they form the memory field cross. DRAM semiconductor device according to one of claims 1 to 6, with all global I / O lines on the second or the third textured metal layer are present. DRAM semiconductor device according to one of claims 1 to 7, wherein the plurality of global I / O lines in the lanes of the second structured metal layer are included. DRAM semiconductor device according to one of claims 1 to 8, wherein at least one of the third power lines substantially parallel or perpendicular to the column selection lines. DRAM semiconductor device according to one of claims 1 to 9, wherein at least one of the third power lines substantially overlapped with a corresponding one of the first or second power lines and connected with it. A DRAM semiconductor device according to claim 10, wherein the connection between the at least one of the third power lines, the essentially over a corresponding one of the first power lines, in one Through hole exists, which allows that at least one third power line directly the one corresponding to the first Contacted power lines. DRAM semiconductor device according to one of claims 1 to 11, wherein at least one of the third power lines has a width has, which is much larger as the width of the underlying second power line. DRAM semiconductor device, comprising: - one Row decoder comprising a row of decoder cells and / or Generates signals on a plurality of main word lines and a Comprises a plurality of control circuits, - a first, second and third structured metal layer, which are arranged above the row decoder, wherein each structured metal layer comprises a plurality of tracks has, and - insulating Layers arranged around the patterned metal layers are to essentially isolate the webs except there, where there are holes located in the insulating layers to make electrical contact to make a train, - where the tracks of the first Metal layer, a plurality of first signal lines, of which each connected to a predetermined one of the control circuits, and a plurality of first power lines for power supply include, which are substantially parallel to the first signal lines, - in which the tracks of the second structured metal layer a plurality of substantially parallel second signal lines, arranged substantially perpendicular to the first signal lines are and - in which the tracks of the third structured metal layer a plurality from third power lines to the power supply, arranged substantially parallel to the second signal lines are and essentially about at least some of the second signal lines are located. The DRAM semiconductor device according to claim 13, further comprising a memory cell array adjacent to A row decoder, wherein at least some of the first or third power lines power the memory cell array. A DRAM semiconductor device according to claim 13 or 14 wherein the tracks of the second patterned metal layer are a plurality of second power lines for power supply, which are substantially parallel to the second signal lines. A DRAM semiconductor device according to claim 15, wherein each of the second power lines has a much smaller width has as the third power lines. A DRAM semiconductor device according to any one of claims 13 to 16, wherein at least one of the third power lines substantially over at least one of the second power lines is located. A DRAM semiconductor device according to any one of claims 13 to 17, wherein at least one of the first power lines on the central half each of the control circuits runs. A DRAM semiconductor device according to any one of claims 13 to 18, wherein at least one of the first power lines on the central half each control circuit runs. A DRAM semiconductor device according to any one of claims 13 to 19, being over each of the decoder cells is one of the first power lines provides internal operating voltage and another of the first Power lines provides a ground voltage. The DRAM semiconductor device of claim 20, wherein over each the decoder cells the first power line, the internal operating voltage and the first power line provides the ground voltage are arranged adjacent to each other, wherein at least one of the first signal lines via the decoder cell and outside the first power line is the internal operating voltage and at least one other of the first signal lines above Decoder cell and outside the first power line that provides the ground voltage. The DRAM semiconductor device of claim 20, wherein over each the decoder cells at least two of the first signal lines each other are adjacent, the first power line, the internal operating voltage providing, outside these signal lines on the one hand and the first power line, which provides the ground voltage, outside these signal lines lying on the other side. DRAM semiconductor device, comprising A memory cell array; - one Column decoder located at the periphery of the memory cell array is; - one first, second and third structured metal layers overlaying the Column decoders are arranged, each structured metal layer a plurality of webs; and - insulating layers, the are arranged around the structured metal layers around essentially insulate the tracks except where there are holes in them one of the insulating layers are located around an electrical To make contact with a train, - where the tracks of the third structured metal layer include a plurality of global I / O lines, which are connected to the memory cell array. The DRAM semiconductor device according to claim 23, wherein the global I / O lines over the memory cell array on tracks of the second structured metal layer guided are each structured with the global I / O lines of the third Metal layer over are connected to the column decoder. A DRAM semiconductor device according to claim 23 or 24, the global I / O lines of the third patterned metal layer over the Memory cell array as tracks of the third structured metal layer guided are. Method for arranging power and signal lines, the above a DRAM array, the process comprising: - Provide primary Power tracks on a third metal layer; - Connect the primary Performance tracks with secondary Power tracks on a first metal layer and / or a second Metal layer, with the secondary Tracks have a smaller track width than the primary tracks, and - Provide of local I / O lines and word lines on the first metal layer. The method of claim 26, further comprising providing of column selection lines on the second metal layer. The method of claim 26 or 27, further providing global I / O lines on the second or the second third metal layer comprises. A method of arranging power and signal lines overlying a DRAM row decoder, the method comprising: providing primary power tracks on a third metal layer; Connecting the primary power tracks with secondary power tracks on a first metal layer and / or a second metal layer, the secondary power tracks having smaller track widths than the primary power tracks, and providing signal lines on the first and second metal layers.