1277179 -Μ 〜九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體非揮發性記憶體元件，特別是有 關於一種單一多晶石夕層(Single Polysilicon layer)所構成之非揮發 性記憶體。 • 【先前技術】 隨著可攜式電子產品，如數位相機、PDA及筆記型電腦等的普 及化，非揮發性記憶體在半導體記憶元件的發展上所扮演的角色 愈來愈重要。近來，氧化矽-氮化矽-氧化矽（Qxide_Nitride{xide， ΟΝΟ)非揮發性記憶體元件逐漸受到業界的青睞，跟其他非揮發性 呂己憶體比較(例如浮動閘極技術，floating gate te^oiogy)，其優勢 在於SONOS結構可以用低電壓編程(pr〇gram)及抹除(erase)，沒 _ 有脫離群體的位元(tail bits)，較佳的下一代縮小能力及較簡單的製 造流程；並因這類型的記憶體在CM0S製程上有相當高的整合 性，可以降低生產成本。 ， 而半導體製程積集度的不斷提昇，現今製作半導體積體電路的 - 趨勢是將記憶元陣列(memory cell array)與其它電路元件進行整 合，例如可將記憶體陣列與高速邏輯電路元件(high-speed 1〇gic circuit elements)同時製作在一個晶片（chip)上，形成一種同時結合 了 δ己憶體陣列以及邏輯電路(i〇gic circuits)的嵌入式記憶體，以大1277179 - Μ ~ IX, invention description: [Technical field of the invention] The present invention relates to a semiconductor non-volatile memory element, and more particularly to a non-single polysilicon layer Volatile memory. • [Prior Art] With the popularization of portable electronic products such as digital cameras, PDAs, and notebook computers, the role of non-volatile memory in the development of semiconductor memory devices is becoming more and more important. Recently, non-volatile memory components of yttrium oxide-yttria-yttrium oxide (Qxide_Nitride{xide, ΟΝΟ) have gradually gained favor in the industry, compared with other non-volatile LV recalls (such as floating gate technology, floating gate te ^oiogy), the advantage is that the SONOS structure can be programmed with low voltage (pr〇gram) and erase (erase), no _ with bits away from the group, better next generation reduction ability and simpler Manufacturing process; and because this type of memory has a fairly high integration in the CM0S process, it can reduce production costs. And the increasing degree of semiconductor process integration, the current trend of making semiconductor integrated circuits - the integration of the memory cell array with other circuit components, such as memory arrays and high-speed logic circuit components (high -speed 1〇gic circuit elements) simultaneously fabricated on a chip to form an embedded memory that combines the δ-resonance array and the logic circuits (i〇gic circuits)
5 1277179 * 幅節省面積並加快訊號的處理速度。 % 前述非揮發性記憶體元件的主要特徵乃是使用氮化矽之絕緣 介電層作為電荷儲存介質(charge trapping medium)。由於氮化石夕層 具有尚度之敵密性，因此可使随穿(tunneling)進入氮化珍層中的熱 電子被捕陷(trap)其中，進而形成一非均勻之濃度分佈，以加快讀 取資料速度並避免漏電流。至於傳統的浮置閘極快閃記憶體，則 _ 使用多晶矽浮動閘極(floatinggate)來儲存電荷，而在浮動閘極之上 還需要再多一個控制閘極(contr〇i gate)。 兩者相較，前者具有製作過程簡單，製作成本低的優點，而後 者因為必需製作浮動閘極-中間介電層-控制閘極的三層閘極堆疊 結構，需要較複雜的製程來配合，因此所耗費的成本也較高。 • 【發明内容】 本發明之主要目的在提供一種改良之非揮發性記憶體元件的 結構以及製造才法。 雜本伽讀佳實_，本發明贿-種鱗發性記憶體元 件&含有-1己憶體單元，設於該非揮發性記憶體元件的一記憶 體陣列區域内，該記憶體單元包含有一 PM0S存取電晶體以及一 PMOS儲存電晶體，經由—浮置且共關p型摻雜與該pM〇s 存取電晶體串接，其中該PM〇s存取電晶體包含有一存取開極、 1277179 -存取閘極氧化層、-P型源極摻雜區，而該浮置且共用的p型 ' ^雜區作為該PM0S存取電晶體的汲極；該mos儲存電晶體包 /有-控制間極、-氧化石夕_氮化石夕_氧化石夕(〇n〇)堆疊層、一 p型 ^極摻雜，義浮置且共用⑽㈣祕料該pM〇s儲存電 體的雜，以及-n壓M〇s電晶體，設_轉發性記憶體元 的:週邊電路區域内，該高遷M0S電晶體包含有一高壓間極以 ^ π壓f雜氧化層’且該冑朗極氧倾的厚度與該存取間極 零 氧化層的厚度相同。 6為了使f審查委員能更清楚瞭解本發明之特徵及技術内 〃明/閱以下有關本發明之詳細說明與附圖。然而所附圖式僅 供參考與辅助說明用，並非用來對本發明加以限制者。 【實施方式】 • 請參閱第1圖，其緣示的是本發明較佳實施例之非揮發性記憶 體的剖面示意圖。如第】圖所示，在一半導體基底励上，例如^ 型矽基底，包括有一記憶體陣列區域1〇1以及一週邊電路區域 102。在記憶體陣列區域101 _離子佈植製程形成有離子井11〇， '例如N型離子井’而在基底100表面上形成有溝渠絕緣結構130， 例如淺溝絕緣(shallow trench isolation，STI)結構。 在記憶體陣列區域101内的N型離子井110上，設有至少一非 揮發性記憶體單元200,其包括有一存取電晶體21〇以及一儲存電 !277179 晶體220。根據本發明之較佳實施例，存取電晶體21 〇及儲存電晶 體220皆為PMOS電晶體，其中，存取電晶體21〇包括有—閘極 2Η、一閘極氧化層212設於閘極214與Ν型離子井no之間、ρ 型汲極/源極摻雜區216、Ρ型汲極/源極摻雜區232以及ρ型輕摻 雜汲極218 ;儲存電晶體220包括有一閘極224、一氧化矽_氮化矽 氧化石夕(ΟΝΟ)介電層150設於閘極224與Ν型離子井no之間、 Ρ型汲極/源極摻雜區232、Ρ型汲極/源極摻雜區226以及ρ型輕 摻雜汲極228。 工 另外，在閘極214與224的側壁上則形成有側壁子230。〇Ν〇 介電層150包括有下氧化石夕層151、氮化石夕捕陷層152以及上氧化 矽層153。根據本發日月之較佳實施例，下氧化石夕層151的厚度約介 於15埃至35埃之間，氮化石夕捕陷層152的厚度約介於％埃至⑽ 埃之間，而上氧化石夕層153約介於45埃至励埃之間。由圖中可 看出’存取電晶體210及儲存電晶體22〇經由ρ型沒極/源極推雜 區232構成串接組態’並形成本發明之非揮發性記憶體單元2⑻。 、在週邊電路區域102内，設有一高壓则電晶體310，藉由 溝渠絕緣結構130構成電性隔絕。根據本發明之較佳實施例，高 壓MOS電晶體310包括有-閘極314、設於閘極314讎上的側 壁子330、-閘極氧化層312設於閘極3Μ與半導體基底！⑻之 間、汲極/源極摻雜區316以及輕摻雜汲極318。高壓腫電晶體 310可以是PMOS電晶體或者職〇8電晶體。而此高壓娜電 1277179 ‘晶體310端視製程或產品需要，而調整其閘極氧化層312之厚卢 、，剌適當元件特性，並且在週邊線路區域僅有此1元件= 氧化層，整個製程相當簡單、需要光罩數目少(因為在週邊區錢 有低壓元件），如此一來，製造成本低廉。 本發明之主要特徵在於在記憶體陣顺域1G1⑽存取電晶體 210的閘極氧化層212的厚度與週邊電路區域1〇2内高壓繼曰$曰電 •晶體烟的閘極氧化層312的厚度相同。而且，本發明非揮發性 记憶體單元200的存取電晶體21〇以及儲存電晶體22〇皆為 電晶體。此外，本發明之另一特徵在於存取電晶體2i〇以及儲存 電晶體220串接在-起，構成單一記憶體單元，因此，本發明之 非揮發性記憶體乃是N0R架構，而不是NAND架構。 明翏閱第2圖至第7圖’其綠示的是本發明較佳實施例製作彼 籲入式鱗發性記㈣綠的麻示賴。魏，如第2圖所示， 料導體基底100上，定義有記憶體陣列區域⑽以及週邊電路 區域102。首先，在基底100的記憶體陣列區域1〇1内以離子佈植 製私形成N型離子井11〇 ’接著，在基底1〇〇表面上形成溝渠絕 .緣結構130。此外，亦可以先形成溝渠絕緣結構13〇，然後再進行 離子井110及】20的離子佈植。接著，進行一 〇N〇製程，在基底 100表面上形成ΟΝΟ堆疊層150，如前所述，0N0堆疊層15〇包 括下氧化矽層15卜氮化矽捕陷層152以及上氧化矽層153。接著， 在記憶體陣列區域101内的〇Ν〇堆疊層15〇上形成光阻遮罩圖案 1277179 • 410，其定義出儲存電晶體的通道區域。 接下來’如第3圖所示’利用光阻遮罩圖案41〇作為侧硬遮 罩’進行刻製程’去除未被光阻遮罩圖案彻覆蓋的堆 疊層150。隨後，去除光阻遮罩圖案41〇。 如第4圖所示，進行一熱氧化製程，在半導體基底⑽上長出 擊層厚度為心的二氧化石夕層112，其用來作為週邊電路區域102 内的高壓MOS電晶體的閘極氧化層，以及作為記憶體陣列區域 1〇1内的存取電晶體的閘極氧化層。根據本發明之較佳實施例，二 氧化矽層112的厚度tl約為5〇-2〇〇埃之間。 接下來，如第5圖所示，於料體基底1〇〇上沈積一推雜多晶 石夕^ 114。然:後，在摻雜多晶㈣m上形成—光阻遮罩圖案·， 籲其定義出週邊電路區域1〇2以及記憶體陣列區域1〇1内的間極位 置與圖案。 =第6圖所示’利用光阻遮罩圖案43〇作為韻刻硬遮罩，進行 一乾韻刻製程’將未被光阻遮罩圖案430覆蓋的摻雜多晶石夕層114 以及一氧化石夕層112 .，如此即完成週邊電路區域脱以及記 憶體陣列區域1G1内的難枝，而於記憶體陣顺域1〇1内形 成閘極氧化層312與間極結構2M、間極結構故、閘極氧化層阳 與閘極結構314。 1277179 如第7圖所示，去除光阻遮罩圖案“ο之後，再分別進行離子 饰植製程，以於間極兩側的半導體基底漏t形成輕汲極源極推 雜區（LDD) 218、228、318 ,·之後進行側壁子製程__啊卟 緊接著是再度分職行離子佈程，以關極繼子兩側的半 ¥體基底100中形成重汲極源極摻雜區ρ^+/ρ+)216、226、232、316。 請參閱第8圖，其繪示的是本發明另一較佳實施例之非揮發性 記憶體的剖面示意圖。如第8圖所示，在一半導體基底1〇〇上， 例如Ρ型矽基底，同樣包括有一記憶體陣列區域1〇1以及一週邊 電路區域102。在記憶體陣列區域1〇1内以離子佈植製程形成有離 子井110，例如Ν型離子井，而在基底1〇〇表面上形成有溝渠絕 緣結構130，例如淺溝絕緣(shan〇w trench is〇iati〇n，STI)結構。本 實施例與第1圖的實施例不同之處在於週邊電路區域1〇2内除了 阿壓MOS電晶體310，另有一結構與記憶體陣列區域1〇1内儲存 電晶體220相同電晶體51〇，其包括〇N〇介電層512、閘極514 以及汲極/源極摻雜區516。電晶體510可以作為修整Sense Amplifier 内參考電路（ReferenceCircuitTrilnming)的電路元件， 使得Sense Amplifier内之參考電路更加精確；或是插入在 Amplifier内’可以提供senseAmpiifier之參考電流使用，如此一 來’參考電路所產生之參考電流可以隨著記憶區内記憶、元件特性 變化而追蹤更動（Tracking)，而晶記憶窗_mQryWind()w^ 變得更大’得到較佳之良率與可靠度。 11 1277179 v 請參閱第9圖至第14圖，其繪示的是本發明另一較佳實施例 製作嵌入式非揮發性記憶體方法的剖面示意圖。如第9圖所示， 在半導體基底100上，定義有記憶體陣列區域1〇1以及週邊電路 區域102。首先，在基底1〇〇的記憶體陣列區域1〇ι内以離子佈植 製程形成N型離子井11〇，接著，在基底100表面上形成溝渠絕 緣結構130。此外，亦可以先形成溝渠絕緣結構13〇，然後再進行 • 離子井110及120的離子佈植。接著，進行一 〇N〇製程，在基底 100表面上形成ΟΝΟ堆疊層150，如前所述，0N0堆疊層15〇包 括下氧化矽層151、氮化矽捕陷層152以及上氧化矽層153。接著， 在記憶體陣列區域1〇1内的0N0堆疊層15〇上形成光阻遮罩圖案 410，其定義出儲存電晶體的通道區域。 接下來’如第10圖所示，利用光阻遮罩圖案410作為_硬 遮罩’進行-侧製程，絲未被光阻遮罩_41 堆疊層150。隨後，去除光阻遮罩圖案410。 如第U _心進行—熱氧化製程，在半導體基底⑽上長 内的的—氧化销112，其用來形成週邊電路區域102 101内的存取以及作為記鍾陣列區域 恳1日日、祕氧化層。根據本發明之較佳實施例，一 m的厚度㈣為㈣g埃之間。接著，在半導體从 100上形成-光阻㈣心 财在牛導體基底 先阻遮罩圖案420,其覆蓋住記憶體陣列區域101以 1277179 =邊電路^域搬内即將形成高壓m〇s電晶體的主動區域 :而暴洛出週邊電路區域搬内即將形成低壓應 主動區域102b。 如第12圖所示，接著進行1刻製程，例如刻製程，將 未被光阻遮罩圖案㈣覆蓋的二氧切層ιΐ2齡。隨後，去除 光阻遮罩圖案420。 如第13圖所示，接著再進行—熱氧化製程，例如爐管熱氧化 製程’在週邊電路區域102内即將形成低壓順電晶體的主動區 域l〇2b上形成厚度的二氧化石夕層122，其中厚度小於厚度 此熱氧化步驟同時縣本厚度t2的二氧切層m增厚到厚度^。 根據本發明之難實補，厚度t3約介於15埃， 介於50-200埃左右，但並不限於此範圍。 又4，’. 接下來’於半導縣底1GG上沈積—獅乡晶销114。然後， 在摻雜多晶铺114上形成-光阻遮罩圖案，其定義出週邊電 路區域102以及記憶體陣列區域1〇1内的閘極位置與圖案。 如第14圖所示，利用光阻遮罩圖案43〇作為蝕刻硬遮罩，進 行一乾蝕刻製程，將未被光阻遮罩圖案43〇覆蓋的摻雜多晶矽層 114蝕除，如此即完成週邊電路區域1〇2以及記憶體陣列區域 内的閘極定義，而於記憶體陣列區域101内形成閘極氧化層M25 1277179 * Saves area and speeds up signal processing. The main feature of the aforementioned non-volatile memory element is the use of an insulating dielectric layer of tantalum nitride as a charge trapping medium. Since the nitride layer has a latent density, the hot electrons entering the nitride layer can be trapped therein, thereby forming a non-uniform concentration distribution to speed up reading. Take data speed and avoid leakage current. As for conventional floating gate flash memory, _ uses a polysilicon floating gate to store charge, and a floating gate requires a control gate (contr〇i gate). Compared with the two, the former has the advantages of simple manufacturing process and low manufacturing cost, and the latter requires a relatively complicated process to cooperate because it is necessary to fabricate a floating gate-intermediate dielectric layer-control gate three-layer gate stack structure. Therefore, the cost is also high. • SUMMARY OF THE INVENTION The main object of the present invention is to provide an improved non-volatile memory device structure and manufacturing method. The invention relates to a bribe-type scalar memory element & a -1-replica memory unit, which is disposed in a memory array region of the non-volatile memory element, the memory unit includes a PM0S access transistor and a PMOS storage transistor are connected in series with the pM〇s access transistor via a floating and common p-type doping, wherein the PM〇s access transistor includes an access open a pole, 1277179 - access gate oxide layer, -P type source doped region, and the floating and shared p-type 'hyster region as the drain of the PM0S access transistor; the MOS storage transistor package / 有-Control Interpole, - Oxidation Stone Xi _ nitride eve _ oxidized stone 〇 (〇n〇) stacked layer, a p-type ^ pole doping, floating floating and sharing (10) (four) secret material pM〇s storage electric body And the -n-voltage M〇s transistor, in the _transferred memory cell: in the peripheral circuit region, the high-migration MOS transistor includes a high-voltage interpole with a π-voltage f-doped oxide layer' and the 胄The thickness of the polar pole is the same as the thickness of the pole zero oxide layer between the accesses. 6 In order to provide a clearer understanding of the features and techniques of the present invention, the detailed description and drawings accompanying the present invention. The drawings are to be considered in all respects as illustrative and not restrictive. [Embodiment] Referring to Figure 1, there is shown a schematic cross-sectional view of a non-volatile memory in accordance with a preferred embodiment of the present invention. As shown in the figure, a semiconductor substrate is excited, for example, a substrate, including a memory array region 1〇1 and a peripheral circuit region 102. In the memory array region 101 _ ion implantation process, an ion well 11 〇, 'for example, an N-type ion well' is formed, and a trench insulating structure 130 is formed on the surface of the substrate 100, such as a shallow trench isolation (STI) structure. . On the N-type ion well 110 in the memory array region 101, at least one non-volatile memory cell 200 is provided, which includes an access transistor 21A and a storage transistor !277179 crystal 220. According to a preferred embodiment of the present invention, both the access transistor 21 and the storage transistor 220 are PMOS transistors, wherein the access transistor 21 includes a gate 2 and a gate oxide 212. Between the pole 214 and the Ν-type ion well no, the p-type drain/source doping region 216, the Ρ-type drain/source doping region 232, and the p-type lightly doped drain 218; the storage transistor 220 includes a The gate 224, the niobium oxide-tantalum nitride oxide oxide dielectric layer 150 is disposed between the gate 224 and the 离子-type ion well no, the Ρ-type drain/source doping region 232, Ρ-type 汲A pole/source doped region 226 and a p-type lightly doped drain 228. Further, sidewalls 230 are formed on the sidewalls of the gates 214 and 224. The dielectric layer 150 includes a lower oxide layer 151, a nitride nitride trap layer 152, and an upper tantalum oxide layer 153. According to a preferred embodiment of the present invention, the thickness of the lower oxidized layer 151 is between about 15 angstroms and 35 angstroms, and the thickness of the nitriding layer 152 is between about angstroms and (10) angstroms. The upper oxidized layer 153 is between about 45 angstroms and between lei. As can be seen, the access transistor 210 and the storage transistor 22 constitute a tandem configuration via the p-type dipole/source noisy region 232 and form the non-volatile memory unit 2 (8) of the present invention. In the peripheral circuit region 102, a high voltage transistor 310 is disposed, and the trench isolation structure 130 is electrically isolated. In accordance with a preferred embodiment of the present invention, the high voltage MOS transistor 310 includes a gate 314, a side wall 330 disposed on the gate 314, and a gate oxide layer 312 disposed on the gate 3 and the semiconductor substrate! Between (8), the drain/source doping region 316 and the lightly doped drain 318. The autoclave transistor 310 can be a PMOS transistor or a 〇8 transistor. And this high-voltage Natal 1277179 'crystal 310 end-view process or product needs, and adjust the thickness of its gate oxide layer 312, 剌 appropriate component characteristics, and only the 1 component = oxide layer in the peripheral line area, the entire process It is quite simple and requires a small number of masks (because there are low-voltage components in the surrounding area), so that the manufacturing cost is low. The main feature of the present invention is that the thickness of the gate oxide layer 212 of the access transistor 210 in the memory array region 1G1 (10) and the gate oxide region 312 of the peripheral circuit region 1 〇 2 The thickness is the same. Moreover, the access transistor 21A and the storage transistor 22A of the non-volatile memory cell 200 of the present invention are all transistors. In addition, another feature of the present invention is that the access transistor 2i and the storage transistor 220 are connected in series to form a single memory unit. Therefore, the non-volatile memory of the present invention is a NOR architecture instead of NAND. Architecture. Referring to Figures 2 through 7 of the present invention, the green color is shown in the preferred embodiment of the present invention for making the squaring note (4) green. Wei, as shown in Fig. 2, a memory array region (10) and a peripheral circuit region 102 are defined on the material conductor substrate 100. First, an N-type ion well 11' is formed by ion implantation in the memory array region 1?1 of the substrate 100. Next, a trench structure 130 is formed on the surface of the substrate. In addition, the trench isolation structure 13〇 may be formed first, and then the ion implantation of the ion wells 110 and 20 may be performed. Next, an N〇 process is performed to form a tantalum stacked layer 150 on the surface of the substrate 100. As described above, the 0N0 stacked layer 15 includes an underlying hafnium oxide layer 15 and a tantalum nitride trap layer 152 and an upper tantalum oxide layer 153. . Next, a photoresist mask pattern 1277179 • 410 is formed on the germanium stack layer 15 in the memory array region 101, which defines a channel region in which the transistor is stored. Next, as shown in Fig. 3, the photoresist stack pattern 41 is used as a side hard mask to perform an engraving process to remove the stack 150 which is not covered by the photoresist mask pattern. Subsequently, the photoresist mask pattern 41 is removed. As shown in FIG. 4, a thermal oxidation process is performed to grow a striation layer 112 having a striking thickness as a core on the semiconductor substrate (10) for use as a gate oxidation of the high voltage MOS transistor in the peripheral circuit region 102. a layer, and a gate oxide layer that serves as an access transistor in the memory array region 101. In accordance with a preferred embodiment of the present invention, the thickness tl of the ruthenium dioxide layer 112 is between about 5 〇 and 2 〇〇. Next, as shown in Fig. 5, a doped polycrystalline stone 114 is deposited on the substrate 1〇〇. Then, a photoresist mask pattern is formed on the doped polysilicon (m) m, which is defined to define the peripheral circuit region 1〇2 and the interpolar position and pattern in the memory array region 1〇1. = Figure 6 shows the use of a photoresist mask pattern 43 〇 as a rhyme hard mask, performing a dry stencil process 'to doped polysilicon layer 114 and oxidized without the photoresist mask pattern 430 The shoal layer 112. Thus completes the peripheral circuit area and the difficult branch in the memory array region 1G1, and forms the gate oxide layer 312 and the interpole structure 2M and the interpolar structure in the memory array region 1〇1. Therefore, the gate oxide layer and the gate structure 314. 1277179 As shown in Fig. 7, after removing the photoresist mask pattern "o, the ion implantation process is separately performed to form a light drain source doping region (LDD) 218 on the semiconductor substrate drains on both sides of the interpole. 228, 318, and then the sidewall process __ 啊 卟 followed by the re-division of the ion distribution process, forming a heavy-dip source-doped region ρ^ in the half-body substrate 100 on both sides of the gate step + / ρ +) 216, 226, 232, 316. Please refer to FIG. 8 , which is a cross-sectional view of a non-volatile memory according to another preferred embodiment of the present invention. As shown in FIG. 8 , A semiconductor substrate 1 , for example, a germanium-type germanium substrate, also includes a memory array region 1〇1 and a peripheral circuit region 102. An ion well 110 is formed in the memory array region 1〇1 by an ion implantation process. For example, a Ν-type ion well is formed with a trench insulating structure 130 on the surface of the substrate, such as a shallow trench insulating (STI) structure. The embodiment and the implementation of FIG. The difference is that in the peripheral circuit area 1 〇 2, in addition to the MOS transistor 310, there is another The same transistor 51A is stored in the memory array region 1-1, and includes a 〇N 〇 dielectric layer 512, a gate 514, and a drain/source doping region 516. The transistor 510 can be used as a trim. The circuit component of the Sense Amplifier reference circuit (ReferenceCircuitTrilnming) makes the reference circuit in the Sense Amplifier more accurate; or it can be inserted into the Amplifier to provide the reference current of the senseAmpiifier, so that the reference current generated by the reference circuit can follow Tracking changes in memory and component characteristics in the memory area, while the crystal memory window _mQryWind()w^ becomes larger' to get better yield and reliability. 11 1277179 v See Figure 9 to Figure 14 is a cross-sectional view showing a method of fabricating an embedded non-volatile memory according to another preferred embodiment of the present invention. As shown in Figure 9, on the semiconductor substrate 100, a memory array region is defined. 1 and the peripheral circuit region 102. First, an N-type ion well 11〇 is formed by an ion implantation process in the memory array region 1〇 of the substrate 1〇, and then, at the base A trench insulating structure 130 is formed on the surface of the trench 100. Alternatively, the trench insulating structure 13 may be formed first, and then the ion implantation of the ion wells 110 and 120 may be performed. Then, an N〇 process is performed to form on the surface of the substrate 100. The stacked layer 150, as described above, the 0N0 stacked layer 15 includes an underlying hafnium layer 151, a tantalum nitride trap layer 152, and an upper hafnium oxide layer 153. Then, the 0N0 stack in the memory array region 1〇1 A photoresist mask pattern 410 is formed on the layer 15 to define a channel region in which the transistor is stored. Next, as shown in Fig. 10, the photoresist mask pattern 410 is used as a _hard mask to perform a side-side process, and the wires are not masked by the photoresist mask _41. Subsequently, the photoresist mask pattern 410 is removed. For example, the U-core-thermal oxidation process, the oxidation pin 112 on the semiconductor substrate (10) is used to form access in the peripheral circuit region 102 101 and as a clock array region. Oxide layer. According to a preferred embodiment of the invention, the thickness (4) of a m is between (four) g angstroms. Next, the semiconductor is formed from 100 - the photoresist (4) is in the cow conductor substrate first blocking mask pattern 420, which covers the memory array region 101 to form a high voltage m〇s transistor in the 1277179 = side circuit The active area: while the violent out of the peripheral circuit area is about to form a low voltage active area 102b. As shown in Fig. 12, a 1-etch process, such as an engraving process, is then performed to cover the 2nd layer of the dioxin layer which is not covered by the photoresist mask pattern (4). Subsequently, the photoresist mask pattern 420 is removed. As shown in Fig. 13, the thermal oxidation process, for example, the furnace tube thermal oxidation process, is performed to form a thickness of the dioxide layer 122 on the active region 10b of the low-voltage paraelectric crystal in the peripheral circuit region 102. Where the thickness is less than the thickness of the thermal oxidation step, the dioxy-cut layer m of the county thickness t2 is thickened to a thickness of ^. According to the present invention, the thickness t3 is about 15 angstroms and is about 50-200 angstroms, but is not limited thereto. Another 4, '. Next' deposited on the 1GG at the bottom of the semi-conducting county - Shixiang Crystal Sales 114. Then, a photoresist mask pattern is formed on the doped polysilicon 114, which defines the gate locations and patterns in the peripheral circuit region 102 and the memory array region 101. As shown in FIG. 14, using the photoresist mask pattern 43 as an etch hard mask, a dry etching process is performed to etch away the doped polysilicon layer 114 not covered by the photoresist mask pattern 43, thus completing the periphery. The gate region 1〇2 and the gate electrode in the memory array region are defined, and the gate oxide layer M2 is formed in the memory array region 101.
13 314 1277179 與閘極結構 閘極氧化層322與閘極結構324。 。 絲絲遮«案之後，縣顺行軒佈難程，以於 閘極賴的半賴基底1G()中形成贿極難摻雜218、⑽、 318、328，·之後進行㈣子製程’緊追隨是再度分別進行離子佈 植製程，以於閘極侧壁子兩側的半導體基底励中形成重沒極源 _ 極摻雜區 216、226、232、316、326。 最後形成之週奴路102内高壓電晶體31〇之閉極氧化層312 厚度與記憶體陣列區域ιοί内存取電晶體21〇之閘極氧化層曰212 厚度相等。 請參閱第15圖，其繪示的是本發明另一較佳實施例之非揮發 • 性圮憶體的剖面示意圖。如第15圖所示，在一半導體基底上， 例如P型矽基底，同樣包括有一記憶體陣列區域1〇1以及一週邊 電路區域102。在記憶體陣列區域1〇1内以離子佈植製程形成有離 子井110，例如N型離子井，而在基底1〇〇表面上形成有溝渠絕 緣結構130，例如淺溝絕緣(shallow trench isolation，STI)結構。本 實施例與第1圖的實施例不同之處在於週邊電路區域1〇2内除了 高壓MOS電晶體310以及^4壓]\^08電晶體320，另有一結構與 記憶體陣列區域1〇1内儲存電晶體220相同電晶體510，其包括 ΟΝΟ介電層512、閘極514以及汲極/源極摻雜區516。電晶體51〇13 314 1277179 and gate structure gate oxide layer 322 and gate structure 324. . After the silk cover, the county’s shunxing Xuan dynasty was difficult, and the formation of bribes in the 1G() of the slabs was extremely difficult to do with 218, (10), 318, 328, and then (4) sub-process Following is the ion implantation process again, to form the plasmon-doped regions 216, 226, 232, 316, 326 in the semiconductor substrate on both sides of the gate sidewall. Finally, the thickness of the closed oxide layer 312 of the high voltage transistor 31 in the Zhounuo Road 102 formed is equal to the thickness of the gate oxide layer 212 of the memory array region ιοί. Referring to Figure 15, there is shown a cross-sectional view of a non-volatile memory of another preferred embodiment of the present invention. As shown in Fig. 15, a semiconductor substrate, such as a P-type germanium substrate, also includes a memory array region 〇1 and a peripheral circuit region 102. An ion well 110, such as an N-type ion well, is formed in the memory array region 1〇1 by an ion implantation process, and a trench isolation structure 130 is formed on the surface of the substrate 1 , for example, shallow trench isolation (shallow trench isolation, STI) structure. The difference between this embodiment and the embodiment of FIG. 1 is that in the peripheral circuit region 1 〇 2, in addition to the high voltage MOS transistor 310 and the ^4 voltage transistor 320, another structure and the memory array region 〇1 The inner storage transistor 220 is identical to the transistor 510, which includes a germanium dielectric layer 512, a gate 514, and a drain/source doped region 516. Transistor 51〇
14 1277179 可以作為修整參考電路的電路元件。 此外’本發明又另一較佳實施例中，除了高壓MOS電晶體310 以及低壓MOS電晶體320之外，週邊電路區域1〇2内亦可以另包 3有中MMOS電晶體(圖未示），其閘極氧化層的厚度介於高麼 MOS電晶體310的閘極氧化層的厚度與低壓M〇s電晶體32〇的 閘極氧化層的厚度之間。 以上所述為本發日仅麵：實施例，凡依本發斜請專利麵 所做之均等變化與料’冑制本發明之涵蓋細。 【圖式簡單說明】 .第1圖繪示的是本發日月較佳實施例之非揮發性記憶體的剖面示 意圖。 第2圖至第7圖_的是本發喊佳實施㈣作喪入式 SONOS非揮發性記憶體方法的剖面示意圖。 第8圖!會示的是本發明另—較佳實施例之非揮發性記憶體的剖 面示意圖。 第9圖至第Μ _邱是本發明另—較佳實施顺作嵌入式 SONOS非揮發性記憶體方法的剖面示意圖。 第15圖繪示献本發料—錄實關之非揮發性記憶體的 剖面示意圖。 127717914 1277179 Can be used as a circuit component to trim the reference circuit. In addition, in another preferred embodiment of the present invention, in addition to the high voltage MOS transistor 310 and the low voltage MOS transistor 320, the peripheral circuit region 1 〇 2 may also include a medium MMOS transistor (not shown). The thickness of the gate oxide layer is between the thickness of the gate oxide layer of the high MOS transistor 310 and the thickness of the gate oxide layer of the low voltage M〇s transistor 32〇. The above description is only for the purpose of the present invention: the equivalent changes made by the patent application according to the present invention are the same as those of the material. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a non-volatile memory of a preferred embodiment of the present invention. Figure 2 to Figure 7 are schematic cross-sectional views of the SONOS non-volatile memory method. Figure 8 is a schematic cross-sectional view showing a non-volatile memory of another preferred embodiment of the present invention. Fig. 9 to Fig. _ Qiu is a cross-sectional view of another preferred embodiment of the invention for implementing the embedded SONOS non-volatile memory method. Figure 15 is a cross-sectional view showing the non-volatile memory of the publication. 1277179
【主要元件符號說明】 100 半導體基底 101 記憶體陣列區域 102 週邊電路區域 102a 主動區域 102b 主動區域 110 N型離子井 112 二氧化矽層 114 摻雜多晶矽層 122 二氧化矽層 130 溝渠絕緣結構 150 ΟΝΟ堆疊層 151 下氧化矽層 152 氮化矽捕陷層 153 上氧化矽層 200 非揮發性記憶體單元 210 存取電晶體 212 閘極氧化層 214 存取閘極 216 Ρ型汲極/源極摻雜區 218 P型輕摻雜汲極 220 儲存電晶體 224 閘極 226 Ρ型汲極/源極摻雜區 228 P型輕摻雜没極 230 側壁子 232 P型没極/源極摻雜區 310 高壓MOS電晶體 312 閘極氧化層 314 閘極 316 汲極/源極摻雜區 318 輕掺雜没極 320 低壓MOS電晶體 322 閘極氧化層 324 閘極 326 >及極/源極換雜區 328 輕摻雜没極 330 側壁子 410 光阻遮罩圖案 420 光阻遮罩圖案 430 光阻遮罩圖案 510 電晶體 512 ΟΝΟ介電層 514 閘極 516 没極/源極摻雜區 16[Main component symbol description] 100 Semiconductor substrate 101 Memory array region 102 Peripheral circuit region 102a Active region 102b Active region 110 N-type ion well 112 Ceria layer 114 Doped polysilicon layer 122 Ceria layer 130 Ditch insulation structure 150 ΟΝΟ Stacked layer 151 Lower yttrium oxide layer 152 Tantalum nitride trapping layer 153 Upper yttrium oxide layer 200 Non-volatile memory cell 210 Access transistor 212 Gate oxide layer 214 Access gate 216 Ρ-type drain/source doping Miscellaneous region 218 P-type lightly doped bungee 220 Storage transistor 224 Gate 226 Ρ-type drain/source doped region 228 P-type lightly doped immersion 230 Sidewall 232 P-type immersion/source doped region 310 high voltage MOS transistor 312 gate oxide layer 314 gate 316 drain/source doped region 318 lightly doped immersion 320 low voltage MOS transistor 322 gate oxide layer 324 gate 326 > and pole / source exchange Miscellaneous region 328 lightly doped immersion 330 sidewall spacer 410 photoresist mask pattern 420 photoresist mask pattern 430 photoresist mask pattern 510 transistor 512 ΟΝΟ dielectric layer 514 gate 516 immersion/source doping region 16