TWI463557B - Method of etching oxide layer and nitride layer - Google Patents

Description

Method for etching oxide layer and nitride layer

This invention relates to a method of etching an oxide layer and a nitride layer, and more particularly to a method of fabricating an oxide-nitride-oxide (ONO) structure.

Integral circuits often include many applications of nitrides and oxides, such as insulating structures between adjacent transistors, spacers on the sidewalls of gates, etch stop layers, protective layers on the outermost layers of the wafer, and ONO structures. .

Taking a non-volatile static random access memory (nvSRAM) as an example, a general nvSRAM includes a static random access unit and a non-volatile memory unit, wherein the static random access unit Part of the information is used to temporarily access data in the case of power supply, while the non-volatile memory unit is used to save data when power is not supplied, and to use non-volatile memory when the power supply is restored. The body unit provides the saved data to the static random access unit for use. The nvSRAM can utilize a germanium-oxide-nitride-oxide-germanium (SONOS) structure as a storage unit. With the operation of the nvSRAM, data signals (such as digital signal 0 and digital signal 1) are written (or programmed), erased, or read in the SONOS structure.

However, in the conventional ONO process for fabricating the SONOS structure, it was found that after the dry etching of the top oxide and nitride, the sidewalls of the swallow trench isolation (STI) structure protruding from the surface of the wafer are often redundant. The residual material layer forms a redundant fence (or sidewall spacer or redundant sidewall). This coverage of the redundant gate wall changes the surface profile of the STI structure and increases the component width of the STI structure. The redundant gate wall will become the mask of the subsequent etching process and the implantation process. Even if the mask position or direction of the implantation process is adjusted, it is difficult to eliminate the influence, thereby reducing the effective area of the doped region and the effective etching window size. In other words, the redundant gate wall will result in a reduction in the effective area of the active area, especially for the narrow width device, and even cause the current of the narrow channel element to drop, affecting its operation.

If an additional isotropic etch process or an anisotropic etch process is added to remove the redundant gate wall, the bottom oxide in the SONOS structure will suffer from a double over-etch, which tends to cause a bottom oxide. The underlying material is damaged, especially in the case where the thickness of the bottom oxide is thin, which in turn affects the electrical properties such as the current amount of the element.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for etching an oxide layer and a nitride layer, which can effectively remove redundant gate walls on the surface of the wafer and prevent damage to the underlying material under the underlying oxide, thereby solving the aforementioned conventional problems.

A method for etching an oxide layer and a nitride layer according to an embodiment of the invention includes the steps of: providing a substrate having an insulating structure on a surface thereof; providing a first oxide layer on the substrate, wherein the first oxide layer is not covered by the insulating structure Providing a nitride layer on the first oxide layer; providing a second oxide layer on the nitride layer; and performing an isotropic etching process to remove the second oxide layer by using an etch mask exposing the insulating structure The exposed portion and the exposed portion of the nitride layer are exposed and the sidewalls of the insulating structure are exposed.

In an embodiment of the invention, the isotropic etching process in the method of etching oxides and nitrides further includes removing a portion of the first oxide layer.

In an embodiment of the invention, the method of etching oxide and nitride further comprises the step of removing the etch mask after the isotropic etching process. In another embodiment of the present invention, the method of etching an oxide and a nitride further includes the steps of: removing the first oxide layer by using an etch mask after the isotropic etching process and before removing the etch mask The exposed part.

In summary, in the embodiment of the present invention, the second oxide layer and the nitride layer are patterned by using a single etching process (for example, an isotropic etching process), and the nitride at the sidewall position of the insulating structure on the substrate is simultaneously removed. And the first oxide layer is only subjected to a single over-etching; compared to the prior art, for the base material under the first oxide layer, even in the case where the thickness of the first oxide layer is thin, in the second oxide layer The etching process with the nitride layer is still not damaged, and the resulting component can have better performance.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Please refer to FIG. 1 to FIG. 5 . FIG. 1 to FIG. 5 are schematic flow charts of a method for etching an oxide layer and a nitride layer according to an embodiment of the present invention. The same elements or parts in the drawings are denoted by the same symbols, and the drawings are for illustrative purposes only and are not drawn in the original size. The method for etching the oxide layer and the nitride layer in this embodiment can be applied to a central processing unit (CPU), a non-volatile memory device, or a digital signal processor. The manufacturing process of semiconductor components such as DSP), but the invention is not limited thereto.

As shown in FIG. 1, a substrate 102 is first provided, such as a germanium substrate, a germanium-containing substrate, or a silicon-on-insulator (SOI) substrate. At least one active region 104 and at least one insulating region 106 may be defined on the substrate 102. The active region 104 can be used to form various active components, such as the ONO structure, the SONOS transistor, or other logic components of the present embodiment, and the shallow trench isolation (STI) or the regional oxidation method can be utilized in the insulating region 106 ( The local oxidation, LOCOS) process creates an isolation structure 108, such as a shallow trench isolation structure or a field oxide layer, to surround and isolate the active components of the active region 104.

During the fabrication of the various components, the top surface 103 of the substrate 102 tends to exhibit an undulating profile with various layout patterns and is therefore not a completely flat surface. For example, in the present embodiment, the isolation structure 108 is an insulating structure of the upper surface 103 of the substrate 102, and is stepped high above the upper surface 103 of the substrate 102, and the height thereof is higher than the substrate on both sides. 300 angstroms (angstrom) or so.

In the above, a bottom oxide layer 110 is provided on the substrate 102. The bottom oxide layer 110 is formed on the upper surface 103 of the substrate 102 to cover the substrate 102 but not over the isolation structure 108 (insulating structure), for example, by thermal oxidation, low-pressure chemical deposition (low-pressure chemical). Vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) processes, in which the bottom oxide layer 110 formed by the thermal oxidation process can have better corrosion resistance, but Not limited to this.

Next, as shown in FIG. 2, a nitride layer 112 is provided on the bottom oxide layer 110. The nitride layer 112 is formed by, for example, a process such as LPCVD or PECVD; the nitride layer 112 covers the bottom oxide layer 110 and the upper surface of the isolation structure 108 (insulating structure) and the sidewalls 1080.

Thereafter, as shown in FIG. 3, a top oxide layer 114 is provided over the nitride layer 112. Specifically, the top oxide layer 114 covers the nitride layer 112, for example, by processes such as LPCVD or PECVD. Here, the top oxide layer 114, the nitride layer 112, and the bottom oxide layer 110 constitute an oxide-nitride-oxide stack layer (ONO stacked layer) 200.

Then, as shown in FIG. 4, a mask layer, such as patterned photoresist 120, is formed on the top oxide layer 114 in the oxide-nitride-oxide stack layer 200, but is not limited thereto. Here, the patterned photoresist 120 does not cover the isolation structure 108 (insulating structure) on the substrate 102. More specifically, the patterned photoresist 120 can be formed, for example, by a coating process and a lithography process; here the patterned photoresist 120 can be located in the active region 104 for defining the location of the subsequent ONO structure. Furthermore, the patterned photoresist 120 preferably includes a deep ultraviolet (DUV) photoresist material, but is not limited thereto. Compared to other photoresist materials, the use of deep ultraviolet photoresist materials can reduce the critical dimensions of the layout pattern and provide better component precision. In other embodiments, a hard mask (not shown) may be additionally formed between the oxide-nitride-oxide stack layer 200 and the patterned photoresist 120, but is not limited thereto.

As shown in FIG. 5, the top oxide layer 114 and the nitride layer 112 may be subjected to an isotropic etching process by directly using the patterned photoresist 120 as an etch mask. As can be seen from FIG. 5, the exposed portion of the top oxide layer 114 (ie, the portion not covered by the patterned photoresist 120) and the exposed portion of the nitride layer 112 are etched away until the bottom oxide layer 110 is exposed, thereby A patterned top oxide layer 114a and a patterned nitride layer 112a are formed, and the nitrided layer 112 that is etched away comprises a nitride layer on the upper surface of the isolation structure 108 and the sidewalls 1080. In addition, the exposed bottom oxide layer 110 is partially removed to form an over-etched bottom oxide layer 110a due to an over-etch, and the removed portion of the bottom oxide layer 110 has a thickness T. It is less than the total thickness of the bottom oxide layer 110.

The isotropic etching process of the embodiment of the present invention will be specifically described below by taking a dry etching process as an example. It should be noted that the isotropic etching process in the embodiment of the present invention is not limited to the dry etching process, and may also be a wet etching process.

Here, the dry etching process may be a radio-frequency plasma etching process which treats the top oxide layer 114 in the oxide-nitride-oxide stack layer 200 in an in-situ manner. The nitride layer 112 is an isotropically etched. More specifically, the RF plasma etch process herein can be performed in a conventional RF plasma etch chamber, and process parameters such as etch temperature, etch gas, RF power, etc., are well known to those skilled in the art. Therefore, it will not be repeated here. The main technical key is that when the nitride layer 112 is etched, the bias on the electrode carrying the substrate 102 on which the oxide-nitride-oxide stack layer 200 is formed is zero or almost zero, so that the substrate 102 is subjected to The DC bias is close to zero, such that the low energy plasma will contact the oxide-nitride-oxide stack layer 200 on the substrate 102 at a lower rate, thereby achieving a better isotropic etch, and In order to preserve some of the original bottom oxide thickness and avoid damage to the surface of the active region 104 due to over-etching, it is necessary to use an etching gas having a good nitride layer and oxide layer etching ratio, for example, using nitrogen fluoride (NF3) and germanium. a mixture of gases (He).

As shown in FIG. 6, after the patterned top oxide layer 114a and the patterned nitride layer 112a are formed, the exposed underetched bottom oxide layer 110a is removed by using the patterned photoresist 120 as an etch mask. The patterned bottom oxide layer 110b is obtained. The etching process herein may be performed by using a buffered oxide etchant. For example, the buffer oxide etchant may include a hydrofluoric acid solution and an ammonium fluoride solution to provide a preferred selectivity; however, the present invention does not This is limited to this.

As shown in FIG. 7, the patterned photoresist 120 is removed and retained under the patterned ONO structure 200a; the ONO structure 200a is located on the substrate 102 and includes a patterned top oxide layer 114a, patterned. The nitride layer 112a and the patterned bottom oxide layer 110b. The removal of the patterned photoresist 120 can be achieved by performing a photoresist stripping process, for example, an ashing process can be performed to remove the patterned photoresist 120.

In other embodiments, as shown in FIG. 8, after removing the patterned photoresist 120, a polysilicon layer 116 may also be formed on the patterned top oxide layer 114a of the ONO structure 200a to produce a SONOS structure.

In summary, the embodiment of the present invention uses a single etching process (eg, an isotropic etching process) to pattern the top oxide layer and the nitride layer in the ONO stacked layer, and the sidewall position of the insulating structure/isolation structure on the substrate. The nitride is removed at the same time and the bottom oxide layer is only subjected to a single overetch; compared to the prior art, for the underlying material under the bottom oxide layer, even in the case where the thickness of the bottom oxide layer is thin, The etching process of the top oxide layer and the nitride layer is still not damaged, so that the finally produced component has better performance.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

102. . . Base

103. . . Upper surface

104. . . Active area

106. . . Insulated area

108. . . Isolation structure

1080. . . Side wall

110. . . Bottom oxide layer

112. . . Nitride layer

114. . . Top oxide layer

200. . . Oxide-nitride-oxide stack

120. . . Patterned photoresist

110a. . . Bottom oxide layer after overetching

112a. . . Patterned nitride layer

114a. . . Patterned top oxide layer

110b. . . Patterned bottom oxide layer

200a. . . ONO structure

116. . . Polycrystalline layer

T. . . thickness

1 is a schematic diagram showing the steps of providing a bottom oxide layer on a substrate in a method of etching oxides and nitrides in accordance with an embodiment of the present invention.

2 is a schematic view showing the steps of providing a nitride layer on the bottom oxide layer shown in FIG. 1.

3 is a schematic view showing the steps of providing a top oxide layer on the nitride layer shown in FIG. 2 to obtain an oxide-nitride-oxide stack layer.

4 is a schematic diagram showing the steps of providing a patterned photoresist on the oxide-nitride-oxide stack of FIG.

FIG. 5 is a schematic diagram showing the steps of performing an isotropic etching process on the oxide-nitride-oxide stack layer using the patterned photoresist shown in FIG. 4 as an etch mask.

FIG. 6 is a schematic diagram showing the steps of further etching away the exposed portion of the underlying oxide layer after over etching using the patterned photoresist shown in FIG. 5 as an etch mask.

FIG. 7 is a schematic diagram showing the steps of removing the patterned photoresist of FIG. 6 to obtain an oxide-nitride-oxide (ONO) structure.

FIG. 8 is a schematic view showing the steps of forming a polysilicon layer on the oxide-nitride-oxide structure shown in FIG.

102. . . Base

104. . . Active area

106. . . Insulated area

108. . . Isolation structure

1080. . . Side wall

110a. . . Bottom oxide layer after overetching

112a. . . Patterned nitride layer

114a. . . Patterned top oxide layer

120. . . Patterned photoresist

T. . . thickness

Claims (8)

A method of etching an oxide layer and a nitride layer, comprising the steps of: providing a substrate having an insulating structure; providing a first oxide layer on the substrate, wherein the first oxide layer does not cover the insulating structure; Providing a nitride layer on the first oxide layer; providing a second oxide layer on the nitride layer; performing an isotropic etching process using an etch mask exposing the insulating structure to remove the An exposed portion of the second oxide layer and an exposed portion of the nitride layer, and exposing sidewalls of the insulating structure; and after the isotropic etching process, removing the exposed portion of the first oxide layer using the etching mask . The method of etching an oxide layer and a nitride layer according to claim 1, wherein the isotropic etching process comprises removing a portion of the first oxide layer. The method of etching an oxide layer and a nitride layer according to claim 1, further comprising the step of removing the etch mask after removing the exposed portion of the first oxide layer. The method for etching an oxide layer and a nitride layer according to claim 3, further comprising the step of: after removing the etch mask, forming a polysilicon layer covering the etched second oxide layer. The method of etching an oxide layer and a nitride layer according to claim 1, wherein the etching mask is a patterned photoresist. The method for etching an oxide layer and a nitride layer according to claim 1, wherein an active region and an insulating region are defined on the substrate, the insulating structure is located in the insulating region, and the etching mask is located in the active region. In the area. The method of etching an oxide layer and a nitride layer according to claim 1, wherein the isotropic etching process is a dry etching process. The method of etching an oxide layer and a nitride layer according to claim 1, wherein the isotropic etching process is a wet etching process.