TWI222015B - Mechanism for extending the number of registers in a microprocessor - Google Patents

Abstract

An apparatus and method are provided, for accessing extended registers within a microprocessor. The apparatus includes translation logic and extended register logic. The translation logic translates an extended instruction into corresponding micro instructions for execution by the microprocessor. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies register address extensions, the register address extensions indicating the extended registers, where the extended registers cannot be specified by an existing instruction set. The extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set. The extended register logic is coupled to the translation logic. The extended register logic receives the corresponding micro instructions, and for accesses the extended registers.

Description

1222015 (Patent No. 09m6959 Specification and Application% | Lifan

V. Description of the Invention (Comparison with related applications [0_ This application is based on the United States and China's application for superiority ----- PI ----- Hongzhuang-(Please read the precautions on the back before (Fill this page), the application is April 2nd, and the patent name is "Apparatus and Method for Increasing the Number of Temporary Registers of U Microprocessors". [00〇2] This application is in the same shot as the following The United States patent application is related to the same application and the same applicant and inventor: TW SERIAL NUMBER DOCKET NUMBER ------_ Patent Name 辎 91116957 CNTR: 2176 Extended microprocessor instruction set Device and method 91116958 CNTR: 2186 Device and method for executing conditional instructions 91116956 CNTR: 2188 Device and method for selectively controlling condition code write-back 91116672 CNTR: 2198 Device and method for selectively controlling result write-back

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics (1) Technical Field of the Invention: [0003] The present invention relates to the field of microelectronics, in particular to an additional addressable register that can be incorporated into an existing microprocessing Technology of the processor instruction set architecture. (II) Technical background of the invention: [0004] Since its development in the early 1970s, the use of microprocessors has been 2 paper sizes applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Employee Consumption Cooperatives 1222015 (Patent No. 091116959 Patent Specification and Revised Range of Benefits) V. Description of Invention (>) Exponential growth. From the earliest applications in science and technology, to the consumer domain that has now introduced business from those special areas, such as desktop and laptop computers, video game controllers, and many other common home and business devices And other products. [0005] With the explosive growth in use over the past thirty years, it has also undergone a corresponding improvement in technology, which is characterized by the following requirements for increased benefits: faster speed, stronger addressing ability , Faster memory access, larger operands, more general-purpose operations (such as floating-point operations, single instruction multiple data (SIMD), conditional moves, etc.) and additional special-purpose operations (such as digital signals Processing functions and other multimedia operations). This has created amazing technological progress in this field, and has been applied to the design of microprocessors' like extensive pipelining, super-scalar architecture, cache structure, out-of-order processing (〇 ut_〇f 〇rder processing), burst a_s mechanism, branch prediction (b_h

Predication) and speculative execution. To put it bluntly, today's microprocessors are more complex and powerful than they were when they first appeared 30 years ago. [0006] But unlike many other products, there is another very important factor that has been limited and continues to limit the evolution of microprocessing. Today's microprocessors can be so complex, a large part of which is due to this factor, the compatibility of legacy software. In consideration of the market, many manufacturers chose to incorporate new architectural features into the latest microprocessor designs, but at the same time, in these latest products, all of the latest products have been retained to ensure compatibility with the older, so-called "old Have the necessary capabilities for legacy applications. ”” — — — — — — — ——— · II (Please read the notes on the back before filling this page) Order ·-

1222015. No. 0W116959 patent case specification and revised range of interest

Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs [0007] This old software compatibility burden is nowhere more apparent than in the history of the development of x86-compatible microprocessors. Everyone knows that today's 32 / 16-bit virtual-mode x86 microprocessors' can still execute 8-bit real-mode applications written in the 1910s. Those skilled in this field also acknowledge that there are many related architectures “coated” stacked in the χ86 architecture, just to support the hybrid with the old applications and operating modes. Relying on the past, developers can add newly developed _ features to existing instructions #_, but nowadays, using these J1 tools secreted by these features, programmatic instructions can be quite rare. More specifically, in some important instruction sets, there are no “redundant” instructions, allowing designers to incorporate updated features into existing architectures. [0008] For example, in the xg6 instruction set architecture, there is no any undefined-byte-size opcode state, and it is not yet used. In the main one-byte size χ86 opcode diagram, all 256 opcode states have been occupied by existing instructions. As a result, designers of χ86 microprocessors must now make a choice between the two. To provide new, programmable features, you must assign opcodes to the features. If there are no redundant opcode states in the existing instruction set architecture, some existing opcode states must be rewired to provide new features. Therefore, to provide new features, it is necessary to sacrifice legacy software compatibility. [0009] A domain that continues to develop but still haunts microprocessor designers is the number and reliance of reduction storage. Early micro

(Please read the notes on the back before filling this page)

This note H national standard (CNS) A4 specifications (210 X 297 public love) printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1222015 (Amended the specification and application scope of the patent case No. 09⑴6959) V. Invention Note (f) The processor design provides one or two general purpose 8-bit registers. Since then, as the calculations in the application have become more complex, the number and size of general-purpose registers have increased. As far as microprocessors used in desktop / laptop software are concerned, less than ten 32-bit general-purpose registers are available at the current technical level. So far, there are still areas of applications that are adversely affected because microprocessors do not provide more addressable general-purpose registers. [0010] Therefore, what we need is an apparatus and method that can incorporate additional general-purpose registers into an existing microprocessor instruction set architecture, where the existing instruction set is completely completed by a defined operation code It can be used, and this technology also allows-microprocessors that meet the old specifications to retain the ability to execute old applications. (3) Brief Description of the Invention [0011] The present invention, like the other applications mentioned above, addresses the problems and disadvantages of the above and other conventional technologies. The present invention provides a better technology for expanding the instruction set of the microprocessor beyond its existing capabilities, and long: for additional general purpose registers, the content of which can be programmed by the microprocessor instruction set Use instructions to perform operations. In a specific embodiment, a device for accessing an extended register in a microprocessor is provided. The device includes a translation logic and an extended register logic. The translation logic translates an extended instruction into a corresponding micro instruction, which is executed by the microprocessor. The extended instruction has an extended prefix and an extended prefix code. It says that the standard applies to the Chinese National Standard (CNS) A4 specification (210 X 297 meals) '----

Binding-Staple: (Please read the notes on the back before filling this page)

Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1222015 (Patent No. 091116959, the amended version of the specification and scope of application of profits) " ----------- V. Description of Invention (ί) (extended prefix tag). The extended preamble specifies the register address extensions. These extensions indicate the extended register, where the extended register cannot be referred to by the existing instruction set ^. The extended preamble mark indicates that the extended preamble 'is another operation code specified in the existing instruction set according to the architecture. The extended register logic is connected to the translation logic to receive the corresponding microinstruction and access the extended register. [(ΚΠ2] An object of the present invention is to propose an extension-existing instruction set mechanism to provide additional operand temporary storage mechanism H. The mechanism includes -extend instruction and -translator. The extended instruction specifies Correspondence—The additional operands of the specified operation are temporarily stored in II, and the extended instruction includes the selected operation difference code of the existing microprocessor instruction set, followed by an η-bit extended preamble. The selected The operation code indicates the extended instruction, and the n-bit extended preamble indicates the additional operand register, wherein the additional operand register cannot be specified separately according to the existing microprocessor instruction set. The translator Receiving the extended instruction and generating a micro instruction sequence to instruct the microprocessor to access the additional operand register when the specified operation is performed. [0013] Another object of the present invention is to provide a Instruction set extension group with instruction set to add the addressing capability of extended temporary H. The instruction set extension module has an escapetag, an extended registers specifier, and an extension Extended register logic. The escape tag is received by a translation logic and indicates that the accompanying part of a corresponding instruction specifies an extended operation to be performed by a microprocessor, where the escape tag is the existing There is one of the first opcode items in the instruction set. The designated element of the extended register is coupled to the escape mark and is the attached part. _______ 6 This paper size applies to China National Standard (CNS) A4 specifications (21 〇X 297 public love) ----- 1 --------- install --- (Please read the precautions on the back before filling this page) Order: A7 1222015 I (Case No. 091116959 The specification of the patent case and the amendment of the claim scope. 5. One of the points of the invention description (L). The extension register designator specifies a plurality of address extension items corresponding to the extension register. The register is the place of the extended operation. The extended register logic is connected to the translation logic. When the specified operation is performed, the extended register is accessed, where the existing instruction set only provides addressing. Has the ability to register, and the extended register can be specified [0014] Another object of the present invention is to provide a method for expanding an existing instruction set architecture to provide a programmable addressing capability of an extended register in a microprocessor. The method includes providing an extended instruction, the extended instruction includes an extended tag and an extended preamble, wherein the extended tag is a first operation code item of the existing instruction set structure; and the extended preamble and the extended The rest of the instruction specifies the extended register, where the extended register is accessed when a specified operation is performed, and the existing instruction set architecture only provides addressable existing registers based on the instruction set architecture. Instructions; and when the specified operation is executed, access the extended register. (IV) Illustration of the invention: [0015] The foregoing and other objects, features, and advantages of the present invention will be better understood after cooperating with the following description and accompanying drawings: [0016] [0017] FIG. 2 is a table describing the instruction 'in an instruction set architecture corresponding to an 8-bit operation code byte in the instruction format of FIG. Bit logic state; 'Paper scale thorn + Guan Jiabiao half ((JNS) A4 specification (210 X 297 public meals-1 I! — I (Please read the precautions on the back before filling this page) · · Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Employee Consumption Cooperative 1222015 (Patent No. 09111 Silicon No. 59 Patent Specification and Amendment Claim Range) V. Explanation of the Invention (?) [0018] FIG. 3 is a block diagram of the extended instruction format of the present invention [0019] FIG. 4 is a table showing how the extended architecture features correspond to the logical states of the bits in an 8-bit extended preamble embodiment according to the present invention; [0020] FIG. 5 is an illustration of the present invention Used to access one of the extended registers [0021] FIG. 6 is a block diagram of a specific embodiment of an extended preamble of an additional register for an addressing microprocessor of the present invention; [0022] FIG. 7 is a diagram [0023] FIG. 8 is a block diagram of the extended register stage logic in the microprocessor of FIG. 5; and [0024] FIG. 9 is a description of the present invention. The operation flowchart of the method for translating and executing the instructions of the extended register of the addressing microprocessor. Explanation of the drawing number: 100 instruction format 102 operation code 200 8-bit operation code figure 202 operation code F1H 300 extended instruction format 302 operation code 304 extended instruction mark 400 8-bit preamble figure ____ 8 Paper size weekly dry country and national standard (210 X 297 meals)

Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Consumption Cooperatives, the prefix 103 address designation element 201 operation code value 301 prefix 303 address designation element 305 extended prefix 401 extension features. (Please read the (Please fill in this page again)

1222015 A7 (Patent No. 091116959 patent specification and application scope amendments) V. Description of invention (ί) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives 500 Pipelined microprocessor 501 Extraction logic 502 Instruction fast Fetch memory / external memory 503 Instruction queue 504 Translation logic 505 Extended translation logic 506 Micro instruction queue 507 Execution logic 508 Extension execution logic 600 Extension prefix 601 Source address Extension field (S3) 602 Destination address Extension block (D3) 603 Spare block 604 Opcode and address designation meta-item 605 Opcode and address designation meta-item 700 Translation stage logic 701 Start status signal 702 Machine-specific register 703 Extended feature field 704 Instruction Buffer 705 Translation logic 706 Translation controller 707 Disable signal 708 Escape instruction detector 709 Extended preamble decoder 710 Instruction decoder 711 Control read-only memory 712 Micro-instruction buffer 714 Micro-op code block 715 Purpose Block 716 Source Block 717 Displacement Block 800 Extended Register Stage Logic 801 Micro Instruction 802 register logic 803 extended register file 804 source address block 805 source address block 806 extended read logic 807 extended write back logic 808 microinstruction buffer 809 operand buffer 9 National Standard (CNS) A4 Specification (21〇χ 297 mm) ——l · —-------- M Pack—— C Please read the notes on the back before filling this page) Order · · 1222015 Ministry of Economic Affairs Printed by the Intellectual Property Bureau's Consumer Cooperative (the specification and application of the case No. 091116959 patent, the revised version of the profit scope) V. Description of the invention (?) Buffers 900 to 926 The operation flow of the method for translating and executing instructions of the extended register of the addressing microprocessor (5) Detailed description of the invention: [0025] The following description is a specific embodiment and its necessity It is provided in the context of conditions, so that those skilled in the art can utilize the present invention. However, various modifications made to the preferred embodiment will be apparent to those skilled in the art, and the general principles discussed herein can also be applied to other embodiments. Therefore, the present invention is not limited to the specific embodiments shown and described herein, but has the widest scope consistent with the principles and novel features disclosed herein. [0026] The foregoing has discussed the background of today's microprocessors on how to extend their architectural features to exceed the capabilities of the relevant instruction set. In view of this, an example of related technology will be discussed in Figs. 1 and 2. The discussion here highlights the dilemma that microprocessor designers have been facing. On the one hand, they want to incorporate the newly developed architecture features into the design of the microprocessor, but on the other hand, they must keep the old implementation. Application capabilities. In the example of Figures 1-2, a fully occupied opcode diagram has added new opcodes to the audible structure of the example architecture, thus forcing the designer to sacrifice some degree of choosing to incorporate new features The old software is mixed, or the latest developments in the architecture-or give up, in order to transfer the microprocessor to the application phase. After discussion of related technologies, as shown in Figures 3-9, ---- l · ------- 4 packs will be provided. (Please read the precautions on the back before filling this page)

The paper size Lai Jin_CNS (A4 x 297 mm) A7 (Description and Amendment of Patent No. 091116959) 5. Description of the invention)

Discussion of the invention. By using an existing but unused opcode as an extension instruction pre-coded tag, the present invention allows microprocessor designers to overcome the limitations of a fully used instruction set architecture, allowing them to provide additional general The purpose register is used by programmers while retaining compatibility with legacy applications. [0027] Please refer to FIG. 1, which is a block diagram of a related art microprocessor instruction format 100. The related technology instruction 100 has a variable number of data items 101-103, and each item is set to a specific value, which together constitutes a specific instruction of the microprocessor. The specific instruction instructs the microprocessor to perform a specific operation, such as adding two operands, or moving an operand from memory to a register in the microprocessor. In general, the operation code item 102 in the instruction 100 specifies the specific operation to be performed, and the optional address designation meta-item 103 is located after the operation code 102, and determines the specific operation. Additional information, such as how to perform the operation, where the operands are located, and so on. The instruction format 100 also allows the programmer to add a preamble item 101 before an operation code 102. When a specific operation specified by the operation code 102 is executed, the preamble 101 is used to indicate whether to use a specific architectural feature. In general, these architectural features can be applied to most of the operations specified by any opcode in the instruction set. For example, today's preamble ⑼ exists in some microprocessors that use ^ the same size operands (such as 8-bit, 16-bit, 32-bit) to perform ^ operations. When such a processor is programmed into a preset size (for example, 32-bit), it is set in its personal order set = provided month J Zhima 101, which still allows the programmer to follow the instructions To selectively override the preset operand size (for example, to implement a 16-bit operation & apply the Chinese national standard ^ iS) A4 specifications ⑽ x Norwegian meal) 1222015 A7 (Case No. 0911) 6959 patent case specification and amendments to the application scope of the application) V. Description of the invention ([ί ---- h ------- Μ 装 —— (Please read the precautions on the back before filling in this page ) Count). The selectable operand size is just one example of architectural features. In many modern microprocessors, these architectural features can be applied to many operations that can be specified by opcode 102 (such as addition, subtraction, multiplication, Bollinger logic, etc.) . [0028] The instruction format 100 shown in FIG. 1 has a well-known example in the industry. This is the X86 instruction format 100, which is used by all modern microprocessors compatible with Bubb. More specifically, the χ86 instruction format 100 (also referred to as the χ86 instruction set architecture 100) uses an 8-bit preamble 101, an 8-bit opcode 102, and an 8-bit address designator 103. The Z6 architecture 100 also has several preambles 101, two of which replace the preset address / data size of the χ86 microprocessor (that is, the opcode states 66Η and 67Η), and the other indicates the microprocessor Interpret the following operation code byte 102 according to different translation rules (that is, the preamble value 0FH 'which makes the translation action based on the so-called exhaustion rule of two-byte operation), and the other preamble Code 101 causes the correlation operation to be repeatedly performed until the repetition condition is satisfied (that is, the REP operation codes: F0H, F2H, and F3h). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs [0029] Please refer to FIG. 2 which shows a form 2⑻ describing how the instruction 201 of an instruction set architecture corresponds to an 8-bit operation code point in the instruction format of FIG. Bit value of tuple 102. Table 200 presents an exemplary 8-bit opcode map 200, which associates up to 256 values of an 8-bit opcode item 102 to the corresponding microprocessor opcode instruction 2 1. The table 200 maps a specific value of the operation code item 102, such as 〇2H, to a corresponding operation code instruction 201 (ie, the instruction 102 02). In the example of the χ86 opcode diagram, as is well known in the art, the opcode value 14 is mapped to the χ86 Add With Carry (ADC) instruction. This instruction is an 8-bit immediate (immediate The operand is added to the architecture register al

1222015 A7 (Case No. 099 116959 Patent Specification and Application, Amendment of Sharpening Scope) V. Included value in the description of the invention (丨 >). Those skilled in this field will also find that the above-mentioned X86 premature 101 (ie, 66Η, 67Η, 0FH, F0H, F2H, and F3H) is the actual operation code value 201, which specifies the requirements in different contexts. A specific architectural extension is applied to the operation specified by the subsequent operation code item 102. For example, adding the preamble 0FH before opcode 14Η (normally, the aforementioned ADC opcode) will cause the χ86 processor to perform a "decompress and insert low-compression single-precision floating-point value" (Unpack and Interleave Low Paeked

Single-Precision Floating-Point Values) instead of the original ADC. This is because ‘when an x86 processor encounters the preamble 0j? H, another translation rule is used. The features described in this x86 example are partially enabled in modern microprocessors. This is because the instruction translation / decoding logic in the microprocessor is to sequentially interpret an item 100 of an instruction 100M. 3. Therefore, in the past, the use of the transposed operation code value as the preamble 1G1 in the instruction set architecture can allow microprocessor designers to incorporate many advanced architectural features into the design towel compatible with the old software microprocessing H. It will have a negative impact on the implementation of old programs that have not brought the status of some specific opcodes. For example, the old programs that have not used the opcode 0FH can still be executed on today's χ86 microprocessors. A newer Lang program, by using the X86 opcode _ as the preamble 101, can use many newly incorporated X86 architecture features, such as a single instruction multiple data (S_) operation, conditional movement operations, and so on. The potassium excess is calculated by the extra material of the shirt. The code value is 2101 = then the code is 101 (also known as the architectural feature mark / indicator). However, when the material is strengthened, it will still be very direct. The reason for this is to meet the obstacles: This paper size applies the Chinese national standard (CNSg ^^ Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Consumption Cooperatives, 丄 222015 I—, ^ 091116959, patent case t and amendments to the scope of application benefits]: -The available opcode values have been used up, that is, the Wang opcode values in opcode image II have been architecturally specified. When all available values are divided into I μ as opcodes When the project ι〇2 or the unique code project ιοί, no remaining opcode value can be used to incorporate new features. This serious problem exists in many microprocessor architectures today, forcing designers to add architecture [0031] The instruction 201 shown in Figure 1 is expressed in a general way (ie, 124, 186), rather than specifically referring to the actual operation ( Such as carry accumulation, subtraction, mutual exclusion or). This is because In some different microprocessor architectures, the fully occupied operation code Figure 200 has been excluded from the possibility of incorporating newer developments. Although the example in Figure 2 mentioned above is an 8-bit operation Code item 102, those skilled in the art will still find that the specific size of the opcode 102, except as a special case, discusses the problems caused by the fully occupied opcode structure 200. 'Other aspects are not the same as the problem itself. Irrelevant. Therefore, a fully occupied 6-bit opcode map will have 64 opcodes / preambles 201 that can be architecturally specified, and will not provide usable / excessive opcode values for expansion. [ 0032] Another alternative is not to completely obsolete the original instruction set 'in a new format 100 and operation code Figure 2', but only to a part of the existing operation code 201, with new instructions Implied substitution, as shown in Figure 2 with opcodes 40Η to 4FH. With this hybrid technology, the microprocessor can operate in one of two modes separately: The old mode uses opcodes 40H-4FH 'system is still There are rules to come Interpretation, or operate in another enhanced mode, at this time the operation code 40H-4FH is interpreted according to the enhanced | architectural rules. This technology does allow designers to incorporate new features into the design paper scale_ , Yi Zui (CNS) A4 specifications (210 X si4 public meals) ----

(Please read the precautions on the back before filling this page)%. 1222015 (The specification of the patent case No. 091116959 and the amended scope of application) 5. V. Description of the invention Disadvantages still exist when microprocessors with specifications operate in enhanced mode, because the microprocessor cannot execute any applications that use the opcodes 40H-4FH. Therefore, from the standpoint of retaining the compatibility of the old software, the technology compatible with the old software / enhancement mode is still unacceptable. [0033] However, for the instruction set 200, where the opcode space has been fully occupied, and the space covers all applications that are executed on a microprocessor that conforms to the old specifications, the inventor of this case has noticed that the opcode 20 1, and they also observe that although some instructions 202 are specified architecturally, they are not used in applications that can be executed by a microprocessor. The IF1 202 described in Figure 2 is an example of this phenomenon. In fact, the same opcode value 202 (ie F1H) is mapped to a valid instruction 202 that is not used in the x86 instruction set architecture. Although the unused χ86 instruction 202 is a valid χ86 instruction 202, which instructs a architecturally specified operation to be performed on a χ86 microprocessor, it is not used on any modern χ86 microprocessor. Run an existing application. This special χ86 instruction 202 is called the In Circuit Emulation Breakpoint (ie, ICE ΒΚΡΤ, the opcode value is F1H). It was previously used exclusively for a microprocessor simulation device that no longer exists. in. ICE BKPT 202 has never been used in applications other than in-circuit simulators, and in-circuit analog devices that previously used ICEBKPT 202 no longer exist. Therefore, in the case of x86, the inventor of this case has found a tool in a completely occupied instruction set architecture 200, by using an effective but unused operation code 202, to allow advanced microprocessors to be incorporated into the design of the microprocessor. Without compromising the compatibility of legacy software. In a fully occupied instruction set architecture 20, the present invention utilizes a structured private paper scale that applies the Chinese National Standard (CNS) A4 specification (21〇X 297 Public Love I — — — — — — — — — — i I (Please read the precautions on the reverse side before filling out this page) Order-• ^ · Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs's Consumer Cooperatives 15 1222015 A7 Yi No. 09111 (Patent Specification No. 5959 and a revised scope of Shenheng Shengli) 5. Description of the Invention (rT) Read the specified but unused operation code 002 as an index mark to indicate the next Π-bit preamble, so the microprocessor designer is allowed to add up to 2η The latest development architecture features are incorporated into the design of the microprocessor while retaining full compatibility with all the old software. [0034] The present invention provides an η-bit extended register designator element preamble 'to The use of the preamble marking / extended preamble concept allows programmers to specify additional general-purpose registers already provided in the microprocessor in addition to the general-purpose registers provided by the existing microprocessor instruction set architecture. use The present invention will now be discussed further with reference to FIGS. 3 to 9. [0035] Please refer to FIG. 3, which is a block diagram of the extended instruction format of the present invention, Deng Yue. Format 1 discussed by Lang Yi 〇It is very similar. The extended instruction format 300 has a variable number of instruction items 301.35. Each-item is set to a specific value, which is aggregated to form a specific instruction of the microprocessor. The specific instruction 300 indicates micro The processor executes a specific operation, such as adding two operations and one operation, or moving an operation heterogenous element from memory to a temporary register written by the microprocessor. Generally speaking, the operation code item 300 of instruction 300 specifies ^ So: the specific operation of Ding, and the selected address specifies 3 meta-items to specify the phase of the specific operation $ 马 = location, etc. The command format is 30. Also the same code 302 刖 plus the preamble item 3〇1 When the specific operation specified is performed, the pre-exhaustion item view is used to === use the existing architectural features. Ding Yi wants to use two. 36] However, 'the extended instructions of the present invention tear one of the formula 〇〇 Superset ㈣ ^ Paper size suitable " ^ National Standard 1222015 A7 (Case No. Specification of Patent No. 091116959 and amendments to the application scope) V. Invention Description (jin) 305 can be selectively used as an instruction extension item and placed before a formatted extension instruction 300 towel before all the remaining items 301-303. These two additional items 304 and 305 allow programmers to specify the address of an additional or extended general-purpose register in a microprocessor that conforms to the old specifications, in order to perform operations on its operands. The extended address cannot be programmed by the existing instruction set of the microprocessor that conforms to the old specifications. The options 304 and 305 are an extended instruction mark 304 and an extended register designator. Prefix 30.5. The extended instruction mark 304 is another operation code specified by the architecture in a microprocessor instruction set. In an x86 embodiment, the extended instruction flag 304, or escape flag 304, uses the opcode state F1H, which is the ice BKPT instruction used earlier. The escape mark 304 indicates to the microprocessor logic that the extended register designation element prefix 305, or extended feature designation element 305, follows, and the extended register designation element 305 designation follows. The extended address of the register in the microprocessor 'corresponds to the operation 70 / result that is required / generated for performing a specified operation. In a specific embodiment, the escape tag 304 indicates that the accompanying sections 301_303 and 305 of the corresponding instruction 300 specify the & operation required by the microprocessor. The extension register designation element 305, or extension preamble 305, specifies a plurality of address extensions corresponding to the extension registers required for the extension operation. The extended register logic in the microprocessor accesses the extended register when the extended operation is executed. [0037] The extension techniques used in the present invention are summarized here. As an extension, the command is to specify an additional operand register in an existing microprocessor instruction set. The additional operand register cannot be specified separately according to the existing microprocessor instruction set. The extended instruction contains the operation code of the existing instruction set / 17 297 mm) This paper standard Gu + Family Standard (CNS) A4 specification (21〇: (Case No. 091116959 patent specification and application for sharpness) One of the scope amendments), the invention description (I; /) instruction 304, and an n-bit extension feature preamble 3505. The selected operation code / instruction is used as an index 304 to indicate the instruction 3〇 〇 is an extended feature instruction 300 (that is, it specifies an extension of the microprocessor architecture), and the n-bit feature preamble 305 indicates the additional operand register. In another specific embodiment, The extension preamble 305 has an octet size and can specify up to 256 different values. It can be configured to specify a plurality of register address extensions corresponding to the extension registers required for a related extension operation. In the embodiment of the n-bit preamble, a maximum of 2n different address extensions can be specified. [0038] Please refer to FIG. 4. A table 400 shows how the register extensions are mapped according to the present invention. Bit logic state to an 8-bit extended preamble embodiment Similar to the operation code diagram 200 discussed in FIG. 2, the table 400 in FIG. 4 presents an example of the code diagram 400 before an 8-bit register designator, which extends an 8-bit register before The maximum 256 values of the coded item 305 are related to the corresponding register address extension item 40 (such as E34, E4D, etc.) of a microprocessor that conforms to the old specification. In a specific embodiment of χ86, The 8-bit extended feature preamble 3 of the present invention is provided to the aforementioned register designator 401 (ie, E00-EFF). These designators 401 are the current instruction set architecture. Failed to provide. [0039] The extended feature 401 shown in Figure 4 is expressed in a general way, rather than specifically referring to the actual feature. This is because the technology of the present invention can be applied to a variety of different architectural extensions. Xiang Xian and a specific instruction set architecture. Those skilled in the art will find that many different architectural features 401, some of which have been mentioned above, can be extended according to the escape mark 304 / extended here The preamble 305 technology incorporates it into the existing instruction set. The 8-bit preamble in Figure 4 implements 1222015 A7 (Case No. The specification of the patent case No. 09⑴6959 and the scope of the amendment are modified too. V. The invention description (J) provides 256 different features. The embodiment of an n-bit preamble has a maximum of 2 n different features. 401 [0040] Different embodiments can be configured according to a special existing microprocessor instruction set to address its existing registers. For example, an embodiment is extended before The code 305 provides a plurality of source register and destination register designating meta blocks, which can completely replace the existing register designating fields in the rest of the extension instruction 3⑻ 301-303. — An expansion block The embodiment includes a plurality of source register and destination register address extension stops, the contents of which can be used as the rest of extension instruction 300 in the 03- 03, the existing register designated stop The extension of the specified source / destination register address. In one form of this embodiment, the address extension term is used as a plurality of higher register address bits, and these bits correspond to the lower temporary registers in the remaining parts 301-303. Register address bits to specify the extended register. Another different embodiment does not use separate blocks to specify the operand register, but uses a specific encoding value of the η-bit extension preamble 305 to specify one of the operations to be applied The source / destination operand register corresponding to the group. According to the present invention, the address of the extension register in the n-bit extension preamble 305 can be encoded in a number of different ways. However, those skilled in the art will find that the specific encoding form used to specify the register extension of the n-bit extension preamble 305 depends on the specific microprocessor architecture and instruction set to which the present invention is applied. . When a selected escape instruction 304 is encountered, it means that there is an η-bit extended preamble 305, and its size can be determined in an optimized manner to match the designation of various extended registers. [0041] Please refer to FIG. 5, which illustrates the present invention for accessing the extension temporary I____19 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 male feet) 1222015 A7 — one (case No. 091116959 patent case description and amendments to the scope of application of profits) V. Description of the invention (Θ) 1 — — — — — — — II (Please read the precautions on the back before filling this page) The pipeline of the register Block diagram of a microprocessor 500. The microprocessor 500 has three distinct types of stages: fetch, translate, and execute. The fetch stage has fetch logic 501 'which fetches instructions from the instruction cache memory 502 or external memory 502. The extracted instructions are sent to the translation stage via the instruction queue 503. The translation stage has translation logic 504, which is coupled to a micro-instruction queue 506. The translation logic 504 includes extended translation logic 505. The execution phase includes execution logic 507, which includes extended execution logic 508. [0042] According to the present invention, during operation, the extraction logic 501 extracts formatting instructions from the instruction cache memory / external memory 502, and places these instructions into the instruction in the order in which they are executed> [宁 列 503 in. These instructions are then extracted from the instruction queue 503 and sent to the translation logic 504. The translation logic 504 translates / decodes each incoming instruction into a corresponding microinstruction sequence to instruct the microprocessor 500 to perform the operations specified by these commands. According to the present invention, the extended translation logic 505 narrows down those instructions with extended preamble flags, and provides translation / decoding of meta-prefixes as corresponding extended registers. In an χ86 embodiment, the 'extended translation logic 505 is configured to detect an extended preamble flag whose value is F1H, which is an ICE BKPT operation code for X86. The extended microinstruction stoppage is provided by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, which is printed in the microinstruction array 506 to allow the designation of an internal register attached to the microprocessor 500. [0043] The microinstruction is sent from the microinstruction system 506 to the execution logic 507, where the extended execution logic 508 is configured to access the inside of the microprocessor as specified by the extended microinstruction block. Register. The plurality of source operands designated for execution of a particular operation are taken from the source operand extension register. Extended execution logic 508 executes the operation specified by the micro instruction, and generates a phase scale of iii, iiiriii, standard (CNS) A4 specification, 〇χ 2927〇 public meal 1222015 A7 (Case No. 09/116959) Revision of the instruction manual and Shenheng's profit scope} V. Invention description (r ") The consumer's cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs prints the corresponding result. After the corresponding result is generated, extended execution logic 508 writes back the corresponding result to the extended micro [0044] Those skilled in the art will find that the microprocessor 500 shown in FIG. 5 is a simplified result of the modern pipelined microprocessor 50. Facts In the above, the modern pipelined microprocessor 500 can include a maximum of 20 to 30 different pipeline stages. However, these stages can be generally classified into three stages shown in the block diagram. Therefore, the block diagram 500 of FIG. It can be used to point out the necessary elements required for the foregoing embodiments of the present invention. For brevity, irrelevant elements in the microprocessor 500 are not shown. [0045] Please refer to FIG. A block diagram of a specific embodiment of an extended preamble 600 for an additional register of an addressing microprocessor. The extended register designated meta-prefix 600 is an 8-bit extended preamble 600, It includes a source address extension entry block 601 (S3), a destination address extension entry block 602 (D3), and a spare block 603. According to the present invention, the S3 block 601 includes a bit of the prefix 600. 〇, and is used by the extended register logic, as a four-bit first extended source register address bit 3. The remaining three bits of the four-bit first extended source register address Meta [2: 0] is specified by the remaining operation code and address designation meta-items 604, which are provided according to the register specific conventions of the existing microprocessor instruction set architecture. According to the present invention, the D3 block 602 includes bit 1 of the preamble 600 and is used by the extended register logic as bit 4 of the first extended source register address of a four bit. The four bits The remaining three bits of the second extended source register address [2: 〇] are determined by the remaining opcodes and bits 21 Μ Zhang feet money National Standard (CNS) A4 k grid coffee X 297 male love)

— 111 — — — — — — — — — — · II (Please read the notes on the back before filling out this page} (Instructions and amendments to the application range) 5. The invention description () The address designation meta-item 605 is specified, which is provided in accordance with the conventional register designation convention of the existing microprocessor instruction set architecture. The second extension source The register address is also used as the destination register address as a result of performing an operation. [0046] The example of the extended preamble 600 of the present invention shown in FIG. 6 reflects that one is applicable to the x86 instruction set architecture. An embodiment of the register extension. The current x86 architecture provides eight general-purpose registers, which are specified in accordance with an opcode byte and an address byte (referred to as the M86d / M and Sffi bytes) are specified in the existing χ86 instruction. By using the extended preamble 600 as shown in the figure, S3 601 and D3 602 blocks, one The number of addressable registers in the χ86 microprocessor can be Increased from eight to sixteen. Those skilled in the art will find that providing two-bit source and destination fields 601 and 602 in the extended preamble will enable addressable temporary storage under an existing architecture. [0047] Please refer to FIG. 7, which is a detailed block diagram of the translation stage logic 700 in the microprocessor of FIG. 5. The translation stage logic 700 has an instruction buffer 704, which Provide extended instructions to the translation logic 705. The translation logic 705 is coupled to a machine-specific register 702 with an extended feature stop 703. The translation logic 705 has a translation controller 706, which A disabling signal 707 is provided to an escape instruction detector 708 and an extension decoder 709. The escape instruction detector 708 is coupled to the extension decoder 709 and an instruction decoder 710. Extension The decoding logic 709 and the instruction decoding logic 71 () access a control read-only memory (ROM) 711, which stores a template micro-instruction sequence corresponding to some extended instructions. The translation logic 705 also contains A micro-instruction buffer 712 having a micro-op code field 714 Paper size for one purpose _ + _ home specifications 29 / x29 /; £ y (Please read the precautions on the back before filling out this page) Decoration δτ · 1222015 (the specification of the case No. 091116959 and the amended profit) V. Description of the invention (vV) 715, a source stop 716, and a displacement stop 717. [0048] Operationally, during the start-up of the microprocessor, the state of the extended stop 703 in the machine specific register 702 is It is determined by a signal power-up state 701 to indicate whether the specific microprocessor can translate and execute the extended instructions of the present invention to address the additional register of the microprocessor. In a specific embodiment, the signal 701 is derived from a feature control register (not shown in the figure). The feature control register reads a fuse array (fUSeaiTay) that has been configured at the time of manufacture. ) (Not shown). The machine-specific register 702 sends the status of the extended feature field 703 to the translation controller 706. The translation control logic 706 controls the instructions fetched from the instruction buffer 704 to be interpreted according to the extended translation rules or the conventional translation rules. The provision of such control features may allow supervisory applications (such as BI0s) to enable / disable the extended execution ship of the microprocessor H. If the extended feature is capable, the instruction with the state of the opcode selected as the extended feature tag will be translated according to the custom translation rules. In the specific embodiment of -x86, the opcode state is selected as the mark, and under the conventional transition rule, encountering Fm will cause an illegal instruction exception. By disabling extended translation, the instruction decoder is said to translate / decode all the provided instructions, and to the micro instruction? All the stops 7H-7n of 12 are configured. However, under the extended translation rule, if a mark is encountered, it will be output by the escape instruction detector 708_. The escape instruction detector 708 thus allows the instruction solution 709 to translate / decode the rest of the extended instruction 'and configure the micro-operation code booth M and the displacement stop 7Π of the micro instruction 712 to extend The solution will decode / translate the extended preamble of the extended instruction and other available parts, 23 micro-instructions 712 of this paper rule + ® National Standard (CNS) A4 specification (210 χ 2Θ7 public meal 7 ---- ---- ^ --------- (Please read the precautions on the back before filling out this page) 1222015 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 (Case No. 091116959 Patent # 之 纲) And _ Zannianwei Amendment> V. Description of the invention) Source and destination block 716, 715. Certain specific instructions will cause access to control ROM 711 to obtain the corresponding micro-instruction sequence template. After configuration The micro-command 712 is sent to a micro-instruction queue (not shown in the figure) for subsequent execution by the processor. [0049] Please refer to FIG. 8 for an extension of the microprocessor in FIG. Block diagram of register stage logic 800. The extended register stage logic 800 has a register logic 802 It extracts extended microinstructions from a microinstruction buffer 801 or a microinstruction queue 801 according to the present invention. The register logic 802 has an extended register file 8 including an existing structure register and an additional register. 〇3. In a χ86 embodiment, the registers R0-R7 are eight existing structure registers, and the registers R8-R15 are eight additional registers. Register R0- R15 is read by the extended read logic 806 to obtain the source operand, and written by the extended write back logic 807 to store the result operand. The extended read logic 806 outputs the source operand OP and OP2 to two Operand buffers 809 and 81. The result operands RSI and RS2 are sent to the extended write-back logic 807 through two result buffers 812 and 813. [0050] In operation, the extended microinstruction system and a pipeline clock (Not shown) Synchronization, from microinstruction queue 801 to register logic 802. In a clock cycle, extended read logic 802 decodes the source address blocks 804 and 805 of the extended microinstruction to determine Among the registers R0-R15, which registers store a source operand used for a specified operation. Yuan 0p and 0p2 are taken out of it and sent to the source operand temporary registers 809, 810. In addition, the extended microinstruction is sent to the buffer 808 through the pipeline for subsequent processing by the microprocessor. Used in the pipeline phase (not shown). In the same clock cycle, the paper size of a recently carried paper is in accordance with the Chinese National Standard (CNS) A4 specification (210 297 mm). --- 丨 丨! 丨 Order --------- (Please read the notes on the back before filling out this page) 1222015 — (Case No. 091116959 Patent Specification and Application & Amendment Revision ) __ 5. Description of the invention (yf) -------------- Install --- (Please read the notes on the back before filling this page) Calculate, the result RS and RS2 are written back to In the destination register specified by the micro-instruction buffer Aokawa Chuan destination register block (not shown). The corresponding result operators RSI and RS2 are sent to buffers 812 and 813. [0051] The register stage logic 800 shown in FIG. 8 provides the ability to consistently access two source registers and two result registers in a single clock cycle. Another embodiment provides two source operands and a single destination operand. In order to ensure the consistency of the registers R0-R15, the extended register logic 802 accesses the source operands 〇ρι, OP2 before writing back the execution results RSI and RS2. [0052] Please refer to FIG. In order to describe the operation flowchart 900 of the method for translating and executing instructions of the extended register of the addressing microprocessor of the present invention. Flow begins at block 902, where a program configured with an extended register addressing instruction is sent to a microprocessor. The flow then proceeds to block 904. [0053] In block 904, the next instruction is fetched from the cache memory / external memory. The flow then proceeds to block 906. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs [0054] In block 906, the next instruction is decoded / translated according to a custom translation rule, wherein the custom translation rule is only applied to an existing structure in an existing instruction set structure. Memory. Flow then proceeds to block 908. [0055] In block 908, the operand and address designation meta fields of the instruction are used to determine the register address corresponding to the operand of a specified operation. The process then proceeds to block 910. [0056] In block 910, a microinstruction sequence is configured to specify a register address of the specified operation and its corresponding operand. The process then proceeds to decision block 912. 25 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 1222015 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (Case No. 091116959 Patent Specification and Amendment to the Claims) V. [0057] In decision block 912, the next instruction extracted in block 904 is checked to determine whether it contains an extended escape tag / code. If not, the flow proceeds to block 918. If the extended escape code is detected, the process proceeds to block 914. [0058] In block 914, since an extended escape tag has been read and detected in block 912, the translation / decoding is performed on a meta-prefix specified by an extension register to determine the extension corresponding to the specified operation. Register address. In a specific embodiment, the extended register designation element preamble provides all the address bits required to determine the address of the extended register. Flow then proceeds to block 916. [0059] In block 916, modify the operand address block of the microinstruction sequence configured in block 910 to display the extended operand register address determined in block 914. Flow then proceeds to block 918. [0060] In block 918, the microinstruction sequence is sent to a microinstruction sequence for execution by a microprocessor. The process then proceeds to block 920. [0061] In block 920, the micro instruction sequence is fetched by the extended register logic of the present invention. The extended register logic extracts operands corresponding to the specified operation from the specified extended register. The flow then proceeds to block 922. [0062] In block 922, the extended execution logic uses the operand extracted in block 920, executes the specified operation, and generates a result operand. The flow then proceeds to block 924. [0063] In block 924, the result operand is sent to the extended register logic and written back to the extended register specified by the microinstruction sequence. Flow then proceeds to block 926. [0064] In block 926, the method is completed. 26 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page)

1222015 A7 (Case No. 091116959)

Description of the Invention (Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs [0065] Another embodiment of the method 900, before the translation operation (blocks 906 and 914), the extended escape code is detected (decision block 912) The micro-instruction sequence is configured in a single step without the need to replace step 916. [0066] Although the present invention and its objects, features, and advantages have been described in detail, other embodiments may also be included in the present invention For example, the present invention has been described in terms of the following technology: using a single-, unused operation off state in the instruction set architecture that has been fully occupied as a marker to indicate the extended feature preamble that follows. But The scope of the present invention is not limited in any aspect to the fully occupied instruction set architecture, or unused instructions, or single-label. On the contrary, the present invention covers incompletely mapped instruction sets, Examples of opcodes and examples using more than one instruction tag. For example, consider-there is no instruction construct that does not use an opcode state. _ Specifically ^ Example Package of the Invention Contains an opcode state that selects one as an escape mark, where the selection criteria are determined based on market factors. In addition, the specific implementation deletes a special combination of one opcode as a mark, such as the continuous appearance of opcode status 7FH. Therefore, The essence of the present invention is the use of a marker sequence, followed by an n-bit extended set code, which allows a programmer to specify an operand register with a power port in an extended instruction, which cannot be changed by another -Provided by the existing instructions of the micro processor instruction set. [0067] Furthermore, although the microprocessor is used as an example to explain the present invention and its objects, features, and advantages, those skilled in the art may still perceive it. The framework of the present invention is thinner than the micro-processing H, and it can cover all forms of programmable devices, such as signal processors and industrial controllers. カ カ — I— IIIII · II (Please read the note on the back first Please fill in this page for matters) Order: ^ ·

& Fresh (CNS) A4 Specification ⑽ x 29277 Male F 1222015 (Case No. 009 丨 1 丨 6959 Patent Specification and Amendment of the Scope of Application) V. Explanation of the Invention (1) Controller), Array Processing And other similar devices. In short, the above are only the preferred embodiments of the present invention, and it should not be used to limit the scope of the present invention. Any equal changes and modifications made in accordance with the scope of the patent application of the present invention should still fall within the scope of the patent of the present invention ', I would like to ask your reviewing committee to make a clear note and pray for your approval. ---_-------- M Pack—— (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy—— _ 28 This paper size applies to Chinese national standards (CNS) A4 size (2w x 297 meals)

Claims (1)

1222015 A8 B8 (Patent No. 091116959 Specification and Chinese Patent Application: g | & revised version) Patent Application Scope 1. A device for accessing an extended register in a microprocessor, including : A translation logic for translating an extended instruction into a corresponding micro-instruction and executed by the microprocessor, wherein the extended instruction includes: an extended preamble for specifying a register address extension item, the temporary The register address extension item indicates the extension register, wherein the extension register cannot be specified by an existing instruction set; and an extension preamble mark indicating the extension preamble, in which the extension The preamble mark is originally an operation code specified by another architecture in the existing instruction set; and an extended register logic is connected to the translation logic to receive the corresponding microinstruction and access the Extended register. 2. The device described in item 1 of the scope of patent application, wherein the extended instruction further includes a plurality of instruction items according to the existing instruction set. 3. The device according to item 2 of the scope of patent application, wherein the instruction items specify an operation to be performed by the microprocessor, and the operation element corresponding to the operation is extracted from / stored in the extended register. 4. The device described in item 3 of the scope of patent application, wherein the instruction items further specify a plurality of architecture register addresses. 5. The device according to item 4 of the scope of patent application, wherein the translation logic uses the register address extensions to determine the extended register. 6. The device according to item 4 of the patent application, wherein the translation logic combines the temporary register address extensions with the architectural register addresses to determine the extended register. This paper size applies Chinese National Standard (CNS) Entry 4 (21〇χ297 公 嫠) --- r ----- I, (Please read the precautions on the back before filling this page], HT »Ministry of Economy Printed by the Intellectual Property Bureau's Consumer Cooperatives 1222015 A8 B8 (Patent No. 091116959 Patent Specification and Application Amendment) Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Scope of Patent Application 7. If applying for a patent ㈣ item 1 The device, wherein the extended preamble includes 8 bits. 8. The device described in item (i) of the scope of patent application, wherein the extended preamble includes: a source register address extension item, A first extended register including a first source operand is designated; and a destination register address extension is coupled to the source register address extension to specify-include-second The second extended register of the source operand, and specifies that the second extended register is used to store a result of a different operation. 9. The device described in item 1 of the scope of patent application, wherein the existing instruction set Contains the x86 instruction set. 〃 10 · If applied The device according to item 9 of the utility model, wherein the extended preamble mark includes the operation code F1 (ICEBKPT) of the x86 instruction set. 11. The device according to item i of the patent application scope, wherein the translation logic includes: a Escape instruction detection logic for detecting the extended preamble mark; an instruction decoding logic that determines an operation to be performed and an architectural register to be used according to the existing instruction set; and-extended decoding logic, Input to the escape instruction _ logic and the instruction decoding logic to determine the extended register, and specify the extended register in the corresponding micro-command. 12.- 面 charge-existing texture n Age_Tiga plus the arithmetic register device, including: & Zhang Ruler I Financial Standards (CN;) A4 · (21GxH Race)-(Please read the precautions on the back before filling this page)-Install · Order (Case No. 091116959 A8 B8 patent, please return to the original), the scope of the patent application is one mt, the status of the application is red-the additional operation of the redshift, the extended instructions include the existing microprocessor instructions iwhere—extended setting of the selected operation code η bits 'The selected operation code indicates the extended instruction, and the extension of the n-bit frame = the preamble indicates the additional operand register, wherein, the meta register cannot be pointed by the existing microprocessor; Sets are specified separately; and a translator, _ is to receive the extended age 'and generate a -microinstruction sequence' to instruct the microprocessor to access the additional operand register when the specified operation is performed. The device described in claim 12 of the patent application scope, wherein the extended instruction further includes: the remaining instruction items are configured to specify the specified operation, wherein the specified operation is executed by the microprocessor, and in which the operand corresponding to the specified operation is The additional operand register is provided from / to. 14. The device according to item 13 of the applied patent, wherein the pre-n-bit code includes: a register extension register, each of which is configured to temporarily store for each of the additional operands Address of the device, specifying its higher address bit. 15. The device according to item 14 of the scope of patent application, wherein the lower address bits are provided by the remaining instruction items in the extended instruction. 16. The device according to item 12 of the scope of patent application, wherein the 11-bit extended preamble includes 8 bits. 17. The device as described in item 12 of the scope of the patent application, wherein the existing microprocessing 31 private paper size is applicable to the Chinese National Standard (CNS) A4 specification (210χ: 297 mm) IIL-IKK ---- ^ II ( (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1222015 (Patent No. 091116959 Patent Specification and Application Revisions) Patent Application Scope The device instruction set is the X86 microprocessor instruction set. 18. The device described in item 17 of the scope of patent application, wherein the selected operation code includes the icebkPT operation code (ie, operation code F1) in the instruction set of the x86 microprocessor. 19. The extended device according to item 13 of the scope of patent application, wherein the translator includes: ^ an escape instruction detector for detecting the selected operation code in the extended instruction; an instruction decoder, Used to decode the rest of the extended instruction to determine the specified operation; and an extended preamble decoder coupled to the escape instruction detector and the instruction decoder to decode the n-bit extension Preamble, and specify the additional operand register in the microinstruction sequence. 2〇 ·-An instruction set extension device that adds the addressing capability of the existing register to the existing instruction set, including: an escape tag, which is received by a translation logic, and indicates a corresponding instruction, which is specified with the part -What micro-processing H is to perform—extended luck, where the escape mark is one of the first opcodes in the existing instruction set;-extended temporary hard-to-find elements, _ to the axis mark, and the hidden part For one, the extended register designator specifies a plurality of address extensions corresponding to the extended register, where the extended register is required for the extended operation; and an extended register logic, which To the translation logic, used for the designation (please read the precautions on the back before filling this page)-binding-order printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (Case No. 091116959 Patent Specification and Application g. Revised version of the game perimeter. 6. When the patent application scope is executed, the extended register is accessed. The existing instruction set only provides the ability to address the existing register, and the extended register specifies the element. Enable The site extends the capacity of the scratchpad. 21. The instruction set extension device described in item 20 of the scope of patent application, wherein the rest of the accompanying part includes a second operation code and a plurality of optional address designators for specifying the extension operation and the plurality Address, where the address extensions are combined with the addresses to generate the extended address of the extended register. 22. The instruction set extension device described in item 20 of the scope of patent application, wherein the extension register designation element includes 8 bits. 23. The instruction set extension device according to item 20 of the scope of patent application, wherein the existing instruction set is an x86 instruction set. 24. The instruction set extension device according to item 23 of the scope of patent application, wherein the first operation code includes the ICE BKPT operation code (ie, operation code F1) in the x86 instruction set. 25. The instruction set extension device according to item 20 of the patent application scope, wherein the translation logic translates the escape mark and the accompanying part into corresponding micro instructions, and the corresponding micro instructions instruct the extended register The logic 'accesses the extended register when the extended nose executes to retrieve / store operands. 26. The instruction set extension device as described in item 20 of the scope of patent application, wherein the translation logic includes:-escape mark system logic to refine the escape mark and instruct the accompanying part's translation action to be based on extension Translation conventions; and ____33 This paper size applies to Chinese National Standards (CNS) A4 specifications (21〇χ 297 mm) a --------- 丨 (Please read the notes on the back before filling (This page)-Binding and ordering 1222015 (Description and Application of Case No. ^ | 8_Amendment) VI. Patent Application Scope-Decoding logic reduced to Wei Jiji logic, based on the existing instruction set Conventionally, the translation action of the instruction is performed, and the translation of the corresponding instruction is performed according to the extended translation routine, so that the ability to address the extended register can be addressed. 27 · —A method of expanding an existing instruction set architecture to provide a programmable addressing capability of an extended register in a microprocessor, the method includes providing an extended instruction, the extended instruction includes an extended mark And an extended preamble, wherein the extended tag is a first opcode item in the existing instruction set architecture; the extended register is designated through the extended preamble and the rest of the extended instruction, wherein the extended register The register is accessed when a specified operation is executed, and the existing instruction set architecture only provides instructions that address the existing register according to the instruction set architecture; and when the specified operation is executed, the register is accessed. Extended register. 28. The method according to item 27 of the scope of patent application, wherein the actions of specifying the extended register include: first specifying the designated operation, wherein the first designated operation uses a second operation in the existing instruction set architecture Code item. Λ 29. The method as described in item 27 of the scope of patent application, wherein the action of providing an extension instruction includes using an 8-bit item to configure the extension donkey coding. J 30. The method as described in item 27 of the scope of patent application, wherein the action of providing an extended instruction includes selecting the code item from the x86 microprocessor instruction set architecture. (Please read the notes on the back before filling out this page) Binding and ordering Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Application amendments), the method described in 31. ==: ° of the patent application, where the -code is selected as = :: X86ICEBKPT operation code (that is, operation 32 · As stated in the patent scope 27 item The method further includes: translating the extended instruction into a micro instruction, the micro instruction instructs an extended lamp logic to access the extended register. 33. ^ The method described in the magic item of the scope of patent application, The action of the translation extension instruction includes: detecting the extension mark in the translation logic; and the extension translation rule decodes the extension preamble and the rest to confirm the extension temporarily required for the translation action. (Please read the precautions on the back before filling out this page) • 1-I I- II-· Equipment · 11-Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs