1242879 九、發明說明： 【發明所屬之技術領域】 本發明提供一種深溝渠單邊埋藏導電帶之製作方& 尤指一種防止摻雜離子反射影響之深溝渠單邊埋藏導電帶 之製作方法。 i 【先前技術】 溝渠式動態隨機存取記憶體(Trench_DRAM)結構是先 在半導體基材中姓刻出深溝渠（deep trench)，再於深溝渠中 製作溝渠電容，然後利用埋入導電帶電連接溝渠電容與金 屬氣化半導體(metal_oxide semiconductor, MOS)電晶體，以 大幅降低記憶胞(memory cell)的橫向單位面積，進而增加 半導體元件的積集度。而為了避免相鄰記憶胞(memory cell) 、 之間的相互干擾，埋入導電帶也逐漸演變成僅具有單邊之 ‘ 埋入導電帶（single sided buried strap，SSBS)，但由於製程的 困難度高，往往造成單邊埋入導電帶寬度變異性大，進而 使得電阻值不穩定而影響電性的表現。 7 1242879 請參考第1圖至第3圖，第1圖至第3圖為習知製作 一深溝渠單邊埋藏導電帶之方法示意圖。如第1圖所示， 首先於一半導體基底10上依序沉積一墊氧化(pad oxide)層 12與一墊氮化(pad nitride)層14，接著利用黃光暨蝕刻製程 ’ 於半導體基底10中形成至少一深溝渠16。 隨後利用沉積、擴散、蝕刻等製程，於深溝渠16中形 成一溝谷（圖未不）以及^一多晶碎層17覆蓋於溝渠電容 上。如第2圖所示，接著進行一沉積製程，形成一氮矽化 合物(silicon nitride)層18當作下遮罩層，然後於氮矽化合 物層18表面再沉積一非晶梦（amorphous silicon，α-Si)層20 當作上遮罩層。之後’進行一斜角離子佈植(tilted implantation)，將掺雜離子22植入非晶矽層20中，然後利 用被離子轟擊之非晶石夕結構與未受佈植之非晶石夕結構的姓 • 刻選擇比的差異，來進行一蝕刻製程，用以去除未植入換 雜離子22之部分的非晶矽層20並裸露出氮矽化合物層 18。之後進行一次濕蝕刻製程，用以去除裸露出來的氣石夕 化合物層18。最後再利用剩下之非晶石夕層20以及氮石夕化 合物層18當作硬遮罩(hard mask)來触刻深溝渠16内之多 晶矽層17，以形成單邊埋藏導電帶。 8 1242879 '、而如第3圖所示’由於進行斜角離子佈植事程 Η因為摻雜離子會發生反射、散射的現象，進 分摻雜離子22會被⑽ =，如第-之虛綠 ===Γ綱州物除㈣成 18讲)24嚴重影響非㈣層加及氮魏合物層 之精確度，進而造成後續製備之單邊埋人導電帶寬 度的馬變異性，使得電阻值不敎㈣響錄電性表現。 如上所述，習知製作深溝渠單邊埋藏導電帶之方法， 主要係利用一斜角離子佈植法，將摻雜離子植入部分之非 晶石夕層中’隨後再進行一餘刻製程，以形成單邊埋入導電 帶之遮罩層。但由於摻雜離子反射、散射因素而影響了遮 罩層之形狀，進而大幅影響後續製備單邊埋入導電帶的寬 Φ 度以及均勻度(uniformity)。 有鑑於此，申請人乃根據此等缺點及依據多年從事製 造該類產品之相關經驗，悉心觀察且研究之，進而提出本 發明’可以避免上述所提之摻雜離子反射與散射現象所產 生的影響。 9 1242879 【發明内容】 本發明之主要目的即在於提供一種防止摻雜離子反射 ‘ 影響之深溝渠單邊埋藏導電帶之製作方法。 本發明係揭露一種單邊埋入導電帶之製作方法。首先 提供一形成有至少一深溝渠之基底，且深溝渠内包含一溝 • 渠電容以及一多晶矽層覆蓋於溝渠電容上。接著形成一遮 罩層覆蓋於多晶矽層上，再塗佈上一犧牲層後，進行一乾 蝕刻製程，去除部分犧牲層。隨後進行一斜角離子佈植， 將摻雜離子植入遮罩層内，並剝雜犧牲層。最後進行一濕 蝕刻製程，蝕除未摻雜之部分遮罩層以及未遮蔽之多晶矽 層，以形成由部分多晶矽層所構成之單邊埋入導電帶。 _ 由於本發明之深溝渠單邊埋藏導電帶之製作方法，係 採用於深溝渠内形成一犧牲層，用以吸收反射之摻雜離 子，因此能形成均一寬度之單邊埋藏導電帶。 1242879 【實施方式】 為了使貴審查委員能更近一步了解本發明之特徵及 技術内谷’請參閱以下有關本發明之詳細說明與附圖。然 而所附圖式僅供參考與輔助說明用，並非用來對本發明加 以限制者。1242879 IX. Description of the invention: [Technical field to which the invention belongs] The present invention provides a method for manufacturing a single-sided buried conductive tape in a deep trench, and more particularly, a method for manufacturing a single-sided buried conductive tape in a deep trench that prevents the influence of doped ion reflection. i [Previous technology] The trench type dynamic random access memory (Trench_DRAM) structure is first carved with a deep trench in a semiconductor substrate, and then a trench capacitor is made in the deep trench. Trench capacitors and metal-oxide semiconductor (MOS) transistors are used to greatly reduce the horizontal unit area of the memory cell, thereby increasing the accumulation of semiconductor elements. In order to avoid mutual interference between adjacent memory cells, the embedded conductive tape has gradually evolved into a single sided buried strap (SSBS) with only one side, but due to the difficulty of the process The high degree often results in large variability in the width of the single-sided embedded conductive tape, which in turn makes the resistance value unstable and affects the electrical performance. 7 1242879 Please refer to Figures 1 to 3, Figures 1 to 3 are the schematic diagrams of the conventional method for making a single trench buried conductive strip in a deep trench. As shown in FIG. 1, a pad oxide layer 12 and a pad nitride layer 14 are sequentially deposited on a semiconductor substrate 10, and then a yellow light and etching process is used on the semiconductor substrate 10. In the formation of at least one deep trench 16. Subsequently, a process such as deposition, diffusion, and etching is used to form a valley (not shown in the figure) in the deep trench 16 and a polycrystalline chip layer 17 to cover the trench capacitor. As shown in FIG. 2, a deposition process is performed to form a silicon nitride layer 18 as a lower mask layer, and then an amorphous silicon (α) is deposited on the surface of the nitrogen silicon compound layer 18. -Si) layer 20 serves as the upper mask layer. After that, a tilted implantation is performed, the doped ions 22 are implanted into the amorphous silicon layer 20, and then the amorphous stone structure bombarded by the ions and the amorphous structure not implanted are used. The difference between the last name and the second choice ratio is used to perform an etching process to remove the amorphous silicon layer 20 and to expose the nitrogen-silicon compound layer 18 in the portion where the replacement ions 22 are not implanted. Then, a wet etching process is performed to remove the exposed gas stone compound layer 18. Finally, the remaining amorphous stone layer 20 and the nitrogen stone compound layer 18 are used as hard masks to touch the polycrystalline silicon layer 17 in the deep trench 16 to form a unilateral buried conductive strip. 8 1242879 ', and as shown in Fig. 3' Due to the beveled ion implantation process, because the doped ions will reflect and scatter, the dopant ions 22 will be ⑽ =, as in the- Green === Γ Gangzhou Divided into 18 lectures) 24 seriously affects the accuracy of the non-㈣ layer plus the nitrogen-nitrogen compound layer, which further causes the horse's variability of the unilateral buried conductive band width in subsequent preparations, making the resistance It's worth noting the recording of electrical performance. As mentioned above, the conventional method for making a single-sided buried conductive strip in a deep trench is mainly using an oblique ion implantation method to implant doped ions into part of the amorphous stone layer, and then perform an additional engraving process. To form a mask layer embedded in the conductive tape on one side. However, due to the reflection and scattering factors of the doped ions, the shape of the mask layer is affected, which further greatly affects the width Φ and uniformity of the single-sided buried conductive strips subsequently prepared. In view of this, the applicant based on these shortcomings and years of relevant experience in manufacturing such products, carefully observed and researched, and then proposed that the present invention 'can avoid the reflection and scattering caused by the doped ions mentioned above. influences. 9 1242879 [Summary of the invention] The main purpose of the present invention is to provide a method for manufacturing a conductive strip buried unilaterally in a deep trench, which prevents the reflection of doped ions. The invention discloses a manufacturing method of a unilaterally embedded conductive tape. First, a substrate with at least one deep trench formed is provided, and the deep trench contains a trench capacitor and a polycrystalline silicon layer covering the trench capacitor. Then, a mask layer is formed to cover the polycrystalline silicon layer, and then a sacrificial layer is coated, and then a dry etching process is performed to remove a part of the sacrificial layer. An oblique ion implantation is subsequently performed, the doped ions are implanted into the mask layer, and the sacrificial layer is stripped away. Finally, a wet etching process is performed to remove the undoped part of the mask layer and the unmasked polycrystalline silicon layer to form a unilaterally buried conductive strip composed of a part of the polycrystalline silicon layer. _ Because the manufacturing method of the unilaterally buried conductive tape of the deep trench of the present invention is to form a sacrificial layer in the deep trench to absorb the reflected dopant ions, it can form a unilateral buried conductive tape with a uniform width. 1242879 [Embodiment] In order for your review committee to better understand the features and technical valleys of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings are for reference and auxiliary explanation only, and are not intended to limit the present invention.
請參考第4圖至第9圖，第4圖至第9圖為本發明之 深溝渠單邊埋藏導電帶製作方法之示意圖。如第4圖所 示，首先提供一半導體基底30，例如矽基底，並於半導體 基底30上依序沉積一墊氧化(paci oxide)層32與一塾氣化 (pad nitride)層34,接著利用黃光暨蝕刻製程於半導 命體基底 30中形成至少一深溝渠36。隨後再利用沉積、坤石夕坡壤 (arsenic silicate glass，ASG)擴散、颠刻、沉積等製程，# 一多 關技 晶石夕層 藝者所 於深溝渠36中形成一溝渠電容（圖未示），以及 37等之導電層覆蓋於溝渠電容上，此為習知相 熟知，在此不多加贅述。 接著利用沉積製程，例如高密度電漿化學氣相 復蓋於半導 之上並於深 CVD)沉積法，形成一遮罩層，且此遮罩層係 體基底30、深溝渠36内之側壁及多晶矽層37 11 1242879 溝渠36内形成-凹槽(recess)。在本發明之較佳實施例中， 遮罩層係為-包含有上遮罩層4〇、下遮罩層38之複合結 構層’例如下遮罩層38可為四乙氧基石夕烧(TE〇s)或氮石夕化 -合物(sili⑶nnitdde)沈積層，而上遮罩層4〇則可為非晶矽 化合物。然後再進行-塗佈製程，將__犧牲層42，塗佈於 上遮罩層4〇表面並覆蓋住整個深溝渠36。其中，犧牲層 42係為-低黯之材料，例如塗式玻璃㈣請細， ♦ S0G)、抗反射層或光阻層等。 隨後，如第5圖所示，以乾式餘刻方式進行一回餘刻 (etch back)製程，將部分犧牲層42去除，以於深溝渠％ 中之忒凹槽底部保留部分不填滿該凹槽之犧牲層C，用來 吸收摻雜離子之反射或散射。然後，如第6圖所示，進行 一斜角離子佈植製程，將摻雜離子44植入上遮罩層4〇中。 ♦但是，由於進行斜角離子佈植製程時，摻雜離子料會有反 射或散射情形產生，因此本發明係利用深溝渠36内之犧牲 層42來吸收離子佈植時所反射或散射出來的摻雜離子 • 44 °其中，值得注意的是，深溝渠36内之犧牲層42之厚 度必須足夠用來吸收離子佈植製程中反射或散射等之能量 較低的摻雜離子44，但是又可允許摻雜離子44直接穿透 犧牲層42而佈植入上遮罩層4〇中，因此犧牲層42之，产 12 1242879 能量以及犧牲層42之材質等相 係與離子佈植製程之佈植 關。 如第7圖所示，在剝除犧牲層42之後，接著進行一濕 U衣私例如氨水濕侧製程’將未受掺雜離子森擊之 上遮罩層4G餘除’並且裸露出下遮罩層％。隨後如第8 圖所示，利用稀釋之氫氟酸（卿）將裸露出來由te〇s 馨構成的下遮罩層38加以敍除，並裸露出部分之多晶石夕層 37*以及墊氧化層32與墊氮化層％。其巾，·!下絲除並 覆蓋於部分之多晶石夕層37上之上、下遮罩層4〇、38是用 來當作本發明製作深溝渠單邊埋入導電帶之硬遮罩46。然 後如第9圖所示，進行-乾_製程，將未被硬遮罩46遮 蔽之部分多晶石夕137⑽，形成由部分多晶石夕層所構成之 單邊埋入導電帶48。最後再利用淺溝隔離(止“匕…让⑼化 隹lsolatlon，STI)製程於單邊埋入導電帶48側邊形成絕緣層， 此亦為習知相關技藝者所热知，故不多贅述。 综上所述，本發明之深溝渠單邊埋藏導電帶之製作方 法相較於習知技術深溝渠單邊埋藏導電帶之製作，可有效 吸收離子佈植之反射或散射的摻雜離子，減少摻雜離子反 射或散射因素之影響，以提高單邊埋入導電帶之硬遮罩的 13 1242879 精確度，進而能防止硬遮罩影響單邊埋入導電帶之形狀及 大小，以利後續製備單邊埋入導電帶之寬度的一致性，確 保溝渠電容與金屬氧化半導體(MOS)電晶體電連接的電性 表現。由此可知，本發明之深溝渠單邊埋藏導電帶之製作 方法能有效提高溝渠式動態隨機存取記憶體 (Trench-DRAM)之生產良率及品質。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範 圍0 【圖式簡單說明】 第1圖至第3圖習知製作一深溝渠單邊埋藏導電帶之方法 φ 示意圖。 第4圖至第9圖為本發明之深溝渠單邊埋藏導電帶製作方 法之示意圖。 1242879 【主要元件符號說明】 ίο半導體基底 * 14墊氮化層 17多晶矽層 20非晶矽層 24底切 # 32墊氧化層 36深溝渠 38下遮罩層 42犧牲層 46硬遮罩 12墊氧化層 16深溝渠 18氮矽化合物層 22摻雜離子 30半導體基底 34塾氮化層 37多晶矽層 40上遮罩層 44摻雜離子 48單邊埋入導電帶 15Please refer to FIGS. 4 to 9, which are schematic diagrams of a method for manufacturing a single-sided buried conductive strip in a deep trench according to the present invention. As shown in FIG. 4, a semiconductor substrate 30, such as a silicon substrate, is first provided, and a paci oxide layer 32 and a pad nitride layer 34 are sequentially deposited on the semiconductor substrate 30, and then used. The yellow light and etching process forms at least one deep trench 36 in the semiconductor substrate 30. Subsequently, the deposition, arsenic silicate glass (ASG) diffusion, inversion, deposition and other processes were used to form a trench capacitor in the deep trench 36 (not shown in the figure) (Shown), and the conductive layer of 37 and so on cover the trench capacitor, which is well known and will not be repeated here. Then a deposition process, such as high density plasma chemical vapor deposition on the semiconductor and deep CVD) deposition method, is used to form a mask layer, and the mask layer is the sidewall of the substrate 30 and the deep trenches 36 And a polycrystalline silicon layer 37 11 1242879 is formed in the trench 36-a recess. In a preferred embodiment of the present invention, the mask layer is a composite structure layer including an upper mask layer 40 and a lower mask layer 38. For example, the lower mask layer 38 may be tetraethoxy stone fired ( TE0s) or silicon nitride compound (siliCDnnitdde) deposition layer, and the upper mask layer 40 may be an amorphous silicon compound. Then, a coating process is performed, and the sacrificial layer 42 is coated on the surface of the upper mask layer 40 and covers the entire deep trench 36. Among them, the sacrificial layer 42 is a low-dark material, such as coated glass (please be thin, S0G), an anti-reflection layer, or a photoresist layer. Subsequently, as shown in FIG. 5, a dry etch back process is performed to perform an etch back process to remove a part of the sacrificial layer 42 so that the bottom part of the trench groove in the deep trench% does not fill the recess. The sacrificial layer C of the trench is used to absorb the reflection or scattering of the doped ions. Then, as shown in FIG. 6, an oblique ion implantation process is performed, and the doped ions 44 are implanted into the upper mask layer 40. ♦ However, since the doped ion material may be reflected or scattered during the bevel ion implantation process, the present invention uses the sacrificial layer 42 in the deep trench 36 to absorb the reflection or scattering of the ion implantation. Doped ions 44 ° Among them, it is worth noting that the thickness of the sacrificial layer 42 in the deep trench 36 must be sufficient to absorb the low-energy doped ions 44 such as reflection or scattering during the ion implantation process. The doped ions 44 are allowed to directly penetrate the sacrificial layer 42 and the cloth is implanted in the upper mask layer 40. Therefore, the sacrificial layer 42 generates 12 1242879 energy and the material of the sacrificial layer 42 and the implantation of the ion implantation process. turn off. As shown in FIG. 7, after the sacrificial layer 42 is stripped, a wet U-clothing process, such as ammonia, is performed on the wet-side process to 'remove the upper masking layer 4G without being doped with ion ions and expose the lower mask. Cover layer%. Subsequently, as shown in FIG. 8, the lower masking layer 38 made of te0s is exposed by using diluted hydrofluoric acid (Qing), and the polycrystalline stone layer 37 * and the pad are exposed. Oxidation layer 32 and pad nitride layer%. The towel is removed and covered on top of the polycrystalline stone layer 37, and the lower mask layers 40 and 38 are used as a hard cover for the single-sided embedded conductive tape of the deep trench in the present invention. Cover 46. Then, as shown in FIG. 9, a dry process is performed to partially 137 ⑽ of polycrystalline stones not covered by the hard mask 46 to form a unilaterally embedded conductive strip 48 composed of a portion of the polycrystalline silicon layers. Finally, a shallow trench isolation process is used to bury the lsolatlon (STI) process on one side to form an insulating layer on the side of the conductive strip 48, which is also well known to those skilled in the art, so I wo n’t go into details. To sum up, compared with the manufacturing method of the deep trench single-sided buried conductive tape of the present invention, the manufacturing method of the single-sided buried conductive tape of the deep trench can effectively absorb the reflection or scattering of the doped ions implanted by the ions, Reduce the influence of reflection or scattering factors of doped ions to improve the accuracy of the 131242879 single-sided buried conductive tape, which can prevent the hard mask from affecting the shape and size of the single-sided buried conductive tape, so as to facilitate subsequent The uniformity of the width of the single-sided buried conductive tape is prepared to ensure the electrical performance of the trench capacitor and the electrical connection of the metal oxide semiconductor (MOS) transistor. From this, it can be known that the method for manufacturing the single-side buried conductive tape of the deep trench of the present invention can Effectively improve the production yield and quality of trench-type dynamic random access memory (Trench-DRAM). The above description is only a preferred embodiment of the present invention, and any changes made in accordance with the scope of patent application of the present invention Modifications should all belong to the scope of the present invention. [Simplified description of the drawings] Figures 1 to 3 are schematic diagrams of the method for making a single-sided buried conductive strip in a deep trench φ. Figures 4 to 9 are the present invention. Schematic diagram of the method for manufacturing a single-sided buried conductive strip in a deep trench. 1242879 [Description of the main component symbols] ίο Semiconductor substrate * 14 Pad nitride layer 17 Polycrystalline silicon layer 20 Amorphous silicon layer 24 Undercut # 32mat oxide layer 36 Deep trench 38 Mask layer 42 Sacrificial layer 46 Hard mask 12 Pad oxide layer 16 Deep trench 18 Nitrogen silicon compound layer 22 Doped ion 30 Semiconductor substrate 34 Nitrided layer 37 Polycrystalline silicon layer 40 Mask layer 44 Doped ion 48 Single side buried Into the conductive tape 15