TWI402946B - Buried bit lines and single side bit line contact process and scheme - Google Patents

Description

Buried bit line and single side bit line contact window and manufacturing method thereof

The invention relates to a buried bit line and a single side bit line contact window and a manufacturing method thereof, in particular to a buried bit line and a single side bit line contact window of a memory and a manufacturing method thereof.

The DRAM bit cell is composed of a metal-oxide-semiconductor (MOS) transistor connected in series to a capacitor. The capacitor is generally designed as a stack capacitor stacked on the surface of the semiconductor substrate or a trench capacitor buried deep in the substrate; the transistor is in a gate channel region relative to the original surface of the semiconductor substrate The orientation classification of the primary surface can be divided into a planar transistor device in which the current direction of the gate channel is parallel to the original surface of the semiconductor substrate, and a vertical transistor structure in which the current direction of the gate channel is perpendicular to the original surface of the semiconductor substrate. Kind.

The MOS transistor system of the conventional DRAM bit cell controls the switch of the MOS transistor by a word line electrically connected to the gate, and utilizes a bit line electrically connected to the source/drain ( Bit line) forms and controls a current transmission path, and then electrically connects to the electrode of the capacitor via the drain/source to achieve storage or output of the DRAM bit cell.

In addition, the conventional DRAM bit cell system is an 8F ² cell, where F represents a feature size, that is, the minimum actual size of the custom process, such as the line width of the semiconductor process. With the trend toward miniaturization of various electronic products, the design of DRAM bit cells must also meet the requirements of high integration and high density. Therefore, the semiconductor industry is working to reduce the size of DRAM bit cells, from 8F ² units to 6F ² unit. With buried bit lines, buried word lines, and vertical MOS transistor structures, the semiconductor industry today has achieved the goal of reducing the feature size of DRAM bit cells to 4F ² cells. Please refer to FIG. 1 , which is a schematic diagram of a layout pattern of a conventional 4F ² unit DRAM array. According to FIG. 1, the DRAM array 100 of the 4F ² cell includes a buried bit line 110, a buried word line 120, and a capacitor 130. In the length direction, the width of the buried word line 120 and the capacitor 130 occupy 2F; in the width direction, the width of the capacitor 130 and the buried bit line 110 occupy 2F, so the area of one DRAM bit cell is 2F×2F=4F ² .

By using the buried circuit design such as the buried bit line 110 and the buried word line 110, the space occupied by each component contact in the memory cell can be reduced, so that the buried circuit design can be used not only for DRAM. In the array, it is widely used in a variety of memory. However, it is worth noting that the buried bit line 110 as shown in FIG. 1 still needs to be electrically connected to the source/drain of the MOS transistor by using a one-line contact window 112 to construct a current transmission path. However, the buried bit line 110 is a three-dimensional structure buried deep in the semiconductor substrate, so how the bit line contact window 112 can be accurately formed in the buried bit line 110, ensuring that each memory is as shown in FIG. The DRAM bit cell can be operated accurately, or the adjacent memory bit cell is abnormally turned on due to the defect of the bit line contact window 112, which is still a problem of continuous concern in the industry.

Accordingly, it is an object of the present invention to provide a buried bit line that can accurately form a contact window in a semiconductor substrate and a method of fabricating the same.

According to the patent application scope provided by the present invention, a method for fabricating a buried bit line is provided, which first provides a semiconductor substrate, and then performs a first etching process to form a plurality of first trenches in the substrate ( And forming a first protective layer on the sidewalls of the first trenches. And subsequently performing a second etching process to etch the semiconductor substrate at the bottom of the first trench to form a plurality of second trenches; and sequentially forming a second protective layer and a first metal composite layer in the second trenches And the height of the first metal composite layer is less than the depth of the second trench. And then removing a portion of the first protective layer to expose a portion of the sidewall of the first trench; subsequently forming a third protective layer on sidewalls of the first trench; and removing a portion of the first protective layer, An opening is formed in each of the first trenches. Then, a contact window is formed in the substrate through the opening, and a second metal composite layer is formed in the first trench and the second trench. The metal composite layer comprises an upper metal composite layer and a lower metal composite layer.

According to the patent application provided by the present invention, a buried bit line includes a trench disposed in a semiconductor substrate, a first protective layer disposed on the sidewall and the bottom of the trench, and a sidewall formed on the trench. An opening in the first protective layer, a contact window formed in the semiconductor substrate corresponding to the opening, a second protective layer formed on the sidewall of the trench opposite to the opening, and a trench disposed on the trench Metal composite layer inside.

The buried bit line and the manufacturing method thereof according to the present invention define the position and size of the opening formed on one side of the buried bit line by forming and removing different protective layers, and then accurately Forming a contact window in the semiconductor substrate to ensure the construction of the buried channel of the buried bit line and the MOS transistor, and avoiding the abnormality of the adjacent memory bit cell due to the defect of the buried bit line contact window. Open.

Please refer to FIG. 2 to FIG. 13 . FIG. 2 to FIG. 13 are cross-sectional views showing a manufacturing process of a first preferred embodiment of a method for fabricating a buried bit line according to the present invention. It should be noted that the method for fabricating the buried bit line provided by the present invention is exemplified by the DRAM. However, those skilled in the art should be aware that the manufacturing method provided by the present invention is not limited to other types of memory such as static random access. Static random access memory (SRAM) or flash memory. As shown in FIG. 2, the method provided by the present invention first provides a semiconductor substrate 200, and then a first etching process is performed on the semiconductor substrate 200, and is formed in the semiconductor substrate 200 through a conventional patterned hard mask 202. A plurality of first trenches 204. Next, a first protective layer 206 is formed in the first trench 204, and the first protective layer 206 covers the bottom and sidewalls of the first trench 204 as shown in FIG. In addition, the first protective layer 206 includes a material having a difference in etching rate from the semiconductor substrate 200 such as tantalum nitride, hafnium oxynitride or an oxide-nitride-oxide (ONO) composite.

Please refer to Figure 3. Performing a second etching process, etching a portion of the first protective layer 206, and forming a residual first protective layer 206 on the sidewalls of each of the first trenches 204, and then patterning the hard mask The shielding protection of the 202 and the sidewalls etches the semiconductor substrate 200 at the bottom of the first trench 204 until a predetermined depth of the buried bit line forms a plurality of second trenches 208.

Referring to FIG. 4 and FIG. 5, a second protective layer 210 and a first metal composite layer 212 are sequentially formed in the second trench 208: first, a thermal oxidation process is performed, and in the second trench The bottom and sidewalls of 208 form a second protective layer 210 having a yttria material. Since the sidewalls of the first trench 204 are covered by the first protective layer 206, only the bottom and sidewalls of the exposed second trench 208 are oxidized to form the second protective layer 210. Next, referring to FIG. 5, after forming the second protective layer 210, a first metal composite layer 212 filling the second trench 208 is formed in the second trench 208, and includes a titanium nitride layer 212a and a The tungsten layer 212b is not limited to forming only the titanium nitride layer 212a in order to prevent the tungsten layer 212b from being affected by subsequent processes. The first protective layer 206 is etched back by an etching back process to expose the first protective layer 206 to form the first metal composite layer 212 as shown in FIG. It should be noted that the height of the first metal composite layer 212 is less than the depth of the second trench 208. In other words, the height of the first metal composite layer 212 is not covered by the first protective layer 206. In addition, the first protective layer 206 and the second protective layer 210 can protect the semiconductor substrate 200 from metal contamination when the first metal composite layer 212 is formed.

Please refer to Figure 6 and Figure 7. After the fabrication of the first metal composite layer 212 is completed, a first photoresist layer 214 is formed on the first metal composite layer 212 in the second trench 208, and the first photoresist layer 214 is as shown in FIG. a second protective layer 210 covering a portion of the second trench 208 and a first protective layer 206 of a portion of the first trench 204. Next, as shown in FIG. 7, the first protective layer 206 not covered by the first photoresist layer 214 is removed, and the sidewalls of the first trench 204 are exposed, and then the first photoresist layer 214 is removed. It should be noted that after removing a portion of the first protective layer 206, the remaining first protective layer 206 is symmetrically disposed on opposite sidewalls of each of the first trenches 204 as shown in FIG.

Please refer to Figure 8. A thermal oxidation process is then performed to form a third protective layer 216 comprising a yttria material on the exposed sidewalls of the first trench 204. Therefore, the second trench 208 is provided with a second protective layer 210 covering the sidewalls and the bottom of the second trench; and the sidewall of the first trench 204 is provided with a first protective layer 206 and a third protective layer from bottom to top. 216. The second protective layer 210 and the third protective layer 216 comprise the same yttria material, and the etch rate is different from the first protective layer 206 disposed between the two.

Please refer to Figure 9. Next, a patterned second photoresist layer 218 is formed in the first trench 204 and the second trench 208, and the second photoresist layer 218 covers the two sidewalls of the first trench 204 and the second trench 208. First, it is preferable to cover the first protective layer 206 and the third protective layer 216 on a single sidewall of the same side of the first trench 204 and the second trench 208. In addition, in order to avoid the problem that the depth of the first trench 204 and the second trench 208 causes the second photoresist layer 218 to be developed, the second photoresist layer 218 is affected to cover the first side first protective layer 206 and the third protective layer 216. The person skilled in the art should be aware that the second photoresist layer 218 may also have an etch rate different from that of the first protective layer 206 and the third protection by a polycrystalline germanium or borophosphosilicate glass (BPSG) (not shown). The film layer of layer 216 is replaced. The polysilicon and BPSG first fill the first trench 204 and the second trench 208, and then perform a patterning step on the film layer, so that the patterned polysilicon or BPSG is like the second photoresist layer 218 in FIG. The first protective layer 206 and the third protective layer 216 on the single sidewall of the same side of the second trench 204 and the second trench 208 further ensure the accuracy of covering the single-sided first protective layer 206 and the third protective layer 216.

Referring to FIG. 10, an etching process is performed to remove the features not covered by the second photoresist layer 218 by using the first protective layer 206 to have an etch rate different from that of the second protective layer 210 and the third protective layer 216. A protective layer 206 defines an opening 222 in each of the first trenches 204, and openings 222 are formed in the same one-side sidewall of each of the first trenches 204. As can be seen from FIGS. 2 to 10, the depth of the first trench 204 determines the position of the bottom of the opening 222; and the height of the first photoresist layer 214 within the first trench 204 determines the position of the top of the opening 222. In other words, the height of the opening 222 can be defined by the depth of the first trench 204 and the height of the first photoresist layer 214 within the first trench 204.

Please refer to Figure 11. Next, the second photoresist layer 218 is removed, and an arsenic-containing layer filling the opening 222 is formed in the first trench 204 and the second trench 208. In the first preferred embodiment, the arsenic-containing layer comprises an arsenic silicate glass (ASG) layer 224.

Please refer to Figure 12. After the ASG layer 224 is formed, a thermal diffusion process is performed to diffuse arsenic ions in the ASG layer 224 from the opening 222 into the semiconductor substrate 200 to form a contact window 226 corresponding to the opening 222. After the contact window 226 is formed, the ASG layer 224 is removed and the opening 222 is exposed. In addition, in another variation of the first preferred embodiment, the contact window 226 may also be formed in the semiconductor substrate 200 by gas-phase doping, so that the contact window 226 may include an N-type such as arsenic. Doping. The contact window 226 formed through the opening 222 is electrically connected to the source/drain of the subsequently formed MOS transistor to ensure the construction of the current draining path.

Next, please refer to Figure 13. After the fabrication of the contact window 226 is completed, a second metal composite layer 230 is formed in the first trench 204 and the second trench 208. The second metal composite layer 230 and the first metal composite layer 212 are used as bit lines. . The second metal composite layer 230 may include a titanium layer 232 filling the opening 222, a tungsten layer 236, and a titanium nitride layer 234 disposed between the titanium layer 232 and the tungsten layer 236, but those skilled in the art. It should be noted that the material selection of the second composite metal layer 230 is not limited thereto, and any suitable metal or metal compound material may be selected as the material of the second metal composite layer 230. In addition, when the metal layer is formed, the second protective layer 210 and the third protective layer 216 are used to protect the semiconductor substrate 200 from metal contamination. Finally, a fourth protective layer 240 is formed over the second metal composite layer 230 to fill the first trench 204 to complete the fabrication of the buried bit line 250. The fourth protective layer 240 may be a hafnium oxide layer, but is not limited thereto.

Please also refer to Figures 14 through 15. 14 to 15 are schematic views showing a second preferred embodiment of the present invention. In the second preferred embodiment, the steps of forming the first protective layer 206, the second protective layer 210, the first metal composite layer 212, the third protective layer 216, the opening 222, and the arsenic-containing layer are the same as those of the first The preferred embodiment is therefore not described in detail, and those skilled in the art will be able to refer to Figures 2 through 11. The second preferred embodiment differs from the first preferred embodiment in that the arsenic-containing layer formed in the first trench 204 and the second trench 208 and filling the opening 222 is an arsenic-containing polysilicon layer.

Please refer to Figure 14. After forming the arsenic-containing polysilicon layer, the arsenic ions in the arsenic-containing polysilicon layer are diffused into the semiconductor substrate 200 from the opening 222 by a thermal diffusion process to form a contact window 226 corresponding to the opening 222, and then the opening 222 is removed. The arsenic-containing polysilicon layer is not filled, but the remaining arsenic-containing polysilicon layer 225 remains in the opening 222. Next, a titanium layer (not shown) is formed in the first trench 204 and the second trench 208, and a self-aligned metal telluride process is performed to react the arsenic-containing polysilicon layer 225 filling the opening 222 with titanium. A metal telluride layer 228 is formed. The above metal telluride process is well known to those of ordinary skill in the semiconductor art and will not be described herein. It is worth noting that due to the formation of the metal telluride layer 228, a spiking phenomenon between the subsequently formed buried bit line and the source/drain of the MOS transistor can be avoided.

Please refer to Figure 15. After the fabrication of the metal telluride layer 228 is completed, a second metal composite layer 230 is formed in the first trench 204 and the second trench 208, and the second metal composite layer 230 and the first metal composite layer 212 are used as a bit. Yuan line. The metal composite layer 230 may include a titanium nitride layer 234 and a tungsten layer 236, but is not limited thereto. Similarly, when the metal layer is formed, the second protective layer 210 and the third protective layer 216 are used to protect the semiconductor substrate 200 from metal contamination. Finally, a fourth protective layer 240 is formed over the second metal composite layer 230 to fill the first trench 204 to complete the fabrication of the buried bit line 250.

Please refer to Figure 13 and Figure 15 again. According to the method of fabricating the buried bit line provided by the present invention, a buried bit line 250 is provided which includes a trench formed by the first trench 204 and the second trench 208. The buried bit line 250 further includes a protective layer disposed on the sidewalls and the bottom of the trench 204/208, respectively. The protective layer is also composed of the foregoing second protective layer 210 and the third protective layer 216. Since both are yttria materials formed by a thermal oxidation process and have the same etch rate, it can be regarded as the same protection. Floor. The protective layer 210/216 can be used to protect the semiconductor substrate 300 from process damage or metal contamination in subsequent processes. More importantly, according to the method provided by the foregoing invention, an opening 222 is easily defined and formed in the protective layer by an etching process by different characteristics of different protective layer etch rates. It should be noted that, on the other sidewall of the trench 204/208 relative to the opening 222, the buried bit line 250 further includes a protective layer 206. The position and size of the protective layer 206 are the same as the position and size of the opening 222. And a material having an etching rate different from that of the protective layer 210/216, such as tantalum nitride, niobium oxynitride or an oxidation-nitriding-oxidation composite.

Corresponding to the opening 222, a contact window 226 is disposed, which comprises an N-type dopant such as arsenic. The contact opening 222 is formed through the opening 222 to form a contact window 226 in the sidewall of the trench 204/208 for subsequent formation. The source/drain of the transistor is electrically connected to ensure the construction of the current path. The buried bit line 250 further includes a metal composite layer 212/330 disposed in the trench 204/208, further comprising a protective layer 240 filling the trench 204/208; the metal composite layer 212/230 is used as a bit Yuan line. As described above, the metal composite layer 212/230 includes the first metal composite layer 212 and the second metal composite layer 230, and the number of composite layers and the material system of the first metal composite layer 212 and the second metal composite layer 230 may be different. . The first metal composite layer 212 and the second metal composite layer 230 may also be regarded as the upper metal composite layer 212 and the lower metal composite layer 230 according to their upper and lower structures. It should be noted that the upper metal composite layer 212 can fill the opening 322 as shown in FIG. Alternatively, when the contact window 226 is formed by thermal diffusion of an arsenic-containing polysilicon layer, as shown in FIG. 15, a metal telluride layer 228 is formed at the opening 222 by a metal telluride process, and the arsenic-containing polysilicon is formed. Layer 225 and metal telluride layer 228 fill opening 222.

In summary, the buried bit line provided by the present invention and the manufacturing method thereof are applicable to different types of memory, and the position formed by the opening is defined by the formation and removal of the protective layer having different etching rates. And size, thus accurately forming a single-sided contact window in the semiconductor substrate, ensuring the construction of the buried channel of the buried bit line and the MOS transistor, and then avoiding the adjacent memory bit cell due to the buried bit line The defect made by the contact window is abnormally opened.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . DRAM array

110. . . Buried bit line

112. . . Bit line contact window

120. . . Buried word line

130. . . Capacitor

200. . . Semiconductor substrate

202. . . Patterned hard mask

204. . . First ditches

206. . . First protective layer

208. . . Second ditches

210. . . Second protective layer

212. . . First metal composite layer

212a. . . Titanium nitride layer

212b. . . Tungsten layer

214. . . First photoresist layer

216. . . Third protective layer

218. . . Second photoresist layer

222. . . Opening

224. . . ASG layer

225. . . Arsenic-containing polycrystalline layer

226. . . Contact window

228. . . Metal telluride layer

230. . . Second metal composite layer

232‧‧‧Titanium layer

234‧‧‧Titanium nitride layer

236‧‧‧Tungsten layer

240‧‧‧ fourth protective layer

250‧‧‧buried bit line

1 is a schematic diagram of a layout pattern of a conventional 4F ² unit DRAM array;

2 to 13 are cross-sectional views showing a manufacturing process of a first preferred embodiment of a method for fabricating a buried bit line provided by the present invention;

14 to 15 are schematic views showing a second preferred embodiment of the present invention.

200. . . Semiconductor substrate

202. . . Patterned hard mask

204. . . First ditches

206. . . First protective layer

208. . . Second ditches

210. . . Second protective layer

212. . . First metal composite layer

212a. . . Titanium nitride layer

212b. . . Tungsten layer

216. . . Third protective layer

222. . . Opening

226. . . Contact window

230. . . Second metal composite layer

232. . . Titanium layer

234. . . Titanium nitride layer

236. . . Tungsten layer

240. . . Fourth protective layer

250. . . Buried bit line

Claims (23)

A method for fabricating a buried bit line and a single-sided bit line contact window comprises the steps of: providing a semiconductor substrate; performing a first etching process to form a plurality of first trenches in the substrate; Forming a first protective layer on the sidewalls of the first trenches; performing a second etching process to etch the semiconductor substrate at the bottom of the first trenches to form a plurality of second trenches; sequentially forming in the second trenches a second protective layer and a first metal composite layer, the height of the first metal composite layer is less than the depth of the second trench, and the first metal composite layer does not cover the first protective layer; a protective layer exposing a portion of the sidewall of the first trench; forming a third protective layer on the sidewall of the exposed first trench; removing a portion of the first protective layer in a side wall of the first trench Forming an opening through the opening; forming a contact window in the substrate; and forming a second metal composite layer in the first trench and the second trench. The method of claim 1, wherein the first protective layer comprises tantalum nitride, hafnium oxynitride or an oxide-nitride-oxide (ONO) composite. The manufacturing method of claim 1, wherein the forming the second protective layer and the first metal composite layer further comprises: performing an oxidation process, forming the second at the bottom and the sidewall of the second trench; a protective layer; and forming the first metal composite layer in the second trench. The manufacturing method of claim 1, wherein the removing the portion of the first protective layer to expose the sidewall of the first trench further comprises: forming a first photoresist layer on the first metal composite layer And the first photoresist layer covers a portion of the first protective layer; and the first protective layer not covered by the first photoresist layer is removed to expose sidewalls of the first trench. The manufacturing method of claim 1, wherein the step of removing a portion of the first protective layer to form the opening further comprises: forming a second photoresist layer in the first trench and the second trench, And the second photoresist layer covers a portion of the first protective layer; the first protective layer is removed to form the opening; and the second photoresist layer is removed. The manufacturing method of claim 5, wherein the second photoresist layer covers the sidewalls on the same side of the first trench and the second trench The first protective layer. The manufacturing method of claim 1, wherein the contact window is formed in the semiconductor substrate by gas-phase doping. The manufacturing method of claim 7, wherein the second metal composite layer fills the opening. The manufacturing method of claim 1, wherein the step of forming the contact window further comprises: forming an arsenic-containing layer in the opening; and performing a thermal diffusion process to form the contact window. The method of claim 9, wherein the arsenic-containing layer comprises an arsenic-containing polycrystalline germanium layer. The manufacturing method of claim 10, further comprising the step of forming a metal telluride layer in the opening after forming the contact window. The manufacturing method according to claim 9, wherein the arsenic-containing layer comprises arsenic silicate glass (ASG). The manufacturing method of claim 12, further comprising the step of removing the arsenic-containing layer to expose the opening, after forming the contact window. The manufacturing method of claim 13, wherein the second metal composite layer fills the opening. The manufacturing method of claim 1, further comprising forming a fourth protective layer on the second metal composite layer to fill the first trenches, and forming the second metal composite After the layer. A buried bit line includes: a trench disposed in a semiconductor substrate; a first protective layer disposed on a sidewall and a bottom of the trench; and a single-sided opening formed on a sidewall of the trench a protective layer formed in the semiconductor substrate corresponding to the one-side opening; a second protective layer formed on the sidewall of the trench opposite to the one-side opening; and a metal composite layer including An upper metal composite layer and a lower metal composite layer are disposed in the trench. The buried bit line of claim 16, wherein the first protective layer comprises cerium oxide. The buried bit line of claim 16, wherein the position and area of the second protective layer are the same as the position and size of the opening. The buried bit line of claim 16, wherein the second protective layer comprises tantalum nitride, hafnium oxynitride or an oxidized-nitrided-oxidized composite. The buried bit line of claim 16, wherein the contact window further comprises an N-type dopant. The buried bit line of claim 20, wherein the N-type dopant comprises arsenic. The buried bit line of claim 20, wherein the upper metal composite layer fills the openings. The buried bit line according to claim 20, further comprising a metal telluride layer filling the opening.