TWI222716B - A structure of a capacitor and a fabricating method thereof - Google Patents

Abstract

A structure of a capacitor and a method for fabricating the same structure is described. The structure is adapted for improving isolation between passing gate and top plate electrode. An undercut profile of inter-dielectric layer is formed, and sequentially, the undercut profile will be filled with the spacer so that the isolation between gate and electrode will be improved.

Description

1222716

[Technical field to which the invention belongs] The present invention relates to a method for manufacturing a 1T-RAM, and more particularly to a method for improving the insulation effect between a gate and a capacitor. [Previous technology] Integrated circuits have been technically shrinking in size, providing the opportunity to integrate System-On-Chip (S0C), that is, more functions can be integrated on the same chip. In the past few years, many technologies have tried to combine logic circuits and memory on the same integrated circuit, but still maintain the original performance of the two. In fact, the integration provided by SOC still has incompatibility problems. However, after the 1T-RAM cell is started, this simple structure can be more conveniently applied to other processes and greatly reduces the process. Incompatible issues. One of the designs of the 1T-RAM structure is to form a buried capacitor in Shallow Trench Isolation (STI), so that the world line can cross the storage node. Although such a design can reduce the area of the unit cell, it will encounter a difficult problem, how to design to effectively improve the isolation window between the gate and the capacitor when the gate is formed on the capacitor. Figure 1 is a schematic cross-sectional view of the structure of the prior art IT-RAM. Referring to FIG. 1, there is a shallow trench isolation (STI) 102 and an oxide layer 104 on a substrate 100, and a capacitor structure is provided on the shallow trench isolation 102. The capacitor structure includes a lower electrode 106 and a capacitor dielectric. Layer 108, an upper electrode 110. An oxide layer 112 is formed on the shallow trench isolation 102. previously

1222716 V. Description of the invention (2) The technology uses many ways to improve the insulation effect between the gate 114 and the capacitor upper electrode 110, including adding a silicon nitride layer 丨 6 above the capacitor's upper electrode 1 1 0 'And add a silicon oxynitride layer ii 8 on the nitride nitride layer 1 丨 6. Among them, the composite spacer wall 12 is used as insulation between the gate electrode 114 and the upper electrode 1o. However, in the actual manufacturing process, the composite spacer wall 1 2 0 formed by the non-uniform etching often cannot effectively isolate the gate electrode 4 and the upper electrode 110. As shown in the area 122 in FIG. 1, the area 122 is enlarged. The figure is shown in Figure 2. Although the use of the composite spacer wall 120 can roughly cover the side wall of the upper electrode 110, it may not be completely covered and the upper end of the side wall of the upper electrode 110 may be exposed, as shown in area 122 in FIG. 2. Therefore, when the gate electrode 1> 14 is to be formed on the capacitor structure, the area 122 shown in FIG. 2 will cause a leakage current, and the isolation window cannot be accepted through the chip. Test (WAT). [Summary of the Invention] In view of the previous technical background, the gap wall cannot effectively insulate the gate and power up, and the poles cause leakage current, that is, the insulation window cannot pass the wafer test, and cannot be long: a good process window (pr〇 cess ^^ 以 ⑽). Therefore, the purpose of the present invention is to provide a capacitor structure suitable for IT-RAM. The composite spacer of this capacitor structure can effectively isolate the upper electrode of the capacitor from the gate. = Another object of the invention is to provide a capacitor structure that allows the composite spacer walls of subsequent processes to be embedded in the undercut structure by the undercut structure of the dielectric layer located above the upper electrode of the valley.

Page 9 1222716

V. Description of the invention (3) Another object of the present invention is to provide a capacitor structure with an undercut structure on the side wall, so that the composite spacer wall of subsequent processes can be embedded in the undercut structure to increase the composite type. The gap wall covers the effect of the side wall of the capacitor structure to completely isolate the upper electrode of the capacitor from the gate. Yet another object of the present invention is to provide a method for manufacturing a capacitor structure, which can improve the disadvantages of the insulation window failing to pass the wafer acceptance test (WAT) after forming the gate electrode on the capacitor, and can also provide a good process window ( process window) ° According to the method of the present invention, the shallow trench insulation can be improved to form a first cover layer moving area and a downward remaining layer in the main area. The opening is sequentially removed. Then, it is within the first first cover layer. For the purpose, the gate and structure are based on oxygen padding and shallow trenches. The mask layer is removed and the photoresist layer is made, so that the first capacitor structure and its manufacturing method are provided. The insulation effect between the electrode layers is first provided on the base layer. An insulating layer is formed on a part of the shallow trench on the insulating structure. Next, a first conductive-conductor layer can be deposited on the first conductor to form a "exposed pre-insulating structure to resist layer". Shallow, shape a patterned photoresistor capacitor to define a plurality of layers. According to the edge structure on the layer, the oxidation trenches are then formed in sequence: a layer and an anti-reflection layer are coated on the active layer and a second anisotropically engraved part of the anti-reflection layer to plate the trench insulation structure. The body layer and the first dielectric layer are formed by padding oxygen = acoustic-dielectric layer and a second conductive structure. Among them, the first dielectric layer, one or two layers: a stop layer to form an electrolytic solution to form a sidewall of the capacitor structure. Then use: Insect: J Second Dielectric Layer

Page 10 1222716 V. Description of the invention (4) Electrical layer, forming a coating film and a second capacitor and pad oxygen oxidation layer on the first composite layer on the active area and shallow trenches According to the present invention, the structure is structured above the electrode on the capacitor. The occurrence of a complete current can be summarized as described above, and the undercut junction and the gate are filled. Promoted. An undercut structure (undercut prof i 1 e) is formed on the side wall, and then the first undercut structure is filled and filled. Layer, and then a non-uniformity is formed on the pad oxide layer, and then a gate structure is formed on the capacitor structure. An undercut structure is formed on the capacitor manufacturing method, and the undercut 'sequence gap' can be formed by covering the upper electrode with the three dielectric layers located on the anti-reflection layer and then forming a first etch step to form a gate oxide. Structure, the active capacitor junction structure is located in the undercut gate where the capacitor is embedded to avoid leakage of the structure of the present invention. This is so large that it provides an undercut structure that can greatly enhance the process window, that is, the insulating window can be accepted through the chip. Enough to allow the gap wall to fill the effective insulation power-on test, the yield will be [Embodiment] In order to make the present invention and the above-mentioned objects, features, and preferred embodiments and results listed below 'and cooperate; to refer to item 3, A structure 202 (STI) is formed on a semiconductor substrate 200, and an active region 204 (Active Arej, J, ...) is defined. The active region 204 is ion-implanted to form a dopant. Miscellaneous well area (not shown p. 11 i 厶 厶 z / 丄 ο

(Shown on the figure). 1 From 1_, > jz ^ ^ ^ Earth material sequentially deposits pad oxide layer 206 (Pad Oxide) gasification :, = 2G8. The material of the first mask layer 2G8 is, for example, 例如 formed by plasma enhanced chemical vapor deposition (PE-CVD) = 疋 chemical vapor deposition (LP-CVD) method. The deposition height ranges from 60 Angstroms to 500 Angstroms. : ♦ Figure 4, a lithographic etching process is used to remove the first mask layer 208 partially above the shallow trench, and then the first mask layer 208 is used as a mask to remove the exposed pads by an etching process. The oxide layer 206 and a portion of the shallow trenches below it are isolated from the 002 to form a plurality of openings 2 1 0. The openings 2 0 are suitable for the subsequent formation of a capacitor structure therein. Referring to FIG. 5, a first conductor layer 212 is conformally deposited on the openings and the first mask layer 208. The material of the first conductor layer may be polysilicon or other conductive metal layers, and the first conductor layer 212 is used as the lower electrode of the capacitor. Please continue to refer to FIG. 5, and use chemical mechanical polishing or etch-back to remove a portion of the first conductive layer 212 above the first mask layer 208, and the first mask layer 208 serves as a stop layer. Then, the first mask layer 208 is removed using hot phosphoric acid (hot H3P04) to define the capacitor lower electrode 214 as shown in FIG. Referring to FIG. 7, the first dielectric layer 2 16, the second conductor layer 218, the second dielectric layer 220, and the anti-reflection layer plating film 222 are sequentially deposited conformally. The material of the first dielectric layer 21 6 is a double-layer structure of silicon nitride and silicon oxide. The material of the second conductive layer 218 may be polycrystalline silicon or other conductive metal layers. The second dielectric layer 220 may be an oxide or a nitride, and the deposition height is from 50 angstroms to 500 angstroms.

1222716 V. Description of the invention (6) Egypt varies. The material of the anti-reflection coating 2 2 2 is a stretchable silicon oxynitride (SiON) ′ which is formed by a low pressure-chemical vapor deposition (Lp_CVD) method. Referring to FIG. 8, the non-isotropically etched part of the first dielectric layer 2 6, the second conductor layer 218, the second dielectric layer 220, and the anti-reflection layer coating film 222 is formed by using the pad oxide layer 206 as a stop layer. A capacitor structure 224 is above the shallow trench isolation 202. Please refer to FIG. 9. Using an acid agent such as a hydrofluoric acid aqueous solution to treat a capacitor, the structure 2 2 4 this first " electric layer 2 2 0 will be slightly etched by the acid agent to form the picture on the figure. The undercut structure 226 is shown. =, ”FIG. 10, and then depositing a third dielectric layer 228 on the capacitor structure and the oxide layer 206, and then depositing an oxide layer 23 on the third dielectric layer. What is important is that the third dielectric layer 228 fills the undercut structure 226 to form an embedded tenon 232 that penetrates into the capacitor structure. Wherein, the material for forming the third dielectric layer 228 may be nitride nitride deposited by a chemical vapor deposition process. According to FIG. 11, the oxide layer 230 is etched with non-uniform etching to form the first layer and the capacitor structure. The second dielectric layer spacer 228 is located on the pad oxide layer 206. The two sides of the removed spacer wall are generally l-shaped, and the plutonium oxide layer 206 out of the storm is removed. Because the composition of the yttrium oxide layer 230 is the heart, the gate oxide layer 2 and Γ Γ1 Γ23 are formed. Finally, above the movable region 2 0 4 and then the gate is formed. Page 13 1222716

Just 238. This process is well known to those skilled in the art, so it will not be repeated here. The feature of the present invention is that, before the third dielectric layer 228 is deposited, a dilute acid agent such as dilute hydrofluoric acid is used to process the capacitor structure. The acid agent will slightly etch the second dielectric layer 220 to form an undercut structure. 226. The subsequently formed third dielectric layer 228 will have a dowel 232 embedded in the undercut structure 226. Therefore, when the third dielectric layer 228 is subsequently etched to form the spacer 228, a higher height spacer 228 'can be obtained So that the spacer 228 'can completely cover the exposed portion of the second conductor layer 218 located on the side wall of the capacitor structure 224, so that the gate and the upper electrode can be completely insulated, that is, the isolation window is improved, and avoidance is avoided. The occurrence of leakage current.

1222716 Brief description of the drawings [Simplified description of the drawings] In order to cooperate with the description of the preferred embodiment of the present invention, the drawings will be described in detail with the illustrations, in which: Figure 1 shows the cross section of 1T-RAM of the conventional art schematic diagram. Figure 2 shows an enlarged view of the range 52 in Figure 1. Figures 3-11 show the flowchart of the 1T-RAM manufacturing method of the present invention. [Simple description of the representative symbols of the components] 100, 200: Substrate 102, 202: Shallow trench isolation 104, 230: Oxide layer 106, 2 1 4: Lower electrode I 0 8: Capacitive dielectric layer II 0: Upper electrode 112, 206: Pad oxide layer 11 4: Gate 11 6: Silicon nitride layer 11 8: Silicon oxynitride layer 120, 234: Composite Type spacers 122, 122 ': area 204: active area 208: cover layer 210: openings 212, 218: conductor layer

Page 15 1222716 Schematic description of 216, 220, 228: Dielectric layer 222: Anti-reflection layer coating 224: Capacitive structure 226: Undercut structure 228 ': Dielectric barrier wall 230': Oxide barrier wall 232: Embedded Tenon 236: Gate oxide layer 2 3 8: Gate

Page 16

Claims (1)

1222716 VI. Scope of applying for patents ---, this state of the art manufacturing method is suitable for forming a capacitor on a substrate :: Shallow trench isolation, including at least the following steps ... = An opening is formed on the shallow trench insulation Forming a lower electrode within the opening; ^ two first dielectric layers over the lower electrode and the shallow trench isolation; a first conductor, a second dielectric layer, and an anti-reflection layer are coated on Yuanzhuo; Above the dielectric layer, except that the anti-reflection layer coating, the second dielectric layer, and the second conductor = the first; an electric layer to form a capacitor structure on the shallow trench isolation; a spear, a mouth The second dielectric layer of the P-knife is undercut profile of the capacitor structure; forming a bottom = forming a third dielectric layer on the capacitor structure and the pad oxide layer, which really fills the undercut structure; Forming an oxide layer on the third dielectric layer; and etching the oxide layer and the third dielectric layer by at least one etching step to form a composite spacer on a sidewall of the capacitor structure. Said :: Γ package: the method described in the range item 1 ... forming the lower electrode to deposit a polycrystalline silicon layer within the opening and above the shallow trench isolation; and removing the polycrystalline silicon above the shallow trench isolation The thickness of the lower electrode of the Shi Xi layer is 3. The method described in item 1 of the patent application range is from 60 angstroms to 50 angstroms. Page 17 1222716 6. Scope of Patent Application 4. The method as described in item 2 of the scope of patent application, wherein the removal of the polycrystalline silicon layer includes a chemical mechanical polishing process. 5. The method according to item 2 of the patent application, wherein the removing of the polycrystalline silicon layer includes an etch-back process. 6. The method according to item 1 of the scope of patent application, wherein the material of the first dielectric layer is a multiple layer structure of silicon nitride and silicon oxide. 7. The method according to item 1 of the scope of patent application, wherein the material of the first conductor layer is a polycrystalline silicon. 8. The method according to item 1 of the patent application scope, wherein the second dielectric layer may be silicon oxide. 9. The method according to item 1 of the patent application scope, wherein the second dielectric layer may be silicon nitride. 10. The method as described in item 1 of the scope of the patent application, wherein the deposition height of the second dielectric layer ranges from 50 angstroms to 50 angstroms. 11. The method according to item 1 of the scope of the patent application, wherein the anti-reflection layer coating is a silicon oxynitride formed by plasma enhanced-chemical vapor deposition. Page 18 1222716 6. Scope of patent application 1 2 · The method as described in item 1 of the scope of patent application, in which a portion of the second dielectric layer is removed by etching with fluorinated acid. ™ 1 3 · The method according to item 1 of the scope of patent application, wherein the third dielectric chip material is a silicon nitride layer deposited by low-pressure chemical vapor deposition. 14. The method as described in item 1 of the scope of the patent application, wherein the deposition height of the third dielectric reed ranges from 100 Angstroms to 500 Angstroms. θ 1 5 · The method as described in item i of the patent application range, wherein the reed oxide is formed by low pressure chemical vapor deposition. 9 "1 ^ 6. The method as described in item i of the patent scope, wherein the oxidized sound intensity ranges from 200 angstroms to 70 angstroms. 9, including: 11. A method for manufacturing a capacitor The method includes at least the following steps: forming a capacitor structure on a substrate, and the capacitor is connected with an electrode; a capacitor dielectric layer is formed on the lower electrode; an upper electrode is disposed on the capacitor dielectric layer; A first dielectric layer is located on the upper electrode; and an anti-reflection layer coating film is formed on the sidewall of the first dielectric to form a first removed portion of the first dielectric layer. Page 19 1222716 VI. Patent application undercut profile; sequentially forming a second dielectric layer and an oxide layer to cover the capacitor structure; and performing at least one #etching step to etch the oxide layer and the second The dielectric layer is used to form a composite spacer on the sidewall of the capacitor structure. The method as described in item 17 of the patent application scope, wherein the material for forming the lower electrode may be a polycrystalline stone. 19. If the scope of patent application is 17 The method, wherein the thickness of the lower electrode ranges from 60 angstroms to 50 angstroms. 20. The method according to item 17 of the scope of patent application, wherein the material of the capacitor dielectric layer is a Multiple layer structure of silicon nitride and silicon oxide. 2 1. The method as described in item 17 of the scope of patent application, wherein the material for forming the upper electrode can be a polycrystalline chip. 2 2. As the scope of patent application scope 1 The method according to item 7, wherein the first dielectric layer may be silicon oxide. 2 3 · The method according to item 17 of the scope of patent application, wherein the first dielectric layer may be silicon nitride. 2 4 · The method according to item 17 of the scope of patent application, wherein the first dielectric Fan Li on the 20th page requested the application of the layers of the anti-oxidation and anti-nitrogen layer, the formation of the sculpting process, and the description of the spheroids. The 17fb type thickening slurry was used for the membrane. Forging 1222716 VI. Scope of patent application The deposition height of the layers ranges from 50 angstroms to 50 angstroms. 26. The method according to item 17 of the scope of the patent application, wherein the first dielectric layer is partially etched using hydrofluoric acid. 27. The method according to item 17 of the scope of the patent application, wherein the material of the second dielectric layer is a silicon nitride layer deposited by low-pressure chemical vapor deposition. 2 8. The method as described in item 17 of the scope of patent application, wherein the second dielectric layer is deposited at a height ranging from 100 angstroms to 50 angstroms. 29. The method as described in item 17 of the scope of patent application, wherein the oxide layer is formed by low pressure chemical vapor deposition. 30. The method as described in item 17 of the scope of patent application, wherein the deposition depth of the oxide layer ranges from 200 angstroms to 70 angstroms. 31. A capacitor structure including at least: a lower electrode; a first dielectric layer on the lower electrode; Page 21 1222716 6. Scope of patent application-an upper electrode is located on the first dielectric layer; a second dielectric layer is located on the upper electrode; an anti-reflection layer is located on the first dielectric layer; and A gap wall is on both sides of a capacitor; wherein the second dielectric layer has an undercut structure, and the gap wall has a dowel that can be embedded in the undercut structure to improve the insulation window. 32. The structure as described in claim 31, wherein the material of the lower electrode is a polycrystalline silicon. 3 3. The structure according to item 31 of the scope of the patent application, wherein the material of the first dielectric layer is a multiple layer structure of silicon nitride and silicon oxide. 3 4. The structure according to item 31 of the scope of patent application, wherein the material forming the upper electrode is a polycrystalline stone. 3 5. The structure according to item 31 of the scope of patent application, wherein the material for forming the second dielectric layer may be silicon nitride. 36. The structure according to item 31 of the scope of patent application, wherein the material for forming the second dielectric layer may be silicon oxide. 3 7. The structure according to item 31 of the scope of patent application, wherein the material forming the anti-reflection layer is silicon nitroxide. Page 22 1222716 VI. Scope of patent application 3 8. The structure described in item 31 of the scope of patent application, wherein the spacer is a composite spacer composed of silicon nitride and silicon oxide. il p. 23