TWI242741B - Method for accessing frame data and data accessing device thereof - Google Patents

Abstract

A method for accessing frame data and data accessing device thereof are provided to access X-bit frame data. The method includes providing Y memories BANKi (0 < Y <= X), wherein BANKi represent ith memory bank (0 <= i < Y); arranging partial frame data WL,A (X/Y bits) in BANKj, wherein WL,A represent Lth line Ath frame data word and j=(L+A) mod Y; receiving and according to Y word addresses WAk to determine WL,A be located at which memory bank, wherein WAk represent address of kth frame data (0 <= k < Y); and obtaining the partial frame data (X/Y bits) from each BANKi, according to the determining result and combine them to the frame data (X bits).

Description

1242741 V. Description of the invention (1) The technical field to which the invention belongs ^ The present invention relates to a method and device for data access, and more particularly to a frame data access method and data access device. In the prior art, in dynamic compensation video compression algorithms (such as MPEG-1, MPEG-2, MPEG-4, etc.), 'the frame vector must be used to capture the reference according to the motion vector (m0ti〇rl vector). Reference block. The size of a basic block is usually 8 * 8 or 16 * 16 pixels (pixels). Because the capture unit of the motion vector in the horizontal and vertical directions may be half a pixel larger than the pixel and the horizontal line, so refer to the block. The capture is usually 9 * 9 or 17 * 17 pixels. Fig. 1 shows an example of extracting a 9 * 9 reference block (for example, a dashed box 110 in the figure) in a search window 100. Where "Pi" represents the ^ th pixel data of the i-th row (8 bits). Because the motion vector may occur anywhere in the search window, the reference block 110 is usually not the same as the basic block boundary in the search window (frame 120 in the figure). The fake sigh has 64-bit memory buses to capture a whole line of basic η around 120 in each clock cycle, that is, it can access 8: fixed pixel data in the basic box range 120 each time. Each line in the reference box 11〇 covers two basic blocks of her circumference 120, so to retrieve 9 * 9 reference box u〇 will require 9 * 2 = 18. From Figure 1, we can clearly see that the two data in the extracted data are two. Not required. For example, in the first line, a total of data is retrieved :, but only P2, 3, L, ..., P21 丨 pixel data is used. The same is true when fetching other rows. Therefore causing waves

1242741 V. Description of the Invention (2) Disadvantages of memory bus bandwidth. Inner macro of the invention The purpose of the present invention is to save memory access time and provide a frame data access method to improve the overall system performance with the present invention. The purpose of each item ^ is to provide a data access device, in addition to the aforementioned frequency j, which can be operated at a lower power consumption because of unnecessary data access. $ β ^ Proposes a frame data access method to obtain frame data with X bits and squares, where X is a positive integer. This picture frame data access BANK · 矣 + Chu, first provide a memory bank ΑΝΚί, where \ ^ \ memory banks, Y is an integer greater than 1 and less than or equal to X, eight II, blowing 4: ^ equal to 0 and less than An integer of Y. Store the part with χ / γ bits in the ΒAA title, where "U represents the Lth row and the Ath part Y",: ^ and ^ are integers greater than or equal to 0, and (L + A) m〇 d 'two is a conversion operation. Then it receives and judges according to the Y character address WAk ^ desire = taken ^ which frame data is located in each memory bank, among which WA is not k to read some frame data Address, k is an integer greater than or equal to 0 and less than Υ. According to the foregoing judgment result, each part of frame data with X / Υ bits is obtained from memory bank BANK. A combination of part of frame data output by each bank BANKi That is to read the frame data. 2 Ming also proposed a data access device for outputting pre-stored data with one of X bits according to the address signal, where 乂 is a positive integer. This data access device includes memory Controller, γ memory bank and multiplexing combination circuit. The memory controller is used to receive address signals and output γ memory bank bits

1242741 V. Description of the invention (3) Address and memory judgment signal, where, are integers. The γ memory banks are all coupled to, and the corresponding memory bank addresses are greater than 1 and less than or equal to X. Among them, the mind-controller's-memory bank is partially pre-stored with X / Y bits. A ', and turn out the corresponding memory controller and each memory bank, use, and. The multiplexing combination circuit is coupled to each part with X / Y bits received in order to output the pre-stored data of X bits according to the judgement signal of the memory bank: 3 save the poor ^ more I switch and combine according to the address signal It is determined by which pre-storage controller which is to be read and which pre-stored data are respectively stored in each part of the package 3 which is a memory judgment signal. Thinking and outputting its judgment results widely. Ί = Because the data (such as frame data and search window data) are stored separately in different records and seats, Α 7 士 —, four bamboo knives open ^ + 4 Φ ^ ^ ^, ν, 7, so that when the mother ζ reads the data, all parts of the shell material he wants to read can be humbled by the same day ^ # 丨 7 a JJU 呀 obtained from the corresponding memory bank Therefore, data access, memory access bandwidth is saved, and the sturgeon is improved. Therefore, the memory access operation can be performed at a lower clock frequency, thereby reducing power consumption. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described below in detail with reference to the accompanying drawings, as follows. Embodiment FIG. 2 is a flowchart of a method for accessing frame data according to a preferred embodiment of the present invention. Please refer to FIG. 2. This embodiment is used, for example, for video processing, and particularly for obtaining a reference block of frame in video processing to obtain an X-bit

1242741

Frame information. Where X is a positive integer. The picture frame information BANK. '1 Dagger following each step-step. In step S2 1 0, Y banks are provided. Β: ′ BANKi represents the H-th memory bank, γ is a positive number greater than 1 and less than X, and i is an integer greater than or equal to 0 and less than ¥. S220, storing the frame data Wla in the memory bank βανκ〗, and the middle ^ indicates = in the A part of the frame data (χ / γ bit), the L shots are all larger than 0, J — (L + A) mod Y (where mod is a modulo operation). Step S230: Receive and judge in which memory part of the frame data to be read according to the γ character addresses W4. Among them, it represents the address of the frame data to be read, and k is an integer greater than or equal to 0 and smaller. In step S240, the frame data to be read is obtained from each memory bank according to the judgment result in step S23. 1 The above step S240 can be implemented with reference to the following steps. In step S241, according to the judgment result in step S230, γ memory bank addresses are generated, where the access addresses of the ith memory bank are indicated. In step S242, the bank BANKi is accessed according to the bank position 1 address BAi. Step S243: Obtain corresponding frame data from each memory bank BANKi. In step S244, the arrangement order of some frame data (χ / γ bit) output from each bank BANL is judged according to the character address, and the combination is output as the frame data (X bit) to be read.

To sum up, it is assumed here that the system memory bus (memory bus) counts 64-bits' and uses 2 banks to store frame data. In other words, let's say ‘that false a and X are specific to 6 4’ and Y is 2. Therefore, each memory bank outputs a part of 32-bit frame data. FIG. 3 is a diagram illustrating a search window (search window) using two memories according to a preferred embodiment of the present invention.

1242741 V. Description of the invention (5) Examples of the data structure of BANKG and BANK! The size of the search window 300 is 64 * 48 images, as shown in Figure 3. Here, it is assumed that the search character contains 4 pixel data: this column: ,, for example, 32-bit P2, 1 ,? 2, 2, P2, 3 and other pixel data. therefore

For example, %%, 〇 is included in P 2, reference block (reference bloc), as shown in FIG. 1, and ^ is in block 31, which is to be retrieved. ⑻110 is included in the dotted line in FIG. 3 This uses two memory banks, but this should not be used to limit this βανΓΛ to have X-bits. 'You can use ⑽ memory cells): and "Γα: integer (usually a power of two, for example, 64-bit: ί and an integer less than or equal to X (for example, 2, 4, 8 and the whole I 1 represents the first memory bank '丨 is greater than or equal to 0 and the part of the frame adjacent to the block 座 Γ of V is stored in Otherwise, for example, 'if ^ is stored in the 0th memory NK〇, ^, tk 4BANKl &quot; ° ^ ^

For example, if w &quot; house 1; bucket i, j, and% + 1, it must also be stored in a different memory bank. Example. Itr memory 8-way, then W3 ,. Stored in the memory bank BAW i will have part of the map with χ / γ bits (for example, 32 bits), in the A-memory bank BAMj, all of which are greater than or equal to 0, and (L + A) mod Y . In the previous formula, mod is a modulo operation. In Figure 1 of the Ix # technique, if you want to capture through a 64-bit memory bus as in the embodiment, \ 'requires 9 * 2 = 18 clock cycles. According to the actual situation, the dotted box 3 1 0 in FIG. 3 can be obtained. For example, at the time of J 13203twf.ptd page 10 1242741 V. Description of the invention (6) &quot; -------- = Period order fetch Wu (obtained from BANK〇) and (obtained from βΑΝΚι) · Hours During the pulse cycle, machi 2 (taken from BANKq) and ^ are extracted. (Take the pass from βΑΝΚι), extract WS1 (obtained from BANKg) and ^ BANK in the third clock cycle, and so on. Each clock cycle can be simultaneously = Get some of the frame data you want to obtain in the memory bank BANKi. Finally, W1G, G (obtained from BANKQ) and wi (M (obtained from bANKi)) are extracted during the wirth cycle on the wth day; only ~ 2 (obtained from BANKq) are acquired during the 14th clock cycle. Therefore, In this embodiment, only 14 clock cycles are required to complete the fetching process of the reference block 1 (). Therefore, this embodiment significantly improves the disadvantage of wasting memory bandwidth in the conventional technology. This further accelerates the reading efficiency of the reference block. ^ Another embodiment is used to illustrate the present invention. This embodiment is similar to the previous embodiment, except that it uses 4 memory banks to output a portion of the frame of 64 bits In other words, it is assumed that 乂 is equal to 64 and γ is 4. ^ Each memory bank outputs a 16-bit portion of the frame data. Figure 4 is a drawing according to another preferred embodiment of the present invention. An example of a data structure using 4 memory banks BANK0 to 3 and 8 in a search window of the. Please refer to FIG. 4, and also assume that the size of the search window 400 is 6 4 * 48 pixel data To distinguish from the frame data% j of the 32-bit part of the frame in FIG. 3, in FIG. j partial frame data (16 bits). In this embodiment, for example, it contains 2 pixel data. For example, h2, q contains pixel data such as dagger, Q, dagger, 1 in this example. This embodiment It only needs 12 clock cycles to complete the extraction of 9 * 9 reference blocks. The detailed operation of this embodiment is similar to that of the previous embodiment. Those skilled in this art can be obtained by analogy in the previous embodiment, so it will not be repeated here. .

1242741 V. Description of the invention (7) In summary, the data access method and data structure of the present invention are compared with the conventional techniques by taking the search window data as an example. The comparison result is shown in FIG. 5. FIG. 5 is a comparison table of data reading performance of the present invention and the conventional technology. As can be seen from Figure 5, the more memory banks (the smaller the data width), the better the reading performance.

Here is another embodiment according to the present invention, as shown in FIG. 6. FIG. 6 is a block diagram of a data access device according to a preferred embodiment of the present invention. This data access device is used to output pre-stored data (such as frame data or search window data) rdata with X bits according to the address signal addr. The memory controller 61 receives the address signal addr, the read request req — r, the write request req — w, and the write data data — w, and outputs Y memory bank addresses b 0 — addr to bY-1 — addr, memory enable signals CSO to CSY-1, read-write control signals r / w, write data bO_data_w to bY-1_data_w, and memory bank judgement signal BS. Among them, the definitions of X and Y are the same as those in the foregoing embodiment.

The memory bank BANL SBANKw is coupled to the memory controller. In this embodiment, for example, the search window data is stored separately in the memory bank BANK according to the data structure of the foregoing embodiment. Into BANKK. Each bank BANKq to bank ^ receives the corresponding bank address, bank enable signal ^ S () to CSY-1, read / write control signal r / w, and write data b〇 一 data — w to bY -1—data —w, to store the search window data, or each output—output the corresponding pre-stored data b0 —data — r to bY-1 —data — r (X / Y bits). Among them, the memory controller 610 receives and determines according to the address signal ^ = the pre-stored data rdata to be read, where each part of the pre-stored material is located in the memory, and outputs its judgment result. For the record

1242741 V. Description of the invention (8) The memory judges the signal BS. The multiplexing combination circuit 620 is coupled to the memory_610 and the memory bank BANK. To ΒΑΝΚη, used to judge &amp; = BS to multiplex the received part of pre-stored data with χ / γ bits ^ = and combine to output X-bit pre-stored data rdata (chain in this embodiment , Is frame data or search window data). In order to explain the present invention more clearly, the following assumes that the pre-stored data rdata read by the system memory bus has 64 bits, and uses 2 memories to store the search window data. In other words, it is assumed that X is equal to 64 and Y is 2 in this embodiment. Therefore, each memory bank outputs “bit-wise = minute search window data, as shown in FIG. 7A. FIG. 7A is a data access device using two banks according to a preferred embodiment of the present invention. Refer to FIG. 7A, for example, the search window data is stored separately in the memory banks BANKG and BANK! According to the data structure of FIG. 3 in the foregoing embodiment. The address generator AG generates a read request req —r, read Address signals addr — r0 and addr — rl in order to manipulate the corresponding first character (w〇r (j 〇) and the second word = two via write request req — w, write address signal addr — w And write data = d ^ ta — w to cause the external circuit to update the search_data in the memory banks BANKq and M ·. In this embodiment, the address signals addr_r0, add ^ _rl, and the write bit are read. The address signal addr — w is, for example, 0 bits, and the first child of the first child and the written data data are w, for example, 32 bits (if each pixel data is 8 bits, it contains 4 pixel data). The memory controller 710 is used to arbitrate read requests and write requests, and Do not generate memory read and write the desired BANKq and ΒΑΝΚι control signal r / w, i ^ · 13203twf.ptd Page 131242741

V. Description of the invention (9)

άfe, Ku Zhicheng 5 tigers C S 0 and C S1, and memory address b 〇 — a d d r and b 1 an addr. The memory controller 71 0 also generates a memory judgment signal "to indicate which of the first character system is located in each memory bank. For example, when BS = 0, it means that the first character system is located in bank BANKQ. If BS = 1 means that the first character is located in the memory bank BANK. From the data structure shown in Figure 3, it can be clearly seen that the first character and the second character must be extracted from different memories. That is to say When the first character line is located in the bank BANK., The second character is located in the bank BANK! Conversely, if the first character line is in the bank BANK !, the second character is located in the bank BANKQ. Every The output of a memory bank bO-data-r and bl-data-r (both are 32-bit) will be switched and combined into the search brother to be read via the multiplexing combination circuit 7 2 0 (based on the judgement signal bs of the memory bank). Window data rdata (64-bit). This search window data rdata can be used, for example, by a dynamic compensation circuit ME in video processing.

Here, the above-mentioned memory controller 710 can be implemented by referring to FIG. 7B, for example. FIG. 7B is a block diagram of a memory controller 710 in FIG. 7a according to a preferred embodiment of the present invention. The read address signal addr_rO, ad dr — r 1 and the write address signal add r — w are switched by the multiplexers 711 and 712 (in accordance with the read request req-r and the write request req — w) to generate the first Character address w0 —addr and the second character address wl_addr. In this embodiment, for example, the first character address w0-addr is coupled to the judgment circuit 71 3 to generate a memory judgment signal bs. The first character address w0_addr and the second character address wl_addr are respectively switched and output to the memory addresses b0_addr and bl_addr required by the memory banks ΑΝΚ0 and BANK1 through the switching circuit 714 according to the memory judgment signal bs. . For example, when bs = 0, the first character is in the memory

13203twf.ptd Page 14 1242741 V. Description of the invention (ίο)-In BANKG, the first character address W0-addr is coupled and output as the memory bank address b0_addr, and the second character address wl An addr transfer output is ^ self ^ library address bl_addr. Conversely, if bs = l, it means that the first character is located in the memory "bank BANI", so the first character address w0-addr will be rotated out as-busy library address bl-addr, and the second character The character address wl-addr || is connected to the output of the memory address bO_addr. The switching circuit 714 is composed of, for example, multiplexers 714a and 714b. Among them, the multiplexer 71 4a selects the first character according to the determination signal bs Address eight w0 —addr and one of the second character addresses wl-addr are output as the memory address b0-addr. The multiplexer 714b is similar to the multiplexer 714a, except that the multiplexer ^ | 714a outputs the first character address w0_addr as the memory bank address 1) 0 — 8 (1 (11 ', then the multiplexer 7141) sets the second character address “— &amp; ( 1 (^ output is the memory address bl-addr 'and so on. The judgment signal bs is buffered by the delay circuit 71 5 and the output is judged signal bs. Because the memory bank often needs several clock cycles ( (Depending on the type of memory used, its required clock cycle is also different) in order to output the required data 'so the delay circuit 71 5 is used to match Combined with the output timing of the memory bank. In this embodiment, the 'judging circuit 713' can be implemented, for example, with reference to Fig. 7c. Fig. 7C is a circuit diagram of a judging circuit 713 shown in Fig. 7B according to a preferred embodiment of the present invention. Please refer to FIG. 3 and FIG. 7C at the same time. It can be seen from FIG. 3 that the 0th bit (denoted by w0-addr [〇]) and the 4th bit (denoted by w0 of the character address w0-addr). —Addr [4] indicates) If both are 0 (or 丨), the reference window data (frame data) corresponding to the first character address w0-addr is

13203twf.ptd Page 15 1242741 V. Description of the invention (11) Stored in memory bank BANK. . Conversely, if w0-addr [4] is different, the reference window data (frame data) corresponding to the first character address wO_ad dr is stored in the memory bank BANK !. Therefore, the judgment circuit 6 1 3 can be completed by simply mutating the OR gate X0R. In this embodiment, the multiplexing combination circuit 72 may be implemented by referring to FIG. 7D, for example. FIG. 7D is a block diagram illustrating a multiplexing combination circuit 7 2 0 in FIG. 7A according to a preferred embodiment of the present invention. Please refer to Figure 7D, where

r data [63: 32] represents the 32th to 63th bits of data in the search window data r data. Similarly, rdata [31: 0] represents the 0th to 31st bits of data in the search window data rdata. Therefore, the 64-bit search window data rdata is obtained to provide the next-level circuit (such as a dynamic compensation circuit) for further processing. The data b0 —data_r and bl —data—r (both 32 bits) output by the memory banks BANK0 and BANK in FIG. 7a will be connected to the multiplexers 721 and 722. The multiplexer 7 2 1 selects data b0-data-r and bl-data-r according to the memory judgment signal BS (produced by the memory controller 7 丨 〇) and outputs it as the search window. Data rdata [63:32]. Conversely, the multiplexer 722 selects the data b0_data_r and bl_data_r as the second character according to the memory judgment signal BS and outputs it as the search window data rdata [31: 0]. For example, when BS = 0, the multiplexer 721 chooses to output data b0 — data_r as a search window.

Data rdata [63:32], and multiplexer 72 2 chooses to output data bl_data_r as search window data rdata [31: 0]; otherwise, if BS = 1, multiplexer 721 chooses to output data bl_data_r The output is search window data rdata [63:32], and multiplexer 722 chooses to output data b0-data_r as search window data rdata [31: 0].

1242741 V. Description of the Invention (12) Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes without departing from the spirit and scope of the present invention. Changes and retouching, therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application. ❿

13203twf.ptd Page 17 1242741 Brief description of the figure Figure 1 shows an example of a 9 * 9 reference box (the dashed box in the figure) that is generally taken in the search window. FIG. 2 is a flowchart of a frame data access method according to a preferred embodiment of the present invention. FIG. 3 is an example of a data structure using two memories in a search window according to a preferred embodiment of the present invention. FIG. 4 is an example of a data structure of four memory banks BANKq SBANK3 in a search window according to another preferred embodiment of the present invention. FIG. 5 is a comparison table of data reading performance of the present invention and the conventional technology. FIG. 6 is a block diagram of a data access device according to a preferred embodiment of the present invention. FIG. 7A is a block diagram of a data access device using two Lu Jiyi banks according to a preferred embodiment of the present invention. FIG. 7B is a block diagram of a memory controller in FIG. 7A according to a preferred embodiment of the present invention. ° Fig. 7C is a circuit diagram showing a kind of interrupt circuit in Fig. 7B according to a preferred embodiment of the present invention. FIG. 7D is a block diagram of a multiplexed combination circuit in FIG. 7A according to a preferred embodiment of the present invention. Xi [The icon is not explained] 100: Know the structure of the search window data 11 0: 9 * 9 Reference box 1 2 0: Extract the basic box range

1242741 Schematic illustration 300 310 610 620 711 713 715 4 0 0: Search window data structure according to the preferred embodiment of the present invention. The range of the reference block to be read. 7 1 0: Memory controller 720: Multiplex combination circuit 712, 714a, 714b, 721, 722: Multiplexer judgment circuit delay circuits S2 10 to S244: Steps of a frame data access method according to a preferred embodiment of the present invention

13203twf.ptd Page 19

Claims (1)

1242741 VI. Scope of patent application 1 · A frame data access method to obtain frame data with one of X bits to read, where X is a positive integer, the frame data access method includes the following steps: a · Provide Y memory banks BANKi, where BANKi represents the i-th memory bank 'Y is an integer greater than 1 and less than or equal to X, i is an integer greater than or equal to 0 and less than Y; b. Store the frame information WL A in BANK] Among them, WL, A represents the frame data of the Ath part of the Lth row with X / Y bits, L and A are integers greater than or equal to 0, and (L + A) mod Y, and m〇d is the modulus Number operation; c · Receive and judge which part of the frame data to be read is located in the memory according to γ character addresses ψ Ak, which indicates the position of the kth part of the frame data to be read Address, k is an integer greater than or equal to 0 and less than γ; and d. According to the judgment result of step c, the partial frame data with X / Y bits are obtained from the memory bank BANKi, and the memory bank BANKi outputs the The combination of some frame data is the frame data to be read. 2 · The frame data access method described in item 1 of the scope of patent application, wherein step d includes: generating γ memory bank addresses according to the judgment result of step c, where BAi represents the access bit of the i-th memory bank Access to the memory bank BANKi based on the memory bank address BAi; obtain the corresponding frame data from § self-memory bank BANKi; and determine the output of each memory bank BANK with the χ / γ bit according to the character address WAk The arrangement order of the partial frame data is output as Page 20 1242741 Sixth, the scope of patent application X-bit should read the frame information. 3 · If the scope of patent application is the first one, it is used for video processing (= frame data access method returned by members, Vldeo process). 4 · The method for accessing frame data as described in the patent application Fan Qidi J Q 5 JL # π 11 A, which is used to obtain the frame processing. Picture frame test box (feature b 1 ock 5 · — a kind of data access equipment γ. ^ ^ Fk is used to output pre-stored data with one of the X bits according to a single address signal. X is a positive integer. The data access device includes a 'S memory controller, which uses Ur memory to recall the address of the memory and-to remember the address signal of the memory and outputs γ integers equal to X; It is' where Υ is greater than 1 and less than Υ memory banks, which are respectively coupled to the memory bank and receive the corresponding memorizer π g # ^ 涊 一 — 隐 —one of the mouth and cryptic bank addresses and output them separately Corresponding j has a part of the X / Y bits of pre-stored data; and, the barriers are: 22 :! Road is coupled to the memory controller and the records ^ ^ "Kang" judgement signal will be received With X / Y bits = multiplexed switching of stored data and combined output as X-bit read and judged according to the address signal to the desired / t +, 4 kg of these pre-stored data are located in ° Which one is in the hidden library, and judge it by έA 屮 々 々, to determine the signal. 竹 丹 y , Memory 6. The information of the application of paragraph 5 ^ patentable scope of the access device for fruit output, wherein Y 1242741 6. The scope of patent application is equal to 2. 7. As described in item 6 of the scope of the patent application, the address signal contains-筮 ^ ^ "Beijing access device, where ^ Diyiwu address and Yidi-jinyi memory controller include: Diyizi This address is a judgment circuit that is used to receive the first-byte character address to the "Xi Xi" part of the eight cats ^ Yufan address and use this to determine the corresponding delta portion of t in the library basin. The stored data exists in one of the 圮 G rhinoceros, so as to be equal to γ 4 2. Ji and Yude 5 Hai 圮 memory library to determine the signal; the knife change circuit, used to input to the eyes early force according to the memory circuit No. A decides to switch one of the coupling states between the W output, the first abundance A t Λ coupling state is to receive the received ~, and only the second character address is coupled to output a The address of the first library 1S is q coin — ^ 7Γ + L Λ The first 5 is the address of the library, and the received address is loaned with r —A — xt library address The second memory address is the second memory address and the output is the second memory address; one of the two memory addresses, where the first memory bank ^ ^ The memory address of Leyi is the judgment address of these memory addresses respectively I = the data access device described in item 7 of the patent scope, in which the neighbors of the addresses are mutually exclusive or Brake, the mutex or brake receives the first character break segment quantile data and performs mutual OR operation to output the memory judgment The data access device described in item 6 of the multiplexing application patent scope, wherein the storage circuit determines the arrangement order of the parts of the pre-prepared materials according to the judgement signal of the memory bank, and combines and outputs the data. Pre-stored data. • The data access device described in item 5 of the scope of patent application, which is 1242741 6. Scope of patent application For a video process 〇 1 1. The data access device as described in item 10 of the scope of patent application, which is used to access a frame of data. 1 2. The data access device as described in item 11 of the scope of patent application, which is used to obtain a reference block in the frame data. 11 13203twf.ptd Page 23