TW200537369A - Method for accessing frame data and data accessing device thereof - Google Patents

Abstract

A method for accessing frame data and data accessing device thereof are provided to access X-bit frame data. The method includes providing Y memories BANKi (0 < Y ≤ X), wherein BANKi represent ith memory bank(0 ≤ i < Y); arranging partial frame data WL,A (X/Y bits) in BANKj, wherein WL,A represent Lth line Ath frame data word and j=(L+A) mod Y; receiving and according to Y word addresses WAk to determine WL,A be located at which memory bank, wherein WAk represent address of kth frame data (0 ≤ k < Y); and obtaining the partial frame data (X/Y bits) from each BANKi according to the determining result and combine them to the frame data(X bits).

Description

200537369 Description of the invention (1) The technology to which the invention belongs The present invention relates to a method and device for data access, and relates to a frame data access method and data access method. In dynamic compensation video compression algorithms (eg MPEG — 丨, Μρε ^ 2, MPEG-4, etc.), it is necessary to extract the reference block in the frame according to the motion vector (_; ^ ⑽ vector). biOck). The size of the baS1C block is usually 8 * 8 or 16 * 16 pixels (pixels). The horizontal and vertical capture units of the motion vector may be half a pixel larger than the pixels and horizontal lines, respectively. The reference side or the like is usually 9 * 9 or 17 * 17 pixels. Fig. 1 is an example showing a 9 * 9 reference block (for example, a dashed box 110 in the figure) is generally taken in a search window 100. Among them Pi〗 is the j-th pixel data of the i-th row (8 bits). Because the motion vector may occur anywhere in the search window, the reference block 110 is usually not the same as the basic block boundary in the search window (frame 120 in the figure). Assume that there is a 64-bit memory bus that fetches an entire line in the basic block range 120 in each clock cycle, that is, 8 pixels of data in the basic block range 120 can be accessed each time. Each row in reference block ι10 covers two basic block ranges 120, so accessing 9 * 9 reference block ho will require 9 * 2 = 18 clock cycles. From Figure 1, we can clearly see that some of the captured data is not needed. For example, p2 is captured in the first row. ..... P2,15, but only need to use P2,3, P24 ... p2, u pixel data. The same is true when fetching other rows. And therefore waste

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200537369

V. Description of the Invention (2) Disadvantages of Memory Bus Bandwidth Summary of the Invention 4 The purpose of this invention is to provide a frame data access method, that is, to equal the bandwidth of the body access and improve the overall system performance. Another purpose of the month is to provide a data access device, in addition to the foregoing: ★ It can operate at a lower clock frequency due to the reduction of unnecessary data access, thereby reducing power consumption. The present invention provides a frame data access method to obtain frame data with X bits 疋, where χ is a positive integer. This frame data access method includes the following steps. First, γ memory banks BAN &amp; are provided, where BANKi represents the ith memory bank, γ is an integer greater than 1 and less than or equal to X, and 1 is an integer greater than or equal to 0 and less than Y. Store part of the frame data WL and A with χ / γ bits in BANKj, where wLA represents the data of part A of the L-th row of the frame, L and A are integers greater than or equal to 0, j = (L + A) mOd Y ′ m〇j is a modulo operation. Then, it receives and determines according to the Y character address WAk in which memory part of the frame data to be obtained is located, which represents the address of the kth frame data to be read, where k is greater than or equal to 0 and k and an integer less than Y. According to the aforementioned judgment results, BANKi is obtained from the memory bank, and there are frame data of each part of the χ / γ bit. The combination of some frame data output by each memory bank BANKi is to read the frame data. The present invention further provides a data access device for outputting pre-stored data having one of X bits according to an address signal, where χ is a positive integer. This data access device includes a memory controller, γ memory banks, and a multiplexed combination of β and G memory controllers to receive address signals and output γ memory banks.

200537369

^ And the memory judgment signal, where γ is greater than i and small-number. The γ memory banks are all coupled to the memory control $, and any bank receives one of the corresponding memory bank addresses,. Hidden library knife dougu γ / v a-seven plus, this from and in turn respectively corresponding to the X / Y position of the part / knife pre-stored data. Multiplex combination circuit memory controller and each memory bank, used to save σ ^ -V a ^ v / v-used to judge the signal according to the memory bank to receive the /, X / Y positions Pre-stored data is multiplexed and output as X-bit pre-stored data. Among them, the memory controller receives and judges which parts of the pre-stored data contained in the pre-stored data to be read according to the address signal, and outputs the judgment result as a memory judgment signal.

In the present invention, because data (for example, frame data and search window data) are stored separately in different memories, each time the data is read, each part of the data can be read from the corresponding one at the same time. Obtained in the memory, thus reducing unnecessary data access, saving memory access bandwidth and improving overall system performance. Therefore, the memory access operation can be performed at a lower clock frequency, thereby reducing power consumption. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described below in detail with reference to the accompanying drawings, as follows. Embodiment FIG. 2 is a flowchart of a method for accessing frame data according to a preferred embodiment of the present invention. Please refer to FIG. 2. This embodiment is used, for example, for video processing, and particularly for obtaining a reference block of frame in video processing to obtain an X-bit

13203twf.ptd Page 8 200537369 V. Description of the Invention (4) One of the Yuan Yuan wants to read the frame information. Where 'X is a positive integer. The frame data access method includes the following steps. In step S210, ¥ banks BANK are provided. Among them, BANK represents the i-th memory bank, γ is an integer greater than i and less than or equal to X, and i is an integer greater than or equal to 0 and less than Y. In step S220, the frame data WL, A are stored in the memory bank βANK, and the straight middle w represents the frame data (χ / γ bit) of the Ath part of the Lth row, and L is an integer that is equal to 0. , P (L + A) mod Y (where mod is a modulo operation). Step S230: Receive and judge in which memory part of the frame data to be read according to the γ character addresses WAk. Among them, W4 represents the first (the address of the frame data to be read, k is an integer greater than or equal to 0 and less than Y. Step S240, according to the judgment result of step S230, obtain the frame to be read from each memory bank ^ ㈣ Data. 1 The above step S240 can be implemented with reference to the following steps. Step S241, according to the judgment result of step S230, γ memory bank addresses are generated, among which BAi table 2 is the access address of the ith memory bank. Step S242, according to The memory bank 1 accesses the bank BAMi. Step S243: Obtain the right, two-part frame data from each bank "M. Step S244, judge the part of the frame data U output from each of the 5 banks BANKi based on the character address ^. / Y bit) and output the frame data (X bit) according to the combination. &Lt; As mentioned above, it is assumed that the system memory bus (fflemory bus) ^ bit, and use 2 memory banks to store picture frame data. In other words, ^ 'is assumed that χ is equal to 64, and. Therefore, each memory bank has its own part of the given ^. Figure 3 is a preferred implementation according to the present invention. Used in a search window (search wind〇w) 2 Memory bank 1 13203twf.ptd Page 9 200537369 V. Explanation of the invention (5) An example of the data structure of BANK〇 and BANK! Please refer to FIG. 3, and assume that the size of the search window 300 is 64 * 48 pixel data, and In the figure, w represents the frame data of the j-th part of the first row. In this embodiment,%〗 is, for example, a 32-bit word το ', which contains 4 pixel data. For example, W2 q contains the image shown in Figure 2, Cape 2. 〇, Pu, Dagger 2, P2, 3 and other pixel data. Therefore, the reference block (reference block) 11 in the figure] is included in the dotted box 3 1 0 in Figure 3. This: Although the embodiment uses two memory banks, this RANHf should not be limited in this way. 1 S memory bus has X bits, and Y memory banks can be used. Among them, X is a positive integer (usually 2) Powers, for example, bit = 'is an integer greater than 1 and less than or equal to χ (for example, 2, 4, 8, and Y ii I i BANKi represents the first memory bank, 1 is greater than or equal to 0 and the same as ΓΓ temple The frame data Wi, j and ^ adjacent to V are stored in Fuji WW: For example, if W2, they are stored in the 0th memory In BANK0, J f is placed in the first memory bank BANIK. And the adjacent two lines of the same position frame data Wij and Vj must also be stored in different memory banks. For example. In the memory bank BANK °, Then W3 ,. is stored in the memory bank BANKi frame data w 'will have the entire Λ memory bank BANU with a part of the graph of X / Y bits (for example, 32 bits), where L and Α are both greater than or equal to 0, Xibu ( L + A) mOd Y. In the above formula, m 0d is a modulus operation. Figure! Zhi ^^ ° ^ # i If you want to extract through the 64-bit memory bus as in the example, work: "At 10, 9 * 2 = 18 clock cycles are required. If according to the actual situation, the dotted line 31 in FIG. 3 can be obtained. For example, at time i

I 13203twf.ptd Page 10 200537369 V. Description of the invention (6) W2,0 (obtained from BANK0) and W21 (obtained from βΑΝΚι) in 5 cycles ^ 2,2 (obtained from BANKg) and %. (Take from [[take; =; extract W3i (obtained from BMKO) and (obtained from BAN &amp;) in the 3rd clock cycle, and so on.) Each clock cycle can be simultaneously retrieved from each bank BANKi Get some of the frame data you want to get. Finally, get Vg (from BANK.) _Igi (from ΑΝΚι) in the wth pulse cycle, and ^ 2 (from βΑΝΚ〇) at the 14th clock cycle. (Acquisition). Therefore, this embodiment only needs 14 clock cycles to complete the reference block.] The extraction process in this embodiment significantly improves the shortcomings of wasted memory and bandwidth in the conventional technology, thereby speeding Reference is made to the reading efficiency of the block. Here is another embodiment to illustrate the present invention. This embodiment is similar to the previous embodiment, except that it uses 4 memory banks to output a part of the frame data of 64 bits. In other words, it is assumed that the meaning is equal to 64 and γ is 4. Therefore, each memory bank outputs a part of the frame data # of 16 bits, respectively. FIG. 4 is a diagram according to another preferred embodiment of the present invention. Search window using data from 4 banks BANKg to ΒΑΝκ3 An example of the structure. Please refer to FIG. 4. Here, it is also assumed that the size of the search window 400 is 64 * 48 pixel data. To distinguish it from the 32-bit portion of the frame data% in FIG. 3, it is shown in FIG. The i-th row and j-th part of the frame information (16 bits ^). In this embodiment, for example, it contains 2 pixel data. For example, "Za" contains pixel data such as 1 &quot; 2, 0, etc. in this figure. This The embodiment only needs 12 clock cycles to complete the 9 * 9 reference block acquisition. The detailed operation of this embodiment is similar to the previous embodiment. Those who are familiar with this art can be obtained by analogy in the previous embodiment, so it is not here. To repeat.

IH 13203twf.ptd Page 11 200537369 V. Description of the invention (7) To sum up, I will use the search window data as an example to compare the data access method and data structure of the present invention with the conventional technology. The comparison results are shown in the figure. 5 shown. FIG. 5 is a comparison table of data reading performance of the present invention and the conventional technology. As can be seen from Figure 5, the more memory banks (the smaller the data width), the better the reading performance. &gt;

Here is another embodiment according to the present invention, as shown in FIG. 6. FIG. 6 is a block diagram of a data access device according to a preferred embodiment of the present invention. This data access device is used to output pre-stored data (such as frame data or search window data) rdata with X bits according to the address signal addr. The memory controller 610 receives the address signal a (idr, read request req — r, write request req — w, and write data data — w, and outputs Y memory bank addresses b 0 — addr to bY-1 An addr, a memory enable signal CS0 to CSY-1, a read / write control signal r / w, a write data b0-data-w to bY-1-data-w, and a memory judgment signal BS. Among them, X and The definition of γ is the same as the previous embodiment. The memory bank is coupled to the memory controller 61. In this embodiment, for example, the search window data is stored separately in the memory bank BANK according to the data structure of the previous embodiment. It is stored in BANK. Each bank BANKq1 banKw receives the corresponding bank address, bank enable signal to CSY-1, buy / write control signal r / w, and write data b〇 — data —w to

1—data—w to store the search window data, or output the corresponding pre-stored data bO—data —r to bY-1-data—r (X / Y bits). Among them, § The self-memory controller 61 〇 receives the pre-stored data to be read according to the address signal addr 2 and judges which part of the pre-stored data contained in rdata is located in the memory respectively. The output is recorded

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The memory library judges the signal BS. The multiplexing combination circuit 62 is coupled to the memory controller 610 and the memory bank BANKqSBANKw, and is used to multiplex and switch the received part of the pre-stored data with χ / γ bits according to the memory judgment signal BS and output as X. Bit pre-stored data rdata (for example, frame data or search window data in this embodiment). In order to explain the present invention more clearly, the following assumes that the pre-stored data rdata read through the system memory bus counts 64 bits, and 2 = banks are used to store the search window data. In other words, it is assumed that 64 'and Y is 2 in this embodiment. Therefore, each memory bank outputs 32-bit data: the search window data of the two channels, as shown in FIG. 7A. FIG. 7A is a data access device block φ m cT 'using two memories according to the present invention, which is also not shown in the drawing. According to FIG. 7A, for example, the search window data is separated according to the aforementioned 4 U4 data structure. Stored in memory banks BANKD and BANKi. &gt; (hHH ^ AG generates a read request req —Γ, reads the address signal addr-r0i-f — in order to extract the corresponding first character (word 0) and the second character data Η + requires req-w, Write address signal addr — w and write search window a? And = circuit update memory bank BANK.

addr— &quot; and the nested example of the 'read address signal addr-r0, one character—the address signal addrj is, for example, all 10 bits, and the first two characters and write The data data-w are, for example, 32 bits (if ^ is 8 bits, it contains 4 pixel data). And the eight-body controller 71 is used to arbitrate the read request and the write request, and generates the memory bank ^^ () and the read-write control signal r / w

200537369 V. Description of the invention (9) The δ-fe library enabling signals C S 0 and C S1 and the memory address b 0 _ a d d r and bl —addr. The memory controller 7i〇 also generates a memory judgment signal "to indicate which of the first character system is located in each memory bank. For example, when BS = 0, it means that the first character system is located in bank BANKQ. If BS = 1 indicates that the first character is located in the BAN &amp; from the data structure shown in Figure 3, it can be clearly seen that the extraction of the first character and the second character must come from different memory banks. That is, when the first character line is located in the memory bank BANKq, the second character is located in the memory bank ΑΝΚι; conversely, when the first character line is located in the memory bank BANI ', the second character is located in the memory bank Bank. Every The outputs bO-data_r and bl-data-r (both 32-bit) of a memory bank will be switched and combined into the search window data rdata ( 64 bit). This search window data rdata can be used, for example, to provide a dynamic compensation circuit ME in video processing. Here, the above-mentioned memory controller 71 can be implemented with reference to FIG. 7B. FIG. 7B is a comparison according to the present invention. One of the best embodiments shown in FIG. 7A Memory controller 710 block diagram. The read address signal addr_rO, addr_rl and the write address signal addr_w are switched by the multiplexers 711 and 712 (according to the read request req_r and the write request req_w) to generate the first One character address ~ 0-8001 (1): and second character address ~ 1-3 (1 (1) :. In this embodiment, for example, the first character address w0- addr is coupled to the judging circuit 713 to generate a memory judgment signal bs. The first character address w0_addr and the second character address wl_addr are respectively switched and output as memories according to the memory judgment signal bs via the switching circuit 714 The bank addresses bO — addr and bl — addr required for banks BANK0 and BANK1. For example, when bs = 〇, it means that the first character is located in the memory bank

13203twf.ptd Page 14 200537369 V. Description of the invention (ίο) In the BAN KQ, the first character address w 0 — addr is outputted as the memory address bO-addr, and the second character bit The address w l_addr is coupled to the output of the memory library address bl_addr. Conversely, if bs = l, it means that the first character is located in the memory and bank BANI ^ t, so the first character address wO_addr_ is connected to the memory address bl_addr, and the second character is The address wl_addr is coupled to the output bX_addr.

The switching circuit 714 is composed of, for example, multiplexers 71 4a and 71 4b. Among them, the multiplexer 71 4a selects one of the first character address, wO_addr and the second character address wl_addr according to the judgment signal bs, and outputs it as the memory address bO_addr. The multiplexer 714b is similar to the multiplexer 714a, except that if the multiplexer 714a outputs the first character bit iW〇aa (jdr is output as the memory bank address bO_addr, the multiplexer 714b will The second character bit awl_ ° ad ^ is output as the memory address bl_addr 'and so on. The judgment signal "is buffered by the delay circuit 715 and is output as the judgment signal. Because memory line read instructions often require several clocks Period (depending on the adopted body shape, the required clock period is also different): the required data 'so use the delay circuit 715 to match the two timing. T _ mountain in this embodiment' judgment circuit 713 can be, for example. Figure 3 shows the circuit diagram of circuit 713, which is redundant and broken according to the preferred embodiment of the present invention. Please also refer to Figure 3 and use the first judgment to see that the character address wO — addr 〇 Yang, the picture can be shown) and the fourth bit (w0-addr [4] table stem) from = WW〇 ~ addr [0] table-character address corresponding to w〇_addr ^ At the same time, the agency is 0 (or 1) 'then the> number _ data (frame data)

200537369 V. Description of invention (11) Stored in memory bank BANK. . Conversely, if w0 —addr [0] and w0 —addr [4] are different, the reference window data (frame data) corresponding to the first character address wO_addr is stored in the memory bank BANK]. Therefore, the judging circuit 613 can be simply mutually exclusive OR gate X0R. In this embodiment, the multiplexing combination circuit 720 can be implemented with reference to FIG. 7D, for example. FIG. 7D is a block diagram illustrating a multiplexing combination circuit 720 in FIG. 7A according to a preferred embodiment of the present invention. Please refer to FIG. 7D, where rdata [63:32] represents the 32-63th bit data in the search window data rdata 'similarly' rdata [31: 0] represents the search window data r (0-31 bit data in the jata Therefore, the 64-bit search window data rdata is obtained to provide the next-level circuit (such as a dynamic compensation circuit) for further processing. In Figure 7A, the memory bank BANK0 and BANK output data b0_data_r and bl- data_r (both 32 bits) will be connected to the multiplexers 721 and 722. The multiplexer 721 selects the data b0 —data_r and bl_ according to the memory judgment signal BS (generated by the memory controller 71). data —r The output of the first character is the search window data rdata [63:32]. Conversely, the multiplexer 722 selects the data BS according to the memory judgment signal b〇 a data — r and bl — data — r The second character of the two is output as search window data rdata [31: 〇]. For example, when B ^ O ', the multiplexer 721 chooses to output the data b〇—data—r as the search window data. rdata [63: 32], and the multiplexer 72 2 selects the data bl a data ~ r _, and outputs it as the search window data ^ 3 [31: 〇]; If 33 = 1, then more than 1 is 721 and the data bl_data_r is selected as the search window data rdata [63:32], and the multiplexer 722 is selected to output the data b〇-data_r as the search window data rdata [3 1: 0].

200537369 V. Description of the invention (12) Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes without departing from the spirit and scope of the present invention. Changes and retouching, therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

13203twf.ptd Page 17 200537369 Brief description of the diagram Θ 疋, ’, and the staff show an example of a 9 * 9 reference box (the dashed box in the figure) in the search window. FIG. 2 is a flowchart of a frame data access method according to a preferred embodiment of the present invention. Fig. 3 is an example of a data structure using two memories in a search window shown in a preferred embodiment of the present invention. ^ 囷 4 疋 依 ", an example of a data structure using 4 memories βΑΝΚ〇 ～ ^ 龙 ^ in a search window shown in another preferred embodiment of the present invention. FIG. 5 is the present example. Comparison table of the data reading performance of the invention and the conventional technology. Figure 6: A block diagram of a device according to a preferred embodiment of the present invention. Access to material Figure 7A is a diagram according to a preferred embodiment of the present invention. A block diagram of a data access device for Lu Jiyi Library. Fig. 7B is a block diagram of a memory controller in accordance with a preferred embodiment of the present invention. Fig. 7C is a diagram according to a preferred embodiment of the present invention. 7B is a circuit diagram of a broken circuit in FIG. 7β. FIG. 7D is a block diagram of an industrial-combination circuit according to the preferred embodiment of the present invention. Know the structure of the search window data 110: 9 * 9 Reference box 120: Extract the basic box range

13203twf.ptd Page 18 200537369 Brief description of the diagrams 3 0 0, 4 0 0: Search window data structure according to the preferred embodiment of the present invention 3 1 0: The range of the reference block to be read 6 1 0, 7 1 0 : Memory controllers 620, 720: Multiplex combination circuits 711, 712, 714a, 714b, 721, 722: Multiplexer 7 1 3: Judgment circuit 71 5: Delay circuits S210 ~ S244: According to a preferred embodiment of the present invention Steps of a picture frame data access method

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Claims (1)

200537369 VI. Scope of Patent Application1. A frame data access method to obtain frame data with one of X bits to buy frame data 'where X is a positive integer. The frame data access method includes the following steps: a · Provide Y memory banks BANKi, where BANKi represents the H-th memory bank 'Y is an integer greater than 1 and less than or equal to X, i is an integer greater than or equal to 0 and less than Y; b. Store frame data WL A in BANK〗 , Where wl a represents the frame data of the Lth row and the Ath part with X / Y bits! ^ And A are integers greater than or equal to 0, and (L + A) mod Y, and m〇d is a modulo operation; • Receive and judge according to the Y character address WAk which part of the map data you want to read is located in those memories, which indicates the address of the first read part of the frame data, k is greater than or equal to 0 And less than the number of ¥; and '_ d. According to the judgment result of step C, obtained from the memory bank 68 and ^ and there is χ / γ imitation of the image, and a is the data of the frame to be read. 2. The frame described in item 丨 of the scope of patent application, wherein step d includes: m sub-multiplication method, according to the judgment result of step c, γ memory bank addresses are underrepresented, which indicates the access address of the ith memory bank ; 18 access to memory bank BANK according to memory address BAi; self-remembered memory bank BANKi obtained the corresponding frame data · judging from the 70 address WAk of each bank BANKi turns out to be ancient γ / ν R The order of the parts of the frame data and according to this group == Ptd l32〇3twf. Page 20 200537369 X bit should read frame data. 3. The frame data access method as described in item 丨 of the declared patent scope, which is used for a video processing (vide〇 pr〇cess). ^ 4. The frame data access method described in item 3 of the scope of patent application, which is used to obtain a reference frame of reference in the video processing. L A data access device for outputting pre-stored data with one of X bits according to an address signal, where 1 is a positive integer. The data access device includes: A memory controller for receiving the address signal and outputting γ memory bank addresses and a memory judgment signal, where γ is an integer greater than 丨 and less than or equal to X; a memory bank is coupled to the A memory controller, which receives any one of the corresponding memory bank addresses and outputs a corresponding part of pre-stored data having χ / γ bits respectively; and a multiplexing combination circuit Connected to the memory controller and the banks' to multiplex and switch the received partial pre-stored data with χ / γ bits according to the memory judgment signal and output them as X-bit The pre-stored data, The memory controller receives and judges, based on the address signal, which part of the pre-stored data contained in the pre-stored data to be read is located in the memory banks, and outputs the judgment result as the Memory judgment signal. &quot; 6. The data access device described in item 5 of the scope of patent application, wherein γ 200537369 6. The scope of patent application is equal to 2. 7. The data access device as described in item 6 of the scope of patent application, wherein the address signal includes a first character address and a second character address, and the memory controller includes: a judgment circuit, It is used for receiving the first character address and judging that the part of the pre-stored data corresponding to the first sub-address exists in one of the memories, and outputs the judgement signal of the memory according to the judgment result. And a switching circuit for determining a coupling state between the input and output of the switching circuit according to the memory judgment signal, the coupling state is the received first character address and the second character The addresses are respectively coupled to output a first memory address and a second memory address, and the received first character address and the second character address are respectively coupled to output as the One of the second memory bank address and the first memory bank address, wherein the first memory bank address and the first memory bank address are respectively "8. The data access device described in item 7 of the patent scope, which = The disconnection circuit includes a mutex or gate, which receives the partial data of the first character and performs a mutex or operation and outputs the memory bank to determine the state of the patent. The data access device described above, where :: Ϊ ΐ ί: The road system determines the sequence of the partial pre-ΓΛ? Columns according to the judgement signal of the memory bank, and merges and outputs them as the pre-stored data. Data access device, which is 200537369 VI. Patent application scope for a video process 〇1 1. The data access device described in item 10 of the patent application scope, which is used for accessing a video process Frame data (frame) 1 2. The data access device as described in item 11 of the scope of patent application, which is used to obtain a reference block in the frame data. 13203twf.ptd Page 23