TWI898163B - Semiconductor package device - Google Patents

Abstract

A semiconductor package device is provided. The semiconductor package device includes a chip and a redistribution layer disposed on the chip and electrically connected to the chip. The redistribution layer includes a plurality of first metal lines and a plurality of second metal lines, wherein at least one of the second metal lines is disposed between two adjacent first metal lines. The included angle between the at least one of the second metal lines and the two adjacent first metal lines is greater than or equal to 0 degrees and less than or equal to 10 degrees. The first width of one of the two adjacent first metal lines is greater than the second width of the at least one of the second metal lines.

Description

semiconductor package devices

The present disclosure relates to an electronic device, and more particularly to a semiconductor package device that uses a special circuit structure to protect signal traces.

The redistribution layer of a fan-out packaged chip must span the chip and packaging material, causing the signal traces in the redistribution layer to be subjected to significant stress at the interface between the heterogeneous materials, making the redistribution layer susceptible to delamination or cracking.

According to one embodiment of the present disclosure, a semiconductor package device is provided, comprising: a chip; and a redistribution wiring layer disposed on the chip and electrically connected to the chip, the redistribution wiring layer comprising a plurality of first metal wires and a plurality of second metal wires, wherein at least one of the plurality of second metal wires is disposed between two adjacent plurality of first metal wires, an angle between the at least one second metal wire and the two adjacent plurality of first metal wires is greater than or equal to 0 degrees and less than or equal to 10 degrees, and a first width of one of the two adjacent plurality of first metal wires is greater than a second width of the at least one second metal wire.

The following disclosure provides many different embodiments for implementing different features of the present invention. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the disclosed embodiments describe a first feature component formed on or above a second feature component, it may include embodiments in which the first feature component and the second feature component are in direct contact, and may also include embodiments in which additional feature components are formed between the first feature component and the second feature component, so that the first feature component and the second feature component may not be in direct contact.

It should be understood that additional operating steps may be implemented before, during, or after the method, and in other embodiments of the method, some operating steps may be replaced or omitted.

In addition, spatially relative terms such as "below," "beneath," "lower," "above," "above," "higher," and similar terms may be used. These spatially relative terms are used to facilitate description of the relationship between one component or features and another component or features in the diagrams. These spatially relative terms include different orientations of the device in use or operation, as well as the orientations depicted in the drawings. When the device is rotated 45 degrees or in other orientations, the spatially relative adjectives used therein will also be interpreted based on the rotated orientation. In some embodiments of the present disclosure, terms such as "connected," "interconnected," and the like, unless otherwise specified, may refer to two structures being in direct contact, or may refer to two structures not being in direct contact but having another structure disposed therebetween. Furthermore, such terms may include situations where both structures are movable or both structures are fixed.

In the specification, the terms "about", "approximately", "generally", "substantially" generally indicate that a characteristic value is within plus or minus 15%, or within plus or minus 10%, or within plus or minus 5%, or within plus or minus 3%, or within plus or minus 2%, or within plus or minus 1%, or within plus or minus 0.5% of a given value.

It should be understood that although the terms "first," "second," "third," etc. are used herein to describe different elements, components, regions, layers, and/or sections, these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below could be referred to as a second element, component, region, layer, or section without departing from the technology of the present disclosure.

Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and this disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the present disclosure.

Please refer to Figures 1 and 2. According to an embodiment of the present disclosure, a semiconductor package device 10 is provided. Figure 1 is a schematic cross-sectional view of the semiconductor package device 10. Figure 2 is a top view of the semiconductor package device 10. In the present disclosure, the semiconductor package device 10 may include an antenna device, a display device, a radar device, a lidar device, a package component, a package module, etc., but the present disclosure is not limited thereto. The package component may, for example, include architectures such as a system-in-package (SiP) or a system-on-chip (SoC), but the present disclosure is not limited thereto. The semiconductor package device 10 may be applicable to packaging such as wafer-level packaging (WLP) or panel-level packaging (PLP), and may, for example, include packaging methods such as chip-first or RDL-first, but the present disclosure is not limited thereto. It should be noted that the electronic device can be any combination of the aforementioned arrangements, but the present disclosure is not limited thereto.

As shown in FIG. 1 , a semiconductor package device 10 includes a chip 12, a redistribution layer (RDL) 14, and a protective layer 16. The RDL 14 is disposed on the chip 12 and electrically connected to the chip 12. The protective layer 16 surrounds the chip 12. For example, in a cross-sectional view, the protective layer 16 contacts at least two side surfaces 12s of the chip 12. According to some embodiments, the semiconductor package device 10 may further include bumps 20 disposed on the RDL 14. The chip 12 can be electrically connected to an electronic component 22 via the RDL 14, the bumps 20, and the bonding pads 18 to form an electronic device. In some embodiments, the redistribution wiring layer 14 may be composed of an alternating stack of insulating layers and conductive layers, and may further include, for example, a thin film transistor (TFT) (including gate/source/drain/semiconductor layers), a resistor, a capacitor, or an inductor, but the present disclosure is not limited thereto. Other suitable components may also be included in the redistribution wiring layer 14. In some embodiments, the conductive layer of the redistribution wiring layer 14 contacting the bump 20 may serve as an under-bump metallization (UBM). In some embodiments, the protective layer 16 may include an epoxy molding compound (EMC). In some embodiments, bumps 20 may include, but are not limited to, solder balls, anisotropic conductive film (ACF), copper pillars, or other suitable bumps. In some embodiments, electronic components 22 may include, for example, printed circuit boards (PCBs), resistors, capacitors, inductors, antennas, circuit components, or driver circuit components. However, the present disclosure is not limited thereto, and other suitable electronic components are also applicable to the present disclosure. The circuit components or driver circuit components may include, but are not limited to, semiconductor materials or thin-film transistors.

As shown in Figure 2, semiconductor package device 10 includes a chip area 10a and a package area 10b. Chip area 10a and package area 10b are adjacent to each other, or located within package area 10b, or surrounding chip area 10a. Chip area 10a can be defined by edge 12e of chip 12, while package area 10b can be defined by edge 16e of protective layer 16. The following Figures 3-5 illustrate the detailed structure of the redistribution layer 14 within the first area 24 and second area 26 shown in Figure 2, respectively. For example, they illustrate the arrangement and dimensional relationship between signal traces and protective structures within redistribution layer 14.

Referring to FIG. 3 , according to one embodiment of the present disclosure, the detailed structure of the redistribution wiring layer 14 in a portion of the semiconductor package 10 is illustrated. FIG. 3 is a top view of a portion of the semiconductor package 10 (e.g., the first region 24 in FIG. 2 ). Referring to FIG. 2 , the first region 24 spans between the chip 12 and the protective layer 16 . For example, the first region 24 spans the edge 12 e of the chip 12 .

The disclosed redistribution layer 14 may include a plurality of first metal lines 28 (which may serve as protective structures) and a plurality of second metal lines 30 (which may serve as signal traces). Referring to FIG. 3 , an example is provided of a single second metal line 30 and two first metal lines 28 located on either side of the second metal line 30. The number of first metal lines 28 and second metal lines 30 in the redistribution layer 14 can be adjusted based on product requirements, so that a second metal line 30 is placed between two first metal lines 28. In Figure 3 , second metal line 30 is disposed between two adjacent first metal lines 28, and second metal line 30 and the two adjacent first metal lines 28 span between chip 12 and protective layer 16. In other words, second metal line 30 and the two adjacent first metal lines 28 extend beneath protective layer 16, passing through edge 12e of chip 12. Alternatively, chip 12 overlaps a portion of first metal line 28, while protective layer 16 overlaps another portion of first metal line 28, and one portion of first metal line 28 is connected to another portion of first metal line 28. In some embodiments, second metal line 30 in redistribution layer 14 is electrically connected to chip 12.

In some embodiments, the angle between the second metal wire 30 and two adjacent first metal wires 28 is approximately greater than or equal to 0 degrees and approximately less than or equal to 10 degrees. That is, the second metal wire 30 is substantially parallel to the two adjacent first metal wires 28. The first width W1 of one of the two adjacent first metal wires 28 is greater than the second width W2 of the second metal wire 30. In some embodiments, the first width W1 of the first metal wire 28 is approximately greater than or equal to twice the second width W2 of the second metal wire 30. In some embodiments, the first width W1 of the first metal wire 28 is approximately greater than or equal to twice the second width W2 of the second metal wire 30 and approximately less than or equal to three times the second width W2 of the second metal wire 30. The above design can protect or prevent excessive structural stress on the first metal line 28 from affecting the metal line 30 and, in turn, impacting electrical properties or signal quality, but is not limited thereto. In some embodiments, the spacing S between the second metal line 30 and two adjacent first metal lines 28 is approximately less than or equal to twice the second width W2 of the second metal line 30. In some embodiments, the spacing S between the second metal line 30 and two adjacent first metal lines 28 is approximately less than or equal to twice the second width W2 of the second metal line 30 and approximately greater than or equal to three times the second width W2 of the second metal line 30. The above design provides a buffer spacing of at least twice the length of the width of the metal wire 30 and metal wire 28 to prevent structural interference, or to prevent excessive buffer spacing from rendering the metal wire 28 ineffective. In some embodiments, the length L of one of two adjacent first metal wires 28 is approximately greater than or equal to 16 times the second width W2 of the second metal wire 30 (e.g., 16*W2≤L). In some embodiments, the length L of one of two adjacent first metal wires 28 is approximately greater than or equal to 16 times the second width W2 of the second metal wire 30 and less than or equal to 20 times the second width W2 of the second metal wire 30. The above design ensures that metal wire 28 provides protection across chip 12 and protective layer 16, and prevents excessive metal wire 28 from affecting structural stress, wasting space, or generating parasitic capacitance that affects electrical quality. In some embodiments, the aforementioned widths can be measured using, for example, an optical microscope (OM), a scanning electron microscope (SEM), or other suitable measurement methods, with the measurement direction being perpendicular to the extension direction of the metal wire.

In some embodiments, the two adjacent first metal wires 28 may be ground traces. In some embodiments, the two adjacent first metal wires 28 may be dummy structures, for example, metal structures that are not electrically connected to other devices or components. In some embodiments, the second metal wire 30 and the two adjacent first metal wires 28 may be located in the same layer in the redistribution wiring layer 14. In some embodiments, the second metal wire 30 and the two adjacent first metal wires 28 may be formed in the same process step. According to some embodiments of the present disclosure, the redistribution wiring layer 14 may be formed, for example, by electroplating, lithography, etching, physical vapor deposition (PVD), chemical vapor deposition (CVD), a combination thereof, or other suitable manufacturing methods, but is not limited thereto.

Please refer to FIG. 4 , which illustrates the detailed structure of the redistribution wiring layer 14 in a portion of the semiconductor package 10 according to one embodiment of the present disclosure. FIG. 4 is a top view of a portion of the semiconductor package 10 (e.g., the first region 24 in FIG. 2 ).

Here (Figure 4) illustrates a single second metal line 30 and two first metal lines 28 located on either side of the second metal line 30. The primary difference between the embodiment disclosed in Figure 4 and the embodiment disclosed in Figure 3 lies in the structure of the first metal line 28. Other portions similar to those in Figure 3 are not further described here. In Figure 4, one of the two adjacent first metal lines 28 has a first portion 28a and a second portion 28b. The second portion 28b is connected to the first portion 28a. The first portion 28a overlaps the chip 12, while the second portion 28b overlaps the protective layer 16. The first portion 28a and the second portion 28b have different widths. In some embodiments, the width W12 of the second portion 28b is greater than the width W11 of the first portion 28a. The above design can reduce or mitigate the risk of delamination or cracking of signal traces on the redistribution layer (RDL) due to the greater stress in the heterogeneous interface area, thereby improving reliability, but this is not the only solution.

In some embodiments, the angle between the second metal wire 30 and the two adjacent first metal wires 28 is approximately greater than or equal to 0 degrees and approximately less than or equal to 10 degrees. That is, the second metal wire 30 is substantially parallel to the two adjacent first metal wires 28. The width W12 of the second portion 28b of one of the two adjacent first metal wires 28 is greater than the second width W2 of the second metal wire 30. In some embodiments, the width W12 of the second portion 28b of the first metal wire 28 is approximately greater than or equal to twice the second width W2 of the second metal wire 30. In some embodiments, the width W12 of the second portion 28b of the first metal wire 28 is approximately greater than or equal to twice the second width W2 of the second metal wire 30 and approximately less than or equal to three times the second width W2 of the second metal wire 30. The above design can protect or prevent excessive structural stress on the first metal line 28 from affecting the metal line 30 and, in turn, impacting electrical properties or signal quality, but is not limited thereto. In some embodiments, the spacing S between the second metal line 30 and the second portions 28b of two adjacent first metal lines 28 is approximately less than or equal to twice the second width W2 of the second metal line 30. In some embodiments, the spacing S between the second metal line 30 and the second portions 28b of two adjacent first metal lines 28 is approximately less than or equal to twice the second width W2 of the second metal line 30 and approximately greater than or equal to four times the second width W2 of the second metal line 30. The above design provides a buffer distance of at least twice the length of the metal wire 30 to prevent interference between the metal wires 30 and 28 structures, or to prevent excessive buffer distances from rendering the metal wires 28 ineffective. In some embodiments, the length L of one of two adjacent first metal wires 28 is approximately greater than or equal to 16 times the second width W2 of the second metal wire 30. In some embodiments, the length L of one of two adjacent first metal wires 28 is approximately greater than or equal to 16 times the second width W2 of the second metal wire 30 and approximately less than or equal to 20 times the second width W2 of the second metal wire 30.

Referring to FIG. 5 , according to one embodiment of the present disclosure, the detailed structure of the redistribution layer 14 in a portion of the semiconductor package 10 is illustrated. FIG. 5 is a top view of a portion of the semiconductor package 10 (e.g., the second region 26 in FIG. 2 ). Referring to FIG. 2 , the second region 26 spans between the chip 12 and the protective layer 16 . For example, the second region 26 spans the corner 12 c of the chip 12 .

Here ( FIG. 5 ) illustrates two first metal wires 28 and a plurality of second metal wires 30 located between the two first metal wires 28. In FIG. 5 , the plurality of second metal wires 30 are disposed between two adjacent first metal wires 28, and the plurality of second metal wires 30 and the two adjacent first metal wires 28 span between the chip 12 and the protective layer 16. For example, the plurality of second metal wires 30 and the two adjacent first metal wires 28 extend through the corner 12 c of the chip 12 toward the bottom of the protective layer 16. Furthermore, the plurality of second metal wires 30 and the two adjacent first metal wires 28 extending below the protective layer 16 do not overlap the bumps 20. That is, the plurality of second metal lines 30 extending below the protective layer 16 and the two adjacent first metal lines 28 avoid the edge 20e of the bump 20. In addition, the edge 12e of the chip 12 does not overlap the bump 20. In some embodiments, the second metal lines 30 in the redistribution layer 14 are electrically connected to the chip 12.

Stress analysis reveals that the structural stresses generated in the second region 26 of the semiconductor package 10 shown in FIG5 include, for example, tensile stress f1 generated along the edge 12e of the chip 12 and tensile stress f2 generated at the corner 12c of the chip 12 due to the mutual tension between the stresses. Simulation analysis reveals that, from the end point c' (e.g., adjacent to the corner c of the chip 12), extending along the edge 12e of the chip 12 in directions x and y, respectively, a distance of 1/25 of the chip length to, for example, the end points g and h, respectively. The direction of extension connecting the two end points g and h corresponds approximately to the location where tensile stress f2 is generated (i.e., approximately at a 45-degree angle with the edge 12e of the chip 12), as shown in FIG5 . At this point, if the first metal wire 28 is positioned perpendicular to the direction of extension of the tensile stress f2, it can effectively prevent the tensile stress f2 from damaging the second metal wire 30. In Figure 5, the two adjacent first metal wires 28 positioned outside the second metal wire 30 as a protective structure form a protective area P. The protective area P is defined by the area enclosed by the extension distance DS of the tensile stress f2 and the length L of the first metal wire 28.

In some embodiments, the second metal wire 30 includes a first portion 30a and a second portion 30b, with the second portion 30b connected to the first portion 30a. The first portion 30a extends along a first direction d1, and the second portion 30b extends along a second direction d2 or a third direction d3, where the first direction d1 is different from the second direction d2 and the third direction d3. As shown in FIG5 , the second portion 30b of the second metal wire 30 extends in a direction different from the first direction d1 (e.g., the second direction d2 or the third direction d3) to avoid the edge 20e of the bump 20 and does not overlap with the bump 20. In some embodiments, the angle between the first portion 30a of the second metal wire 30 and two adjacent first metal wires 28 is approximately greater than or equal to 0 degrees and approximately less than or equal to 10 degrees. In other words, the first portion 30a of the second metal wire 30 is substantially parallel to the two adjacent first metal wires 28. The first width W1 of one of the two adjacent first metal wires 28 is greater than the second width W2 of the second metal wire 30. In some embodiments, the first width W1 of the first metal wire 28 is approximately greater than or equal to twice the second width W2 of the second metal wire 30. In some embodiments, the first width W1 of the first metal wire 28 is approximately greater than or equal to twice the second width W2 of the second metal wire 30 and approximately less than or equal to three times the second width W2 of the second metal wire 30. In some embodiments, the spacing S between the first portion 30a of the second metal wire 30 and the two adjacent first metal wires 28 is approximately less than or equal to twice the second width W2 of the second metal wire 30. In some embodiments, a distance S between the first portion 30a of the second metal wire 30 and two adjacent first metal wires 28 is approximately less than or equal to twice the second width W2 of the second metal wire 30 and approximately greater than or equal to four times the second width W2 of the second metal wire 30. In some embodiments, a length L of one of the two adjacent first metal wires 28 is approximately greater than or equal to 16 times the second width W2 of the second metal wire 30. In some embodiments, a length L of one of the two adjacent first metal wires 28 is approximately greater than or equal to 16 times the second width W2 of the second metal wire 30 and approximately less than or equal to 20 times the second width W2 of the second metal wire 30. Since the stress generated at the corner 12c of the chip 12 is greater than the stress generated at the edge 12e, the first width W1 of the first metal line 28 arranged across the corner 12c in FIG. 5 may be greater than or equal to the first width W1 of the first metal line 28 arranged across the edge 12e in FIG. 3.

In some embodiments, the two adjacent first metal lines 28 may be ground traces. In some embodiments, the two adjacent first metal lines 28 may be dummy structures, e.g., metal structures not electrically connected to other devices or components. In some embodiments, the second metal line 30 and the two adjacent first metal lines 28 are located on the same layer within the redistribution layer 14. In some embodiments, the second metal line 30 and the two adjacent first metal lines 28 may be formed in the same process step.

Please refer to FIG6, which illustrates the detailed structure of the redistribution wiring layer 14 in a portion of the semiconductor package device 10 according to one embodiment of the present disclosure. FIG6 is a top view of a portion of the semiconductor package device 10 (such as the first region 24 in FIG2).

Here ( FIG. 6 ), two sets (e.g., first set 32 and second set 34 ) of second metal lines 30 (signal traces) and first metal lines 28 (protective structures) are used as an example for illustration. Each set includes a single second metal line 30 and two first metal lines 28 located on either side of the second metal line 30. The second metal line 30 is disposed between two adjacent first metal lines 28, and the second metal line 30 and the two adjacent first metal lines 28 span between the chip 12 and the protective layer 16. In other words, the second metal line 30 and the two adjacent first metal lines 28 extend through the edge 12 e of the chip 12 and toward the bottom of the protective layer 16. On the other hand, the second metal line 30 extending below the protective layer 16 connects the endpoints of two adjacent first metal lines 28 to the bonding pad 18. That is, the bonding pad 18 is arranged corresponding to the endpoints of the first metal line 28 and the second metal line 30. In some embodiments, the second metal line 30 in the redistribution layer 14 is electrically connected to the chip 12.

In some embodiments, the distance D1 between two adjacent bonding pads 18 is approximately greater than or equal to four times the first width W1 of the first metal wire 28 and less than or equal to eight times the first width W1 of the first metal wire 28. This design provides ample protective space to secure the metal wire 30b, while being less than or equal to eight times the first width W1 of the first metal wire 28. This prevents excessive space from effectively protecting the metal wire 30b, but is not limited to this. In FIG. 6 , the first metal wire 28 includes a first portion 28a and a second portion 28b, with the second portion 28b connected to the first portion 28a. The second metal wire 30 includes a first portion 30a and a second portion 30b, with the second portion 30b connected to the first portion 30a. Taking the first group 32 as an example, the angle between the second portion 30b of the second metal wire 30 and the second portions 28b of the two adjacent first metal wires 28 is approximately greater than or equal to 0 degrees and approximately less than or equal to 10 degrees. In other words, the second portion 30b of the second metal wire 30 is substantially parallel to the second portions 28b of the two adjacent first metal wires 28. Taking the second group 34 as an example, the angle between the first portion 30a of the second metal wire 30 and the first portions 28a of the two adjacent first metal wires 28 is approximately greater than or equal to 0 degrees and approximately less than or equal to 10 degrees. In other words, the first portion 30a of the second metal wire 30 is substantially parallel to the first portions 28a of the two adjacent first metal wires 28. It can be seen that when describing that the second metal wire 30 and two adjacent first metal wires 28 are substantially parallel (for example, the angle between the two is approximately greater than or equal to 0 degrees and approximately less than or equal to 10 degrees), the comparison is made with the line segments of the second metal wire 30 and the two adjacent first metal wires 28 extending in the same direction.

In addition to being applicable to semiconductor packaging devices, the disclosed technology can also be applied to other electronic devices, such as display devices, light-emitting devices, solar cells, sensor devices, automotive electronic devices, or antennas.

To address the problem of signal traces in redistribution layers (RDLs) experiencing significant stress at heterogeneous interface regions, which can lead to delamination or cracking, this disclosure addresses the circuit design by adding special trace structures (e.g., ground traces or dummy structures) on both sides of the signal traces in the RDLs of semiconductor packages to protect them. This approach improves stress matching, enhances the overall RDL trace structure strength, reduces delamination or cracking, and ultimately improves the reliability of semiconductor packages.

The components of some of the above-mentioned embodiments are provided so that those skilled in the art can better understand the perspectives of the embodiments of the present disclosure. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and/or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and replacements without violating the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope of the attached patent application. In addition, although the present disclosure has been disclosed above with several embodiments, they are not intended to limit the present disclosure.

Reference throughout this specification to features, advantages, or similar language does not imply that all features and advantages that may be achieved with the present disclosure should or may be achieved in any single embodiment of the present disclosure. Rather, language referring to features and advantages is to be understood as meaning that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, discussion of features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same embodiment.

Furthermore, the described features, advantages, and characteristics of the present disclosure may be combined in any suitable manner in one or more embodiments. Based on the description herein, one skilled in the relevant art will recognize that the present disclosure may be practiced without one or more of the specific features or advantages of a particular embodiment. In other cases, additional features and advantages may be identified in some embodiments that may not be present in all embodiments of the present disclosure.

10: Semiconductor package device 10a: Chip area 10b: Package area 12: Chip 12c: Chip corner 12e: Chip edge 12s: Chip side 14: Redistribution layer 16: Protective layer 16e: Edge of protective layer 18: Bonding pad 20: Bump 20e: Bump edge 22: Electronic component 24: First region 26: Second region 28: First metal wire 28a: First portion of first metal wire 28b: Second portion of first metal wire 30: Second metal wire 30a: First portion of second metal wire 30b: Second portion of second metal wire 32: First group 34: Second group c: Chip corner c': End point d1: First direction d2: Second direction d3: Third direction D: Chip width D1: Bond pad spacing DS: Tensile stress extension distance f1, f2: Tensile stress g, h: Point L: Length of first metal wire M: Width of package area P: Protective area S: Spacing between first and second metal wires W1: First width of first metal wire W2: Second width of second metal wire W11: Width of first portion of first metal wire W12: Width of second portion of first metal wire x, y: Direction

The following describes the disclosed embodiments in detail with reference to the accompanying drawings. It should be noted that the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the components may be enlarged or reduced to clearly illustrate the technical features of the disclosed embodiments. FIG1 is a schematic cross-sectional view of a semiconductor package device according to an embodiment of the present disclosure; FIG2 is a top view of a semiconductor package device according to an embodiment of the present disclosure; FIG3 is a top view of a portion of a semiconductor package device according to an embodiment of the present disclosure; FIG4 is a top view of a portion of a semiconductor package device according to an embodiment of the present disclosure; FIG5 is a top view of a portion of a semiconductor package device according to an embodiment of the present disclosure; and FIG6 is a top view of a portion of a semiconductor package device according to an embodiment of the present disclosure.

12: Chip

12e: Edge of the chip

14: Re-routing Layers

16: Protective layer

24: District 1

28: First Metal Wire

30: Second metal wire

L: Length of the first metal wire

S: The distance between the first metal wire and the second metal wire

W1: The first width of the first metal wire

W2: The second width of the second metal wire

Claims (8)

A semiconductor package device comprises: a chip; a redistribution layer disposed on the chip and electrically connected to the chip, the redistribution layer comprising a plurality of first metal wires and a plurality of second metal wires; and a protective layer surrounding the chip. In a top view, two adjacent first metal wires and at least one second metal wire cross the chip and the protective layer, such that the two adjacent first metal wires and the at least one second metal wire cross a heterogeneous region defined between the chip and the protective layer. The at least one second metal wire is disposed between the two adjacent first metal wires. An angle between the at least one second metal wire and the two adjacent first metal wires is greater than or equal to 0 degrees and less than or equal to 10 degrees. A first width of one of the two adjacent first metal wires is greater than a second width of the at least one second metal wire. The two adjacent first metal wires comprise ground traces or dummy structures. The semiconductor package device of claim 1, wherein the plurality of first metal wires are ground traces. The semiconductor package device of claim 1, wherein the first width is greater than or equal to twice the second width. The semiconductor package device of claim 1, wherein the at least one of the plurality of second metal wires is electrically connected to the chip. A semiconductor package device as claimed in claim 1, wherein one of the two adjacent first metal wires has a first portion and a second portion, the second portion is connected to the first portion, the first portion overlaps the chip, and the first portion and the second portion have different widths. The semiconductor package device of claim 1, wherein the protective layer contacts at least two sides of the chip. The semiconductor package device of claim 1 further includes a plurality of bonding pads arranged corresponding to the end points of the plurality of first metal wires and the plurality of second metal wires, and the distance between two adjacent plurality of bonding pads is greater than or equal to 4 times the first width and less than or equal to 8 times the first width. The semiconductor package device of claim 1, wherein a distance between at least one of the plurality of second metal wires and two adjacent plurality of first metal wires is less than or equal to twice the second width.