TWI757667B - Boost converter - Google Patents

Abstract

A boost converter includes an inductor, a compensation capacitor, a first switch element, a second switch element, a third switch element, a controller, and an output stage circuit. A first parasitic capacitor is built in the first switch element. The first switch element selectively couples the inductor to a first common node according to a clock voltage. The compensation capacitor is coupled to the first parasitic capacitor. A second parasitic capacitor is built in the second switch element. The second switch element selectively couples the compensation capacitor to the first common node according to a control voltage. A third parasitic capacitor is built in the third switch element. The third switch element selectively couples the compensation capacitor to the output stage circuit according to the control voltage. The controller generates the control voltage according to an output voltage of the output stage circuit.

Description

boost converter

The present invention relates to a boost converter, especially a boost converter with high output efficiency.

In conventional boost converters, the boost inductors tend to resonate with the parasitic capacitors of the power switch and generate reverse inductor currents. Such reversed inductor current will cause power dissipation in the form of thermal energy (hereinafter referred to as "heat dissipation"), and at the same time will result in lower output efficiency of the boost converter. In view of this, it is necessary to propose a new solution to overcome the difficulties faced by the previous technology.

In a preferred embodiment, the present invention provides a boost converter, comprising: an inductor for receiving an input potential; a first switch with a built-in first parasitic capacitor, wherein the first switch is selectively coupling the inductor to a first common node according to a clock potential; an output stage circuit for generating an output potential; a compensation capacitor coupled to the first parasitic capacitor; a second switching a second switch with a built-in second parasitic capacitor, wherein the second switch selectively couples the compensation capacitor to the first common node according to a control potential; a third switch with a built-in third parasitic a capacitor, wherein the third switch selectively couples the compensation capacitor to the output stage circuit according to the control potential; and a controller generates the control potential according to the output potential.

In order to make the objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are given in the following, and are described in detail as follows in conjunction with the accompanying drawings.

Certain terms are used throughout the specification and claims to refer to particular elements. It should be understood by those skilled in the art that hardware manufacturers may refer to the same element by different nouns. This specification and the scope of the patent application do not use the difference in name as a way to distinguish elements, but use the difference in function of the elements as a criterion for distinguishing. The words "including" and "including" mentioned in the entire specification and the scope of the patent application are open-ended terms, so they should be interpreted as "including but not limited to". The word "substantially" means that within an acceptable error range, those skilled in the art can solve the technical problem within a certain error range and achieve the basic technical effect. Furthermore, the term "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is described as being coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connecting means. Second device.

FIG. 1 shows a schematic diagram of a boost converter 100 according to an embodiment of the present invention. The boost converter 100 can be applied to a mobile device, such as a desktop computer, a notebook computer, or an all-in-one computer. As shown in FIG. 1, the boost converter 100 includes: an inductor L1, a compensation capacitor CM, a first switch 110, a second switch 120, a third switch 130, a controller 140, and an output stage circuit 150, wherein the first switch 110 builds a first parasitic capacitor CP1, the second switch 120 builds a second parasitic capacitor CP2, and the third switch 130 builds a third parasitic capacitor CP3 . It should be noted that, although not shown in FIG. 1, the boost converter 100 may further include other components, such as a voltage regulator or/and a negative feedback circuit.

The inductor L1 can be considered as one of the boost inductors of the boost converter 100 . The inductor L1 is used to receive an input potential VIN. The input potential VIN can come from an external power source, wherein the input potential VIN can be an alternating current potential with an arbitrary frequency and an arbitrary amplitude. For example, the frequency of the AC potential may be about 50 Hz or 60 Hz, and the rms value of the AC potential may be about 110V or 220V. In other embodiments, the input potential VIN can also be changed to a DC potential, and its potential level can be between 90V and 264V. The first switch 110 can be regarded as one of the power switches of the boost converter 100 . The first switch 110 can selectively couple the inductor L1 to a first common node NC1 according to a clock potential VA. For example, if the clock potential VA is at a high logic level (eg, logic "1"), the first switch 110 couples the inductor L1 to the first common node NC1 (ie, the first switch 110 can be approximately On the other hand, if the clock potential VA is at a low logic level (eg, logic “0”), the first switch 110 will not couple the inductor L1 to the first common node NC1 (ie, a logic “0”). , the first switch 110 may approximate an open path). The total parasitic capacitance between the two terminals of the first switch 110 can be modeled as the aforementioned first parasitic capacitor CP1, which is not an external independent component. The clock potential VA can be maintained at a fixed potential when the boost converter 100 is initialized, and can provide a periodic clock waveform after the boost converter 100 enters a normal use stage. The compensation capacitor CM is coupled to the first switch 110 and its first parasitic capacitor CP1. The second switch 120 can selectively couple the compensation capacitor CM to the first common node NC1 according to a control potential VC. For example, if the control potential VC is at a high logic level, the second switch 120 couples the compensation capacitor CM to the first common node NC1 (ie, the second switch 120 can approximate a short-circuit path); otherwise, if When the control potential VC is at a low logic level, the second switch 120 does not couple the compensation capacitor CM to the first common node NC1 (ie, the second switch 120 can approximate an open path). The total parasitic capacitance between the two terminals of the second switch 120 can be modeled as the aforementioned second parasitic capacitor CP2, which is not an external independent component. The third switch 130 may selectively couple the compensation capacitor CM to the output stage circuit 150 according to the control potential VC. For example, if the control potential VC is at a high logic level, the third switch 130 couples the compensation capacitor CM to the output stage circuit 150 (ie, the third switch 130 can approximate a short-circuit path); otherwise, if the control When the potential VC is at a low logic level, the third switch 130 does not couple the compensation capacitor CM to the output stage circuit 150 (ie, the third switch 130 can approximate an open path). The total parasitic capacitance between the two terminals of the third switch 130 can be modeled as the aforementioned third parasitic capacitor CP3, which is not an external independent component. The output stage circuit 150 is used to generate an output potential VOUT. The output potential VOUT can be a DC potential, wherein the potential level of the output potential VOUT is higher than the maximum value of the input potential VIN. The controller 140 generates the control potential VC according to the output potential VOUT. It must be noted that when the inductor current IL through one of the inductors L1 just drops to zero, the first parasitic capacitor CP1 can be coupled to the second parasitic capacitor CP2 and the third parasitic capacitor CP3 via the compensation capacitor CM to reduce the boost voltage The total equivalent capacitance value of the converter 100 . According to the actual measurement results, this circuit design can prevent the inductor L1 of the boost converter 100 from generating heat consumption due to the non-ideal reverse current, so that the output efficiency of the boost converter 100 can be improved.

The following embodiments will introduce the detailed structure and operation of the boost converter 100 . It must be understood that these drawings and descriptions are only examples and are not intended to limit the scope of the present invention.

FIG. 2 shows a schematic diagram of a boost converter 200 according to an embodiment of the present invention. In the embodiment of FIG. 2, the boost converter 200 has an input node NIN and an output node NOUT, and includes an inductor L1, a compensation capacitor CM, a first switch 210, and a second switch 220 , a third switch 230, a controller 240, and an output stage circuit 250, wherein the first switch 210 has a built-in first parasitic capacitor CP1, the second switch 220 has a built-in second parasitic capacitor CP2, and The third switch 230 has a built-in third parasitic capacitor CP3. The input node NIN of the boost converter 200 can receive an input potential VIN from an external power source, and the output node NOUT of the boost converter 200 can be used to output an output potential VOUT, wherein the potential level of the output potential VOUT is higher than the input potential The maximum value of the potential VIN.

The first end of the inductor L1 is coupled to the input node NIN, and the second end of the inductor L1 is coupled to a first node N1.

The first switch 210 includes a first transistor M1. The first transistor M1 may be an N-type MOSFET. The control terminal of the first transistor M1 is used for receiving a clock potential VA, the first terminal of the first transistor M1 is coupled to a first common node NC1, and the second terminal of the first transistor M1 is coupled to to the first node N1. For example, the clock potential VA can be maintained at a fixed potential (eg, a ground potential of 0V) when the boost converter 200 is initialized, and a periodic clock waveform can be provided after the boost converter 200 enters a normal use stage . The total parasitic capacitance between the first terminal and the second terminal of the first transistor M1 can be modeled as the aforementioned first parasitic capacitor CP1, which is not an external independent component. The first terminal of the first parasitic capacitor CP1 is coupled to the first node N1, and the second terminal of the first parasitic capacitor CP1 is coupled to the first common node NC1.

The first end of the compensation capacitor CM is coupled to the first common node NC1, and the second end of the compensation capacitor CM is coupled to a second node N2. In some embodiments, the first common node NC1 is further coupled to the ground, but it is not limited thereto.

The second switch 220 includes a second transistor M2. The second transistor M2 can be an N-type MOSFET. The control terminal of the second transistor M2 is coupled to a third node N3 to receive a control potential VC, the first terminal of the second transistor M2 is coupled to the first common node NC1, and the second transistor M2 The second end is coupled to the second node N2. The total parasitic capacitance between the first terminal and the second terminal of the second transistor M2 can be modeled as the aforementioned second parasitic capacitor CP2, which is not an external independent component. The first terminal of the second parasitic capacitor CP2 is coupled to the second node N2, and the second terminal of the second parasitic capacitor CP2 is coupled to the first common node NC1.

The output stage circuit 250 includes a diode D1 and an output capacitor CO. The anode of the diode D1 is coupled to the first node N1, and the cathode of the diode D1 is coupled to the output node NOUT. The first end of the output capacitor CO is coupled to the output node NOUT, and the second end of the output capacitor CO is coupled to a second common node NC2. In some embodiments, the second common node NC2 is further coupled to the ground potential, but not limited thereto.

The third switch 230 includes a third transistor M3. The third transistor M3 can be an N-type MOSFET. The control terminal of the third transistor M3 is coupled to the third node N3 to receive the control potential VC, the first terminal of the third transistor M3 is coupled to the second node N2, and the second terminal of the third transistor M3 is coupled to the output node NOUT. The total parasitic capacitance between the first terminal and the second terminal of the third transistor M3 can be modeled as the aforementioned third parasitic capacitor CP3, which is not an external independent component. The first terminal of the third parasitic capacitor CP3 is coupled to the second node N2, and the second terminal of the third parasitic capacitor CP3 is coupled to the output node NOUT.

The controller 240 includes a voltage dividing circuit 241, a comparator 242, and a sensing resistor RS. The voltage dividing circuit 241 includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is coupled to the output node NOUT, and the second end of the first resistor R1 is coupled to a fourth node N4. The first end of the second resistor R2 is coupled to the fourth node N4, and the second end of the second resistor R2 is coupled to the second common node NC2. The voltage dividing circuit 241 can provide a reference potential VR at the fourth node N4. The first end of the sensing resistor RS is coupled to the first common node NC1, and the second end of the sensing resistor RS is coupled to the second common node NC2. The sense resistor RS can provide a sense potential VS at the second common node NC2. The positive input terminal of the comparator 242 is coupled to the fourth node N4 to receive the reference potential VR, the negative input terminal of the comparator 242 is coupled to the second common node NC2 to receive the sensing potential VS, and the output of the comparator 242 The terminal is coupled to the third node N3 to output the control potential VC.

In some embodiments, the boost converter 200 operates in a first mode, a second mode, a third mode, and a fourth mode in sequence, and the detailed operation principle can be described below.

In the first mode, the boost converter 200 is in an initialization state, and at this time, the first transistor M1, the second transistor M2, and the third transistor M3 are all disabled.

In the second mode, the clock potential VA is at a high logic level, so the first transistor M1 is enabled and the diode D1 is disabled, and an inductor current IL through the inductor L1 increases gradually. Since the diode D1 is disabled, the sense resistor RS will not pass any current, and the inactive controller 240 will disable both the second transistor M2 and the third transistor M3.

In the third mode, the clock potential VA is at a low logic level, so the first transistor M1 is disabled and the diode D1 is enabled, and the inductor current IL through the inductor L1 decreases gradually. The inductor current IL then flows to the sensing resistor RS through the diode D1, so that the sensing resistor RS can generate the sensing potential VS. In addition, the output potential VOUT of the output capacitor CO is divided by the first resistor R1 and the second resistor R2, so that the voltage dividing circuit 241 can generate the reference potential VR. Since the sensing potential VS is higher than the reference potential VR in the third mode, the controller 240 outputs the control potential VC of a low logic level to disable the second transistor M2 and the third transistor M3.

In the fourth mode, the inductor current IL through the inductor L1 just drops to zero, so that the sensing potential VS of the sensing resistor RS also drops to zero. Since the sensing potential VS is lower than the reference potential VR in the fourth mode, the controller 240 outputs the control potential VC of a high logic level to enable the second transistor M2 and the third transistor M3. FIG. 3 shows an equivalent circuit diagram of the boost converter 200 (operating in the fourth mode) according to an embodiment of the present invention. The total equivalent capacitance of the first parasitic capacitor CP1, the second parasitic capacitor CP2, the third parasitic capacitor CP3, the compensation capacitor CM, and the output capacitor CO can be expressed as the following equation (1):

…………………………….(1) 其中「CT」代表總等效電容值，「CP1」代表第一寄生電容器CP1之電容值，「CP2」代表第二寄生電容器CP2之電容值，「CP3」代表第三寄生電容器CP3之電容值，「CM」代表補償電容器CM之電容值，而CO代表輸出電容器CO之電容值。

………………………….(1) “CT” represents the total equivalent capacitance value, “CP1” represents the capacitance value of the first parasitic capacitor CP1, and “CP2” represents the capacitance of the second parasitic capacitor CP2 "CP3" represents the capacitance value of the third parasitic capacitor CP3, "CM" represents the capacitance value of the compensation capacitor CM, and CO represents the capacitance value of the output capacitor CO.

According to FIG. 3 and equation (1), when the control potential VC enables the second transistor M2 and the third transistor M3 (ie, when the inductor current IL through the inductor L1 just drops to zero), the first The parasitic capacitor CP1 will be coupled to the second parasitic capacitor CP2, the third parasitic capacitor CP3, and the output capacitor CO via the compensation capacitor CM, such that the first parasitic capacitor CP1, the second parasitic capacitor CP2, the third parasitic capacitor CP3, the compensation capacitor CM , and the total equivalent capacitance value of the output capacitor CO approaches zero. Under this design, the first switch 110 can be regarded as having almost no parasitic capacitance, which can effectively avoid the non-ideal characteristics generated when the inductor L1 and the first parasitic capacitor CP1 resonate.

FIG. 4 is a waveform diagram showing the inductor current of a conventional boost converter. As shown in Figure 4, the inductor current of a conventional boost converter has some non-ideal inverse parts (as shown by the dotted box), which will cause unnecessary heat dissipation. FIG. 5 is a waveform diagram of the inductor current IL of the boost converter 200 according to an embodiment of the present invention. According to the measurement results shown in FIG. 5, after using the proposed compensation capacitor CM and the corresponding switch, the boost converter 200 of the present invention can generate a completely non-reverse inductor current IL, which can not only reduce heat consumption, but also Furthermore, the output efficiency of the boost converter 200 can be greatly improved.

In some embodiments, the component parameters of the boost converter 200 may be as follows. The capacitance value of the first parasitic capacitor CP1 may be between 297pF and 303pF, preferably 300pF. The capacitance value of the second parasitic capacitor CP2 may be between 297pF and 303pF, preferably 300pF. The capacitance value of the third parasitic capacitor CP3 may be between 297pF and 303pF, preferably 300pF. The capacitance value of the compensation capacitor CM may be between 9.9pF and 10.1pF, preferably 10pF. The capacitance value of the output capacitor CO may be between 2700 μF and 3300 μF, preferably 3000 μF. The inductance value of the inductor L1 can be between 190 μH and 210 μH, preferably 200 μH. The resistance value of the first resistor R1 may be approximately equal to 3999Ω. The resistance value of the second resistor R2 may be approximately equal to 1Ω. The resistance value of the detection resistor RS may be approximately equal to 1Ω. The reference potential VR may be approximately equal to 0.1V. The switching frequency of the clock potential VA may be about 65 kHz. The above parameter ranges are obtained according to multiple experimental results, which help to optimize the conversion efficiency of the boost converter 200 .

The present invention proposes a novel boost converter comprising a compensation capacitor and a corresponding switch. According to the actual measurement results, using the boost converter of the above design can greatly reduce the non-ideal reverse inductor current. Generally speaking, the present invention can effectively improve the output efficiency of the boost converter, so it is very suitable for application in various electronic devices.

It should be noted that the potential, current, resistance value, inductance value, capacitance value and other component parameters mentioned above are not limitations of the present invention. Designers can adjust these settings according to different needs. The boost converter of the present invention is not limited to the states illustrated in FIGS. 1-5. The present invention may include only any one or more of the features of any one or more of the embodiments of Figures 1-5. In other words, not all of the features shown must be simultaneously implemented in the boost converter of the present invention. Although the embodiments of the present invention use MOSFETs as an example, the present invention is not limited to this, and those skilled in the art can use other types of transistors, such as junction field effect transistors, or fins type field effect transistor, etc., without affecting the effect of the present invention.

The ordinal numbers in this specification and the scope of the patent application, such as "first", "second", "third", etc., do not have a sequential relationship with each other, and are only used to mark and distinguish two identical different elements of the name.

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

100, 200: Boost converter 110, 210: The first switch 120, 220: Second switch 130, 230: The third switch 140, 240: Controller 150, 250: output stage circuit 241: Voltage divider circuit 242: Comparator CM: Compensation capacitor CO: output capacitor CP1: first parasitic capacitor CP2: Second Parasitic Capacitor CP3: Third Parasitic Capacitor D1: Diode IL: inductor current L1: Inductor M1: first transistor M2: second transistor M3: The third transistor N1: the first node N2: second node N3: The third node N4: Fourth Node NC1: first common node NC2: Second Common Node NIN: input node NOUT: output node R1: first resistor R2: Second resistor RS: sense resistor VA: clock potential VC: control potential VIN: input potential VOUT: output potential VR: reference potential VS: sense potential

FIG. 1 shows a schematic diagram of a boost converter according to an embodiment of the present invention. FIG. 2 shows a schematic diagram of a boost converter according to an embodiment of the present invention. FIG. 3 shows an equivalent circuit diagram of a boost converter according to an embodiment of the present invention. FIG. 4 is a waveform diagram showing the inductor current of a conventional boost converter. FIG. 5 is a waveform diagram showing the inductor current of the boost converter according to an embodiment of the present invention.

100: Boost Converter

110: First switcher

120: Second switcher

130: Third Switcher

140: Controller

150: Output stage circuit

CM: Compensation capacitor

CP1: first parasitic capacitor

CP2: Second Parasitic Capacitor

CP3: Third Parasitic Capacitor

IL: inductor current

L1: Inductor

NC1: first common node

VA: clock potential

VC: control potential

VIN: input potential

VOUT: output potential

Claims (9)

A boost converter includes: an inductor for receiving an input potential; a first switch with a built-in first parasitic capacitor, wherein the first switch selectively switches the voltage according to a clock potential The inductor is coupled to a first common node; an output stage circuit is used to generate an output potential; a compensation capacitor is coupled to the first parasitic capacitor; a second switch has a built-in second parasitic capacitor, The second switch selectively couples the compensation capacitor to the first common node according to a control potential; a third switch has a built-in third parasitic capacitor, wherein the third switch is based on the control potential to selectively couple the compensation capacitor to the output stage circuit; and a controller to generate the control potential according to the output potential; wherein the inductor has a first end and a second end, the inductor The first end of the inductor is coupled to an input node to receive the input potential, and the second end of the inductor is coupled to a first node. The boost converter as described in claim 1, wherein the first switch comprises: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the first transistor The control terminal of the crystal is used for receiving the clock potential, the first terminal of the first transistor is coupled to the first common node, and the second terminal of the first transistor is coupled to the first node; wherein the first parasitic capacitor has a first terminal and a second terminal, the first terminal of the first parasitic capacitor is coupled to the first node, and the first parasitic capacitor The second end of the capacitor is coupled to the first common node. The boost converter of claim 2, wherein the compensation capacitor has a first terminal and a second terminal, the first terminal of the compensation capacitor is coupled to the first common node, and the The second end of the compensation capacitor is coupled to a second node. The boost converter of claim 3, wherein the second switch comprises: a second transistor having a control terminal, a first terminal, and a second terminal, wherein the second transistor The control terminal of the crystal is coupled to a third node to receive the control potential, the first terminal of the second transistor is coupled to the first common node, and the second terminal of the second transistor is coupled to the second node; wherein the second parasitic capacitor has a first terminal and a second terminal, the first terminal of the second parasitic capacitor is coupled to the second node, and the second parasitic capacitor The second end of the capacitor is coupled to the first common node. The boost converter of claim 4, wherein the output stage circuit comprises: a diode having an anode and a cathode, wherein the anode of the diode is coupled to the first node , and the cathode of the diode is coupled to an output node to output the output potential; and an output capacitor having a first terminal and a second terminal, wherein the first terminal of the output capacitor is coupled to the output node, and the second terminal of the output capacitor is coupled to a second common node . The boost converter as described in claim 5, wherein the third switch comprises: a third transistor having a control terminal, a first terminal, and a second terminal, wherein the third transistor The control terminal of the crystal is coupled to the third node to receive the control potential, the first terminal of the third transistor is coupled to the second node, and the second terminal of the third transistor is coupled to the output node; wherein the third parasitic capacitor has a first end and a second end, the first end of the third parasitic capacitor is coupled to the second node, and the third parasitic capacitor has The second terminal is coupled to the output node. The boost converter of claim 6, wherein the controller comprises a voltage divider circuit, and the voltage divider circuit comprises: a first resistor having a first terminal and a second terminal , wherein the first end of the first resistor is coupled to the output node, and the second end of the first resistor is coupled to a fourth node; and a second resistor has a first One end and a second end, wherein the first end of the second resistor is coupled to the fourth node, and the second end of the second resistor is coupled to the second common node. The boost converter as described in claim 7, wherein the controller further comprises: a comparator having a positive input terminal, a negative output terminal, and an output terminal, wherein the positive input terminal of the comparator is coupled to the fourth node, and the negative input terminal of the comparator is coupled to the second common node, and the output terminal of the comparator is coupled to the third node to output the control potential; and a sensing resistor having a first terminal and a second terminal, wherein the sensing The first end of the resistor is coupled to the first common node, and the second end of the sense resistor is coupled to the second common node. The boost converter of claim 6, wherein when the control potential enables the second transistor and the third transistor, the first parasitic capacitor is coupled to the first through the compensation capacitor Two parasitic capacitors, the third parasitic capacitor, and the output capacitor make the total equivalent capacitance value of the first parasitic capacitor, the second parasitic capacitor, the third parasitic capacitor, the compensation capacitor, and the output capacitor approximate at zero.

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