TW202201648A - 3d memory array device and method of manufacturing the same - Google Patents

Abstract

A memory array device includes a stack of transistors over a semiconductor substrate, a first transistor of the stack being disposed over a second transistor of the stack. The first transistor includes a first memory film along a first word line and a first channel region along a source line and a bit line, the first memory film being disposed between the first channel region and the first word line. The second transistor includes a second memory film along a second word line and a second channel region along the source line and the bit line, the second memory film being disposed between the second channel region and the second word line. The memory array device includes a first via electrically connected to the first word line and a second via electrically connected to the second word line, the second staircase via and the first staircase via having different widths.

Description

3D Memory Array Contact Structure

Semiconductor memory is used in integrated circuits for electronic applications including radios, televisions, cell phones, and personal computers, as examples. Semiconductor memory includes two main categories. One category is volatile memory; the other category is non-volatile memory. Volatile memory includes random access memory (RAM), which can be further divided into two subcategories: static random access memory (SRAM) and dynamic random access memory Access memory (dynamic random access memory; DRAM). Both SRAM and DRAM are volatile because they lose their stored information when not powered.

On the other hand, non-volatile memory can keep the data stored on it. One type of non-volatile semiconductor memory is ferroelectric random access memory (FeRAM or FRAM). The advantages of FeRAM include its faster write/read speed and smaller size.

The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first feature is formed in direct contact with the second feature, and may also include additional features that may be formed in Embodiments in which the first feature and the second feature are formed such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in various instances. This repetition is for the purpose of simplicity and clarity, and does not in itself prescribe the relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper" and the like may be used herein to describe The relationship of one element or feature to another element or feature(s) as shown in the figures. In addition to the orientation depicted in the figures, spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Various embodiments provide a 3D stacked memory array having a plurality of vertically stacked memory cells. Each memory cell includes a thin film transistor (TFT) having a wordline region serving as a gate electrode, a bitline region serving as a first source/drain electrode, and a second The source line region of the source/drain electrodes. Each TFT further includes an insulating memory film (eg, as a gate dielectric) and an oxide semiconductor (OS) channel region.

In some embodiments, the contact step structure is formed by a stack of conductive layers separated by a dielectric layer. The stepped structure provides word lines for the memory array, and vias are formed to extend downward and electrically connect to each of the conductive layers. The width of the vias can vary. For example, the width of the via may increase as the via is further spaced from the transistor region of the memory array. Etch loading effects (e.g., wider stepped via critical dimensions for deeper etch depths, and narrow stepped via critical dimensions for shallower etch depths) are used to prevent degradation due to step heights between upper and lower layers. The over-etching of the opening of the stepped via and the short-circuiting of the upper-layer word lines caused by the large difference. Material savings (eg, mask material), lower manufacturing costs, and simplified processing flow can be achieved for the production of 3D stacked memory array devices with reliable word line contact connectivity.

1A, 1B, and 1C illustrate examples of memory arrays in accordance with some embodiments. 1A shows an example of a portion of memory array 200 in three-dimensional view; FIG. 1B shows a circuit diagram of memory array 200; and FIG. 1C shows a top-down view of memory array 200 in accordance with some embodiments. The memory array 200 includes a plurality of memory cells 202 that can be arranged in a grid of columns and rows. The memory cells 202 can be further stacked vertically to provide a three-dimensional memory array, thereby increasing device density. The memory array 200 may be disposed in a back end of line (BEOL) semiconductor die. For example, a memory array may be disposed in an interconnect layer of a semiconductor die, such as over one or more active devices (eg, transistors) formed on a semiconductor substrate.

In some embodiments, the memory array 200 is a flash memory array, such as a NOR flash memory array or the like. Each memory cell 202 may include a thin film transistor (TFT) 204 having an insulating memory film 90 as the gate dielectric. In some embodiments, the gate of each TFT 204 is electrically coupled to a respective word line (eg, conductive line 72 ), and the first source/drain region of each TFT 204 is electrically coupled to a respective bit element lines (eg, conductive line 106 ), and the second source/drain region of each TFT 204 is electrically coupled to a respective source line (eg, conductive line 108 ) that connects the second source The pole/drain region is electrically coupled to ground. The memory cells 202 in the same vertical row of the memory array 200 may share a common bit line (BL) 116A and a common source line (SL) 116B, while in the same horizontal row of the memory array 200 The memory cells 202 in can share a common word line (WL) 116C.

The memory array 200 includes a plurality of vertically stacked conductive lines 72 (eg, word lines) with the dielectric layer 52 disposed between adjacent ones of the conductive lines 72 . The conductive lines 72 extend in a direction parallel to the major surface of the underlying substrate (not explicitly shown in FIGS. 1A and 1B ). The conductive lines 72 may have a stepped configuration such that the lower conductive lines 72 are longer than the end points of the upper conductive lines 72 and extend laterally beyond the end points of the upper conductive lines 72 . For example, in FIG. 1A , multiple stacked layers of conductive lines 72 are shown, with the topmost conductive line 72 being the shortest and the bottommost conductive line 72 the longest. The respective lengths of the conductive lines 72 may increase in the direction towards the underlying substrate. In this manner, a portion of each of the conductive lines 72 can be accessed from above the memory array 200 and conductive contacts can be formed for the exposed portions of each of the conductive lines 72 .

The memory array 200 further includes a plurality of conductive lines 106 (eg, common bit lines 116A) and conductive lines 108 (eg, common source lines 116B). Conductive line 106 and conductive line 108 may each extend in a direction perpendicular to conductive line 72 . Dielectric material 98 is disposed between conductive lines 106 and adjacent ones of conductive lines 108 and isolates the adjacent ones. In some embodiments, at least a portion of the dielectric material 98 is a low hydrogen material formed using a precursor that includes hydrogen introduced at a reduced flow rate. For example, at least a portion of dielectric material 98 (eg, dielectric material 98A) in physical contact with oxide semiconductor (OS) layer 92 (described below) may have a relatively low hydrogen concentration, such as less than 3 atomic percent (atomic percent) %). A low hydrogen concentration (eg, within the above ranges) can reduce hydrogen diffusion into OS layer 92, thereby reducing defects and improving device stability. For example, by reducing hydrogen diffusion with the dielectric material 98, the threshold voltage (V _th ) curve of the TFT 204 may be shifted in the positive bias direction, thereby enhancing the stability of the TFT 204, according to one embodiment. Relatively low hydrogen concentrations in dielectric material 98 can be achieved by, for example, reducing the flow rate of a precursor that includes hydrogen used to deposit dielectric material 98 . For example, in embodiments where the dielectric material 98 includes silicon oxide, silicon nitride, or the like, the dielectric material 98 may be deposited by a process with a relatively low _SiH precursor flow rate to suppress H ^o Or H ⁺ diffuses into dielectric material 98 and OS layer 92.

Pairs of conductive lines 106 and 108 together with intersecting conductive lines 72 define the boundaries of each memory cell 202, and dielectric material 102 is disposed between and isolates adjacent pairs of conductive lines 106 and 108. the adjacent pair. In some embodiments, conductive line 108 is electrically coupled to ground. Although FIG. 1A shows a particular placement of conductive lines 106 relative to conductive lines 108, it should be understood that the placement of conductive lines 106 and conductive lines 108 may be reversed in other embodiments.

As discussed above, the memory array 200 may also include an oxide semiconductor (OS) layer 92 . The OS layer 92 may provide a channel area for the TFTs 204 of the memory cells 202 . For example, regions of the OS layer 92 that intersect the conductive lines 72 may allow current flow (eg, above the respective threshold voltage (V _th ) of the corresponding TFT 204 ) when an appropriate voltage (eg, above the respective threshold voltage (V th ) of the corresponding TFT 204 ) is applied via the corresponding conductive lines 72 . , in the direction indicated by arrow 206 ) from conductive line 106 to conductive line 108 . OS layer 92 may have a relatively low hydrogen concentration, such as at about 10 ²⁰ atoms per cubic centimeter as measured by Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS) analysis to the range of about 10 ²² atoms. Therefore, the stability of the TFT 204 can be improved compared to a TFT having an OS layer with a higher hydrogen concentration.

Memory film 90 is disposed between conductive line 72 and OS layer 92 , and memory film 90 may provide a gate dielectric for TFT 204 . In some embodiments, the memory film 90 includes a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon doped hafnium oxide, or the like. Therefore, the memory array 200 may also be referred to as a ferroelectric random access memory (FERAM) array. Alternatively, the memory film 90 may be a multilayer structure including a _SiNx layer between two _SiOx layers (eg, ONO structure), different ferroelectric materials, different types of memory layers (eg, capable of storing bits) or similar.

In embodiments in which the memory film 90 includes a ferroelectric material, the memory film 90 can be polarized in one of two different directions, and can be obtained by applying an appropriate voltage differential across the memory film 90 and producing an appropriate electric field to change the polarization direction. Polarization may be relatively localized (eg, generally contained within each boundary of memory cell 202 ), and a continuous region of memory membrane 90 may extend across multiple memory cells 202 . Depending on the polarization direction of a particular region of the memory film 90, the threshold voltage of the corresponding TFT 204 varies, and a digital value (eg, 0 or 1) can be stored. For example, when the region of the memory film 90 has the first electrical polarization direction, the corresponding TFT 204 may have a relatively low threshold voltage, and when the region of the memory film 90 has the second electrical polarization direction, the corresponding TFT 204 Can have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as a threshold voltage shift. A larger threshold voltage shift makes reading the digital values stored in the corresponding memory cells 202 easier (eg, less error-prone).

To perform a write operation on the memory cells 202 in such embodiments, a write voltage is applied across the portion of the memory film 90 corresponding to the memory cells 202 . For example, the write voltage may be applied by applying appropriate voltages to corresponding conductive lines 72 (eg, word lines) and corresponding conductive lines 106/108 (eg, bit lines/source lines). By applying a write voltage across portions of the memory film 90, the direction of polarization of regions of the memory film 90 can be changed. Therefore, the corresponding threshold voltage of the corresponding TFT 204 can also be switched from a low threshold voltage to a high threshold voltage, or vice versa, and the digital value can be stored in the memory cell 202 . Since conductive line 72 intersects conductive line 106 and conductive line 108, individual memory cells 202 may be selected for write operations.

To perform a read operation on memory cells 202 in such embodiments, a read voltage (a voltage between a low threshold voltage and a high threshold voltage) is applied to corresponding conductive lines 72 (eg, word lines). Depending on the polarization direction of the corresponding region of the memory film 90, the TFTs 204 of the memory cells 202 may or may not be turned on. Thus, conductive line 106 may or may not be discharged through conductive line 108 (eg, a source line coupled to ground), and the digital value stored in memory cell 202 may be determined. Since conductive line 72 intersects conductive line 106 and conductive line 108, individual memory cells 202 may be selected for read operations.

FIG. 1A further shows a reference cross-section of memory array 200 used in subsequent figures. The cross section BB' is along the longitudinal axis of the conductive line 72, and in a direction parallel to the current flow direction of the TFT 204, for example. Cross-section CC' is perpendicular to cross-section BB' and parallel to the longitudinal axis of conductive line 72. Cross section CC' extends through conductive line 106 . Cross-section DD' is parallel to cross-section CC' and extends through dielectric material 102 . For the sake of clarity, subsequent figures refer to these reference cross-sections.

In Figure 2, a substrate 50 is provided. Substrate 50 may be a semiconductor substrate that may be doped (eg, with p-type or n-type dopants) or undoped, such as a bulk semiconductor, semiconductor-on-insulator (SOI) substrate or similar. The substrate 50 may be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on a substrate (typically a silicon substrate or a glass substrate). Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors, Contains silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide, and/or indium gallium arsenide phosphide; or a combination thereof.

FIG. 2 further illustrates circuits that may be formed over substrate 50 . The circuitry includes active devices (eg, transistors) at the top surface of substrate 50 . The transistor may include a gate dielectric layer 203 over the top surface of the substrate 50 and a gate electrode 205 over the gate dielectric layer 203 . Source/drain regions 207 are disposed in substrate 50 on opposite sides of gate dielectric layer 203 and gate electrode 205 . Gate spacers 208 are formed along the sidewalls of the gate dielectric layer 203 and separate the source/drain regions 207 from the gate electrode 205 by a suitable lateral distance. In some embodiments, the transistor may be a field effect transistor (FET), a fin field effect transistor (finFET), a nano-field effect transistor (nano-field effect transistor; nanoFET) or similar.

The first ILD 210 surrounds and isolates the source/drain regions 207 , the gate dielectric layer 203 and the gate electrode 205 , and the second ILD 212 is above the first ILD 210 . Source/drain contact 214 extends through second ILD 212 and first ILD 210 and is electrically coupled to source/drain region 207, and gate contact 216 extends through second ILD 212 and is electrically coupled to the gate electrode 205 . Over the second ILD 212, the source/drain contacts 214, and the gate contact 216, an interconnect structure 220 includes one or more stacked dielectric layers 224 and is formed on one or more Conductive features 222 in a dielectric layer 224 . Although FIG. 2 shows two stacked dielectric layers 224, it should be understood that interconnect structure 220 may include any number of dielectric layers 224 having conductive features 222 disposed therein. The interconnect structure 220 can be electrically connected to the gate contact 216 and the source/drain contact 214 to form a functional circuit. In some embodiments, the functional circuits formed by the interconnect structure 220 may include logic circuits, memory circuits, sense amplifiers, controllers, input/output circuits, image sensor circuits, the like, or combinations thereof. Although FIG. 2 discusses transistors formed over substrate 50, other active devices (eg, diodes or the like) and/or passive devices (eg, capacitors, resistors, or the like) may also be formed as functional circuits part.

In FIGS. 3A and 3B , a multi-layer stack 58 is formed over the interconnect structure 220 of FIG. 2 . For simplicity and clarity, the substrate 50, transistors, ILDs, and interconnect structures 220 may be omitted from subsequent figures. Although multilayer stack 58 is shown contacting dielectric layer 224 of interconnect structure 220 , any number of intervening layers may be disposed between substrate 50 and multilayer stack 58 . For example, one or more additional interconnect layers including conductive features in an insulating layer (eg, a low-k dielectric layer) may be disposed between substrate 50 and multilayer stack 58 . In some embodiments, the conductive features can be patterned to provide power, ground, and/or signal lines for active devices on substrate 50 and/or memory array 200 (see FIGS. 1A and 1B ).

Multilayer stack 58 includes alternating layers of conductive layers 54A-54C (collectively referred to as conductive layers 54 ) and dielectric layers 52A through 52D (collectively referred to as dielectric layers 52 ). Conductive layer 54 may be patterned in subsequent steps to define conductive lines 54 (eg, word lines). Conductive layer 54 may include a conductive material such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like, and dielectric layer 52 may include an insulating material such as silicon oxide, nitrogen Silicon oxide, silicon oxynitride, combinations thereof, or the like. Conductive layer 54 and dielectric layer 52 may each be formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced deposition CVD (plasma enhanced CVD; PECVD) or similar operations to form. Although FIGS. 3A and 3B show a specific number of conductive layers 54 and dielectric layers 52 , other embodiments may include different numbers of conductive layers 54 and dielectric layers 52 . Furthermore, the multi-layer stack 58 may include any number of suitable types of material layers, and the number and order of the material layers may be based on the desired device intended to be formed in the multi-layer stack 58 .

4-12B are views of intermediate stages of fabricating the stepped structure 68 of the memory array 200 in accordance with some embodiments. 4 to 11 and 12B are shown along the reference cross-section BB' shown in FIG. 1 . Figure 12A is shown in a three-dimensional view.

In FIG. 4 , photoresist 56 is formed over multilayer stack 58 . As discussed above, the multi-layer stack 58 may include alternating layers of conductive layers 54 (labeled 54A, 54B, and 54C) and dielectric layers 52 (labeled 52A, 52B, 52C, and 52D). Photoresist 56 may be formed by using spin coating techniques.

In FIG. 5 , photoresist 56 is patterned to expose multi-layer stack 58 in region 60 while masking the remainder of multi-layer stack 58 . For example, the topmost layer (eg, dielectric layer 52D) of multi-layer stack 58 may be exposed in region 60 . Photoresist 56 may be patterned using acceptable lithography techniques.

In FIG. 6 , exposed portions of multilayer stack 58 in region 60 are etched using photoresist 56 as a mask. The etching can be any acceptable etching process, such as by wet or dry etching, reactive ion etch (RIE), neutral beam etch (NBE), similar etching, or combinations thereof. Etching can be anisotropic. Portions of dielectric layer 52D and conductive layer 54C in removable region 60 are etched to define openings 61 . Since dielectric layer 52D and conductive layer 54C have different material compositions, the etchants used to remove exposed portions of these layers may be different. In some embodiments, conductive layer 54C acts as an etch stop layer when dielectric layer 52D is etched, and dielectric layer 52C acts as an etch stop layer when conductive layer 54C is etched. Accordingly, portions of dielectric layer 52D and conductive layer 54C can be selectively removed without removing the remaining layers of multilayer stack 58, and opening 61 can extend to a desired depth. Alternatively, a timed etch process may be used to terminate the etching of opening 61 after opening 61 reaches the desired depth. In the resulting structure, dielectric layer 52C is exposed in region 60 .

In FIG. 7 , photoresist 56 is trimmed to expose additional portions of multilayer stack 58 . The photoresist can be trimmed using acceptable lithography techniques. Due to trimming, the width of photoresist 56 is reduced and portions of multilayer stack 58 in regions 60 and 62 may be exposed. For example, the top surface of dielectric layer 52C may be exposed in region 60 and the top surface of dielectric layer 52D may be exposed in region 62 .

In FIG. 8, portions of dielectric layer 52D, conductive layer 54C, dielectric layer 52C, and conductive layer 54B in regions 60 and 62 are removed by an acceptable etch process using photoresist 56 as a mask. The etching can be any acceptable etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), similar etching, or combinations thereof. Etching can be anisotropic. Etching may extend opening 61 further into multilayer stack 58 . Since dielectric layer 52D/dielectric layer 52C and conductive layer 54C/conductive layer 54B have different material compositions, the etchants used to remove exposed portions of these layers may be different. In some embodiments, conductive layer 54C acts as an etch stop layer when etching dielectric layer 52D; dielectric layer 52C acts as an etch stop layer when etching conductive layer 54C; conductive layer 54B acts as an etch stop layer when etching dielectric layer 52C ; and the dielectric layer 52B acts as an etch stop layer when etching the conductive layer 54B. Accordingly, portions of dielectric layer 52D/dielectric layer 52C and conductive layer 54B/conductive layer 54C may be selectively removed without removing the remaining layers of multilayer stack 58, and opening 61 may extend to a desired depth. Furthermore, during the etching process, the unetched portions of conductive layer 54 and dielectric layer 52 act as a mask for the underlying layers, and thus previous patterns (see FIG. 7 ) of dielectric layer 52D and conductive layer 54C can be transferred to the underlying layer Volt dielectric layer 52C and conductive layer 54B. In the resulting structure, dielectric layer 52B is exposed in region 60 and dielectric layer 52C is exposed in region 62 .

In FIG. 9 , photoresist 56 is trimmed to expose additional portions of multilayer stack 58 . The photoresist can be trimmed using acceptable lithography techniques. Due to trimming, the width of photoresist 56 is reduced and portions of multilayer stack 58 in regions 60, 62, and 64 may be exposed. For example, the top surface of dielectric layer 52B may be exposed in region 60 ; the top surface of dielectric layer 52C may be exposed in region 62 ; and the top surface of dielectric layer 52D may be exposed in region 64 .

In FIG. 10, dielectric layer 52D, dielectric layer 52C, and portions of dielectric layer 52B in regions 60, 62, and 64 are removed by an acceptable etch process using photoresist 56 as a mask. The etching can be any acceptable etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), similar etching, or combinations thereof. Etching can be anisotropic. Etching may extend opening 61 further into multilayer stack 58 . In some embodiments, conductive layer 54C acts as an etch stop layer when etching dielectric layer 52D; conductive layer 54B acts as an etch stop layer when etching dielectric layer 52C; and conductive layer 54A acts as an etch stop layer for etching dielectric layer 52B . Accordingly, portions of dielectric layer 52D, dielectric layer 52C, and dielectric layer 52B may be selectively removed without removing the remaining layers of multilayer stack 58, and opening 61 may extend to a desired depth. Furthermore, during the etch process, each of the conductive layers 54 acts as a mask for the underlying layer, and thus the previous pattern of conductive layer 54C/conductive layer 54B (see FIG. 9 ) can be transferred to the underlying dielectric layer 52C /Dielectric layer 52B. In the resulting structure, conductive layer 54A is exposed in region 60; conductive layer 54B is exposed in region 62; and conductive layer 54C is exposed in region 64.

In FIG. 11, photoresist 56 may be removed, such as by an acceptable ashing or wet strip process. Thus, the stepped structure 68 is formed. The stepped structure 68 includes a stack of alternating layers of conductive layers 54 and dielectric layers 52 . The lower conductive layer 54 is wider and extends laterally beyond the upper conductive layer 54 , and the width of each of the conductive layers 54 increases in the direction toward the substrate 50 . For example, conductive line 54A may be longer than conductive line 54B; conductive line 54B may be longer than conductive line 54C; and conductive line 54C may be longer than conductive line 54D. Thus, in subsequent processing steps, conductive contacts may be formed for each of the conductive layers 54 from above the stepped contact structure 68 .

In FIG. 12A , an inter-metal dielectric (IMD) 70 is deposited over the multilayer stack 58 . IMD 70 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Dielectric materials may include: Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (Boron-Doped Phospho-Silicate Glass) ; BPSG), undoped silicate glass (undoped Silicate Glass; USG) or the like. Other insulating materials formed by any acceptable process can be used. IMD 70 extends along the sidewalls of conductive layer 54 and the sidewalls of dielectric layer 52 . Additionally, IMD 70 may contact the top surface of each of dielectric layers 52 .

As further shown in FIG. 12A , a removal process is then applied to IMD 70 to remove excess dielectric material over multilayer stack 58 . In some embodiments, planarization processes, such as chemical mechanical polish (CMP), etch-back processes, combinations thereof, or the like may be utilized. According to some embodiments, the planarization process exposes the multilayer stack 58 such that the top surfaces of the multilayer stack 58 and IMD 70 are flush after the planarization process is completed. In other embodiments, the planarization process planarizes IMD 70 to a desired height above the topmost layer (eg, dielectric layer 52D) of multilayer stack 58 .

FIG. 12B is a perspective view of stepped structure 68 in accordance with some embodiments. In particular, FIG. 12B shows a stepped contact structure 68 that has been formed from a multilayer stack 58 including four of the dielectric layers 52 and five of the conductive lines 54 . Additionally, Figure 12B shows a note according to some embodiments. Although embodiments of the stepped structure 68 have been shown to include a specific number of conductive lines 54 and dielectric layers 52, it should be understood that the stepped contact structure 68 may be formed with any other suitable layers of material and may have any number of Conductive lines 54 and dielectric layer 52 .

13-17B are views of intermediate stages of fabricating a memory array 200 using the multi-layer stack 58 of FIG. 3A, according to some embodiments. In FIGS. 13-17B , a multi-layer stack 58 is formed, and trenches are formed in the multi-layer stack 58 , thereby defining conductive lines 72 . The conductive lines 72 may correspond to word lines in the memory array 200 , and the conductive lines 72 may further provide gate electrodes for the resulting TFTs of the memory array 200 . Figure 17A is shown in a three-dimensional view. 13 to 16 and 17B are shown along the reference cross-section CC' shown in FIG. 1A.

In FIG. 13 , a hard mask 80 and photoresist 82 are deposited over the multilayer stack 58 . The hard mask 80 may comprise, for example, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. For example, photoresist 82 may be formed by using spin coating techniques.

In FIG. 14 , photoresist 82 is patterned to form trenches 86 . The photoresist can be patterned using acceptable lithography techniques. For example, photoresist 82 is exposed to light for patterning. After the exposure process, photoresist 82 may be developed to remove exposed or unexposed portions of the photoresist depending on whether a negative resist or positive resist is used, thereby defining the patterning of trenches 86 .

In FIG. 15, the pattern of photoresist 82 is etched using an acceptable etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), similar etching, or a combination thereof. Transfer to hard mask 80 . Etching can be anisotropic. Thus, trenches 86 extending through hard mask 80 are formed. For example, photoresist 82 may be removed by an ashing process.

In Figure 16, the hard etch is etched using one or more acceptable etching processes, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), similar etching, or a combination thereof. The pattern of reticle 80 is transferred to multilayer stack 58 . The etching process can be anisotropic. Thus, trenches 86 extend through multi-layer stack 58 and conductive lines 72 (eg, word lines) are formed from conductive layer 54 . Adjacent conductive lines 72 may be separated from each other by etching trenches 86 through conductive layer 54 .

Subsequently, in FIGS. 17A and 17B, the hard mask 80 may then be removed by an acceptable process, such as a wet etch process, a dry etch process, a planarization process, a combination thereof, or the like Process. Due to the stepped shape of the multilayer stack 58 (see, eg, FIG. 12A ), the conductive lines 72 may have varying lengths that increase in the direction toward the substrate 50 . For example, conductive line 72A may be longer than conductive line 72B; and conductive line 72B may be longer than conductive line 72C.

FIGS. 18A-23C illustrate the formation and patterning of channel regions of TFTs 204 (see FIG. 1A ) in trenches 86 . 18A, 19A, and 23A are shown in three-dimensional views. In FIGS. 18B, 19B, 20, 21, 22A, 22B, and 23B, cross-sectional views are provided along line CC' of FIG. 1A. Figure 23C shows a corresponding top-down view of the TFT structure.

In FIGS. 18A and 18B , memory film 90 is conformally deposited in trench 86 . In FIG. 18A, memory film 90 has been omitted from the bottom of trench 86 and over the top surface of multilayer stack 58 for visual clarity. The memory film 90 may have a material capable of storing bits, such as a material that can be switched between two different polarization directions by applying an appropriate voltage difference across the memory film 90 . For example, the polarization of the memory film 90 may vary due to the electric field created by the applied voltage difference.

For example, the memory film 90 may be a high-k dielectric material, such as a hafnium (Hf) based dielectric material or the like. In some embodiments, the memory film 90 includes a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon doped hafnium oxide, or the like. In other embodiments, the memory film 90 may be a multilayer structure (eg, an ONO structure) including a _SiNx layer between two _SiOx layers. In yet other embodiments, the memory film 90 may include different ferroelectric materials or different types of memory materials. Memory film 90 may be deposited by CVD, PVD, ALD, PECVD, or the like to extend along the sidewalls and bottom surfaces of trenches 86 . After depositing the memory film 90, an annealing step (eg, at a temperature ranging from about 300°C to about 600°C) may be performed to achieve a desired crystalline phase, improve film quality, and reduce film-related defects/defects of the memory film 90 impurities. In some embodiments, the annealing step may be further below 400°C to meet the BEOL thermal budget and reduce defects that may lead to other features from the high temperature annealing process.

In FIGS. 19A and 19B , OS layer 92 is conformally deposited in trench 86 over memory film 90 . In FIG. 19A , OS layer 92 and memory film 90 have been omitted at the bottom of trench 86 and over the top surface of multilayer stack 58 for visual clarity. OS layer 92 includes a material suitable for providing a channel region for a TFT (eg, TFT 204, see FIG. 1A). In some embodiments, OS layer 92 includes a material including _indium , such as _InxGayZnzMO , _where M can be Ti, Al, Ag, Si, Sn, or the like. X, Y, and Z can each be any value between 0 and 1. In other embodiments, different semiconductor materials may be used for OS layer 92 . OS layer 92 may be deposited by CVD, PVD, ALD, PECVD, or the like. OS layer 92 may extend along the sidewalls and bottom surface of trench 86 over memory film 90 . After the OS layer 92 is deposited, an annealing step in an oxygen-related environment (eg, at a temperature ranging between about 300° C. and about 450° C.) may be performed to activate the charge carriers of the OS layer 92 .

In FIG. 20 , dielectric material 98A is deposited on the sidewall and bottom surfaces of trench 86 and over OS layer 92 . Dielectric material 98A may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like.

In FIG. 21, for example, the bottom portion of dielectric material 98A in trench 86 is removed using a combination of lithography and etching. The etching can be any acceptable etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), similar etching, or combinations thereof. Etching can be anisotropic.

Subsequently, as also shown in FIG. 21 , dielectric material 98A may be used as an etch mask to etch through the bottom portion of OS layer 92 in trench 86 . The etching can be any acceptable etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), similar etching, or combinations thereof. Etching can be anisotropic. Etching OS layer 92 may expose portions of memory film 90 on the bottom surface of trench 86 . Accordingly, portions of OS layer 92 on opposite sidewalls of trenches 86 may be separated from each other, which improves isolation between memory cells 202 of memory array 200 (see FIG. 1A ).

In FIG. 22 , additional dielectric material 98B may be deposited to fill the remainder of trenches 86 . Dielectric material 98B may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. In some embodiments, dielectric material 98B may have the same material composition as dielectric material 98A and be formed using the same process as dielectric material 98A. Alternatively, dielectric material 98B may have a different material composition than dielectric material 98A and/or be formed by a different process than dielectric material 98A.

For ease of illustration, subsequent figures show further processing based on the embodiment of FIG. 22 (eg, in which dielectric material 98B and dielectric material 98A have the same material composition). Dielectric material 98B and dielectric material 98A may be collectively referred to as dielectric material 98 hereinafter. It should be understood that similar processing is applicable to embodiments in which dielectric material 98B and dielectric material 98A have different material compositions.

In FIGS. 23A-23C , a removal process is then applied to dielectric material 98 , OS layer 92 , and memory film 90 to remove excess material over multilayer stack 58 . In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like may be utilized. The planarization process exposes the multi-layer stack 58 so that the top surface of the multi-layer stack 58 is flush after the planarization process is completed. Figure 23C shows a corresponding top-down view of the structure shown in Figure 23A.

FIGS. 24A-27C illustrate intermediate steps in the fabrication of conductive lines 106 and 108 (eg, source lines and bit lines) in memory array 200 . Conductive lines 106 and 108 may extend in a direction perpendicular to conductive lines 54 such that individual cells of memory array 200 may be selected for read and write operations. In FIGS. 24A-27C, the graphs ending in "A" show 3D views; the graphs ending in "B" show top-down views, and the graphs ending in "C" show line C with FIG. 1A -C' parallel corresponding cross-sectional view.

In FIGS. 24A, 24B, and 24C, trench 100 is patterned through OS layer 92 and dielectric material 98, including dielectric material 98A and dielectric material 98B. Figure 24C shows a cross-sectional view of line CC' in Figure 24B. For example, patterning of trenches 100 may be performed through a combination of lithography and etching. The trenches 100 may be disposed between opposing sidewalls of the memory film 90, and the trenches 100 may physically separate adjacent stacks of memory cells in the memory array 200 (see FIG. 1A).

In FIGS. 25A , 25B, and 25C, dielectric material 102 is deposited in trench 100 and fills trench 100 . Figure 25C shows a cross-sectional view of line CC' in Figure 25B. The dielectric material 102 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. Dielectric material 102 may extend along the sidewalls and bottom surface of trench 100 over OS layer 92 . After deposition, a planarization process (eg, CMP, etch-back, or the like) may be performed to remove excess portions of the dielectric material 102 . In the resulting structure, the top surfaces of the multi-layer stack 58, memory film 90, OS layer 92, and dielectric material 102 may be substantially flush (eg, within process variations). In some embodiments, the materials of dielectric material 98 and dielectric material 102 may be selected such that the materials can be selectively etched relative to each other. For example, in some embodiments, dielectric material 98 is an oxide, and dielectric material 102 is a nitride. In some embodiments, dielectric material 98 is a nitride and dielectric material 102 is an oxide. Other materials are also possible.

In FIGS. 26A , 26B and 26C , trenches 104 are patterned for conductive lines 106 and 108 . Figure 26C shows a cross-sectional view of line CC' in Figure 26B. For example, trenches 104 are formed by patterning dielectric material 98 (including dielectric material 98A and dielectric material 98B) using a combination of lithography and etching.

For example, photoresist 120 may be deposited over multilayer stack 58 , dielectric material 98 , dielectric material 102 , OS layer 92 , and memory film 90 . For example, the photoresist 120 may be formed by using a spin coating technique. Photoresist 120 is patterned to define openings 122 . Each of the openings 122 can overlap a corresponding region of the dielectric material 102 , and each of the openings 122 can further partially expose two separate regions of the dielectric material 98 . For example, each opening 122 may expose a region of the dielectric material 102; partially expose a first region of the dielectric material 98; and partially expose a second region of the dielectric material 98, the second region by the dielectric material The region of 102 exposed by opening 122 is separated from the first region of dielectric material 98 . In this manner, each of the openings 122 may define a pattern of conductive lines 106 and adjacent conductive lines 108 separated by the dielectric material 102 . The photoresist can be patterned using acceptable lithography techniques. For example, photoresist 120 is exposed to light for patterning. After the exposure process, the photoresist 120 may be developed to remove exposed or unexposed portions of the photoresist depending on whether a negative resist or a positive resist is used, thereby defining the patterning that forms the openings 122 .

The portions of dielectric material 98 exposed by openings 122 may then be removed, for example, by etching. The etching can be any acceptable etching process, such as by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), similar etching, or combinations thereof. Etching can be anisotropic. The etching process may use an etchant that etches the dielectric material 98 without significantly etching the dielectric material 102 . Thus, even though the openings 122 expose the dielectric material 102, the dielectric material 102 may not be removed significantly. The pattern of trenches 104 may correspond to conductive lines 106 and 108 (see Figures 27A, 27B, and 27C). For example, a portion of dielectric material 98 may remain between each pair of trenches 104 , and dielectric material 102 may be disposed between adjacent pairs of trenches 104 . For example, after patterning trench 104, photoresist 120 may be removed by ashing.

In FIGS. 27A , 27B, and 27C, trenches 104 are filled with conductive material to form conductive lines 106 and 108 . Figure 27C shows a cross-sectional view of line CC' in Figure 27B. Conductive lines 106 and 108 may each comprise conductive materials such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof or the like. After conductive lines 106 and 108 are deposited, planarization (eg, CMP, etch back, or the like) may be performed to remove excess portions of conductive material, thereby forming conductive lines 106 and 108 . In the resulting structure, the top surfaces of the multilayer stack 58, memory film 90, OS layer 92, conductive lines 106, and conductive lines 108 may be substantially flush (eg, within process variations). Conductive lines 106 may correspond to bit lines in the memory array, and conductive lines 108 may correspond to source lines in the memory array 200 . Although FIG. 27C shows a cross-sectional view showing only conductive line 106, the cross-sectional view of conductive line 108 may be similar.

Thus, the stacked TFTs 204 can be formed in the memory array 200 . Each TFT 204 includes a gate electrode (eg, corresponding to a portion of conductive line 54 ), a gate dielectric (eg, corresponding to a portion of memory film 90 ), a channel region (eg, corresponding to a portion of OS layer 92 ), and a source A pole electrode and a drain electrode (eg, corresponding to portions of conductive line 106 and conductive line 108 ). The dielectric material 102 is in the same row and isolates adjacent TFTs 204 at the same height. The TFTs 204 may be arranged in an array of vertically stacked columns and rows.

In FIGS. 28A and 28B , stepped vias 110 are formed for conductive lines 54 (eg, word line 116C), and sources are formed for conductive lines 106 and 108 (eg, source line 116B and bit line 116A) Pole/bit line contact 112 and source/bit line contact 114. 28A shows a perspective view of both of the memory array 200 and the stepped contact structures 68 adjacent to the memory array 200, according to some embodiments. In some embodiments, the stepped contact structures 68 are formed on opposite sides of the transistor stack regions 1201 of the memory array 200 . Figure 28B shows a top-down view of the stepped contact structure 68 in Figure 28A.

In the embodiment shown, the multi-layer stack 58 includes six of the conductive lines 54 separated by seven of the dielectric layers 52, which may be formed by repeating the steps described above. form. In some embodiments, the stepped shape of the multi-layer stack 58 may provide a surface on each of the conductive lines 54 for the stepped vias 110 to land on.

As also shown by the perspective view of FIG. 28A, source/bit line contact 112 and source/bit line contact 114 may also be formed for conductive line 106 and conductive line 108, respectively. The source/bit line contact 112 and the source/bit line contact 114 may be formed using any of the materials and techniques suitable for forming the stepped via 110 .

In the illustrated embodiment, the IMD 70 is shown as recessed compared to the stepped via 110 in FIG. 28A; however, the stepped via 110 and the horizontal plane of the IMD 70 may be coplanar. In other embodiments, IMD 70 may be formed coplanar with memory array 200 , and an optional dielectric layer 120 (see FIG. 29 ) may be formed over IMD 70 and memory array 200 . In such an embodiment, the opening of the stepped via 110 is formed through the optional dielectric layer and the IMD 70, and the source/bit line contacts 112 and source are formed through the optional dielectric layer /The opening of the bit line contact 114.

According to some embodiments, the size of the stepped via 110 increases as the height of the stepped via 110 increases from the uppermost conductive line 54 to the bottommost conductive line 54 . For example, the diameter of the stepped via 110 at the topmost surface of the stepped contact structure 68 may increase with increasing distance from the transistor stack region 120 . In this way, the diameter of the stepped via 110 closest to the transistor stack region 1201 is smaller than the diameter of the stepped via 110 farthest from the transistor stack region 1201 . In FIGS. 28A and 28B , the stepped via 110 closest to the transistor stack region 1201 may have a first height H1 , and the stepped via 110 farthest from the transistor stack region 1201 may have an nth height H(n) . The nth height H(n) is greater than the first height H1. In addition, the stepped via 110 closest to the transistor stack region 1201 may have a first diameter W(0), and the stepped via 110 farthest from the transistor stack region 1201 may have an nth diameter W(n). The nth diameter W(n) is larger than the first diameter W(0).

Furthermore, source/bit line contact 112 and source/bit line contact 114 may be formed with any suitable size (eg, height and diameter) for stepped via 110 . Although source/bit line contact 112 and source/bit line contact 114 are shown as being the same size (eg, first height H1 and first width W(0)), the source/bit line contact Points 112 and source/bit line contacts 114 may also be of different sizes. FIG. 28B further illustrates the tangent EE′ through the stepped via 110 of the stepped contact structure 68 .

29-31 illustrate intermediate steps in forming stepped vias 110 in accordance with some embodiments. Figures 29-31 show cross-sectional views of the stepped contact structure 68 along the line EE' of Figure 28B.

In particular, FIG. 29 illustrates forming openings 2901 through IMD 70 in desired locations of stepped vias 110 in accordance with some embodiments. In some embodiments, the shape of the stepped structures 68 may provide a surface on each of the conductive lines 54 for the stepped vias 110 to land. Forming stepped vias 110 may include patterning openings in IMD 70 and dielectric layer 52 to expose portions of conductive lines 54 , eg, using a combination of lithography and etching. In some embodiments, openings 2901 may be patterned to have substantially vertical sidewalls. In such embodiments, the width of the opening 2901 may be uniform from the top of the opening to the bottom of the opening. In other embodiments, the openings 2901 can be patterned to have angled sidewalls. In such embodiments, the width of the opening 2901 may be greater at the top of the opening as compared to the width at the bottom of the opening.

Once the opening 2901 has been formed, the extension Ext1 to the extension Ext(n) of the conductive line 54 are exposed. Extensions Ext1 to Ext(n) may refer to portions of respective ones of conductive lines 54 that extend beyond overlying ones in dielectric layer 52 and/or overlying ones in conductive lines 54 . In some embodiments, the extensions Ext1 to Ext(n) have equal lengths. In other embodiments, the extensions Ext1 to Ext(n) may have different lengths. FIG. 29 further illustrates centerline CL1 to centerline CL(n) of opening 2901 that may be aligned with the center of extension Ext1 to extension Ext(n) in the illustrated embodiment. According to some embodiments, the openings 2901 can have different widths (eg, W(0)-W(n) and H1-H(n)), and each of the openings 2901 is at an associated extension of the conductive line 54 ( For example, in the middle above Ext1 to Ext(n)).

Turning now to Figure 30, this figure illustrates the etch loading effect of opening 2901, according to some embodiments. According to some embodiments, the first opening may be located at a first distance D1 from the transistor stack region 1201, and the remaining openings may be formed at locations along a line up to a second distance D2 from the first opening. In some embodiments, openings 2901 are formed at locations along lines of regular pitch P1. In other embodiments, the opening 2901 may be formed at any suitable location along the line between the first distance D1 and the second distance D2.

In particular, FIG. 30 illustrates the correlation between a desired width and a desired depth of opening 2901 as a result of the etch process used to pattern opening 2901, according to some embodiments. For example, as the second distance D2 increases, the width of the opening 2901 increases (eg, W(0) to W(n)), and the etching depth of the opening 2901 (eg, H1 to H(n)) also increases, where n is a positive integer. According to some embodiments, the width of opening 2901 (eg, W(0) to W(n)) may be between about 10 nanometers and about 500 nanometers. In some embodiments, the heights of openings 2901 (eg, H1 to H(n)) may be between about 50 nanometers and about 5,000 nanometers. However, any suitable width and height may be used for opening 2901. Due to the etch loading effect, openings 2901 of different widths may be patterned using a single patterning step due to the difference in depth to which each of the openings 2901 extends.

Continuing with FIG. 31 , this figure illustrates the formation of stepped vias 110 in openings 2901 in accordance with some embodiments. Forming the stepped via 110 may include forming a liner (not shown) such as a diffusion barrier layer, an adhesive layer, or the like, and forming a conductive material in the opening. The liner may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as CMP may be performed to remove excess material from the surface of IMD 120 . The remaining liner and conductive material form stepped vias 110 in openings 2901 . In some embodiments, IMD 120 may be omitted, and the planarization process makes stepped via 110 flush with the top surface of IMD 70 .

Furthermore, FIG. 31 shows that the centerline CL1 to the centerline CL(n) of the stepped via 110 may be in the middle above the extension of the conductive line 54 according to some embodiments. In addition, according to some embodiments, the first stepped via 110 is located at a first distance D1 from the transistor stack region 1201 . According to some embodiments, the widths (eg, W( 0 ) to W(n) ) of the stepped vias 110 may increase as the second distance D2 increases from the first stepped vias 110 . Any suitable distance can be used for the first distance D1 and the second distance D2. In the illustrated embodiment, the stepped via 110 is planarized with the IMD 120 . As such, the tops of the stepped vias 110 are exposed in the coplanar surface of the IMD 120 according to some embodiments.

In FIGS. 32A, 32B, 32C and 32D, a common bit line 116A and a common source are formed for the source/bit line contact 112, the source/bit line contact 114 and the stepped via 110, respectively. line 116B and common word line 116C. 32D shows that stepped via 110 and source/bit line contact 112 and source/bit line contact 114 may be electrically connected to common bit line 116A, common source line 116B, and common word line 116C, respectively , the common bit line 116A, common source line 116B, and common word line 116C connect the memory array to the underlying/overlying circuitry (eg, control circuitry) and/or the signal, power of the semiconductor die and ground wire. For example, common bit line 116A, common source line 116B, and common word line 116C may be routed through one or more dielectric layers 3201 (shown in Figures 32C and 32D) and connected to extending through the IMD 70 vias 118 to electrically connect the common word line 116C to the underlying circuitry of the interconnect structure 220 and active devices on the substrate 50, as shown in FIG. 32C. Additional vias 118 may be formed through IMD 70 to electrically connect common bit line 116A and common source line 116B to the underlying circuitry of interconnect structure 220 . In alternative embodiments, routing to and from the memory array and/or may be provided by interconnect structures formed over the memory array 200 in addition to or instead of the interconnect structures 220. power line. Thus, the memory array 200 can be completed.

Although the embodiments of FIGS. 2-32C show particular patterns of conductive lines 106 and 108, other configurations are possible. For example, in these embodiments, conductive lines 106 and 108 have a staggered pattern. In some embodiments, the conductive lines 106 and 108 in the same column of the array are both aligned with each other.

FIG. 33 shows a top-down view, and FIG. 34 shows a cross-sectional view along line CC' of FIG. 33 . FIG. 35 shows a cross-sectional view along line DD' of FIG. 33 . In Figures 33, 34, and 35, the same reference numerals denote the same elements formed by the same process as the elements of Figures 2-32C.

Turning now to FIG. 36, this figure shows a stepped contact structure 68 according to another embodiment. 36 is similar to FIG. 31 , except that each of the stepped vias 110 is spaced a third distance D3 along the extension Ext1 to the extension Ext(n) of the conductive line 54 rather than along the middle of the extension. As such, the stepped via to word line distance (eg, the third distance D3 ) is the same for each of the stepped vias 110 in the illustrated embodiment of FIG. 36 . Having a uniform stepped via to word line distance provides reliable contact connections for the fabrication of the stepped contact structure 68 and the operation of the memory array device 200 . Once the stepped contact structure 68 has been formed according to the illustrated embodiment, the memory array device 200 may be further processed as discussed with respect to FIGS. 32A-35 .

Continuing with Figure 37, this figure illustrates a stepped contact structure 68 according to yet another embodiment. The widths (eg, W(0) to W(n)) of the stepped vias 110 are proportional to the first width W(0) (where n is a positive integer, and where W(n) is between about 10 nanometers and about 500 nm), Figure 37 is similar to Figure 31. For example, the stepped via ratio W(n)/W(0) may be between about 1:1 and about 50:1. However, any suitable ratio can be utilized. In some embodiments, the nth width W(n) increases as the second distance D2 increases from the first stepped via 110 . According to some embodiments, the nth width W(n) = [W(0) + W(0)/n], where n is a positive integer, and where W(n) is between about 10 nm and 500 nm width between. However, any suitable width may be utilized. In such an embodiment, the opening 2901 (shown in FIG. 30 ) is formed with the desired width and in the desired location of the stepped via 110 . Once the stepped contact structure 68 has been formed according to the illustrated embodiment, the memory array device 200 may be further processed as discussed with respect to FIGS. 32A-35 .

Various embodiments provide a 3D stacked memory array with vertically stacked memory cells. The memory cells each include a TFT having a memory film, a gate dielectric material, and an oxide semiconductor channel region. TFTs include source/drain electrodes, which are also source lines and bit lines in a memory array. A dielectric material is disposed between and isolates adjacent ones of the source/drain electrodes.

In some embodiments, the contact step structure is formed by a stack of conductive layers separated by a dielectric layer. The contact ladder structure provides word line contacts for stacked memory arrays. The upper conductive layer provides word line contacts for the upper memory cells of the stacked memory array, and the lower conductive layer provides word line contacts for the lower memory cells of the stacked memory array. In this way, the step height of the lower conductive layer is greater than that of the upper conductive layer. Etch loading effects (e.g., wider stepped via critical dimensions for deeper etch depths, and narrow stepped via critical dimensions for shallower etch depths) are used to prevent degradation due to step heights between upper and lower layers. The over-etching of the opening of the stepped via and the short-circuit of the upper-layer word line caused by the large difference. Material savings (eg, mask material), lower manufacturing costs, and simplified processing flow can be achieved for the production of 3D stacked memory array devices with reliable word line contact connectivity.

According to one embodiment, a memory array device includes a transistor stack over a semiconductor substrate, the transistor stack including a first thin film transistor, the first thin film transistor overlying a second thin film transistor, the first thin film transistor including : the first memory film, along the first word line; and the first channel region, along the first source line and the first cell line, wherein the first memory film is disposed in the first channel region and the first word between lines; the second thin film transistor includes: a second memory film, along the second word line; and a second channel region, along the first source line and the first cell line, wherein the second memory film is disposed between the second channel region and the second word line; a first stepped via electrically connected to the first word line, the first stepped via having a first width; and a second stepped via electrically connected to the first stepped via For two word lines, the second stepped via has a second width, and the second width is greater than the first width. In one embodiment, the first stepped via is located at a first distance from the transistor stack, and the second stepped via is located at a second distance from the transistor stack, and the second distance is greater than the first distance. In one embodiment, the first stepped via is in the middle on the first extension of the first word line, wherein the second stepped via is in the middle on the second extension of the second word line, wherein The first extension of the first word line is the part of the first word line that extends beyond the third word line above the first word line, and the second extension of the second word line is the second word line The portion of the line that extends beyond the first word line. In one embodiment, the first stepped via is located at a third distance along the first extension of the first word line, and wherein the second stepped via is located at a third distance along the second extension of the second word line. three distances, wherein the first extension of the first word line is the portion of the first word line that extends beyond the third word line above the first word line, and wherein the second extension of the second word line is the portion of the second word line that extends beyond the first word line. In one embodiment, the first width is in the range of 10 nm to 500 nm. In one embodiment, the ratio of the second width to the first width is in the range of 1:1 to 50:1. In one embodiment, the first stepped via and the second stepped via are included in a plurality of stepped vias, wherein the width of the n-th stepped via in the plurality of stepped vias is equal to the n-th width W(n), where the nth width W(n) = [W(0) + W(0)/n], and where W(0) is the first width, and n is a positive integer.

According to another embodiment, an apparatus includes: a semiconductor substrate; a stack of word lines; a first stepped via connected to a first word line of the stack of word lines, the first stepped via including a first width and a first height ; a second stepped via, connected to a second word line of the word line stack, the first word line is located above the second word line, the second stepped via includes a second width and a second height, the second width greater than the first width, and the second height is greater than the first height; and a memory cell stack, the memory cell stack comprising: a first thin film transistor, wherein a portion of the first word line provides a gate electrode of the first thin film transistor; and A second thin film transistor, wherein the first thin film transistor is disposed over the second thin film transistor, and wherein a portion of the second word line provides a gate electrode of the second thin film transistor. In one embodiment, the first stepped through hole is located at a first distance from the memory cell stack, and the second stepped through hole is located at a second distance from the memory cell stack, and the second distance is greater than the first distance. In one embodiment, the first width is between about 10 nanometers and about 500 nanometers. In one embodiment, the ratio of the second width to the first width is between about 1:1 and about 50:1. In one embodiment, the first stepped via is in the middle above the first extension of the first word line, and the second stepped via is in the middle above the second extension of the second word line, wherein The first extension of the first word line is the portion of the first word line that extends beyond the third word line of the word line stack, wherein the third word line is disposed above the first word line, and wherein the second word line The second extension portion of the word line is a portion of the second word line extending beyond the first word line. In one embodiment, the first stepped via is located at a third distance along the first extension of the first word line, and the second stepped via is located at a third distance along the second extension of the second word line. distance, wherein the first extension of the first word line is the portion of the first word line extending beyond the third word line of the word line stack, wherein the third word line is disposed above the first word line, And the second extension part of the second word line is the part of the second word line extending beyond the first word line. In one embodiment, a total of n stepped vias are connected to the word line stack, wherein the width of the nth stepped via is equal to the nth width W(n), where the nth width W(n) = [W(0) + W(0)/n], and where W(0) is the first width, and where n is a positive integer between 1 and 50.

In yet another embodiment, a method includes forming a memory cell stack in a first region of a multilayer stack of conductive layers, a portion of the first conductive layer being a gate electrode of a first memory cell in the memory cell stack, and A portion of the second conductive layer is the gate electrode of the second memory cell in the memory cell stack; a conductive stepped structure is formed in the second region of the multilayer stack of the conductive layer; a dielectric layer is formed over the conductive stepped structure; by forming exposing the first conductive layer through a first opening through the dielectric layer, the first opening having a first width and located at a first distance from the first region; exposing the second conductive layer by forming a second opening through the dielectric layer a conductive layer, the second opening includes a second width and is located at a second distance from the first region, the second width is greater than the first width, and the second distance is greater than the first distance; a first via hole is formed in the first opening; and A second via hole is formed in the second opening. In one embodiment, the first width is a width between about 10 nanometers and about 500 nanometers. In one embodiment, the ratio of the second width to the first width is between about 1:1 and about 50:1. In one embodiment, the multilayer stack of conductive layers includes a total of n conductive layers, wherein the method further includes exposing the nth conductive layer by forming an nth opening through the dielectric layer, the nth opening having a width equal to the first width The sum of the quotients of the first width divided by n, where n is a positive integer between 1 and 50. In one embodiment, the first opening is in the middle above the first extension of the first conductive layer, and the second opening is in the middle above the second extension of the second conductive layer, wherein the first conductive layer An extension is the part of the first conductive layer that extends beyond the third conductive layer above the first conductive layer, and the second extension of the second conductive layer is the part of the second conductive layer that extends beyond the first conductive layer. In one embodiment, the first opening is located at a third distance along the first extension of the first conductive layer, and the second opening is located at a third distance along the second extension of the second conductive layer, wherein the first The first extension portion of the conductive layer is the portion of the first conductive layer that extends beyond the third conductive layer above the first conductive layer, and the second extension portion of the second conductive layer is the portion of the second conductive layer that extends beyond the first conductive layer. part.

The foregoing summarizes the features of several embodiments so that aspects of the present disclosure may be better understood by those of ordinary skill in the art. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those of ordinary skill in the art may Various changes, substitutions and alterations are made in the .

50: base 52, 52A, 52B, 52C, 52D, 224, 3201: Dielectric layer 54, 54A, 54B, 54C: Conductive layer 54D, 72, 72A, 72B, 72C, 106, 108: Conductive wire 56,82,120: Photoresist 58: Multilayer Stacking 60,62,64: District 61,122,2901: Opening 68: Ladder structure 70: Intermetal dielectric 80: Hard cover 86,100,104: Ditch 90: Insulating memory film 92: oxide semiconductor layer 98, 98A, 98B, 102: Dielectric Materials 110: Stepped through hole 112, 114: Source/Bit Line Contacts 116A: bit line 116B: source line 116C: word line 118: Via hole 200: memory array 202: Memory Cell 203: gate dielectric layer 204: Thin Film Transistor 205: gate electrode 206: Arrow 207: source/drain region 208: Gate spacer 210: First ILD 212: Second ILD 214: source/drain contacts 216: gate contact 220: Interconnect structure 222: Conductive Features 1201: Transistor stack area B-B', C-C', D-D': cross section CL1, CL(n): center line D1: first distance D2: Second distance D3: The third distance E-E': Tangent Ext1,Ext(n): extension H1: first height H(n): nth height P1: Pitch W(0): first diameter W(n): nth diameter

Aspects of the present disclosure are best understood from the following description when read in conjunction with the accompanying drawings. It should be noted that in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. 1A, 1B, and 1C show perspective views, circuit diagrams, and top-down views of a memory array in accordance with some embodiments. Figure 2, Figure 3A, Figure 3B, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12A, Figure 12B, Figure 13, Figure 14, Figure 15, Figure 16 , Figure 17A, Figure 17B, Figure 18A, Figure 18B, Figure 19A, Figure 19B, Figure 20, Figure 21, Figure 22, Figure 23A, Figure 23B, Figure 23C, Figure 24A, Figure 24B, Figure 24C, Figure 25A, Figure 23 25B, 25C, 26A, 26B, 26C, 27A, 27B, and 27C illustrate variant views of fabricating a memory array in accordance with some embodiments. 28A and 28B illustrate a perspective view of a memory array and adjoining stepped contact structures and a top-down view of the stepped contact structure, according to some embodiments. 29, 30, and 31 illustrate various views of fabricating stepped joint structures in accordance with some embodiments. 32A, 32B, 32C, and 32D illustrate various views of the formation of conductive lines to word, source, and bit lines of a memory array and to vias in a redistribution structure, according to some embodiments. 33, 34, and 35 illustrate variant views of memory arrays in accordance with some embodiments. 36 illustrates a stepped contact structure according to some other embodiments. 37 shows a stepped contact structure according to some other embodiments.

52: Dielectric layer

54: Conductive layer

68: Ladder structure

70: Intermetal dielectric

90: Insulating memory film

98: Dielectric Materials

106,108: Conductive thread

110: Stepped through hole

112, 114: Source/Bit Line Contacts

200: memory array

1201: Transistor stack area

H1: first height

H(n): nth height

Claims (20)

A memory array device, comprising: a stack of transistors located above the semiconductor substrate, the stack of transistors comprising a first thin film transistor over a second thin film transistor, the first thin film transistor comprising: a first memory film, along a first word line; and a first channel region, along a first source line and a first cell line, wherein the first memory film is disposed between the first channel region and the first word line; The second thin film transistor includes: a second memory film, along the second word line; and a second channel region, along the first source line and the first cell line, wherein the second memory film is disposed between the second channel region and the second word line; a first stepped via electrically connected to the first word line, the first stepped via including a first width; and A second stepped via is electrically connected to the second word line, the second stepped via includes a second width, and the second width is greater than the first width. The memory array device of claim 1, wherein the first stepped via is located at a first distance from the transistor stack, and wherein the second stepped via is located a second distance from the transistor stack distance, the second distance is greater than the first distance. The memory array device of claim 2, wherein the first stepped via is in the middle on the first extension of the first word line, and wherein the second stepped via is in the first The middle on the second extension of the two word line, wherein the first extension of the first word line is the third extension of the first word line beyond the top of the first word line portion of a word line, and wherein the second extension of the second word line is the portion of the second word line that extends beyond the first word line. The memory array device of claim 2, wherein the first stepped via is located at a third distance along a first extension of the first word line, and wherein the second stepped via is located at a third distance along a first extension of the first word line at the third distance along a second extension of the second wordline, wherein the first extension of the first wordline extends beyond the first wordline The portion of a third word line above a word line, and wherein the second extension of the second word line is the portion of the second word line that extends beyond the first word line. The memory array device of claim 2, wherein the first width is in the range of 10 nm to 500 nm. The memory array device of claim 5, wherein a ratio of the second width to the first width is in the range of 1:1 to 50:1. The memory array device of claim 5, wherein the first stepped through hole and the second stepped through hole are included in a plurality of stepped through holes, wherein the nth step of the plurality of stepped through holes The width of the via is equal to the nth width W(n), where the nth width W(n) = [W(0) + W(0)/n], and where W(0) is the first width , and n is a positive integer. A memory array device, comprising: semiconductor substrate; word line stacking; a first stepped via, connected to a first word line of the word line stack, the first stepped via includes a first width and a first height; a second stepped via, connected to a second word line of the word line stack, the first word line is located above the second word line, the second stepped via includes a second width and a second height, the second width is greater than the first width, and the second height is greater than the first height; and A stack of memory cells, the stack of memory cells comprising: a first thin film transistor, wherein a portion of the first word line provides a gate electrode of the first thin film transistor; and A second thin film transistor, wherein the first thin film transistor is disposed over the second thin film transistor, and wherein a portion of the second word line provides a gate electrode of the second thin film transistor. The memory array of claim 8, wherein the first stepped via is located at a first distance from the memory cell stack, and the second stepped via is located at a second distance from the memory cell stack , the second distance is greater than the first distance. The memory array of claim 9, wherein the first width is between about 10 nanometers and about 500 nanometers. The memory array of claim 10, wherein the ratio of the second width to the first width is between about 1:1 and about 50:1. The memory array of claim 10, wherein the first stepped via is in the middle above the first extension of the first word line, and the second stepped via is in the second in the middle above the second extension of the word line, wherein the first extension of the first word line is the third word line of the first word line that extends beyond the word line stack , wherein the third word line is disposed above the first word line, and wherein the second extension of the second word line is the extension of the second word line beyond the part of the first word line. The memory array of claim 10, wherein the first stepped via is located at a third distance along the first extension of the first word line, and the second stepped via is located along the at the third distance from the second extension of the second wordline, wherein the first extension of the first wordline is for the first wordline to extend beyond the wordline stack portion of a third word line of , wherein the third word line is disposed above the first word line, and wherein the second extension of the second word line is the second word An element line extends beyond the portion of the first word line. The memory array of claim 10, wherein a total of n stepped vias are connected to the word line stack, wherein a width of an nth stepped via is equal to an nth width W(n), wherein the nth width W(n) = [W(0) + W(0)/n], and where W(0) is the first width, and where n is a positive integer between 1 and 50. A method of manufacturing a memory array, comprising: A memory cell stack is formed in a first region of the multi-layer stack of conductive layers, a portion of the first conductive layer in the multi-layer stack of conductive layers is a gate electrode of a first memory cell in the memory cell stack, and the A portion of the second conductive layer in the multilayer stack of conductive layers is the gate electrode of the second memory cell in the memory cell stack; forming a conductive stepped structure in a second region of the multilayer stack of conductive layers; forming a dielectric layer over the conductive stepped structure; exposing the first conductive layer by forming a first opening through the dielectric layer, the first opening comprising a first width and located at a first distance from the first region; exposing the second conductive layer by forming a second opening through the dielectric layer, the second opening comprising a second width and located at a second distance from the first region, the second width is greater than the first width, and the second distance is greater than the first distance; forming a first via hole in the first opening; and A second via hole is formed in the second opening. The method of claim 15, wherein the first width is a width between about 10 nanometers and about 500 nanometers. The method of claim 16, wherein the ratio of the second width to the first width is between about 1:1 and about 50:1. The method of claim 16, wherein the multilayer stack of conductive layers includes a total of n conductive layers, wherein the method further comprises exposing the nth conductive layer by forming an nth opening through the dielectric layer , the width of the nth opening is equal to the sum of the first width and the quotient of the first width divided by n, where n is a positive integer between 1 and 50. The method of claim 16, wherein the first opening is in the middle over the first extension of the first conductive layer, and the second opening is in the second extension of the second conductive layer upper middle, wherein the first extension of the first conductive layer is the portion of the first conductive layer that extends beyond a third conductive layer above the first conductive layer, and wherein the second conductive layer The second extension of the layer is the portion of the second conductive layer that extends beyond the first conductive layer. The method of claim 16, wherein the first opening is located a third distance along a first extension of the first conductive layer, and the second opening is located along a third distance of the second conductive layer At the third distance of the two extensions, wherein the first extension of the first conductive layer is a portion of the first conductive layer extending beyond the third conductive layer above the first conductive layer, and The second extension portion of the second conductive layer is a portion of the second conductive layer extending beyond the first conductive layer.

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