WO2019125352A1

WO2019125352A1 - Three-dimensional integrated circuit memory cell having a ferroelectric field effect transistor with a floating gate

Info

Publication number: WO2019125352A1
Application number: PCT/US2017/066932
Authority: WO
Inventors: Elijah Karpov; Brian Doyle; Abhishek Sharma; Prashant Majhi; Ravi Pillarisetty
Original assignee: Intel Corp
Current assignee: Intel Corp
Priority date: 2017-12-18
Filing date: 2017-12-18
Publication date: 2019-06-27
Anticipated expiration: 2020-06-18

Abstract

A three-dimensional integrated circuit memory device may be fabricated to have memory cells comprising a layered stack structure formed from a plurality of dielectric layers and at least one conductive layer positioned between adjacent dielectric layers of the plurality of dielectric layers. A via may be defined by a sidewall extending through the layered stack structure and a gate dielectric layer may be formed within the via. A channel material layer may be formed within the via contacting the gate dielectric layer. A floating gate material layer may be formed between adjacent dielectric layers of the plurality of dielectric layers, wherein the floating gate material layer contacts the channel material layer. A ferroelectric material layer may be formed between adjacent dielectric layers of the plurality of dielectric layers, wherein the ferroelectric material layer contacts the floating gate material layer and the at least one conductive layer.

Description

THREE-DIMENSIONAL INTEGRATED CIRCUIT MEMORY CELL HAVING A FERROELECTRIC FIELD EFFECT TRANSISTOR WITH A FLOATING GATE

TECHNICAL FIELD

Embodiments of the present description generally relate to the field of integrated circuit memory devices, and, more specifically, to three-dimensional integrated circuit memory cells having ferroelectric field effect transistors with a floating gate, memory systems including the same, and methods of manufacturing the same.

BACKGROUND ART

The integrated circuit industry is continually striving to produce ever faster and smaller integrated circuit devices for use in various server and mobile electronic products, including, but not limited to, computer server products and portable products, such as wearable integrated circuit systems, portable computers, electronic tablets, cellular phones, digital cameras, and the like. In particular, data center and server markets are continually seeking larger capacity, more compact, faster, and more reliable non-volatile memory storage solutions.

Various ways to achieve these goals may include increasing integration density and utilizing unique materials and configurations for transistor components within the memory devices, which may be an improvement over traditional silicon semiconductor channel based non-volatile memory devices. With regard to increasing integration density, memory devices are generally two-dimensional arrangement on an electronic substrate in a row direction, which required a large area to store a high capacity of data and, as the integration density of the two-dimensional increase, interference and disturbance between adjacent devices may increase. Thus, such memory device may be formed as three-dimensional structures.

In three dimensional structures, memory cells may be stacked in a direction substantially perpendicular to an electronic substrate. Each of the memory cells may be comprise a plurality of dielectric layers and a plurality of conductive layers that are alternately stacked, wherein a vertical gate dielectric layer extends through the dielectric layers and the conductive layers with a vertical channel layer adjacent the gate dielectric layer.

With regard to utilizing unique materials and configurations for transistor components within the memory devices, a variety of devices and materials have been developed or proposed, which may be an improvement over traditional silicon semiconductor channel based non-volatile memory devices. Such devices and materials may include tunneling field effect transistors, ferroelectric-gate field effect transistors, nonvolatile organic field-effect transistor, nanowire field effect transistors, and the like. However, each of these field-effect transistors may have issues with regard to reliability, speed, and difficulties with regard to manufacturing.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter of the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. It is understood that the accompanying drawings depict only several embodiments in accordance with the present disclosure and are, therefore, not to be considered limiting of its scope. The disclosure will be described with additional specificity and detail through use of the accompanying drawings, such that the advantages of the present disclosure can be more readily ascertained, in which:

FIG. 1 illustrates an oblique view of a layer stack structure, according to one embodiment of the present description.

FIG. 2 illustrates the layer stack structure of FIG. 1 having at least one via formed therethrough, according to an embodiment of the present description.

FIG. 3 illustrates a side cross-sectional view of a three-dimensional memory device, according to an embodiment of the present disclosure.

FIGs. 4-9 illustrate a method of fabricating a three-dimensional memory device by a recessed floating gate process, according to an embodiment of the present disclosure.

FIGs. 10-15 illustrate a method of fabricating a three-dimensional memory device by a replacement layer process, according to one embodiment of the present disclosure.

FIG. 16 is a flow chart of a process of fabricating an integrated circuit package, according to an embodiment of the present description.

FIG. 17 illustrates top plan views of a wafer and dice that may include any of the three-dimensional memory devices of any of the embodiments disclosed herein.

FIG. 18 illustrates a cross-sectional side view of an integrated circuit device that may include any of the three-dimensional memory devices of any of the embodiments disclosed herein. FIG. 19 is a cross-sectional side view of an integrated circuit device assembly that may include any of the three-dimensional memory devices of any of the embodiments disclosed herein.

FIG. 20 illustrates an electronic system, according to one embodiment of the present description.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. References within this specification to“one embodiment” or“an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present description. Therefore, the use of the phrase“one embodiment” or“in an embodiment” does not necessarily refer to the same embodiment. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description.

The terms“over”,“to”,“between” and“on” as used herein may refer to a relative position of one layer with respect to other layers. One layer“over” or“on” another layer or bonded“to” another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer“between” layers may be directly in contact with the layers or may have one or more intervening layers. Embodiments of the present description relate to a three-dimensional integrated circuit memory device having ferroelectric floating gates. Memory cells of the three- dimensional integrated circuit memory device may comprise a layered stack structure formed from a plurality of dielectric layers and at least one conductive layer wherein the at least one conductive layer is between a pair of dielectric layer of the plurality of dielectric layers. At least one via may be defined by a sidewall extending through the layered stack structure from an upper surface to a lower surface of the layered stack structure. A gate dielectric layer may be formed within the via, wherein the gate dielectric layer contacts the plurality of dielectric layers. A channel material layer may be formed within the via contacting the gate dielectric layer. A floating gate material layer may be formed between adjacent dielectric layers of the plurality of dielectric layers, wherein the floating gate material layer contacts the channel material layer. A ferroelectric material layer may be formed between adjacent dielectric layers of the plurality of dielectric layers, wherein the ferroelectric material layer contacts the floating gate material layer and the at least one conductive layer.

As shown in FIG. 1 , a memory cell may be formed by first providing or forming a layered stack structure 110 comprising a plurality of dielectric layers (illustrated as elements 112i-112₄) and at least one conductive layer (illustrated as elements 114i-1 14,) that are alternately stacked. As shown in FIG. 2, at least one via 120 may be formed through the layered stack structure 110, wherein the at least one via 120 is defined by at least one sidewall 122 extending from an upper surface 116 of the layered stack structure 110 to a lower surface 118 of the layered stack structure 110. The vias 120 may be formed by any technique known in the art, including, but not limited to, laser ablation, ion bombardment drilling, and lithography. Although FIGs. 1 and 2 illustrate four dielectric layers 112i-1124 and three conductive layers 114i-1143, it is understood that the embodiments of the present description are not so limited and there may be any appropriate number of dielectric and conductive layers.

The dielectric layers 112i-112₄ may be any appropriate dielectric material, including, but not limited to, silicon dioxide, doped silicon dioxide, silicon nitride, doped silicon oxide, low-k dielectrics, such as polyimide, polynorbomenes, benzocyclobutene, and

polytetrafluoroethylene, and the like. The conductive layers 114i-114₃ may be any appropriate conductive or semiconductive material, including, but not limited to, polysilicon, metals (such as tungsten, copper, aluminum, gold, silver, and alloys thereof), metal containing materials, and the like. The embodiments of the memory cells described herein may include a ferroelectric- gate field effect transistor. The operation of a ferroelectric-gate field effect transistor is well known in the art and will not be discussed herein for purposes of conciseness. However, standard ferroelectric-gate field effect transistors may have issues with speed and reliability due to endurance failures. Thus, the embodiments of the present description incorporate the ferroelectric-gate material into a floating gate configuration, as will be discussed, to order to improve speed and reliability of the transistor.

As shown in FIG. 3, a memory cell may be formed by first providing or forming the layered stack structure 110 with at least one via 120 may be formed through the layered stack structure 110, as described with regard to FIGs. 1 and 2. As shown in FIG. 4, the conductive layers 114i-1143 may be etched such that recesses 172 are formed therein. A ferroelectric material layer 132 may be formed on the sidewall 122 of the via 120 and in the recesses 172 (see FIG. 11), as shown in FIG. 5. The ferroelectric material layer 132 may be formed from any appropriate ferroelectric material. In one embodiment, the ferroelectric material layer 132 comprises hafnium and oxygen, such as hafnium oxide. The hafnium oxide can be doped, for example by silicon, zirconium, lanthanum, aluminum, and the like, and may have dopant concentrations between about 3 and 30% by weight. The ferroelectric material layer 132 can be formed by well-known techniques, such as by depositing a gate electrode material, such as atomic layer deposition (“ALD”).

As shown in FIG. 6, the floating gate material layer 134 may be formed on the ferroelectric material layer 132, such that the remainer of the recesses 172 (see FIG. 11) are filled with the floating gate material layer 134. The floating gate material layer 134 may be formed from any appropriate conductive material, including, but not limited to silicon and metals, such as ruthenium and aluminum, as well as metal nitride, such as titanium nitride and tantalum nitride. The floating gate material layer 134 can be formed by well-known techniques, such as by depositing a gate electrode material, such as chemical vapor deposition (“CVD”), physical vapor deposition (“PVD”), and atomic layer deposition (“ALD”).

As shown in FIG. 7, a portion of the ferroelectric material layer 132 and a portion of the floating gate material layer 134 may be removed, such as by etching, to form

discontinuous ferroelectric material layer portions l32d and discontinuous floating gate material layer portions l34d within the recesses 172 (see FIG. 11). The term“discontinuous” in this context means that the material layers do not extend from the upper surface 116 to the lower surfacel l8 in an uninterrupted manner.

As shown in FIG. 8, the gate dielectric layer 136 may be formed on the discontinuous floating gate material layer portions l34d, the discontinuous ferroelectric material layer portions 132, and the sidewall 122 of the via 120. The gate dielectric layer 136 may be formed from any well-known gate dielectric material, including but not limited to silicon dioxide (SiC ), silicon oxynitride (SiO_xN_y), silicon nitride (Si₃N₄), and high-k dielectric materials such as hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The gate dielectric layer 136 can be formed by well-known techniques, such as by depositing a gate electrode material, such as chemical vapor deposition (“CVD”), physical vapor deposition (“PVD”), and atomic layer deposition (“ALD”).

As shown in FIG. 9, the channel material layer 138 may be formed on the gate dielectric layer 136. As yet still further shown in FIG. 3, a channel material layer 138 may be formed on the gate dielectric layer 136. The channel material layer 138 may be formed from any well-known semiconducting material, including but not limited to silicon, germanium, silicon-germanium, amorphous oxide semiconductor (such as indium gallium zinc oxide), or a III-V compound semiconductor material. The channel material layer 138 can be formed by well-known techniques, such as by depositing a gate electrode material, such as chemical vapor deposition (“CVD”), physical vapor deposition (“PVD”), and atomic layer deposition (“ALD”).

As further shown in FIG. 9, the channel material layer 138 may be electrically to a source structure 142 proximate lower surface 118 of the layered stack structure 110 and the channel material layer 138 may be electrically connected to a drain structure 146 proximate upper surface 116 of the layered stack structure 110 to form a memory cell 150.

FIGs. 10-15 illustrate a replacement layer method of forming a memory cell, according to an embodiment of the present description. As shown in FIG. 10, a layered replacement stack structure 160 may be provided or formed comprising the plurality of dielectric layers 112i-1124 and at least one replacement layer (illustrated as elements 162i- l62₃) that are alternately stacked. As further shown in FIG. 10, the at least one via (shown as a first via 120i and a second via 1022) may be formed through the layered replacement stack structure 160.

As previously discussed, the dielectric layers 112i-1124 may be any appropriate dielectric material, including, but not limited to, silicon dioxide, doped silicon dioxide, silicon nitride, doped silicon oxide, low-k dielectrics, such as polyimide, polynorbomenes, benzocyclobutene, and polytetrafluoroethylene, and the like. The replacement layers 162i- 1623 may be any appropriate material that can be selectively removed, such as by etching, relative to the dielectric layers 112i-1124. In one embodiment, the dielectric layers 112i-112₄ may be silicon dioxide and the replacement layers 162i-162₃ may be silicon nitride.

As shown in FIG. 11, the gate dielectric layer 136 and the channel material layer 138 can be formed in the first via 102i and the second via 1022. as discussed with regard to FIGs. 8 and 9. As shown in FIG. 12, a trench 152 may be formed in the layered replacement stack structure 160 to expose each of the replacement layers 162i-162₃. The replacement layers 162i-162₃. of FIG. 12 may be removed, such as by an etching technique, through the trench 152, as shown in FIG. 13.

As shown in FIG. 14, the floating gate material layer 134 can be disposed between and in contact with the dielectric layers 112i-1 12₄. the ferromagnetic material layer 132 can be formed to contact the floating gate material layer 134, and the conductive layers 114i- 114₃, such as a tungsten fill, may be formed to contact the ferromagnetic material layer 132, by any technique known in the art. As shown in FIG. 15, the trench 152 (see FIG. 14) may be filled with a dielectric material 154 and a source contact 156 may be formed through the dielectric material 154 to contact a shared source structure 158. The channel material layers 138 within the first via 102i and the second via 1022 (see FIG. 14) may also be electrically connected to the shared source structure 158 proximate lower surface 118 of the layered stack structure 110. The channel material layer 138 within the first via 102i may be electrically connected to a first drain structure 146i proximate the upper surface 116 of the layered stack structure 110 to form a first memory cell 150i, and the channel material layer 138 within the second via l02₂ may be electrically connected to a second drain structure 1462 proximate the upper surface 116 of the layered stack structure 110 to form a second memory cell 1502.

FIG. 16 is a flow chart of a process 200 of fabricating a memory cell according to the various embodiments of the present description. As set forth in block 202, a layered stack structure may be formed comprising a plurality of dielectric layers and at least one conductive layer which are alternately stacked such that the at least one conductive layer is between a pair of dielectric layers of the plurality of dielectric layers. At least one via may be formed defined by a sidewall extending through the layered stack structure from an upper surface of the layered stack structure to a lower surface of the layered stack structure, as set forth in block 204. As set forth in block 206, a ferroelectric material layer may be formed within the at least one via contacting the at least one conductive layer of the layered stack structure. A floating gate material layer contacting the ferroelectric material layer, as set forth in block 208. As set forth in block 210, a fate dielectric layer may be formed contacting the floating gate material layer. A channel material layer may be formed contacting the date dielectric layer, as set forth in block 212.

The memory cells 150, 150i, and 1502 disclosed herein may be included in any suitable electronic device. FIG. 17 depicts top views of a wafer 400 and dice 410 that may be formed from the wafer 400. The dice 410 may include any of the memory cells 150, 150i, and l50₂ disclosed herein. The wafer 400 may include semiconductor material and may include one or more dice 410 having integrated circuit elements (e.g., memory cells 150,

150i, and 1502) formed on or above a surface of the wafer 400. Each of the dice 410 may be a repeating unit of a semiconductor product that includes any suitable device. After the fabrication of the semiconductor product is complete, the wafer 400 may undergo a singulation process in which the dice 410 are separated from one another to provide discrete "chips" of the semiconductor product. A die 410 may include one or more memory cells 150, 150i, and 1502 and/or supporting circuitry to route electrical signals to the memory cells 150, 150i, and 1502, as well as any other integrated circuit components. In some embodiments, the wafer 400 or the die 410 may include other memory devices, logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 410. For example, a memory device formed by multiple memory arrays (e.g., multiple sets of memory cells 150, 150i, and 1502) may be formed on a same die 410 as a processing device or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

FIG. 18 is a cross-sectional side view of an integrated circuit device 500 that may include any of the memory cells 150, 150i, and 1502 disclosed herein. The integrated circuit device 500 may be formed on a substrate 502 (e.g., the wafer 400 of FIG. 17) and may be included in a die (e.g., the die 410 of FIG. 17). The substrate 502 may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p- type materials systems (or a combination of both). The substrate 502 may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the substrate 502 may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the substrate 502. Although a few examples of materials from which the substrate 502 may be formed are described here, any material that may serve as a foundation for an integrated circuit device 500 may be used. The substrate 502 may be part of a singulated die (e.g., the dice 410 of FIG. 17) or a wafer (e.g., the wafer 400 of FIG. 17).

The integrated circuit device 500 may include one or more device layers 504 disposed on the substrate 502. The device layer 504 may include features of one or more

transistors 540 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 502. The device layer 504 may include, for example, one or more source and/or drain (S/D) regions 520, a gate 522 to control current flow in the transistors 540 between the S/D regions 520, and one or more S/D contacts 524 to route electrical signals to/from the S/D regions 520. The transistors 540 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 540 are not limited to the type and configuration depicted in FIG. 18 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap around or all-around gate transistors, such as nanoribbon and nano wire transistors.

Each transistor 540 may include a gate 522 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.

The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 540 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

In some embodiments, when viewed as a cross-section of the transistor 540 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

The S/D regions 520 may be formed within the substrate 502 adjacent to the gate 522 of each transistor 540. The S/D regions 520 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate 502 to form the S/D regions 520. An annealing process that activates the dopants and causes them to diffuse farther into the substrate 502 may follow the ion-implantation process. In the latter process, the substrate 502 may first be etched to form recesses at the locations of the S/D regions 520. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 520. In some implementations, the S/D regions 520 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 520 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 520.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 540) of the device layer 504 through one or more interconnect layers disposed on the device layer 504 (illustrated in FIG. 18 as interconnect layers 506-510). For example, electrically conductive features of the device layer 504 (e.g., the gate 522 and the S/D contacts 524) may be electrically coupled with the interconnect structures 528 of the interconnect layers 506-510. The one or more interconnect layers 506- 510 may form a metallization stack (also referred to as an "ILD stack") 519 of the integrated circuit device 500.

In some embodiments, one or more memory cells 150, 150i, and 1502 may be disposed in one or more of the interconnect layers 506-510, in accordance with any of the techniques disclosed herein. FIG. 18 illustrates a single memory array 100, comprising a plurality of memory cells 150, 150i, and l50₂, in the interconnect layer 508 for illustration purposes, but any number and structure of memory cells 150, 150i, and 1502 may be included in any one or more of the layers in a metallization stack 519. A memory cell 150, 150i, and 1502 (not shown) or the memory array 100 included in the metallization stack 519, in combination with computing logic (e.g., some or all of the transistors 540) in the integrated circuit device 500, may be referred to as an "embedded" memory array, as discussed above.

In embodiments in which the integrated circuit device 500 does not include any computing logic, but does include one or more memory cells 150, 150i, and 1502, or the memory array 100, the integrated circuit device 500 may be referred to as a "standalone" memory device. One or more memory cells 150, 150i, and l50₂, or the memory array 100 in the metallization stack 519 may be coupled to any suitable ones of the devices in the device layer 504, and/or to one or more of the conductive contacts 536 (discussed below).

The interconnect structures 528 may be arranged within the interconnect layers 506- 510 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 528 depicted in FIG. 18). Although a particular number of interconnect layers 506-510 is depicted in FIG. 18, embodiments of the present disclosure include integrated circuit devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures 528 may include lines 528a and/or vias 528b filled with an electrically conductive material such as a metal. The lines 528a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 502 upon which the device layer 504 is formed. For example, the lines 528a may route electrical signals in a direction in and out of the page from the perspective of FIG. 18. The vias 528b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 502 upon which the device layer 504 is formed. In some embodiments, the vias 528b may electrically couple lines 528a of different interconnect layers 506-510 together.

The interconnect layers 506-510 may include a dielectric material 526 disposed between the interconnect structures 528, as shown in FIG. 18. In some embodiments, the dielectric material 526 disposed between the interconnect structures 528 in different ones of the interconnect layers 506-510 may have different compositions; in other embodiments, the composition of the dielectric material 526 between different interconnect layers 506-510 may be the same.

A first interconnect layer 506 (referred to as Metal 1 or "Ml") may be formed directly on the device layer 504. In some embodiments, the first interconnect layer 506 may include lines 528a and/or vias 528b, as shown. The lines 528a of the first interconnect layer 506 may be coupled with contacts (e.g., the S/D contacts 524) of the device layer 504. A second interconnect layer 508 (referred to as Metal 2 or "M2") may be formed directly on the first interconnect layer 506. In some embodiments, the second interconnect layer 508 may include vias 528b to couple the lines 528a of the second interconnect layer 508 with the lines 528a of the first interconnect layer 506. Although the lines 528a and the vias 528b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 508) for the sake of clarity, the lines 528a and the vias 528b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual Damascene process) in some embodiments.

A third interconnect layer 510 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 508 according to similar techniques and configurations described in connection with the second interconnect layer 508 or the first interconnect layer 506. In some embodiments, the interconnect layers that are "higher up" in the metallization stack 519 in the integrated circuit device 500 (i.e., farther away from the device layer 504) may be thicker.

The integrated circuit device 500 may include a solder resist material 534 (e.g., polyimide or similar material) and one or more conductive contacts 536 formed on the interconnect layers 506-510. In FIG. 18, the conductive contacts 536 are illustrated as taking the form of bond pads. The conductive contacts 536 may be electrically coupled with the interconnect structures 528 and configured to route the electrical signals of the

transistor(s) 540 to other external devices. For example, solder bonds may be formed on the one or more conductive contacts 536 to mechanically and/or electrically couple a chip including the integrated circuit device 500 with another component (e.g., a circuit board).

The integrated circuit device 500 may include additional or alternate structures to route the electrical signals from the interconnect layers 506-510; for example, the conductive contacts 536 may include other analogous features (e.g., posts) that route the electrical signals to external components.

FIG. 19 is a cross-sectional side view of a device assembly 600 that may include any of the memory cells 150, 150i, and 1502 disclosed herein in one or more packages. A "package" may refer to an electronic component that includes one or more integrated circuit devices (e.g., the integrated circuit devices 500 discussed above with reference to FIG. 18) that are structured for coupling to other components; for example, a package may include a die coupled to a package substrate that provides electrical routing and mechanical stability to the die. The device assembly 600 includes a number of components disposed on a circuit board 602. The device assembly 600 may include components disposed on a first surface 640 of the circuit board 602 and an opposing second surface 642 of the circuit board 602;

generally, components may be disposed on one or both surfaces 640 and 642.

In some embodiments, the circuit board 602 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 602. In other embodiments, the circuit board 602 may be a package substrate or flexible board.

The device assembly 600 illustrated in FIG. 19 includes a package-on-interposer structure 636 coupled to the first surface 640 of the circuit board 602 by coupling

components 616. The coupling components 616 may electrically and mechanically couple the package-on-interposer structure 636 to the circuit board 602 and may include solder balls, male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure 636 may include a package 620 coupled to an interposer 604 by coupling components 618. The coupling components 618 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 616. Although a single package 620 is shown in FIG. 19, multiple packages may be coupled to the interposer 604; indeed, additional interposers may be coupled to the interposer 604. The interposer 604 may provide an intervening substrate used to bridge the circuit board 602 and the package 620. The package 620 may include one or more memory cells 150, 150i, 1502, for example. Generally, the interposer 604 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 604 may couple the package 620 (e.g., a die) to a ball grid array (BGA) of the coupling components 616 for coupling to the circuit board 602. In the embodiment illustrated in FIG. 19, the package 620 and the circuit board 602 are attached to opposing sides of the interposer 604; in other embodiments, the package 620 and the circuit board 602 may be attached to a same side of the interposer 604. In some embodiments, three or more components may be interconnected by way of the interposer 604.

The interposer 604 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 604 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 604 may include metal interconnects 608 and vias 610, including, but not limited to, through-silicon vias (TSVs) 606. The interposer 604 may further include embedded devices 614, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices (e.g., the memory cells 150, 150i, and 1502). More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 604. The package-on-interposer structure 636 may take the form of any of the package-on-interposer structures known in the art.

The device assembly 600 may include a package 624 coupled to the first surface 640 of the circuit board 602 by coupling components 622. The coupling components 622 may take the form of any of the embodiments discussed above with reference to the coupling components 616, and the package 624 may take the form of any of the embodiments discussed above with reference to the package 620. The package 624 may include one or more memory cells 150, 150i, and 1502, for example.

The device assembly 600 illustrated in FIG. 19 includes a package-on-package structure 634 coupled to the second face 642 of the circuit board 602 by coupling

components 628. The package-on-package structure 634 may include a package 626 and a package 632 coupled together by coupling components 630 such that the package 626 is disposed between the circuit board 602 and the package 632. The coupling components 628 and 630 may take the form of any of the embodiments of the coupling components 616 discussed above, and the packages 626 and 632 may take the form of any of the embodiments of the package 620 discussed above. Each of the packages 626 and 632 may include one or more memory cells 150, 150i, and 1502, for example.

FIG. 20 illustrates an electronic system or computing device 700 in accordance with one implementation of the present description. The computing device 700 may house a board 702. The board 702 may include a number of integrated circuit components attached thereto, including but not limited to a processor 704, at least one communication chip 706 A, 706B, volatile memory 708, (e.g., DRAM), non-volatile memory 710 (e.g., ROM), flash memory 712, a graphics processor or CPU 714, a digital signal processor (not shown), a crypto processor (not shown), a chipset 716, an antenna, a display (touchscreen display), a touchscreen controller, a battery, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a camera, and a mass storage device (not shown) (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the integrated circuit components may be physically and electrically coupled to the board 702. In some implementations, at least one of the integrated circuit components may be a part of the processor 704.

The communication chip enables wireless communications for the transfer of data to and from the computing device. The term“wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device may include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others

The term“processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

Any of the integrated circuit components within the computing device 700 may include memory cells 150, 150i, and 1502, or an array thereof, which comprises a layered stack structure comprising a plurality of dielectric layers and at least one conductive layer which are alternately stacked such that the at least one conductive layer is between a pair of dielectric layers of the plurality of dielectric layers; at least one via defined by a sidewall extending through the layered stack structure from an upper surface of the layered stack structure to a lower surface of the layered stack structure; a gate dielectric layer within the via, wherein the gate dielectric layer contacts the plurality of dielectric layers, a channel material layer within the via contacting the gate dielectric layer, a floating gate material layer between adjacent dielectric layers of the plurality of dielectric layers, wherein the floating gate material layer contacts the channel material layer; and a ferroelectric material layer between adjacent dielectric layers of the plurality of dielectric layers, wherein the ferroelectric material layer contacts the floating gate material layer and the at least one conductive layer.

In various implementations, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device may be any other electronic device that processes data.

It is understood that the subject matter of the present description is not necessarily limited to specific applications illustrated in FIGs. 1-20. The subject matter may be applied to other integrated circuit device and assembly applications, as will be understood to those skilled in the art.

The following examples pertain to further embodiments, wherein Example 1 is a memory cell comprising a layered stack structure comprising a plurality of dielectric layers and at least one conductive layer which are alternately stacked such that the at least one conductive layer is between adjacent dielectric layers of the plurality of dielectric layers; at least one via defined by a sidewall extending through the layered stack structure from an upper surface of the layered stack structure to a lower surface of the layered stack structure; a gate dielectric layer within the via, wherein the gate dielectric layer contacts the plurality of dielectric layers; a channel material layer within the via contacting the gate dielectric layer; a floating gate material layer between adjacent dielectric layers of the plurality of dielectric layers, wherein the floating gate material layer contacts the channel material layer; and a ferroelectric material layer between adjacent dielectric layers of the plurality of dielectric layers, wherein the ferroelectric material layer contacts the floating gate material layer and the at least one conductive layer.

In Example 2, the subject matter of Example 1 can optionally include a source structure electrically connected to the channel material layer proximate the lower surface of the layered stack structure and a drain structure electrically connected to the channel material layer proximate the upper surface of the layered stack structure.

In Example 3, the subject matter of either Example 1 or 2 can optionally include the ferroelectric material layer comprising hafnium and oxygen.

In Example 4, the subject matter of Example 3 can optionally the ferroelectric material layer further comprising a dopant.

In Example 5, the subject matter of Example 4 can optionally include the dopant being selected from a group consisting of silicon, zirconium, lanthanum, and aluminum.

The following examples pertain to further embodiments, wherein Example 6 is an integrated circuit device comprising at least one logic transistors and at least one memory cell electrically connected to the at least one logic transistor, wherein the at least one memory cell comprises a layered stack structure comprising a plurality of dielectric layers and at least one conductive layer which are alternately stacked such that the at least one conductive layer is between a pair of dielectric layers of the plurality of dielectric layers; at least one via defined by a sidewall extending through the layered stack structure from an upper surface of the layered stack structure to a lower surface of the layered stack structure; a gate dielectric layer within the via, wherein the gate dielectric layer contacts the plurality of dielectric layers; a channel material layer within the via contacting the gate dielectric layer; a floating gate material layer between adjacent dielectric layers of the plurality of dielectric layers, wherein the floating gate material layer contacts the channel material layer; and a ferroelectric material layer between adjacent dielectric layers of the plurality of dielectric layers, wherein the ferroelectric material layer contacts the floating gate material layer and the at least one conductive layer.

In Example 7, the subject matter of Example 6 can optionally include a source structure electrically connected to the channel material layer proximate the lower surface of the layered stack structure and a drain structure electrically connected to the channel material layer proximate the upper surface of the layered stack structure.

In Example 8, the subject matter of either Example 6 or 7 can optionally include the ferroelectric material layer comprising hafnium and oxygen.

In Example 9, the subject matter of Example 8 can optionally the ferroelectric material layer further comprises a dopant. In Example 10, the subject matter of either Example 7 or 8 can optionally include the dopant being selected from a group consisting of silicon, zirconium, lanthanum, and aluminum.

The following examples pertain to further embodiments, wherein Example 11 is an electronic system, comprising a board and an integrated circuit component attached to the board, wherein the integrated circuit component includes at least one memory cell comprising a layered stack structure comprising a plurality of dielectric layers and at least one conductive layer which are alternately stacked such that the at least one conductive layer is between a pair of dielectric layers of the plurality of dielectric layers; at least one via defined by a sidewall extending through the layered stack structure from an upper surface of the layered stack structure to a lower surface of the layered stack structure; a gate dielectric layer within the via, wherein the gate dielectric layer contacts the plurality of dielectric layers; a channel material layer within the via contacting the gate dielectric layer; a floating gate material layer between adjacent dielectric layers of the plurality of dielectric layers, wherein the floating gate material layer contacts the channel material layer; and a ferroelectric material layer between adjacent dielectric layers of the plurality of dielectric layers, wherein the ferroelectric material layer contacts the floating gate material layer and the at least one conductive layer.

In Example 12, the subject matter of Example 11 can optionally include a source structure electrically connected to the channel material layer proximate the lower surface of the layered stack structure and a drain structure electrically connected to the channel material layer proximate the upper surface of the layered stack structure.

In Example 13, the subject matter of either Example 11 or 12 can optionally include the ferroelectric material layer comprising hafnium and oxygen.

In Example 14, the subject matter of Example 13 can optionally the ferroelectric material layer further comprises a dopant.

In Example 15, the subject matter of Example 14 can optionally include the dopant is selected from a group consisting of silicon, zirconium, lanthanum, and aluminum.

The following examples pertain to further embodiments, wherein Example 16 is a method of forming a memory cell, comprising forming a layered stack structure comprising a plurality of dielectric layers and at least one conductive layer which are alternately stacked such that the at least one conductive layer is between a pair of dielectric layers of the plurality of dielectric layers; forming at least one via defined by a sidewall extending through the layered stack structure from an upper surface of the layered stack structure to a lower surface of the layered stack structure; forming a gate dielectric layer within the via, wherein the gate dielectric layer contacts the plurality of dielectric layers; forming a channel material layer within the via contacting the gate dielectric layer; forming a floating gate material layer between adjacent dielectric layers of the plurality of dielectric layers, wherein the floating gate material layer contacts the channel material layer; and forming a ferroelectric material layer between adjacent dielectric layers of the plurality of dielectric layers, wherein the ferroelectric material layer contacts the floating gate material layer and the at least one conductive layer.

In Example 17, the subject matter of Example 16 can optionally include forming a source structure electrically connected to the channel material layer proximate the lower surface of the layered stack structure and forming a drain structure electrically connected to the channel material layer proximate the upper surface of the layered stack structure.

In Example 18, the subject matter of either Example 16 or 17 can optionally include forming the ferroelectric material layer comprising forming a layer comprising hafnium and oxygen.

In Example 19, the subject matter of Example 18 can optionally include forming the ferroelectric material layer further comprising doping the layer comprising hafnium and oxygen.

In Example 20, the subject matter of Example 19 can optionally include doping the layer comprising hafnium and oxygen with a dopant selected from a group consisting of silicon, zirconium, lanthanum, and aluminum.

In Example 21, the subject matter of either Example 16 to 17 can optionally include forming at least one recess formed in the at least one conductive layer of the layered stack structure extending from the at least one via, wherein the ferroelectric material layer resides within the recess without contacting the sidewall of the at least one via, and wherein the floating gate contacts the ferroelectric material layer within the recess without contacting the sidewall of the at least one via.

In Example 22, the subject matter of Example 21 can optionally include forming the gate dielectric layer contacting the floating gate material layer, the ferroelectric material layer, and the plurality of dielectric layers of the layered stack structure within the at least one via. In Example 23, the subject matter of Example 21 can optionally include forming the gate dielectric layer to contact the floating gate material layer without contacting the ferroelectric material layer.

Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.

Claims

CLAIMS What is claimed is:

1. A memory cell, comprising:

a layered stack structure comprising a plurality of dielectric layers and at least one conductive layer which are alternately stacked such that the at least one conductive layer is between adjacent dielectric layers of the plurality of dielectric layers;

at least one via defined by a sidewall extending through the layered stack structure from an upper surface to a lower surface of the layered stack structure;

a gate dielectric layer within the via, wherein the gate dielectric layer contacts the plurality of dielectric layers;

a channel material layer within the via contacting the gate dielectric layer;

a floating gate material layer between adjacent dielectric layers of the plurality of dielectric layers, wherein the floating gate material layer contacts the channel material layer; and

a ferroelectric material layer between adjacent dielectric layers of the plurality of dielectric layers, wherein the ferroelectric material layer contacts the floating gate material layer and the at least one conductive layer.

2. The memory cell of claim 1, further comprising:

a source structure electrically connected to the channel material layer proximate the lower surface of the layered stack structure; and

a drain structure electrically connected to the channel material layer proximate the upper surface of the layered stack structure.

3. The memory cell of either claim 1 or 2, wherein the ferroelectric material layer comprises hafnium and oxygen.

4. The memory cell of claim 3, wherein the ferroelectric material layer further comprises a dopant.

5. The memory cell of claim 4, wherein the dopant is selected from a group consisting of silicon, zirconium, lanthanum, and aluminum.

6. An integrated circuit device, comprising:

at least one logic transistor, and

at least one memory cell electrically connected to the at least one logic transistor, wherein the at least one memory cell comprises:

at least one via defined by a sidewall extending through the layered stack structure from an upper surface of the layered stack structure to a lower surface of the layered stack structure;

a channel material layer within the via contacting the gate dielectric layer; a floating gate material layer between adjacent dielectric layers of the plurality of dielectric layers, wherein the floating gate material layer contacts the channel material layer; and

7. The integrated circuit device of claim 6, further comprising:

8. The integrated circuit device of either claim 6 or 7, wherein the ferroelectric material layer comprises hafnium and oxygen.

9. The integrated circuit device of claim 8, wherein the ferroelectric material layer further comprises a dopant.

10. The integrated circuit device of claim 4, wherein the dopant is selected from a group consisting of silicon, zirconium, lanthanum, and aluminum.

11. An electronic system, comprising:

a board; and

an integrated circuit component attached to the board, wherein the integrated circuit component includes at least one memory cell comprising:

12. The electronic system of claim 11, further comprising:

13. The electronic system of either claim 11 or 12, wherein the ferroelectric material layer comprises hafnium and oxygen.

14. The electronic system of claim 13, wherein the ferroelectric material layer further comprises a dopant.

15. The electronic system of claim 14, wherein the dopant is selected from a group consisting of silicon, zirconium, lanthanum, and aluminum.

16. A method of forming a memory cell, comprising:

forming a layered stack structure comprising a plurality of dielectric layers and at least one conductive layer which are alternately stacked such that the at least one conductive layer is between adjacent dielectric layers of the plurality of dielectric layers;

forming at least one via defined by a sidewall extending through the layered stack structure from an upper surface of the layered stack structure to a lower surface of the layered stack structure;

forming a gate dielectric layer within the via, wherein the gate dielectric layer contacts the plurality of dielectric layers;

forming a channel material layer contacting the gate dielectric layer;

forming a floating gate material layer between adjacent dielectric layers of the plurality of dielectric layers, wherein the floating gate material layer contacts the channel material layer; and

forming a ferroelectric material layer between adjacent dielectric layers of the plurality of dielectric layers, wherein the ferroelectric material layer contacts the floating gate material layer and the at least one conductive layer.

17. The method of claim 16, further comprising:

forming a source structure electrically connected to the channel material layer proximate the lower surface of the layered stack structure; and

forming a drain structure electrically connected to the channel material layer proximate the upper surface of the layered stack structure.

18. The method of either claim 16 or 17, wherein forming the ferroelectric material layer comprises forming a layer comprising hafnium and oxygen.

19. The method of claim 18, wherein forming the ferroelectric material layer further comprises doping the layer comprising hafnium and oxygen.

20. The method of claim 19, wherein doping the layer comprising hafnium and oxygen comprises doping the layer comprising hafnium and oxygen with a dopant selected from a group consisting of silicon, zirconium, lanthanum, and aluminum.

21. The method of either claim 16 or 17, further comprising forming at least one recess in the at least one conductive layer of the layered stack structure extending from the at least one via, wherein the ferroelectric material layer resides within the recess without contacting the sidewall of the at least one via, and wherein the floating gate contacts the ferroelectric material layer within the recess without contacting the sidewall of the at least one via.

22. The method of claim 21, wherein forming the gate dielectric layer comprises forming the gate dielectric layer to contact the floating gate material layer, the ferroelectric material layer, and the plurality of dielectric layers of the layered stack structure within the at least one via.

23. The method of claim 21, wherein forming the gate dielectric layer comprises forming the gate dielectric layer to contact the floating gate material layer without contacting the ferroelectric material layer.