KR102626193B1 - Capacitive-coupled non-volatile thin-film transistor strings in three dimensional arrays - Google Patents

Abstract

Multi-gate NOR flash thin-film transistor (TFT) string arrays are composed of three-dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer connected to substrate circuitry. Data storage in the active strip is provided by a number of control gates provided by adjacent local word lines and a charge storage element between the active strips. The parasitic capacitance of each active strip is used to eliminate the wiring ground connection to the shared source or virtual source, making it semi-floating. A pre-charge voltage temporarily supplied from the board through a single port per active strip provides the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. to provide. TFTs on multiple active strips can be pre-charged separately and then read, programmed and erased together in massively parallel operation.

Description

CAPACITIVE-COUPLED NON-VOLATILE THIN-FILM TRANSISTOR STRINGS IN THREE DIMENSIONAL ARRAYS}

Cross-references to related applications

This invention is filed on August 26, 2016 and is entitled “Capacitive-Coupled Non-Volatile Thin-Film Transistor Strings in Three Dimensional Arrays” and is co-pending U.S. Provisional Patent Application (“Co-Pending Provisional Application”) No. No. 15/248,420; (i) Co-pending U.S. Provisional Application filed September 30, 2015 and entitled “Multi-gate NOR Flash Thin-film Transistor Strings Arranged in Stacked Horizontal Active Strips With Vertical Control Gates” (“Co-pending Provisional Application I”) ) No. 62/235,322; (ii) U.S. Provisional Application No. 62/260,137, filed November 25, 2015 and entitled “Three-dimensional Vertical NOR Flash Thin-film Transistor Strings” (“Co-pending Provisional Application II”); U.S. Provisional Application (“Co-Pending Provisional Application”) No. 15/, filed July 26, 2016 and entitled “Multi-Gate NOR Flash Thin-film Transistor Strings Arranged in Stacked Horizontal Active Strips With Vertical Control Gates” No. 220,375; and co-pending U.S. Provisional Application No. 62/363,189, entitled “Capacitive Coupled Non-Volatile Thin-film Transistor Strings,” filed July 15, 2016 (“Co-Pending Provisional Application III”), and the objection Claim priority. Co-pending Provisional Application, Co-pending Provisional Application I, Co-pending Provisional Application II, Co-pending Provisional Application, and Co-pending Provisional Application III are hereby incorporated by reference in their entirety.

Technology field

The present invention relates to high-density memory structures. In particular, the present invention relates to a high-density, low-read-latency memory structure formed by interconnected thin-film storage elements (e.g., thin-film storage transistors or "TFTs" consisting of NOR-type TFT strings or "NOR strings"). It relates to stacks of.

In this disclosure, a memory circuit structure is described. These memory circuit structures can be fabricated on planar semiconductor substrates (eg, silicon wafers) using conventional fabrication processes. For clarity in this description, the term "vertical" refers to a direction perpendicular to the surface of the semiconductor substrate, and the term "horizontal" refers to any direction parallel to the surface of the semiconductor substrate.

A number of high-density non-volatile memory structures, sometimes referred to as “three-dimensional vertical NAND strings,” are known in the art. Many of these high-density memory structures are formed using thin-film storage transistors (TFTs) formed from deposited thin films (e.g., polysilicon thin films), organized into arrays of “memory strings”. do. One type of memory string is referred to as a NAND memory string, or simply “NAND string.” A NAND string consists of multiple TFTs connected in series. Reading or programming any of the series-connected TFTs requires activation of all series-connected TFTs in the NAND string. Under this NAND arrangement, active TFTs that are not read or programmed may experience undesirable program-disturb or read-disturb conditions. Additionally, TFTs formed from polysilicon thin films have lower channel mobility and therefore higher resistance than conventional transistors formed on single crystal silicon substrates. The higher series resistance in NAND strings actually limits the number of TFTs in a string, typically less than 64 or 124 TFTs. The low read current required to be conducted through long NAND strings results in long latency.

Another type of high-density memory structure is referred to as a NOR memory string or “NOR string.” A NOR string includes a number of storage transistors each connected to a shared source region and a shared drain region. Therefore, the transistors in the NOR string are connected in parallel so that the read current in the NOR string conducts with a lower resistance than the read current through the NAND string. To read or program a storage transistor in a NOR string, except when the storage transistor needs to be activated (i.e. "on" or conducting), all other storage transistors in the NOR string must be in a dormant state (i.e. , may be kept “off” or non-conducting. As a result, the NOR string allows faster detection of which storage transistor is active to be read. In a conventional NOR transistor, when an appropriate voltage is applied to the control gate, electrons are accelerated in the channel region by the voltage difference between the source region and the drain region, and a charge-trapping layer between the control gate and the channel region. ) is programmed by the channel hot-electron injection technique. Channel thermal electron injection programming requires relatively high electron currents to flow through the channel region, limiting the number of transistors that can be programmed in parallel. Unlike transistors that are programmed by hot electron injection, in transistors that are programmed by Fowler-Nordheim tunneling or by direct tunneling, the channel is programmed by a high electric field applied between the control gate and the source and drain regions. Electrons are injected from the region into the charge confinement layer. Fowler-Nordheim tunneling and direct tunneling are much more efficient than channel hot electron injection and allow massively parallel programming; However, this tunneling is sensitive to program disturb conditions.

A 3D NOR memory array is disclosed in U.S. Patent No. 8,630,114 to H.T Lue, entitled “Memory Architecture of 3D NOR Array,” filed on March 11, 2011, and registered on January 14, 2014.

US2016/0086970 A1, titled “Three-Dimensional Non-Volatile NOR-type Flash Memory,” filed on September 21, 2015 and published on March 24, 2016, by Haibing Peng Consisting of an array of basic NOR memory groups, with each memory cell stacked along a horizontal direction parallel to the semiconductor substrate with source and drain electrodes shared by all field effect transistors located on one or two opposite sides of the conducting channel. A non-volatile NOR flash memory device is disclosed.

A three-dimensional NAND memory structure is described, for example, in the U.S. patent by Alsmeier et al., entitled “Compact Three Dimensional Vertical NAND and Methods of Making Thereof,” filed January 30, 2013, and issued November 4, 2014. Disclosed in No. 8,878,278. Alsmeier describes “terabit cell array transistor (TCAT)” NAND arrays (Figure 1a) and “pipe-shaped bit-cost scalable (P-BiCS)” flash memory (Figure 1a). 1b), and “vertical NAND” memory string structures. Likewise, U.S. Patent No. 7,005,350 to Walker et al., entitled “Method for Fabricating Programmable Memory Array Structures Incorporating Series -Connected Transistor Strings,” filed on December 31, 2002, and granted on February 28, 2006 (“Walker I") also discloses multiple three-dimensional high-density NAND memory structures.

Walker's U.S. Patent No. 7,612,411 ("Walker II"), entitled "Dual-Gate Device and Method," filed August 3, 2005, and granted November 3, 2009, has a common area of activity. A “dual gate” memory structure is disclosed that serves independently controlled storage elements in two NAND strings formed on opposite sides of a.

U.S. Patent No. 6,744,094 to Forbes ("Forbes"), entitled "Floating Gate Transistor with Horizontal Gate Layers Stacked Next to Vertical Body," filed May 3, 2004, and granted October 3, 2006, covers adjacent parallel A memory structure having a vertical body transistor with a horizontal gate layer is disclosed.

U.S. Patent No. 6,580,124 to Cleaves et al., entitled “Multigate Semiconductor Device with Vertical Channel Current and Method of Fabrication,” filed August 14, 2000, and issued June 17, 2003, describes a device for producing a transistor along the vertical surface of a transistor. Disclosed is a multi-bit memory transistor having two or four charge storage media formed.

A three-dimensional memory structure containing horizontal NAND strings controlled by vertical polysilicon gates was presented by W. Kim et al., 2009 Symposium on VLSI Tech. Dig. of Technical Papers, pp 188-189, published in the paper “Multi-layered Vertical gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage.” Additionally, another three-dimensional memory structure containing vertical polysilicon gates and horizontal NAND strings has been described by H.T. By Lue et al., 2010 Symposium on VLSI: Tech. Dig. It is disclosed in the paper “A Highly Scalable 8-Layer 3D Vertical-gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device” published in Of Technical Papers, pp.131-132.

U.S. Patent No. 8,026,521 to Zvi Or-Bach et al., entitled “Semiconductor Device and Structure,” filed on October 11, 2010, and registered on September 27, 2011, states that the first and second layers are horizontally oriented. Disclosed are first and second layers of layer-transferred mono-crystallized silicon including transistors. In that structure, a second layer of horizontally oriented transistors overlaps a first layer of horizontally oriented transistors, and each group of horizontally oriented transistors has a side gate.

In the memory structures discussed herein, the stored information is represented by a stored charge that can be introduced using any of a variety of techniques. For example, Eitan's U.S. Patent No. 5,768,192, entitled "Memory Cell Utilizing Asymmetrical Charge-trapping," filed July 23, 1996, and granted June 16, 1998, is based on the thermal electron channel injection technique. Initiates operation of the NROM type memory transistor.

Transistors that have a conventional non-volatile memory transistor structure but have a short retention time may be referred to as “quasi-volatile.” In this context, conventional non-volatile memory has data retention times exceeding decades. Planar quasi-volatile memory transistors on single crystal silicon substrates were developed by H.C. By Wann and C.Hu, IEEE Electron Device letters, Vol. 16, no. It is disclosed in the paper "High-Endurance Ultra-Thin Tunnel Oxide in Monos Device Structure for Dynamic Memory Application" published on November 11, 1995, pp 491-493. A quasi-volatile 3D NOR array with quasi-volatile memory is disclosed in US Patent No. 8,630,114 to H.T Lue, discussed above.

According to one embodiment of the invention, an array of memory cells includes TFTs formed in stacks of horizontal active strips driven parallel to the surface of a silicon substrate and vertical local words driven along one or both sidewalls of the active strips. and a control gate in a line, the control gate being separated from the active strip by one or more charge storage elements. Each active strip includes at least one channel layer formed between two shared source or drain layers. TFT consists of NOR strings. The TFTs associated with each activity strip may belong to one or two NOR strings depending on whether one or both sides of each activity strip are used.

In one embodiment, only one of the shared source or drain layers in the active strip is connected by a conductor to the supply voltage through the selection circuit, while the other source or drain layers have a voltage determined by the amount of charge provided to the source or drain layer. is maintained. Before a read, write, or erase operation, some or all of the TFTs in the NOR string along the active strip that are not selected for the read, write, or erase operation act as strip capacitors, and the channel and source or drain layers of the active strip act as strip capacitors. One capacitor plate is provided, and the control gate electrode within the TFT of the NOR string, referenced to ground, provides another capacitor plate. The strip capacitor is precharged prior to a read, write, or erase operation by turning on one or more TFTs (“precharge TFTs”) to instantaneously transfer charge to the strip capacitor from a source or drain layer connected to a voltage source by a conductor. After the pre-charge operation, the selection circuit is deactivated such that the pre-charged source or drain layer remains substantially floating at the pre-charged voltage. In that state, the charged strip capacitor provides a virtual reference voltage for read, write or erase operations. The pre-charged state enables massively parallel read, write or erase operations on multiple addressed TFTs. In this way, multiple NOR strings of TFTs on one or more active strips in one or more blocks of the memory array can be read, written, or erased concurrently. In fact, blocks on the memory array can be pre-charged for program or erase operations, while other blocks within the memory array can also be pre-charged for read operations.

In one embodiment, the TFT is formed using both vertical side edges of each active strip, and vertical local wordlines are provided along both vertical side edges of the active strip. In that embodiment, a local wordline along one of the vertical edges of the active strip is touched by a horizontal global wordline provided above the active strip, while a local wordline along the other vertical edge of the active strip is provided below the active strip. By touching the horizontal global word line, double-density is achieved. All global word lines can be driven in a direction transverse to the direction along the length of the corresponding active strip. Higher storage densities can be achieved by storing more than one bit of data in each TFT.

Configuring TFTs with NOR strings in memory arrays rather than prior art NAND strings is associated with (i) reduced read latency that approaches that of dynamic random access memory (DRAM) arrays, and (ii) long NAND strings. (iii) reduced sensitivity to read-disturb and program-disturb conditions known to occur, (iii) lower cost per bit and reduced power loss associated with planar NAND or 3D NAND arrays, and (iv) multiple The activity of results in the ability to read, write or erase the TFT on the strip together.

According to one embodiment of the invention, changes in threshold voltage within a NOR string in a block can be compensated for by providing an electrically programmable reference NOR string within the block. The impact on the read operation due to the background leakage current inherent in the NOR string can be substantially eliminated by comparing the sensing results of the TFT being read with that of the TFT being read from the reference NOR string. In other embodiments, the charge storage elements of each TFT may have their structure modified to provide high write/erase cycle endurance (even with shorter data retention times requiring periodic refreshing). In this detailed description, such TFTs that have higher write/erase cycle endurance but shorter retention times than conventional memory TFTs (e.g., TFTs in conventional NAND strings) are referred to as “quasi-volatile.” However, because these quasi-volatile TFTs require significantly less frequent refreshes than conventional DRAM circuits, the NOR strings of the present invention may be used in place of DRAM in some applications. Using the NOR string of the present invention in DRAM applications allows for a substantially lower cost per bit figure of merit compared to conventional DRAM and substantially lower read latency compared to conventional NAND strings.

According to some embodiments of the invention, the active strip is manufactured in a semiconductor process where the source or drain layer, and the channel layer are formed and annealed separately for each plane in the stack. In other embodiments, the source or drain layers are annealed individually or collectively (i.e., in a single step for both the source or drain layers) before forming the channel layer together in a single step.

The invention will be better understood upon consideration of the detailed description below in conjunction with the accompanying drawings.

1A-1 shows a plane (e.g., plane 110) and an activity strip (e.g., plane 110) in one memory array or block 100 formed on a substrate 101, according to one embodiment of the invention. , a conceptualized memory structure showing an array of memory cells comprised of active strips 112).
1A-2 shows that the memory cells of the memory array or block 100 of FIG. 1A-1 are divided into a page (e.g., page 113), a slice (e.g., slice ( 114)) and columns (e.g., columns 115).
Figure 1B shows a basic circuit diagram of four NOR string pairs, with each NOR string pair located in each of the four planes, according to one embodiment of the invention; The corresponding TFTs of each NOR string share common vertical local word lines.
Figure 1C shows a basic circuit diagram of four NOR strings, with each NOR string located in each of the four planes, according to one embodiment of the invention; The corresponding TFTs of each NOR string share a common local word line.
2A shows active layers 202-0 to 202- (each separated from the next active layer by a separation layer 203-0 to 203-7), according to one embodiment of the present invention. 7) shows a cross-sectional view in the YZ plane of the semiconductor structure 200 after it has been formed on the semiconductor substrate 201, but before the formation of each active strip.
2B-1 shows semiconductor structure 220a with N ⁺ sublayers 221 and 223 and P ^- sublayer 222; Semiconductor structure 220a may be used to implement any of active layers 202-0 through 202-7 of Figure 2A, according to one embodiment of the present invention.
Figure 2B-2 shows semiconductor structure 220b with a metal sublayer 224 added to semiconductor structure 220a of Figure 2B-1; Metal sublayer 224 is formed adjacent to N ⁺ sublayer 223 according to one embodiment of the present invention.
Figure 2B-3 shows semiconductor structure 220c with a metal sublayer 224 added to semiconductor structure 220a of Figure 2B-1; The metal sublayer 224 is formed adjacent to either the N ⁺ sublayer 221 or the N ⁺ sublayer 223 according to one embodiment of the present invention.
FIG. 2B-4 shows the semiconductor structure of FIG. 2B-1 after partial annealing by a shallow rapid laser anneal step (represented by laser device 207), according to one embodiment of the present invention. (220a) is shown.
2B-5 shows the semiconductor structure of FIG. 2B-1 after including additional ultra-thin sublayers 221-d and 223-d in the semiconductor structure 220a of FIG. 2B-1, according to an embodiment of the present invention. Structure 220d is shown.
2C shows buried contacts connecting the N ⁺ sublayer 223 of active layers 202-0 and 202-1 to circuits 206-0 and 206-1 in semiconductor substrate 201. , 205-0 and 205-1) shows a cross-sectional view in the YZ plane of structure 200 in FIG. 2A.
FIG. 2D shows the formation of trench 230 in structure 200 of FIG. 2A in a cross-section in the XY plane through active layer 202-7 in a portion of semiconductor structure 200 of FIG. 2A.
FIG. 2E shows a portion of the semiconductor structure 200 of FIG. 2A showing charge confinement layers 231L and 231L on opposite side walls of the active strip along trench 230 in a cross-section in the XY plane through active layer 202-7. 231R) is shown to be deposited.
FIG. 2F shows depositing a conductor 208 (e.g., N+ or P+ doped polysilicon or metal) to fill trench 230 of FIG. 2E.
FIG. 2G shows that after photo-lithographical patterning and etching steps on the semiconductor structure of FIG. 2F, the exposed portions of the deposited conductors 208 are removed to form local conductors (“wordlines”) 208W and Achieving a pre-filled word line 208-CHG shows filling the resulting shaft 209 with an insulating material, or alternatively leaving the shaft as air gap isolation.
FIG. 2H shows a cross-sectional view of the ZX plane through a row of local word lines 208W of FIG. 2G, showing active strips in active layers 202-7 and 202-6.
FIG. 2I shows that the local word line 208W of FIG. 2H is connected to one of the global word lines 208g-a (routed in one or more conductive layers provided above active layers 202-0 to 202-7), or to (active) Embodiments of the present invention (EMB- 1) (see also Figure 4a).
Figure 2ia (Figure 2i-1) shows that the local word line 208W-s or the local pre-charge word line 208-CHG is connected to the global word line 208g-s, and the local word line 208W-a is connected to the global word line 208g-s. Connected to the global word line 208g-a, each active layer with an ^N _ss , V _bl, V _pgm , V _inhibit and V _erase ), the horizontal active layer 202 of the embodiment of FIG. 2I (EMB-1), which is shown as connected via select circuitry to any of the decoding, sensing and other circuits. -4 to 202-7) show three-dimensional drawings; These circuits are schematically shown as circuits 206-0 and 206-1 on substrate 201.
Figure 2j shows an embodiment of the invention (EMB-2) in which only top global word lines 208g-a are provided - i.e., no bottom global word lines; In embodiment EMB-2 the local word line 208W-STG along one edge of the active strip is staggered with respect to the local word line 208W-a along the opposite edge of the active strip (also , see Figure 4b).
2K shows a pair of TFTs (e.g., TFTs) formed on opposite sidewalls of an adjacent active strip and its respective adjacent charge confinement layer (e.g., confinement layers 231L and 231R), each of the local word lines 208W. shows an embodiment of the invention (EMB-3) controlling TFTs 281 and 283; Isolation trenches 209 are etched to separate each TFT pair (e.g., TFTs 281 and 283) from adjacent TFT pairs (e.g., TFTs 285 and 287) (see also Figure 4C).
2KA (FIG. 2K-1) shows an optional P ^- doped filler 290 provided to fill part or all of the isolation trench 209 to selectively connect the P-sublayer 222 to the substrate circuitry. An embodiment (EMS-3) is shown in Figure 2K; P-doped pillar 290 may supply a back bias voltage (V _bb ) or an erase voltage (V _erase ) to P ^- sublayer 222 (see also FIGS. 3A and 4C ).
Figure 3A shows the method and circuit elements used to set the source voltage (V _ss ) in the N ⁺ sublayer 221; Specifically, the source voltage (V _ss ) is connected to the wire decoded source line connection 280 (shown in dashed lines), or alternatively to the pre-charged TFT 303 and the bit line voltages (V _ss, V _bl , It can be set by activating the decoded bit line connection 270 to any of V _pgm , V _inhibit and V _erase ).
FIG. 3B shows the source, drain, selected word line, and unselected word lines for the circuit of FIG. 3A during a read operation in which the N ⁺ sublayer 221 is applied with a source voltage (V _ss ) through wired connection 280. An example waveform of line voltage is shown.
FIG. 3C shows a semi-floating source region after the N ⁺ sublayer 221 is instantaneously precharged to V _ss (~0V) by the precharge word line 208-CHG. Provides example waveforms for the source, drain, selected word line, unselected word line, and precharge word line voltages for the circuit of FIG. 3A during a read operation.
4A is an implementation of FIGS. 2I and 2IA (FIG. 2I-1), showing contacts 291 connecting local word lines 208W-a to global word lines 208g-a at the top of the memory array. Example (EMB-1) is a cross section in the XY plane; Likewise, local word line 208W-s is connected to global word line 208g-s (not shown) running at the bottom of the memory substantially parallel to the top global word line.
Figure 4b shows a staggered configuration of TFTs along both sides of each active strip, with local word lines 208W-a and staggered local word lines 208W-STG only on the top global word lines 208g-a; Or alternatively, a cross-section in the
FIG. 4C connects local word line 208W-a to global word line 208g-a at the top of the memory array, or alternatively to global word line 208g-s at the bottom of the array (not shown). 2K and FIG. 2K , showing contact 291 and isolation trench 209 separating TFT pairs 281 and 283 and TFT pairs 285 and 287 on adjacent active strips of active layer 202-7. This is a cross section in the XY plane of the embodiment (EMB-3) of 2ka (Figure 2k-1).
4D shows an active layer, optionally including one or more optional P ^- doped pillars 290 that provide a substrate back bias voltage (V _bb ) and an erase voltage (V _erase ) to the P-sublayer 222. Cross section in the XY plane of the embodiment (EMB-3) of FIGS. 2K and 2KA (FIG. 2K-1) through 202-7.
FIG. 5A shows horizontal active layers 502-0 to 502-7 formed one above the other and separated by respective separation layers 503-0 to 503-7 (of material ISL) on the semiconductor substrate 201. A cross-sectional view through the YZ plane of the semiconductor structures is shown, after being separated from each other.
5B shows buried contacts 205-0 and 205-1, where N ⁺ sublayers 523-1 and 523-0 are connected to circuits 206-0 and 206-1 in semiconductor substrate 201. It is a cross section of the YZ plane through .
FIG. 5C is a planar view of structure 500 after trench 530 along the Y direction has been anisotropically etched through active layers 502-7 through 502-0 to reach below landing pad 264 of FIG. 5B. A cross section in the ZX plane, showing active layers 502-6 and 502-7; The SAC2 material filling trench 530 has different etch characteristics than that of the SAC1 material.
5D shows a sublayer 522 of SAC1 material, showing a second trench 545 anisotropically etched into the SAC2 material filling trench 530 reaching the bottom of the stack of active layers 502-7 through 502-0. shows the upper plane or active layer 502-7 in the XY plane through ); Anisotropic etching is performed by forming a cavity between the N ⁺ sublayer 521 and N ⁺ sublayer 523 in each active strip of the active layers 502-0 to 502-7, so that the etchant The SAC1 material is etched away to expose the sidewalls 547 of the stack to allow for making room for the sublayer 522.
FIG. 5E shows the Z It is a cross section through; In the cavity 537 resulting from excavating the SAC1 material in sublayer 522, an optional ultra-thin dopant diffusion barrier layer 521-d is deposited, either undoped or P ^- doped polysilicon 521. provided.
5F shows a trench where P-doped pillar 290, local word line 280W and precharge word line 208-CHG are provided between and along adjacent active strips of active layer 502-7. At 530 a cross-sectional view in the Prior to forming the word line, charge confinement layers 231L and 231R are conformally deposited on the sidewalls of the active strip (an ultra-thin dopant diffusion barrier layer 521-d is optional).
Figure 5g shows the formation of an ultra-thin dopant diffusion barrier layer 521-d in the sub-layer 522 forming the channel region of the TFT ( _TR 585, _TR 587), and the formation of undoped or P ^- doped polysilicon. , shows a cross-sectional view in the ZX plane of active layers 502-6 and 502-7 of Example (EMB-3A), after deposition of amorphous silicon, or silicon germanium; Sublayer 522 ( ^P- ) is also deposited on the trench sidewalls as filler 290 to connect the channel region within the stack (i.e., P ^- sublayer 522) to substrate circuitry 262. .
5H-1 shows a cross ^- section 500 in the Z .
5H-2 illustrates (along the direction indicated by reference numeral 537) to form an optional support spine from SAC1 material (e.g., spine (SAC1-a)), according to one embodiment of the present invention. ) Cross-section 500 in Figure 5H-1, after laterally selective etching of the SAC1 material, filling the recess with a P ^- doped channel material (e.g., P ^- doped polysilicon) on the sidewalls of the active strip. ) is shown.
Figure 5H-3 shows the P ^{-material after removal of the P-} material leaving the P ^- sub-layer 522 in the recess from the region 525 along the sidewall of the active strip, according to one embodiment of the present invention. Cross section 500 of 2 is shown; 5H-3 also illustrates the removal of isolation material from trench 530, formation of charge confinement layer 531 and local word line 208-W, and thus transistors T _L 585 and T _R on opposite sides of the active strip. 585).
Figure 6A shows semiconductor structure 600, a three-dimensional representation of a memory array comprised of quadrants Q1 through Q4; In each quadrant, (i) a plurality of NOR strings (e.g., NOR strings 112) are each formed in an activity strip extending along the Y direction, and (ii) a page (e.g., page 113). extends along the (iii) a slice (e.g., slice 114) extending in both the (e.g., plane 110) extends along both the
6B shows a TFT in a programmable reference NOR string 112-Ref in quadrant Q4 and a TFT in NOR string 112 in quadrant Q2 connected to a sense amplifier SA(a) - Q2. and Q4 are “mirror image quadrants” - shown in structure 600 in Figure 6A; Figure 6b also shows (i) a program in quadrant Q3 that similarly provides the corresponding reference TFT for slice 114 in mirror image quadrant Q1, sharing a sense amplifier SA(b); (ii) a reference TFT in plane 110 in the mirror image quadrant (Q1) sharing a possible reference slice (114-Ref) (represented by region A), and (ii) a sense amplifier (SA(c)), the same It shows a programmable reference plane 110-Ref in quadrant Q2, which provides a corresponding reference TFT for a NOR string (e.g., NOR string 112) in that quadrant.
Figure 6C illustrates the structure 600 of Figure 6A showing slices 116 being used as a high-speed cache due to their proximity to their sense amplifiers and voltage sources 206; Figure 6C also shows an extra plane 117 that can be used to provide replacement or replacement NOR strings or pages in quadrant Q2.
7 shows that the N ⁺ sub-layer 521 serves as a source, the N ⁺ sub-layer 523 serves as a drain, and the P ^- sub-layer 522 serves as a charge storage material 531 and a word line 208W. ) is a cross-section in the ZX plane of the active layer 502-7 of embodiment (EMB-3A), showing in more detail the single-channel TFT (T _R 585) of FIG. 5G serving as a channel; FIG. 7 ^{shows N} ) to prove the deletion operation.
8A illustrates in simplified form a prior art storage system 800 in which a microprocessor (CPU) 801 communicates with a system controller 803 in a flash solid state drive (SSD) employing NAND flash chips 804. show; SSD emulates a hard disk drive, and the NAND flash chip 804 does not communicate directly with the CPU 801 and has relatively long read latency.
8B shows a non-volatile NOR string array 854 or quasi-volatile NOR string array 855 (or both) directly through one or more input/output (I/O) ports 861 and a controller 863. A system architecture 850 using the memory device of the present invention, which communicates indirectly with CPU 801 via , is shown in simplified form.

1A-1 and 1A-2 illustrate, in detail, a conceptualized memory structure 100 illustrating the configuration of a memory cell according to one embodiment of the invention. As shown in Figure 1A-1, memory structure 100 represents a three-dimensional memory array or block of memory cells formed from a deposited thin film fabricated over the surface of a substrate layer 101. Substrate layer 101 may be, for example, a conventional silicon wafer used to fabricate integrated circuits, familiar to those skilled in the art. In this detailed description, the Cartesian coordinate system (as shown in Figure 1A-1) is adopted solely for the purpose of facilitating explanation. Under this coordinate system, the surface of the substrate layer 101 is considered a plane parallel to the XY plane. Accordingly, as used in this description, the term "horizontal" refers to any direction parallel to the XY plane, while the term "vertical" refers to the Z direction. As shown, block 100 is composed of four planes (e.g., planes 110) stacked perpendicular to each other and isolated from each other. Each plane consists of a horizontal active strip of NOR strings (e.g., active strip 112) . Each NOR string includes a number of TFTs (e.g., TFT 111) formed side by side along the active strip, and thin film transistor current flows in a vertical direction, as described in more detail below. Unlike conventional NAND strings, in the NOR string of the present invention, writing, reading or erasing one of the TFTs in the NOR string does not require activation of the other TFTs in the NOR string. Accordingly, each NOR string is randomly addressable, and each TFT within this NOR string is randomly accessible.

Plane 110 is shown as one of four planes stacked on top of each other and separated from each other. TFTs (e.g., TFTs 111) are formed parallel along the length of the horizontal active strip 112. 1A-1, for illustrative purposes only, each plane has four horizontal activity strips separated from each other. Both the plane and the NOR string are individually addressable.

1A-2 introduces additional randomly addressable units of memory cells: “ columns ”, “ pages ” and “ slices ”. 1A-2, each column (e.g., column 115) represents a number of NOR strings of TFTs that share a common control gate or local word line, with the NOR strings forming along multiple planar activity strips. do. Note that, as a conceptualized structure, memory structure 100 is an abstraction of certain salient features of the memory structure of the present invention. Although shown in Figure 1A-1 as an array of 4 × 4 active strips, each having four TFTs along its respective length, the memory structure of the present invention can be configured to include any number of TFTs along any of the X, Y, and Z directions. You can have For example, in the Z direction, strings 1, 2, 4, 8, 16, 32, 64... 2, 4, 8, 16, 32, 64... of the NOR string along the plane, There may be 2 activity strips, each NOR string having 2, 4, 8, 16, … along the Y direction. It can be equipped with 8192 or more side-by-side TFTs. The use of numbers that are integer powers of 2 (i.e., 2 ⁿ , where n is an integer) follows convention in conventional memory design. It is customary to access each addressable unit of memory by decoding its binary address. Thus, for example, the memory structure of the present invention may have M NOR strings along each of the X and Z directions, where M is a number that need not be ²ⁿ for any integer n. The TFTs of the structure 100 of the present invention can be read, programmed, or erased simultaneously or on a per-page or per-slice basis. (As shown in Figure 1A-2, a " page " refers to a row of TFTs along the Y direction, and a " slice " extends along both the X and Z directions and is one memory cell deep along the Y direction. refers to the configuration of adjacent memory cells). The delete operation may also be performed in one step for the entire memory block 100.

As a conceptualized structure, memory structure 100 is not shown extended in any of the X, Y, and Z directions.

Figure 1B shows a basic circuit diagram of four NOR string pairs, with each NOR string pair located in each of the four planes, according to one embodiment of the invention; The corresponding TFTs of each NOR string share a common local word line (e.g., local word line 151n). The detailed structure of this configuration is discussed and illustrated below in conjunction with Figure 2K. As shown in Figure 1B, this basic circuit configuration consists of four NOR string pairs on four separate planes (e.g., NOR strings 150L and 150R) in plane 159-4.

As shown in Figure 1B, NOR strings 150L and 150R may be NOR strings formed along two active strips located on opposite sides of a shared local word line 151a. TFTs 152R-1 to 152R-4 and 152L-1 to 152L-4 may each have four active strips, and TFTs located in the four active strips on opposite sides of the local word line 151a. In this embodiment, as explained in more detail below in conjunction with FIGS. 2K and 4C, greater storage density can be achieved by having shared vertical local wordline control TFTs in adjacent active strips. For example, the local word line 151a is a TFT (152R-1, 152R-2, 152R-3, and 152R-4) from four NOR strings located on four planes, as well as four NOR strings on the corresponding planes. Controls TFTs 152L-1, 152L-2, 152L-3 and 152L-4 from adjacent NOR strings. As discussed in more detail below, in some embodiments, for each NOR string there is a unique parasitic capacitance (C) (e.g., a common N ⁺ source region or N ⁺ drain region of the NOR string and its multiple associated The distributed capacitance between local word lines) can be used as a virtual voltage source under some operating conditions to provide the source voltage (V _ss ).

Figure 1C shows a basic circuit diagram of four NOR strings, with each NOR string located in each of the four planes, according to one embodiment of the invention. In Figure 1C, the corresponding TFTs of each NOR string share a common local word line. Each NOR string can be driven horizontally along the Y direction, with a storage element (i.e. TFT) connected between the source line (153- m ) and the drain or bit line (154- m ) - where m corresponds to The index of the activity strip is 1 to 4 -, the current of the drain-source transistor flows along the Z direction. The corresponding TFTs in the four NOR strings share the corresponding one of the local word lines (151- n ), and n is the index of the local word line. The TFT in the NOR string of the present invention is a variable threshold voltage thin film storage transistor that can be programmed, program-inhibited, erased or read using conventional programming, inhibition, erase and read voltages. In one or more embodiments of the invention, the TFT is implemented by a thin film storage transistor that is programmed or erased using Fowler-Nordhiem tunneling or direct tunneling mechanisms. In another embodiment, channel thermal electron injection may be used for programming.

processing flow

2A shows that active layers 202-0 to 202-7 (each individually separated from the next active layer by a separation layer 203-0 to 203-7) are semiconductor devices, according to one embodiment of the present invention. A cross-sectional view in the YZ plane of the semiconductor structure 200 is shown after it has been formed on the substrate 201, but before the formation of each active strip. Semiconductor substrate 201 represents, for example, a P ^- doped bulk silicon wafer from which support circuitry for memory structure 200 may be formed prior to forming the active layer. This support circuitry, which may be formed alongside contacts 206-0 and 206-1 in FIGS. 2C and 2IA (FIG. 2I-1), may include both analog and digital circuitry. Some examples of these support circuits include shift registers, latches, sense amplifiers, reference cells, power lines, bias and reference voltage generators, inverters, NAND, NOR, Exclusive-Or, and other logic. It includes gates, input/output drivers, address decoders (e.g., bit line and word line decoders), other memory elements, sequencers, and state machines. These support circuits, as known to those skilled in the art, may be configured using conventional devices (e.g., N-wells, P-wells, triple wells, N ⁺ , P ⁺ They can be formed as building blocks for diffusions, isolation regions, low and high voltage transistors, capacitors, resistors, vias, interconnects and conductors.

After the support circuitry is formed in or on the semiconductor substrate 201, an isolation layer 203-0 is provided, which may be, for example, thick silicon oxide deposited or grown.

Then, in some embodiments, one or more interconnection layers may be formed, including “global wordlines” discussed further below. These metal interconnects (e.g., global word line landing pads 264 in FIG. 2C discussed below) have a predetermined orientation that may be perpendicular to the active NOR string to be formed in a later step. It can be provided as a horizontal long narrow conductive strip running along. To facilitate discussion in this detailed description, the global word line is assumed to run along the X direction. Metal interconnects can be formed by applying photo-lithographical patterning and etching steps on one or more deposited metal layers. (Alternatively, these metal interconnects can be formed using a conventional damascene process, such as a copper or tungsten damascene process). A thick oxide is deposited to form the separation layer 203-0, followed by a planarization step using conventional chemical mechanical polishing (CMP) techniques.

Thereafter, active layers 202-0 to 202-7 are formed successively, and each active layer is electrically connected to the previous active layer below by the corresponding separation layer 203-1 to 203-7. is insulated with In Figure 2A, eight active layers are shown, but any number of active layers may be provided. In practice, the number of active layers may vary depending on processing techniques, such as the availability of a well-controlled anisotropic etch process that allows cutting through a tall stack of active layers to reach the semiconductor substrate 201. can depend on Each active layer is etched in an etch step that preferentially cuts through a plane, discussed below, to form multiple parallel active strips, each running along the Y direction.

2B-1 shows semiconductor structure 220a with N ⁺ sublayers 221 and 223 and P ^- sublayer 222. Semiconductor structure 220a may be used to implement any of active layers 202-0 through 202-7 of Figure 2A, according to one embodiment of the invention. As shown in Figure 2B-1, active layer 220a includes deposited sublayers 221-223 of polysilicon. In one implementation, sublayers 221 - 223 may be deposited sequentially within the same processing chamber, without intervening removal. Sublayer 223 may be formed by depositing 10 to 100 nm of in-situ doped N ⁺ polysilicon. Sublayers 222 and 221 may then be formed by depositing undoped or lightly doped polysilicon or amorphous silicon to a thickness range of 10 to 100 nm. Sublayer 221 (i.e., the upper portion of the deposited polysilicon) is then N ⁺ doped. The N ⁺ dopant concentration in the sublayers 221 and 223 should be as high as possible to provide the lowest possible sheet resistance in the N ⁺ sublayers 221 and 223 - for example, 1 × 10 ²⁰ /cm ³ and 1 × 10 ²¹ / ^cm3 Sai – do. N ⁺ doping is achieved by (i) low-energy shallow high-dose ion implantation of phosphorus, arsenic or antimony, or (ii) in-situ phosphorus or arsenic doping of the deposited polysilicon. And an N ⁺ sub-layer 221 with a thickness of 10 to 100 nm can be formed on top. Low-dose implantations of boron (P ^- ) or phosphorus (N ^- ) ions can also be used in the N ^{+ sublayer 221 and the N + sublayer} 221 to achieve a unique enhancement mode threshold voltage in the resulting TFT. It may be implanted into the sublayer 222 between the sublayers 223, or may be performed with sufficient energy to penetrate the in-situ doped N ⁺ sublayer 221. The boron or P ^- dopant concentration of sublayer 222 may be in the range of 1 × 10 ¹⁶ /cm ³ to 1 × 10 ¹⁸ /cm ³ , and the actual boron concentration in sublayer 222 may be in the range of active strip 202- 0 to 202-7) ^, the native transistor turn-on threshold voltage, channel mobility ^{, N + P -} N ^{+ erosion} voltage ( punch-through voltage, N ⁺ P ^- junction leakage and reverse diode conduction characteristics, and channel depletion depth.

Thermal activation of the N ⁺ and P ^- implanted species and recrystallization of sublayers 221, 222 and 223 can be performed after all active layers 202-0 to 202-7 have been formed, using a conventional rapid thermal annealing technique (e.g. e.g., above 700°C), or preferably in one step, using conventional rapid laser annealing techniques, which ensures that all active layers undergo approximately the same amount of elevated temperature processing. ^TFTs acting as channel ^regions Care must be taken to limit P ^- sublayer 222 is sufficiently thick or sufficiently P-doped to prevent N ⁺ P ^- N ⁺ transistor erosion or excessive leakage between N ⁺ sublayer 221 and N ⁺ sublayer 223. is required to be maintained.

Alternatively, each of the N ⁺ and P ^- dopants of active layers 202-0 through 202-7 can be subjected to excimer laser annealing (ELA), for example, at an ultraviolet wavelength (e.g., 308 nm). They can be individually activated by shallow rapid thermal annealing using . Annealing energy absorbed by the polysilicon or amorphous silicon is used to form the sublayers 221 and 222 without excessively heating other active layers beneath the sublayer 223 of the annealed active layer 220a. ) and, in some cases, penetrate into sublayer 223 and affect volume 205 (see FIG. 2B-4).

Although the use of sequential layer-by-layer excimer laser shallow rapid thermal annealing is more expensive than a single deep rapid thermal anneal step, ELA can Localized partial melting of (or amorphous silicon) may result in recrystallization of the annealed volume 205 to form larger silicon polycrystalline grains with substantially improved mobility and uniformity, affecting It has the advantage of reduced TFT leakage due to reduced segregation of the N ⁺ dopant at the grain boundaries of the receiving volume. Recrystallization of both sublayers 221 and 222 and, if appropriate, of sublayer 223 before forming N ⁺ sublayer 221 thereon, or after forming sufficiently thin N ⁺ sublayer 221 thereon. An ELA step may be applied to either the P ^- sublayer 222 or the N ⁺ sublayer 223 to allow. This shallow excimer laser low temperature annealing technique is well known to those skilled in the art. For example, this technique is used to form polysilicon or amorphous silicon films in solar cell and flat panel display applications. For example, “Comprehensive Study of Lateral Grain Growth in Poly-Si Films by Excimer Laser Annealing (ELA) and its applications to Thin Film Transistors” by H. Kuriyama et al., Japanese Journal of Applied Physics, Vol.33, Part 1, Number 10, August 20, 1994, or "Annealing of Silicon Backplanes with 540W Excimer Lasers", technical publication by Coherent Inc. on its website.

The thickness of the P ^- sublayer 222 roughly corresponds to the channel length of the TFT to be formed, which can be as short as 10 nm or less. In one embodiment (see Figure 2B-5), even after several thermal processing cycles, an ultrathin (3 nm thick from one or several atomic layers) film of silicon nitride (e.g., SiN or Si ₃ N ₄ ) The channel length of the TFT is reduced to less than 10 nm by depositing an ultra-thin film, or another suitable diffusion barrier film (see sublayer 223-d in Figure 2b-5) after formation of the N ⁺ sublayer 223. It may be possible to control it. A second ultra-thin film of silicon nitride, or other suitable diffusion barrier (see 221-d in FIGS. 2B-5), is optionally deposited on the P ^- sublayer 222 prior to depositing the N ⁺ sublayer 221. It can be deposited later. The ultra-thin dopant diffusion prevention layers 221-d and 223-d may be deposited by chemical vapor deposition, atomic layer deposition, or any other suitable means (eg, high pressure nitridization at low temperature). Each ultra-thin dopant diffusion barrier acts as a barrier to prevent the N ⁺ dopant in the N ⁺ sublayers 221 and 223 from diffusing into the P ^- sublayer 222, and the N ⁺ sublayer 221 (acting as a source) ) and the N ⁺ sublayer 223 (which acts as the drain) is thin enough to only slightly delay the behavior of the MOS transistor. (Electrons in the surface inversion layer of sublayer 222 easily tunnel directly through the ultra-thin silicon nitride layer, which is too thin to capture these electrons). These additional ultra-thin dopant diffusion barriers increase manufacturing costs, but can help significantly reduce the accumulated leakage current along the active strip in the "off" state from multiple TFTs. However, if leakage current is acceptable, these ultra-thin layers can be omitted.

NOR strings with long, narrow N ⁺ sublayers 223 and N ⁺ sublayers 221 can have very large line resistances (R), including the resistance of narrow, deep contacts to the substrate. Reduced line resistance is desirable because it reduces the “RC delay” of a signal crossing a long conductive strip. (RC delay is a measure of the time delay given by the product of the line resistance (R) and the line capacitor (C)). Reduced line resistance also reduces the "IR voltage drop" across the long, narrow active strip. (IR voltage drop is given by the product of current (I) and line resistance (R)). To significantly reduce line resistance, one or both of the N ⁺ sublayers 221 or 223 adjacent to each active strip may be provided with an optional conductive sublayer 224 (e.g., in FIGS. 2B-2 and 2B-3 A sublayer 224, denoted W, may be added. Sublayer 224 may be provided by one or more deposited metal layers. For example, sublayer 224 may be deposited a 1-2 nm thick layer of TiN, followed by a 1-40 nm thick layer of tungsten, a similar refractory metal, or a polycide or silicide (e.g., nickel silicide). It can be provided by depositing a layer of thickness. Sublayer 224 more preferably ranges from 1 to 20 nm in thickness. Even very thin sublayers 224 (e.g., 2 to 5 nm) can significantly reduce the line resistance of long active strips, allowing the use of less heavily doped N ⁺ sublayers 221 and 223. there is.

As shown in Figure 2C, the conductor within the contact opening 205-1 can be very long for high stacks, thereby conversely increasing the line resistance. In this case, to substantially fill the contact opening 205-1, a metal sublayer 224 (e.g., a tungsten layer) is placed over the N ⁺ sublayer 221, as shown in Figure 2C. Rather, it may be preferably included under the sublayer 223. However, including a metal sublayer 224 in each of the active layers 202-0 to 202-7 means that some of the metal materials undergo anisotropic etching rather than materials such as polysilicon, silicon oxide, or silicon nitride. This increases the cost and complexity of the manufacturing process, including more difficult problems. However, the metal sublayer 224 allows the use of significantly longer active strips, which results in superior array efficiency.

In embodiments where metal sublayer 224 is not included, there are several tradeoffs that can be made: for example, longer active strips are possible if the resulting increased response speed is acceptable. In general, the shorter the active strip, the lower the line resistance and therefore the shorter the latency. (The trade-off is in array efficiency). In the absence of metal sublayer 224, the thickness of N ⁺ sublayers 221 and 223 can be increased (e.g., up to 100 nm) to reduce the intrinsic line resistance and result in a larger stack to be etched. Make them lose. To improve recrystallization and dopant activation and reduce dopant segregation at grain boundaries, the line resistance is increased by increasing the N ⁺ doping concentration in the N ⁺ sublayers 221 and 223 (e.g., by rapid thermal annealing, deep It can be further reduced by applying higher annealing temperatures exceeding 1,000° C. (by laser annealing, or shallow excimer laser annealing).

The shorter active strip may also have superior immunity to leakage between the N ⁺ sublayer 223 and N ⁺ sublayer 221 . The thicker N ⁺ sublayer provides reduced strip line resistance and increased strip capacitance, which are desirable for dynamic sensing (discussed below). Designers of integrated circuits may choose shorter active strips (with or without metal sublayer 224) when low response speed is most important. Alternatively, strip line resistance can be reduced by contacting both ends of each active strip, rather than just one end.

Block-formatin patterning and etching steps define separate blocks in each active layer formed. Each block occupies an area where, as discussed below, multiple (e.g. thousands) activity strips can be formed, driven in parallel, each activity strip driven along the Y direction, and consequently each Forms one or more NOR strings providing a large number (e.g., thousands) of TFTs.

Each of the active layers 202-0 to 202-7 can be formed continuously by repeating the steps described above. Additionally, in the block formation patterning and etching steps discussed above, each subsequent higher active layer allows the upper active layer to access its particular decoder and other circuitry in the semiconductor substrate 101 through designated buried contacts. (e.g., layer 202-1 extends above layer 202-0, as shown in FIG. 2C and discussed below).

As shown in Figure 2C, buried contacts 205-0 and 205-1 are local contacts formed from N ⁺ sublayer 223, for example, in each of active layers 202-0 and 202-1. Contacts 206-0 and 206-1 in the semiconductor substrate 201 are connected to the bit line or source line. The buried contacts (not shown) for the active layers 202-2 to 202-7 are such that the active layer closest to the substrate has the shortest buried contact, and the active layer furthest from the substrate has the longest buried contact. An inverted staircase structure with contacts may similarly be provided to connect the active layers 202-2 to 202-7 to the contacts 206-2 to 206-7. Alternatively, instead of buried contacts, conductor-filled vias extending from the top of the active layer may be etched through isolation layers 203-0 and 203-1. These vias establish electrical contact from the substrate circuitry 206-0 to, for example, the top N ⁺ sublayer 221-0 (or metal sublayer 224, if provided). The vias may be in a "staircase" pattern with the active layer closest to the substrate connected by the longest via and the active layer closest to the top connected by the shortest via. Vias (not shown) have the advantage of allowing more than one plane to be contacted in one masking and etching step, as is well known to those skilled in the art.

Through the switch circuit, each of the contacts 206-0 to 206-7 applies a pre-charge voltage (V _bl ) to each bit line or source line of the corresponding NOR string, or a sense amplifier or It can be connected to the input terminal of the latch. The switch circuit may be configured to operate at a programming voltage (V _pgm ), a stopping voltage (V _inhibit ), an erasing voltage (V _erase ), or any other suitable predetermined or precharge reference voltage (V _bl or Each of the contacts 206-0 to 206-7 may be selectively connected to any of a number of specific voltage sources, such as V _ss ). In some embodiments discussed below that utilize a relatively large parasitic distributed capacitance along the bit line or source line in the active strip, a virtual voltage reference (e.g., providing a ground voltage (V _ss )) is used. A virtual ground) can be created on the source line of each active strip (i.e., N ⁺ sublayer 221) by pre-charging the source line, as discussed below. Virtual ground eliminates the need to wire the N ⁺ sublayer 221 to a voltage source on the board, allowing each active strip to be connected from the top to the board using the stepped via structure described above. Otherwise, it would not be possible to connect the N ⁺ sublayer 221 and N ⁺ sublayer 223 of each active strip alone from the top to the substrate because the via material would short the two sublayers.

FIG. 2C also shows buried contacts 261- connecting global word lines 208g-s to be formed by driving along the X direction to contacts 262-0 to 262-n in the semiconductor substrate 201. 0 to 261-n) are shown. Global word lines 208g-s serve to connect corresponding local word lines 208W-s (e.g., see FIG. 2I) not yet formed to circuits 262-n in substrate 201. do. To allow connection from the top of the horizontally running global word line (208g-s) to the local word line (208W-s) that has not yet been formed in the vertical direction, a landing pad 264 is provided on the global word line. do. Through the switch circuit and the global word line decoder, each of the global word line contacts 262-0 to 262-n has stepped programming voltages (V _program ), a program stop voltage (V _inhibit ), and a read voltage ( It is selectively connected to one of a number of reference voltage sources, such as V _read ) and erase voltage (V _erase ), individually or shared among several global word lines.

The buried contacts, global wordlines and landing pads may be formed using conventional photolithographic patterning and etching steps, followed by one or more suitable conductors (e.g., tungsten metal, alloy or tungsten or silicide). It can be deposited by alloying tungsten.

After the top active layer (e.g., active layer 202-7) is formed, a trench is created by etching through the active layer to reach the bottom global word line (or semiconductor substrate 201) using a strip forming mask. do. The strip forming mask consists of a pattern in the photoresist layer of long narrow strips running along the Y direction. A sequential anisotropic etch etch through the active layers 202-7 through 202-0 and the dielectric isolation layers 203-7 through 203-0. With the number of active layers to be etched, which is 8 in the example of FIG. 2C (and can more typically be 16, 32, 64, or more), the photoresist mask is sufficient to etch through and beyond the lowest active layer. may not be strong enough to maintain the strip formation pattern through etching. Accordingly, a mask reinforced using hard mask materials (eg, carbon or metal) known to those skilled in the art may be required. The etch ends at the dielectric isolation layer on the landing pad of the global word line. It may be advantageous to provide an etch-stop barrier film (e.g., aluminum oxide) to protect the landing pad during the trench etch sequence.

FIG. 2D shows the formation of trench 230 in structure 200 of FIG. 2A in a cross-section in the X-Y plane through active layer 202-7 of a portion of semiconductor structure 200 of FIG. 2A. The long, narrow active strips between adjacent trenches 230 in different active layers have a high aspect-ratio. To achieve the best etch results, the etch chemistry may have to be varied when etching through different sublayers of material, especially in embodiments where a metal sublayer 224 is present. As undercutting of any sub-layer is to be avoided, the activity strips in the bottom active layer (e.g., the activity strips in active layer 202-0) are aligned with the activity strips in the upper active layer (i.e. Anisotropy of the multi-step etch is important to have a width and aperture spacing with adjacent active strips that are approximately equal to the corresponding width and aperture spacing in the active strips of active layer 202-7. Of course, as the number of active layers in the stack to be etched increases, designing a continuous etch becomes more difficult. To alleviate the difficulties associated with etching through multiple (e.g. 32) active layers, etching was performed as described above by Kim, pp. As discussed at 188-189, it can be done in groups of layers - for example eight.

One or more charge confinement layers are then conformally deposited or grown on the sidewalls of the active strip in trench 230. The charge confinement layer is a thin tunneling dielectric film (e.g., a silicon dioxide layer, a silicon oxide-silicon nitride-silicon oxide ("ONO") triple layer) of 2 to 10 nm thick, preferably 3 nm or less. , by chemically depositing or growing a bandgap engineered nitride layer, or silicon nitride layer, followed by a charge confinement material (e.g., a dielectric film or an isolated floating gate). It is formed by deposition of a 4 to 10 nm thick layer of silicon nitride, silicon-rich nitride or oxide, nanocrystals, nanodots) embedded in an isolated floating gate. , and is then capped by a blocking dielectric film. The blocking dielectric film may be, for example, an ONO layer, or a 5-15 nm thick layer composed of a high dielectric constant film (eg, aluminum oxide, hafnium oxide, or some combination thereof). The storage elements to be provided may be SONOS, TANOS, nanodot storage, isolated floating gates or any suitable charge-trapping sandwich structures known to those skilled in the art.

The trench 230 is formed wide enough to accommodate the storage elements on two opposing sidewalls of adjacent active strips and the vertical local wordlines to be shared between the TFTs on their opposing sidewalls. FIG. 2E shows a portion of the semiconductor structure 200 of FIG. 2A showing charge confinement layers 231L and 231L on opposite side walls of the active strip along trench 230 in a cross-section in the X-Y plane through active layer 202-7. 231R) is shown to be deposited.

Contact openings to the bottom global wordlines are then photolithographically patterned at the top of layer 202-7 and through the charge confinement material at the bottom of trench 230 to a bottom global wordline landing pad (e.g. For example, it is exposed by an anisotropic etch stopping at the global word line landing pad 264 in Figure 2C. In one embodiment, which will be described in conjunction with Figure 2I below, only alternating rows of trenches 230 (e.g., rows in which wordlines formed therein are assigned odd addresses) are etched below the entire bottom wordline. In some embodiments, an ultrathin sacrificial film (e.g., 2 to 5 nm thick) is used to protect the vertical surfaces of the blocking dielectric on the sidewalls of trench 230 during anisotropic etching of the charge confinement material at the bottom of trench 230. After deposition of the polysilicon film, etching occurs. The remaining sacrificial film can be removed by a short-term isotropic etch.

Doped polysilicon (eg, P ⁺ polysilicon or N ⁺ polysilicon) can then be deposited over the charge confinement layer to form a control gate or vertical local word line. P ⁺ doped polysilicon may be desirable because its work function is higher compared to N ⁺ doped polysilicon. Alternatively, a metal with a high work function relative to SiO ₂ (eg tungsten, tantalum, chromium, cobalt or nickel) can be used to form the vertical local lines. Trench 230 can now be filled with P ⁺ doped polysilicon or metal. In the embodiment of FIG. 2I discussed below, the metal in alternating rows of trenches 230 (i.e., the rows to host odd-addressed local wordlines 208W-s) is the bottom global wordline ( 208 g-s) and makes ohmic contact. In another of the trenches 230 (i.e., the row to host the local word lines 208W-a assigned to even addresses) the polysilicon is separated from the bottom global word lines. (These local word lines will subsequently be contacted by upper global word lines 208g-a routed above the upper active layer). The photoresist and hard mask can now be removed. A CMP step can then be used to remove the doped polysilicon from the top surface of each block. FIG. 2F shows depositing a conductor 208 (e.g., polysilicon or metal) to fill trench 230 of FIG. 2E.

FIG. 2G shows that after the photolithographic patterning and etching steps on the semiconductor structure of FIG. 2F, the exposed portions of the deposited conductors 208 are removed to form a local conductor (“wordline”) 208W and a precharged wordline (208W). 208-CHG), showing filling the resulting shaft 209 with an insulating material, or alternatively leaving the shaft as an air gap separator. Because removing the doped polysilicon in this example is a high aspect ratio etch step in limited space, a hard mask material (e.g., carbon or metal) using the techniques described above may be required. The resulting shaft 209 may be filled with an insulating material, or may be left void to reduce parasitic capacitance between adjacent local word lines. Doped for excavation to match the local word line 208W-a (see FIG. 2I) and the global word line 208g-a required to be formed in contact with the local pre-charge word line 208-CHG. The mask pattern exposing the polysilicon is a parallel strip running along the X direction.

In Figure 2g, the portion 231 In some embodiments, portions 231X of charge confinement layers 231L and 231R may be removed by conventional etch process steps prior to filling shaft 209 with insulating material or voids. Etching of the charge confinement material from the shaft may be performed along with or after removal of the doped polysilicon. Subsequent etching will also remove any fine polysilicon stringers left by the anisotropic etch; These polysilicon stringers can create undesirable leakage paths that act as resistive leakage paths between adjacent local word lines. Removing some or all of this charge confinement material in portion 231X not only eliminates parasitic edge TFTs, but also impedes potential lateral diffusion of confined charges between adjacent TFTs along the same NOR string. Partial removal of portion 231 there is.

FIG. 2H shows a cross-sectional view of the ZX plane through a row of local word lines 208W of FIG. 2G, showing active strips in active layers 202-7 and 202-6. As shown in Figure 2h, each active layer includes an N ⁺ sublayer 221, a P ^- sublayer 222, and an N ⁺ sublayer 223 (a low-resistance metal layer 224 is optional). In one embodiment, the N ⁺ sublayer 221 (e.g., a source line) is wired to a ground reference voltage (V ss ) (shown as ground reference voltage 280 in FIG. 3A ), and the N ⁺ sub layer 221 (e.g., a source line) is wired to a ground reference voltage (V _ss ) (shown as ground reference voltage 280 in FIG. 3A ). Layers 223 (e.g., bit lines) are connected to contacts in substrate 201 according to the method shown in Figure 2C. Accordingly, the local word line 208W, the portion of the active layer 202-7 or 202-6 facing the word line 208W, and the portion of the word line 208W and the active layer 202-7 or 202-6. The charge confinement layer 231L between those portions forms the storage elements (e.g., storage TFTs 281 and 282) in Figure 2H. On opposite sides on the local word line 208W, TFTs 281 and 282 face TFTs 283 and 284, respectively, which include a charge confinement layer 231R therein. On the other side of the active strips 202-6 and 202-7 providing TFTs 283 and 284 are TFTs 285 and 286. Accordingly, the configuration shown in Figure 2h represents the highest packing density configuration for a TFT, where each local wordline is shared by two active strips along its opposite sides, and each active strip edges its two opposite sides. Shared by the two local word lines that follow. Each local word line 208W, when an appropriate voltage is applied, transfers the charge stored in a designated one of the TFTs formed in each of the active layers 202-0 to 202-7, located in one charge confinement portion 231L or 231R. It can be used to read, write, or delete.

The N ⁺ sublayer 223 (i.e., bit line) is provided with a suitable voltage (e.g., program voltage (V _prog ), stop voltage (V _inhibit ), erase voltage (V _erase ) required for operation of a nearby TFT. ), or can be charged with a reading reference voltage (V _bl )). During a read operation, which of the TFTs 281 to 286 is in the “on” state conducts current in the vertical or Z direction between the sublayers 221 and 223.

As shown in the embodiment of Figure 2H, the optional metal sublayer 224 reduces the resistance of the N ⁺ sublayer 223 to facilitate high-speed memory device operation. In other modes of operation, the N ⁺ sublayer 221 in any of the active layers 202-0 through 202-7 may be in a floating state. In each active layer, one or more of the local word lines (referred to as “precharge word lines”; e.g., precharge word line 208-CHG in Figure 2G) may be used as a non-memory TFT. When an appropriate voltage is applied to the precharge word lines (i.e., putting the precharge TFT in a conducting state), each precharge word line is connected to a voltage source (V _b1 ) by the N ⁺ sublayer 221 (source line) from the substrate. The channel sub-layer 222 is temporarily inverted so that it can be pre-charged with the pre-charge voltage (V _ss ) in the N ⁺ sub-layer 223, which is supplied from . When the voltage on the pre-charge word line is recovered (i.e., the pre-charge TFT returns to its non-conducting state) and all other word lines on both sides of the active strip are also "off", the N ⁺ sublayer 221 and its Because the distributed parasitic capacitors formed between the multiple local word lines are large enough to retain their charge long enough to support program, program-stop, or read operations, the device operates at a precharge voltage (V _ss ) (typically ~0 V). ) to the N ⁺ sublayer 221, which remains electrically charged to provide a virtual voltage reference (see below). Although the TFTs in the NOR strings can also act as pre-charge TFTs along each NOR string, to accelerate pre-charge for read operations (read pre-charge typically requires lower wordline voltages below ~5V). ), some of the memory TFTs (e.g., one of all 32 or 64 memory TFTs along the NOR string) may also be activated. At least for high voltage pre-charge operation, it is desirable to provide TFTs dedicated entirely to the role of pre-charge TFTs, since they are more resistant to program disturb conditions than memory TFTs.

Alternatively, in one embodiment described below (e.g., the embodiment (EMB-3) shown in FIGS. 2K and 2KA (FIG. 2K-1)), each local word line 208W is connected to an appropriate voltage. When forced, it can be used to read, write, or erase the TFT formed in each of the active layers 202-0 to 202-7 located on the charge confinement portion 231L or 231R. However, as shown in Figure 2K, only one of the two sides of each active strip in the active layers 202-0 through 202-7 is formed with a storage TFT, and thus the bottom and top global word lines in this particular embodiment. Eliminates the need for both.

A separating dielectric or oxide can then be deposited and the surface planarized. The semiconductor substrate 201 and the contacts to the local word lines 208W can then be photolithographically patterned and etched. Other preferred back-end processing after this step is well known to those skilled in the art.

Some Specific Embodiments of the Invention

2I and 4A, each of the local wordlines 208W is a global wordline (routed in one or more layers provided above active layers 202-0 through 202-7). 208g-a, or one of global word lines 208g-s (routed in one or more layers provided below the active layer between active layer 202-0 and substrate 201). The local word line (208W-s) connected to the bottom global word line (208g-s) may be assigned an odd address, while the local word line (208W-a) connected to the upper global word line (208g-a) may be assigned an even address. Addresses can be assigned and vice versa. 4A is an implementation of FIGS. 2I and 2IA (FIG. 2I-1), showing contacts 291 connecting local word lines 208W-a to global word lines 208g-a at the top of the memory array. This is a cross-sectional view in the X-Y plane of the example (EMB-1). Likewise, local word line 208W-s is connected to global word line 208g-s (not shown) running at the bottom of the memory array substantially parallel to the top global word line.

Figure 2ia (Figure 2i-1) shows that the local word line 208W-s or the local pre-charge word line 208-CHG is connected to the global word line 208g-s, and the local word line 208W-a is connected to the global word line 208g-s. Connected to the global word line 208g-a, each active layer with an ^N _ss , V _bl, V _pgm , V _inhibit and V _erase ), the horizontal active layer 202 of the embodiment of FIG. 2I (EMB-1), shown as connected via select circuitry to any of the decoding, sensing and other circuits. -4 to 202-7) show three-dimensional drawings. The board circuits are schematically shown at 206-0 and 206-1 on board 201.

Each active strip, in FIG. 2IA (FIG. 2i-1), is connected to the _substrate via an ^N It is shown as having a P-sublayer 222 (channel region) connected to a back-bias voltage (V _bb ) source 290. N ⁺ sublayer 221 and optional low-resistance metal sublayer 224 may be wired to a V _ss voltage supply (e.g., see ground reference connection 280 in FIG. 3A), or alternatively, It may be left floating after being temporarily pre-charged to the virtual source voltage (V _ss ) via the local pre-charge word line (208-CHG). The global word line (208g-a) at the top of the memory array and the global word line (208g-s) at the bottom of the memory array are connected to the virtual local word lines (208W-a and 208W-s) and the precharge word line (208 -CHG). Charge confinement layers 231L and 231R are formed between the virtual local word lines and the horizontal active strips, forming a non-volatile memory TFT at the intersection of each horizontal active strip and each vertical word line on both sides of each active strip. Separation layers (not shown) between active strips on different planes and between adjacent active strips on the same plane are not shown.

The N ⁺ sublayer 221 is wired to a ground voltage (not shown), is left floating without being directly connected to the output terminal, or is pre-charged to a voltage (eg, ground voltage) during a read operation. Pre-charge can be achieved by activating the local pre-charge word line (208-CHG). The P ^- sublayer 222 of each active layer (which provides the channel region of the TFT) is supplied via pillars 290 (described below) to supply voltage V _bb to the substrate 201. In some cases, it is connected selectively. Metal sublayer 224 is an optional low-resistance conductor provided to reduce the resistance of active layers 202-4 to 202-7. For simplicity, the intermediate separation layers 203-0 and 203-1 in FIG. 2C are not shown.

Global word lines 208g-a at the top of the memory array are formed by depositing, patterning, and etching a metal layer after forming contacts or vias. This metal layer can be provided by first forming a thin tungsten nitride (TiN) layer, followed by forming a low-resistance metal layer (eg, metallic tungsten). The metal layer is then photolithographically patterned and etched to form the top global word line. (Alternatively, these global word lines can be provided by a copper damascene process). In one implementation, these global word lines are horizontal, driven along the It is electrically connected to a contact object (not shown). Form local word lines of odd and even addresses, and connect from the top of the memory array via the top global word line, or from the bottom of the memory array via the bottom global word line (and in some embodiments both the top and bottom global word lines). ) Other mask etch process flows known to those skilled in the art are possible, suitably connecting these to their global word lines.

Figure 2j shows an embodiment of the invention (EMB-2) in which only the top global word line 208g-a is provided - that is, no bottom global word line. In an embodiment (EMB-2) the pre-charged local word line 208W-STG along one edge of the active strip is staggered with respect to the local word line 208W-a along the opposite edge of the active strip. (Also see Figure 4b). Figure 4b shows a staggered configuration of TFTs along both sides of each active strip, with the local word line 208W-a and the staggered local word line 208W-STG connected to the top global word line 208g-a only. , or alternatively, a cross-sectional view in the

Staggering the local word lines simplifies the machining flow by eliminating the machining steps required to form the bottom global word line (or, in some cases, the top global word line). The penalty for the staggered embodiment is the loss of the inherent dual density of TFTs, with both edges of each active strip providing a TFT within one pitch of each global word line. Specifically, in the embodiment (EMB-1) of Figure 2i and corresponding Figure 4a, where top and bottom global lines are provided, two TFTs may be included in each active strip of each active layer within one pitch of the global word line. (i.e., in each active strip, one TFT is formed using one sidewall of the active strip and is controlled from the bottom global word line, and another TFT is formed using the other sidewall of the active strip and is controlled from the top global word line. ). (Pitch is the minimum line width of one plus the minimum space required between adjacent lines). In contrast, in the embodiment (EMB-2) shown in Figure 2j and corresponding Figure 4b, only one TFT can be provided within one word line pitch in each active layer. The local word lines 208W on the two sides of each active strip are staggered relative to each other to allow space for the two global word lines needed to contact them.

2K shows a pair of TFTs (e.g., TFTs) formed on opposite sidewalls of an adjacent active strip and its respective adjacent charge confinement layer (e.g., confinement layers 231L and 231R), each of the local word lines 208W. An embodiment of the present invention (EMB-3) controlling TFTs 281 and 283 is shown. Isolation trenches 209 are etched to separate each TFT pair (e.g., TFTs 281 and 283) from an adjacent TFT pair (e.g., TFTs 285 and 287) (see also Figure 4C). As shown in FIG. 2K, each TFT is formed from one or the other of dual-pairs of active strips located on opposite sides of a shared local word line, each dual-pair of active strips being located in a trench ( 230) (see Figure 4c), each active strip is separated from similarly formed adjacent double pairs of active strips by an isolation trench 209 that does not provide a TFT on the opposite edge of the active strip. The trench 209 is made of a dielectric isolation material. It may be filled with (e.g., silicon dioxide or charge confinement material 231), or it may be left as a void, within which no local word lines will be accommodated.

FIG. 4C connects local word line 208W-a to global word line 208g-a at the top of the memory array, or alternatively to global word line 208g-s at the bottom of the array (not shown). 2K and FIG. 2K , showing contact 291 and isolation trench 209 separating TFT pairs 281 and 283 and TFT pairs 285 and 287 on adjacent active strips of active layer 202-7. This is a cross-sectional view in the X-Y plane of the embodiment (EMB-3) of 2ka (Figure 2k-1).

Alternatively, isolation trench 209 may have a pillar of P ^- doped polysilicon connected to the substrate to provide a back bias supply voltage (V _bb ) (e.g., in FIGS. 2K-1 and 4D Pillar 290 (also shown as a vertical connection in FIG. 3A). Pillar 290 supplies a back bias voltage (e.g., V _bb ~0V to 2V) during a read operation to reduce sub-threshold source-drain leakage current. Alternatively, filler 290 may supply a back bias voltage (V _bb ) and an erase voltage (V _erase ) (~12V to 20V) during an erase operation. Pillars 290 may be formed in separate vertical rows as shown in FIG. 4D, or may fill part or all of the length of each trench 209 (not shown). Pillar 290 contacts P ^- sublayer 222 in all active layers 202-0 to 202-7. However, pillar 290 cannot be provided in embodiments where metal sublayer 224 is provided, as this arrangement may result in excessive leakage current paths between different planes.

FIG. 4D shows an active layer, optionally including one or more optional P ^- doped pillars 290 that provide a substrate back bias voltage (V _bb ) and an erase voltage (V _erase ) to the P-sublayer 222. Cross-sectional view in the XY plane of the embodiment (EMB-3) of FIGS. 2K and 2KA (FIG. 2K-1) through 202-7.

FIG. 3A shows the method and circuit elements used to set the source voltage (V _ss ) in the N ⁺ sublayer 221 . Specifically, the source voltage (V _ss ) is applied via a hard-wire decoded source line connection 280 (shown as a dotted line), or alternatively through the pre-charged TFT 303 and the bit It can be set by activating the decoded bit line connection 270 to any of the line voltages (V _ss, V _bl , V _pgm , V _inhibit and V _erase ). Alternatively, the source reference voltage (V _ss ) can be accessed from the top of the memory array via a stepped via or a metal or N ⁺ doped polysilicon conductor connecting in the manner commonly employed in conventional 3D NAND stacking. . Each of the conductors in wired connection 280 can be connected independently so that the source voltages for or within a different plane do not need to be the same. The requirement for wired conductors to connect the N ⁺ sublayer 221 to the reference voltage (V _ss ) requires additional patterning and etching for each of the active layers 202-0 through 202-7, as well as additional address decoding circuitry. steps are required, thereby increasing complexity and manufacturing costs. Therefore, in some embodiments, it is advantageous to eliminate the wired source voltage (V _ss ), using a virtual voltage source at the inherent parasitic capacitance of the NOR string, discussed below.

Dynamic behavior of NOR strings

The present invention utilizes the accumulated inherent parasitic capacitance distributed along each NOR string to significantly increase the number of TFTs that can be programmed, read, or erased in parallel in a single operation, while significantly increasing the number of TFTs in a 3-D NAND flash array. Compared to , the operating power loss is also significantly reduced. As shown in Figure 3A, the local parasitic capacitor 360 (which contributes to the accumulated capacitance C) has a local wordline (as one plate) and N ⁺ /P ^- /N ⁺ activity (as the other plate). It is located at each overlap between layers. For a NOR string of TFTs with a minimum feature size of 20 nm, each local parasitic capacitor is approximately 0.005 femtofarads (each femtofarad is 1×10 ^-15 farads), which is too small to be used for transient charge storage. However, since there may be thousands or more TFTs contributing capacitance from one or both sides of the active strip, in a long NOR string the N ⁺ sublayer 221 (source line) and N ⁺ sublayer 223 (bit line) ) of the overall distributed capacitance (C) may be in the range of -1 to 20 femtofarads. This is approximately the capacitance in the sensing circuit connected via connection 270 (e.g., source voltage (V _bl )).

Having the bit line capacitance of the NOR string approximately equal to the parasitic capacitance of the source line (where charge is temporarily stored) provides a desirable signal-to-noise ratio during sensing operations. Comparatively, a DRAM cell of the same minimum feature size has a storage capacitor of approximately 20 femtofarads, while its bit line capacitance is 100 times that of the storage capacitor, about 2,000 femtofarads. This mismatch in capacitance results in insufficient signal-to-noise ratio and the need for frequent charging. A DRAM capacitor can typically retain its charge for 64 ms, due to leakage of charge from the capacitor through the DRAM cell's access transistor. In contrast, the distributed source line capacitance (C) of a NOR string is not the charge leakage of just one transistor (as in the case of a DRAM cell), but rather the larger charge leakage through thousands or more parallel, unselected TFTs. We have to fight. This leakage occurs in the TFTs on wordline 151b (WL-nsel) of Figure 3A that share the same strip of activity as one selected TFT on wordline 151a (WL-sel), and the distributed capacitance of the NOR string Substantially reducing the charge retention time for (C), perhaps to hundreds of microseconds, requires measures to reduce or neutralize leakage, as discussed below.

As discussed below, due to the thousands or more transistors, leakage current occurs during read operations. During program, program stop or erase operations, both N ⁺ sublayers 221 and 223 are preferably maintained at the same voltage, and therefore leakage current between the two N ⁺ sublayers 221 and 223 is negligible. During program, program stop or erase operations, charge leakage from the accumulated capacitance (C) is mainly transferred to the substrate through the substrate selection circuit, with very small transistor leakage when formed in single crystal or epitaxial silicon. It flows. Nevertheless, a charge retention time of 100 μs is sufficient to complete a read operation of less than 100 ns or a program operation of less than 100 μs of a selected TFT on a NOR string.

Unlike DRAM cells, the TFTs in a NOR string are non-volatile, such that the information stored in the selected TFT remains raw in the charge storage material (i.e., charge confinement layer 231) even if the NOR string's parasitic capacitor is fully discharged. It is a memory transistor. This is the case for all NOR strings in examples (EMB-1, EMB-2 and EMB-3). However, in DRAM cells, without frequent refresh, information will be lost forever. Accordingly, the distributed capacitance (C) of the NOR string of the present invention temporarily reduces the pre-charge voltage on the N ⁺ sublayers 221 and 223 to one of the voltages (V _ss , V _bl , V _progr , V _inhibit , or V _erase ). It is used exclusively for maintenance and is not used to store actual data for any of the TFTs in the NOR string. Immediately after the precharge transistor 303 of FIG. 3A, controlled by word line 151n (i.e., word line 208-CHG), is momentarily activated, the N ⁺ sublayer (not shown) is transferred from the substrate circuitry (not shown). Each read, program, program stop, or delete operation is performed to transfer voltage V _b1 (e.g., via connection 270) to 221). For example, voltage V _bl may be used to pre-charge the N ⁺ sublayer 221 to a virtual ground voltage of ~0 V during a read operation, or to both N ⁺ sublayers 221 and 223 during a program stop operation. It can be set to ~0V to precharge between 5V and ~10V.

The value of the accumulated capacitance (C) can be increased by increasing the NOR string to accommodate thousands or more TFTs along each side of the active strip, and thus the pre ^- charge voltage ( Increases the retention time of V _ss ). However, longer NOR strings suffer from increased line resistance as well as higher leakage current between N ⁺ sublayer 221 and N ⁺ sublayer 223 . This leakage current interferes with the sensed current when reading one TFT addressed with all the other TFTs in the NOR string being in their "off" (and somewhat leaky) state. Additionally, the potentially longer time it takes to pre-charge the larger capacitor during a read operation may conflict with the desirability of low read latency (i.e., fast read access time). To accelerate pre-charge of the accumulated capacitance (C) of long NOR strings, pre-charge TFTs are provided spaced along each side of the active strip (e.g., once per 128, 256 or more TFTs). It can be.

Since in a long NOR string the variable threshold TFTs are connected in parallel, the read operation condition of the NOR string is that all TFTs along both edges of the activity strip operate in enhancement mode (i.e., each of them has a control gate ( It should preferably be ensured that there is a positive threshold voltage applied between 151n) and the voltage (V _ss ) at the source 221. When all TFTs are in enhanced mode, the leakage current between the N ⁺ sublayer 221 and N ⁺ sublayer 223 of the active strip is such that all control gates on both sides of the active strip remain below V _ss of ~0V. suppressed when This improved threshold voltage can be achieved at a suitable dopant concentration for the P ^- sublayer 222 (e.g., 1 × 10 ¹⁶ and 1 × 10 ¹⁷ per cm ³ resulting in a unique TFT threshold voltage between ∼0.5 V and ∼1 V This can be achieved by providing a boron concentration between or higher.

In some implementations, it may be advantageous to implement sublayer 222 using N ^- doped or undoped polysilicon or amorphous silicon. With this doping, some or all of the TFTs along the active string will have a negative threshold voltage (i.e. depletion mode threshold voltage) and may therefore require some means to suppress leakage current. This suppression keeps the voltage on N ⁺ sublayer 221 (V _ss ) from ∼1 V to ∼1.5 V and the voltage on N ⁺ sublayer 223 (V _bl ) while maintaining all local word lines at 0V. This can be achieved by increasing the voltage to ~0.5V to ~2V, which is higher than that of the N ⁺ sublayer 221. This voltage setting gives the same result as maintaining the word line voltage at ~-1 V to -1.5 V for the N ⁺ sublayer 221 (source line), thus resulting in the TFT being at a slightly depleted threshold voltage. Suppresses any leakage. Additionally, after erasing the TFTs in the NOR string, the erase operation involves a subsequent soft programming step that shifts any TFTs in the NOR string that are over-erased back to the depletion mode threshold voltage to the enhancement mode threshold voltage. -programming step) may be requested.

Pseudo-volatile NOR string

Endurance is a measure of the performance degradation of a storage transistor after a certain number of write-erase cycles. Endurance below about 10,000 cycles - i.e., within 10,000 cycles, performance degrades significantly to an unacceptable degree - is considered quite low for some storage applications that require frequent data rewriting. However, the NOR strings of any of the embodiments of the invention (EMB-1, EMB-2, and EMB-3) provide reduced retention times, but significantly increase their durability (e.g., from years to minutes). Alternatively, materials may be used for the charge confinement materials 231L and 231R that reduce retention time to a few hours, while increasing endurance of write/read cycles from thousands to tens of millions. To achieve this higher durability, the silicon oxide film, typically 5 to 10 nm thick, for a charge confinement layer, such as an ONO film or similar combination of a tunnel dielectric layer, is reduced to 3 nm or less, or other It may be replaced entirely by a dielectric film (eg, silicon nitride or SiN), or may have no dielectric layer at all. Similarly, the charge confinement material layer may be CVD-deposited more silicon-rich silicon nitride (e.g., Si _1.0 N _1.1 ) than conventional Si ₃ N ₄ . Under a moderately positive control gate programming voltage, electrons pass through the thinner tunnel dielectric by direct tunneling (as distinct from Fowler-Nordheim tunneling, which typically requires higher programming voltages), allowing the electrons to travel in a matter of minutes to days. It will tunnel into a layer of silicon nitride charge confinement material where it will be temporarily confined for a period of time. A charge-confined silicon nitride layer and a blocking layer of silicon oxide (or aluminum oxide or another high-K dielectric) prevent these electrons from escaping into the word line, but these electrons are negatively charged and As they repel each other, they will eventually leak into the sublayers 221, 222 and 223 of the active strip.

The TFTs that result from these modifications are low data retention TFTs (“semi-volatile TFTs” or “pseudo-volatile TFTs”). These TFTs may require periodic write refresh or read refresh to replenish lost charge. Because the pseudo-volatile TFT of the present invention provides fast read access times with low latency, similar to DRAM, the generated pseudo-volatile NOR string may be suitable for use in some applications that currently require DRAM. The advantages of quasi-volatile NOR strings over DRAM are (i) a very low cost-per-bit figure of merit since DRAM cannot be easily mounted within three-dimensional blocks, and (ii) every ~64 ms as required in current DRAM technology. In comparison, it involves very low power losses since the refresh cycle only needs to be run approximately once every few minutes or once every few hours.

The quasi-volatile NOR string of the present invention appropriately applies program/read/erase conditions to include periodic data refresh. For example, a large threshold voltage between '0' and '1' compared to non-volatile TFTs, requiring at least 10 years of data retention, since each quasi-non-volatile NOR string is frequently read refreshed or program refreshed. There is no need to "hard-program" the quasi-volatile TFT to open a window. The quasi-non-volatile threshold voltage window can be as small as 0.2V to 1V, compared to the typical 1V to 3V for a TFT supporting 10 years of data retention. The reduced threshold voltage window allows these TFTs to be programmed with lower programming voltages and shorter programming pulses, which reduces the accumulated electric field stress on the dielectric layer and thus extends durability. .

Mirror bit NOR string

According to another embodiment of the invention, the NOR string array may also be programmed by channel thermal electron injection, similar to that used in NROM/Mirror Bit transistors known to those skilled in the art. In an NROM/mirror bit transistor, the charge representing one bit is stored at one end of the channel region following the junction with the drain region, and by reversing the polarity of the source and drain, the charge representing the second bit is stored in the channel next to the source junction. It is programmed and stored at the opposite end of the area. Typical programming voltages are 5V at the drain terminal, 0V at the source terminal, and 8V at the control gate. Reading both bits requires reading the source and drain junctions in reverse order, well known to those skilled in the art. However, channel hot electronic programming is significantly less efficient than tunnel programming, and therefore channel hot electronic programming is not suitable for the massively parallel programming made possible by tunneling. Additionally, the relatively large programming current results in a high IR drop between the N ⁺ sublayers (i.e. between the source and drain regions), thus reducing the line resistance as shown in Figure 2B-2 or Figure 2B-3. Limits the length of the NOR string, unless wiring connections are provided to do so. The erase operation in the NROM/mirror bit embodiment may be accomplished using the conventional NROM erase mechanism of band-to-band tunneling-induced hot-hole injection. To neutralize the charge of bound electrons, one applies -5V on the selected word line, 0V on the N ⁺ sublayer 221 (source line), and one applies 0V on the N ⁺ sublayer 223 (drain line). 5V can be applied to the line). The channel thermal electron injection approach doubles the NOR string bit density, making it attractive for applications such as archival memory.

Embodiment under a simplified processing flow (“Processing Flow A”) for simultaneous formation of TFT channels in active strips of multiple planes

The processing described above to form examples (EMB-1, EMB-2, and EMB-3) improves the uniformity of the TFT and the performance of the NOR string through all active strips in multiple planes, while providing an alternative but simplified process. This can be changed to a processing flow (“Processing Flow A”). In processing flow A, P ^- sublayers 222 (i.e. channels) are formed simultaneously in a single sequence for all active strips on all planes. This P ^- channel formation occurs late in the manufacturing processing flow, after all or most of the high temperature steps have been completed. Process flow A is described below in conjunction with examples (EMB-1 and EMB-3), but can be similarly applied to example (EMB-2) and other examples and derivatives thereof. In the remainder of the detailed description, examples manufactured under process flow A are identified by the suffix “A” added to their identifier. For example, a variation of Example (EMB-1) manufactured under processing flow A is identified as Example (EMB-1A).

FIG. 5A shows that the active layers 502-0 to 502-7 are formed as a stack of eight planes, one on top of the other, and each separation layer 503-0 to 503-7 of the material ISL on the semiconductor substrate 201. ) shows a cross-sectional view through the YZ plane of the semiconductor structure 500, after being separated from each other by ). Referring to semiconductor structure 220a of Figure 2B-1, each sublayer 222 of active layers 502-0 through 502-7 is formed of sacrificial material SAC1, instead of P ^- polysilicon. Separation layers 503-0 to 503-7 formed of separation material ISL (dielectric material) separate the active layers on different planes. The sacrificial material SAC1 in sublayers 522-0 through 522-7 will eventually be etched away to make way for the P ^- sublayer. The SAC1 material was selected so that it can be etched quickly and with high etch selectivity compared to the etch rates of the isolation material ISL and N ⁺ sublayers 523-0 to 523-7, and 521-0 to 521-7. do. The ISL material is silicon oxide (e.g. SiO ₂ ) deposited within a thickness range of 20 to 100 nm, the N ⁺ sublayers are heavily doped polysilicon with each layer within a thickness range of 20 to 100 nm, and SAC1 The material may be, for example, one or more of: silicon nitride, porous silicon oxide and silicon germanium, within a thickness range of 10 to 100 nm. The actual thickness used for each layer is preferably at the lower end of the range, where it may be more difficult to anisotropically etch 32, 64 or more stacked planes, in order to keep the overall height of the multiple planes to a minimum. .

5B shows buried contacts 205-0 and 205-1, where N ⁺ sublayers 523-1 and 523-0 are connected to circuits 206-0 and 206-1 in semiconductor substrate 201. This is a cross-sectional view of the YZ plane through . Before the active layers 502-0 to 502-7 are formed, when the N ⁺ sublayer 523-0 is deposited, electrical contact is created with the circuit 206-0 previously formed on the substrate 201. , a buried contact 205-0 is formed by etching into the separation layer 503-0. An optional low-resistance thin metal sublayer (e.g., TiN and tungsten), with a typical thickness range between 5 nm and 20 nm, is deposited before the N+ sublayer 523-0 to lower the line resistance. It can be (not shown in Figure 5b). To reduce the contact resistance to the substrate, a low-resistance metal plug, such as TiN, can be used to fill the buried contact opening, followed by a thin layer of tungsten. Active layer 502-0 is then etched into separate blocks, each of which will then be etched into individual active strips. Each higher plane or active layer (e.g., active layer 502-1) extends downward from above the active layer and has its embedded portion connecting it to circuit 206-1 in substrate 201. A contact object (205-1) is provided.

Connecting the active strips in each plane to the substrate circuitry includes contacts buried from the bottom (e.g., drain sublayers 523-0 and 523-1 in FIG. 5B to substrate circuits 206-0 and 206-1). This is achieved by buried contacts 205-0 and 205-1), or by conductor-filled vias from the top of the semiconductor substrate (not shown), connecting the N ⁺ sublayers 521-0 and 521-. 1) Electrical contact can be made. Since either of the sublayers 523 and 521 in the same active strip can act as a source terminal or a drain terminal for a TFT in the corresponding NOR string, the N ⁺ sublayers 521 or 523 in the same active strip can be exchanged. possible. The vias are first formed in the separation layer 503- 0 to 503-7) is etched through the ISL material. This alternative contact-from-the-top scheme allows vias to be etched to reach more than one plane at a time, thus reducing the number of masking and contact etch steps, which is 32 This is especially useful when you have 64 or more stacked planes. However, because sublayer 523 is below and masked by sublayer 521, there is a risk that conductors in the vias may electrically short out sublayers 521 and 523, thereby forming a stepped layer from the top. It is not easy to contact the sublayer 523 using a via.

According to one embodiment of the invention, in one process, the drain sublayer 523 is connected to the substrate circuitry through a buried contact from the bottom, while the source sublayer 521 is connected from the top by a conductor-filled via. It is connected to the board circuit via a wiring connection (e.g., connection 280 in FIG. 3A). Alternatively, and preferably, the source layer 521 uses TFTs in the NOR string designated as pre-charged TFTs (i.e., those TFTs that are used to charge the parasitic capacitance of the NOR string to provide a virtual voltage source). , can be connected to the substrate circuit by embedded contacts. In this way, the complexity of providing vias or wired conductors is avoided.

The discussion below focuses on the NOR string, where the source and drain sublayers are connected to the substrate circuitry through embedded contacts with pre-charged TFTs (described above). This arrangement provides the drain and source sublayers with voltages suitable for read, program, program stop, and erase operations.

All planes can then be exposed to a high temperature rapid thermal annealing and recrystallization step applied simultaneously to the N ⁺ sublayers 521 and 523. This step can also be applied to each plane individually. Alternatively, rapid thermal annealing, laser annealing for all layers, or shallow laser annealing (eg, ELA) on more than one plane at a time can also be used. Annealing reduces the sheet resistance of the N ⁺ sublayer by activating the dopants, recrystallizing them, and reducing dopant segregation at grain boundaries. Importantly, because this thermal annealing step must occur before the P ^- sublayer 522 is formed in any plane, the annealing temperature and duration beneficial for lowering the resistance of the N ⁺ sublayers 521 and 523 exceeds 1000 degrees Celsius. It can be very high.

FIG. 5C shows the activity of structure 500 after trench 530 along the Y direction is anisotropically etched through active layers 502-7 through 502-0 to reach below landing pad 264 of FIG. 5B. A cross-sectional view in the ZX plane, showing layers 502-6 and 502-7. Alternating layers of N ⁺ material, SAC1 material, N ⁺ material, and ISL material were used to achieve vertical trench sidewalls as close as possible (i.e., achieving substantially equal active strip width and spacing in the top and bottom planes). Deep trench 530 is etched with an anisotropic etch using an appropriate chemical reaction to etch. A hard mask material (eg, carbon) may be used during the multi-step etch sequence.

After removing the hard mask residue, trench 530 is filled with a second sacrificial material (SAC2) having etch characteristics different from those of the SAC1 material. The SAC2 material may be, for example, fast etch SiO ₂ or doped glass (eg, BPSG). Similar to the ISL material, the SAC2 material is selected to resist etching when the SAC1 material is etched. The SAC2 material mechanically supports the long, narrow stack of active strips while the SAC1 material is removed, particularly in subsequent steps, leaving cavities between the N ⁺ sublayers. Alternatively, this support may be provided by local word lines 208W, in implementations where the charge confinement material and local word lines are formed prior to etching the SAC1 material.

The narrow opening is then masked along the It is anisotropically etched. The anisotropic etch exposes the vertical sidewalls 547 of the active strips throughout the active layer to allow removal of SAC1 material from sublayer 522, thereby exposing the vertical sidewalls 547 of the active strips 502-0 through 502-7. In the active strip, a cavity is formed between the N ⁺ sublayer 521 and the N ⁺ sublayer 523 . Second trench 545 allows the formation of a conductive path from sublayer 522 to P ⁺ substrate region 262-0 (labeled V _bb ) in FIG. 5B. The second trenches 545 are preferably each 20 to 100 nm wide and can be spaced a sufficient distance to accommodate 64 or more side by side local word lines, such as local word lines 208W-s. there is. A highly selective etch is then performed on the exposed sidewall 547 of Figure 5D to anisotropically etch away all exposed SAC1 material from sublayer 522, via the paths indicated by arrows 547 and 548. Applies. As discussed below, the SAC1 material can be silicon nitride, while both the ISL material and the SAC2 material can be silicon oxide. With these materials, the hot phosphoric acid leaves all N ⁺ doped polysilicon in N ⁺ sublayers 521 and 523 and the ISL and SAC2 materials in layer 503 and trench 530 essentially intact. It can be used to remove SAC1 material. A dry etch process involving a high selectivity chemical reaction can achieve similar results without leaving residue within the elongated cavity previously occupied by the SAC1 material and walled between the SAC2 material filling the trench 530. You can.

As previously discussed, after selective removal of SAC2 material, there are two options for further processing: (i) first, form a P ^- sublayer 522 in the cavity between N ⁺ sublayers 521 and 523; a first option to subsequently form a charge confinement layer and a local word line 208W; and (ii) a second option that first forms the charge confinement layer and local word lines, followed by the P ^- sublayer 522. The first option is described below with the embodiment (EMB-1A) in FIGS. 5E and 5F. A second option is described below with the embodiment (EMB-3A) in Figure 5G.

FIG. 5E shows the Z This is a cross-sectional view. Cavity 537 results from excavating SAC1 material from the space between sublayers 521 and 523 (i.e., P ^- the space left from sublayer 522). The optional ultra-thin dopant diffusion barrier sublayer 521-d is then applied to the walls of cavity 537 (e.g., as shown in Figure 5E, left wall 501L, right wall 501R, N ⁺ on the bottom wall 501B of the sub-layer 521-7 and on the top portion 501T of the N ⁺ drain sub-layer 523-7). The ultra-thin dopant diffusion barrier layer 521-d may be made of, for example, silicon germanium (SiGe) or another material having an atomic lattice smaller than the diameter of the atoms of the N ⁺ dopant used (e.g., phosphorus, antimony arsenic). It may be nitride and may be in the thickness range of 0 to 3 nm. The dopant diffusion prevention sublayer 521-d is formed by controlled deposition of one to three atomic layers of a diffusion barrier material, for example, using atomic layer deposition (ALD) techniques. By doing so, a thickness of 0 or near 0 nm can be achieved. Unlike the multiple depositions required to form layers 221-d and 223-d for multiple active layers, the dopant diffusion barrier layer 521-d is formed for all active layers. The same dopant diffusion film as the layers 221-d and 223-d of FIGS. 2B to 5A can be provided, except that it is formed in a single deposition step. The gaseous material required for uniform deposition of the dopant diffusion barrier layer 521-d coats the walls of the cavity 537 through the second trench 545, as shown by arrows 547 and 548 in FIG. 5D. In any case, the material or thickness of the dopant diffusion barrier layer 521-d should not substantially reduce electron conduction across it and should not allow material confinement of electrons when tunneling through it. . If the leakage current between the N ⁺ sublayers 521 and 523 in the active strip is tolerably low, the dopant diffusion barrier layer 521-d can be omitted entirely.

Then, a P ^- sublayer 522 (e.g., P ^- sublayer 522-7) extends along the entire length of each active strip, inner walls 501T, 501B, 501R and 501L of each cavity. is formed according to P ^- sublayer 522 is doped polysilicon, undoped or P-doped amorphous silicon, (e.g., boron-doped between 1 × 10 ¹⁶ /cm ³ and 1 × 10 ¹⁸ /cm ³ semiconductor material), silicon germanium, or any suitable semiconductor material in the thickness range of 4 to 15 nm. In some implementations, P-sublayer 522 is thin enough to not completely fill cavity 537, leaving voids. In another implementation, P ^- sublayer 522 is thick enough to completely fill cavity 537. In a later step, after the local wordlines are formed, sublayers 522-6R and 522-6L (with respect to layer 502-6) along vertical walls 501R and 501L are connected to the At one or both side edges, it serves as the P ^- channel of the TFT, and the N ⁺ sublayer 521-6 serves as the N ⁺ source (at voltage (V _ss )), and the N ⁺ sublayer 523-6 ) serves as the N ⁺ drain (providing voltage (V _bl )). At a typical thickness of 3 to 15 nm, the P ^- sublayer 522 may be substantially thinner than the width of its corresponding active strip, which thickness may be defined photolithographically, or as a spacer well known to those skilled in the art. It can be defined by . In fact, the thickness of the P ^- channels formed under this process is independent of the width of the active strip, and for each very thin channel, the P ^- sublayer 522 has a thickness substantially equal to each of the multiple active layers. At this reduced thickness, depending on their doping concentration, the P ^- sublayers 522-6R and 522-6L are thin enough to be easily completely consumed under appropriate wordline voltages, improving transistor threshold voltage control and reducing the active strip. This reduces leakage between the N ⁺ source and drain sublayers.

At the same time, P-doped polysilicon is formed in a second trench 545 to form pillar 290 (not shown in Figure 5E but shown as pillar 290 in Figure 5F) extending from the top plane to the bottom plane. ) is deposited along the vertical walls of the At the bottom plane, a connection is made between pillar 290 and a circuit (eg, a voltage source providing voltage V _bb ) in substrate 201 . When the dopant diffusion prevention sublayer 521-d is provided, before forming the P ^- sublayer 522 and the pillar 290, a back bias voltage (V _bb ) and an erase voltage (V _erase ) are applied from the substrate 201. ) at the bottom of trench 545 to allow direct contact between the P ^- doped pillar 290 and the P ⁺ circuit (e.g., circuit 262-0 in FIG. 5B). A simple anisotropic etching may be necessary to etch away -d). Pillars 290 are configured to accommodate (in a subsequent step) the configuration of 32, 64, 128 or more vertical local word lines 208W between pillars (see FIG. 5F) of the embodiment (EMB-1A). are spaced along the length of each activity strip. (This separation is established by the separation of the second trench 545).

Pillar 290 is connected to the P ^- sublayer 222 of all active layers (e.g., P ^- sublayers 522-6R and 522-6L) to provide an appropriate back bias voltage to P ^- sublayer 222. ) -- which serves as the channel region of the TFT -- connects to the circuitry of the substrate 201. The circuitry in the substrate is typically shared by the TFTs of all active strips within the semiconductor structure 500. Pillar 290 provides a back bias voltage (V _bb ) during read operations and a high voltage (V _erase ), 10 V to 20 V, during block erase operations. However, in some implementations (see below and Figures 6A-6C), the erase operation This can be achieved without the use of a substrate generated voltage, in which case the thin polysilicon along the vertical walls of pillar 290 can be etched away (channel region P ^- sublayer 522 (e.g., wall (Caution is taken not to etch away ^{the P} Connection of pillar 290 to P ⁺ circuit 262-0 may not be necessary.

In the next step, the SAC2 material remaining within trench 530 is removed using, for example, a high selectivity anisotropic etch exposing the sidewalls of all active strips except where spaced fillers 290 are located. . Charge confinement layers 231L and 231R are then deposited conformally on the exposed sidewalls of the active strip. FIG. 5F shows the P-doped pillar 290, local word line 280W, and precharge word line 208-CHG adjacent to the active layer 502-7 after any suitable masking, etching, and deposition steps. A cross-sectional view in the X-Y plane of an embodiment of the invention (EMB-1A), provided in a strip, is shown.

The remaining processing steps, where appropriate, follow the corresponding steps in the formation of the previously discussed examples (EMB-1, EMB-2 and EMB-3). Prior to forming the charge confinement layer 531, the exposed side edges of the optional ultra-thin dopant diffusion barrier layer 521-d are removed by a short isotropic etch, followed by one or both exposed lateral edges of the active layer. This may be followed by forming a charge confinement layer 531 on the sidewalls and forming local word lines 208W along both side edges (e.g., embodiment (EMB-lA) of Figure 5F). Alternatively, an ultra-thin dopant diffusion barrier layer 521-d at the exposed side edges of the cavity is oxidized to form part or all of the thickness of the tunnel dielectric layer over the P ^- sublayer 522, while simultaneously forming the N ⁺ sublayer 521-d. Form a thicker tunnel dielectric layer over the exposed side edges of layers 521 and 523. The thicker tunnel dielectric layer is about 1 to 5 nm thicker than the tunnel dielectric layer over the P ^- sublayer 522 because the oxidation rate of N ⁺ doped polysilicon is significantly faster than that of silicon nitride. Because the Fowler-Nordheim tunneling current depends exponentially on the tunneling dielectric thickness, even a thicker tunnel oxide layer of 1 nm significantly impedes charge tunneling from the N ⁺ region into the charge confinement layer 531 during programming.

Figure 5G shows a cross-sectional view in the ZX plane of active layers 502-6 and 502-7 of an embodiment (EMB-3A) formed using the second option of processing. Figure 5g shows the formation of an optional ultra-thin dopant diffusion barrier layer 521-d in the sub-layer 522 forming the channel region of the TFT ( _TR 585, _TR 587) and the formation of undoped or P ^- doped polysilicon. , shows an example (EMB-3A) after deposition of amorphous silicon or silicon germanium. Channel material is also deposited on the sidewalls of trench 545 to form pillars 290 connecting the channel region of the TFT (i.e., P ^- sublayer 522) to substrate circuitry 262. In all active layers, a simultaneously formed P ^- sublayer 522 provides the channel length (L). Cavities 537 and gaps 538 between neighboring fillers 290 may be completely filled with thicker P ^- polysilicon or silicon germanium, left as partial void isolation, or with dielectric isolation (e.g., silicon dioxide). It can be filled. In embodiment (EMB-3A) the filler 290 surrounding the sides of active strips 502-6 and 502-7 provides desirable electrical shielding to reduce parasitic capacitive coupling between adjacent active strips on the same plane. do. Capacitive shielding between active strips in adjacent planes within the stack may be achieved by partially or entirely removing the ISL material within the separation layer (e.g., separation layers 503-6 and 503-7) (see Figure 5G). (not shown) can be improved by etching.

Under the second option processing, i.e., while forming the charge confinement layer 531 before the P ^- sublayer 522, the ISL material between the active layers is (SAC1) to expose the back side of the charge confinement layer 531. may be etched (prior to removal of the material). The exposed backside of charge confinement layer 531 is comprised of some or all of the exposed charge confinement material (typically silicon-rich silicon nitride) and a tunnel dielectric (typically SiO2), indicated as region 523X in Figure 5g. ₂ ) is allowed to be removed. Shaded region 532 . After the ISL material and exposed charge confinement material are removed, the remaining cavity in region 532x may be filled with another dielectric layer after removal of the SAC1 material from sublayer 522, or may remain as a void. In embodiments where the ISL material is only partially removed, the filler 290 partially separates the N ⁺ sublayer 523 of the TFT ( _TR 585) from the N ⁺ sublayer 521 of the TFT ( _TR 587). The etched ISL can be filled, resulting in a space for filling. As in the embodiment (EMB-1A), all P- sublayers 522 in the active layer are connected to the P ⁺ circuit 262-0 through pillars 290 in substrate 201.

The dopant diffusion barrier 521-d can be formed for all active layers in a single step prior to deposition of the P ^- sublayer 522 (Figure 5g), thus significantly simplifying the iterative process of Figures 2b-5. . However, since the deposition of the P ^- sublayer 522 is performed near the end of processing, after all high temperature annealing has already occurred, the ultra-thin dopant diffusion barrier layer 521-d can be omitted. In embodiments where connection of the pillar 290 to substrate circuitry is not required for the clearing operation, the vertical walls of the P ^- pillar 290 within the trench 530 form a P ^- sub lining the cavity 537. It can be etched away, leaving only layer 522 and trench 530 with void separation between adjacent active strips in all planes.

Pillar 290 and conductor 208W provide electrical shielding to suppress parasitic capacitance coupling between adjacent thin film transistors in each plane. As observed from FIG. 5G, pillar 290 and P ^- sublayer 522 may be formed before or after formation of charge confinement material 531 and local word lines 208W.

It is understood that the processing sequences presented above are examples and that other processing sequences or variations may be used within the scope of the present invention. For example, an alternative approach is to selectively etch the SAC1 material with a controlled lateral etch, instead of completely excavating the SAC1 material to form a cavity that subsequently forms the sublayer 522, thereby forming the N+ sublayer 522. Recesses inward from one or both side edges of the stack leaving a narrowed-down spine of the SAC1 material that mechanically supports the separation between the 523 and N+ sublayers 521. , then simultaneously filling all planes with chemical material in the first sublayer 522 and removing the channel material from the sidewalls of trench 530 to form recesses now separated from each other by the remaining spines of SAC1 material. This results in the remaining P ^- sublayers 522-0 through 522-7, followed by the next processing steps to form charge confinement material 531 and conductor 208W. These steps are shown in Figures 5h-1 to 5h-3. Specifically, Figure 5H-1 is a cross ^- section 500 in the Z shows. 5H-2 shows SAC1 (along the direction indicated by reference numeral 537) to form an optional support spine from SAC1 material (e.g., spine (SAC1-a)), according to one embodiment of the present invention. A cross-section 500 is shown in Figure 5H-1, with the recess filled with P ^- doped channel material (e.g., polysilicon) on the sidewalls of the active strip, after selective etching of the material laterally. Figure 5H-3 shows the P ^{- material after removal of the P -} material leaving the P ^- sublayer 522 in the recess, from the region 525 along the side wall of the active strip, according to one embodiment of the invention. A cross section 500 is shown. 5H-3 also illustrates the removal of isolation material from trench 530, formation of charge confinement layer 531 and local word line 208-W, and thus transistors T _L 585 and T _R 585) is shown to form.

5A, 5B, and 5C, N ⁺ sublayers 521-0 through 521-7 and 523-0 through 523-7 can all be formed in a single deposition step under different processing (“Processing Flow B”). there is. Under processing flow B, a third sacrificial layer (dielectric material (SAC3), not shown) may be deposited in place of N ⁺ sublayers 521 and 523. Thereafter, similar to how the SAC1 material is etched to form a cavity to be filled with P ^- polysilicon, the SAC3 material is etched simultaneously for all planes in semiconductor 500 to form a cavity to be filled with N ⁺ doped polysilicon. It can be etched away for removal. The SAC3 material should already have high etch selectivity over the appropriate ISL, SAC1 and SAC2 materials. To remove the N ⁺ polysilicon within trench 530 - which would otherwise short out vertically adjacent N + source and N + drain sublayers - an anisotropic etch (terminated by a simple isotropic etch to remove thin polysilicon stringers) is performed. there is. Under processing flow B, the SAC3 material from all sublayers 521 and 523 of the active layer is preferably simultaneously fed into the cavity so that all N ⁺ sublayers 521 and 523 can be annealed in a single high temperature rapid annealing step. It is etched and then filled with N ⁺ polysilicon. To form P ^- sublayer 522, cavity 537 (FIGS. 5E and 5G) is formed by etching the SAC1 material only after an annealing step and then filling the resulting cavity with P-polysilicon. . Under processing flow B, all active layers 502-0 through 502-7 use a “stair-step via” approach, instead of the buried contacts 205-0 and 205-1 of FIG. 5B. It can be preferably connected from the top of the semiconductor structure 500 to the substrate circuits 206-0 and 206-1.

Source-drain leakage in long NOR strings

In long NOR strings, the current of one accessed TFT in a read operation must compete with the accumulated subthreshold leakage current from thousands or more parallel unselected TFTs. Similarly, a pre-charged strip capacitor (C) must compete with the charge leakage through thousands or more transistors in a NOR string, rather than with the charge leakage of just one transistor (as in a DRAM circuit). The charge leakage substantially reduces the charge leakage time, possibly by hundreds of microseconds, which requires counter measurements to reduce or neutralize this leakage, as discussed below. However, as will be discussed below, leakage begins to occur for a thousand or so transistors during read operations. During program, program stop, or erase operations, source sublayer 221 and bitline sublayer 223 are preferably maintained at the same voltage, so that transistor leakage between the two sublayers is not significant (program, program stop, or erase operations). During operation the leakage of charge from the capacitor C is mainly to the substrate through the substrate selection circuit, which is formed of single crystal or epitaxial silicon where the transistor leakage is very low). During a read operation, the relatively short retention time of 100 μs of charge on the source and bit line capacitors is sufficient time to complete a sub-100 nanosecond read operation (see below) of the TFT of the present invention. The main difference between TFT and DRAM cells in the NOR string of the present invention is that, unlike DRAM cells, in which information is lost forever unless refreshed, the former is a non-volatile memory transistor, and hence even if the parasitic capacitor (C) is fully discharged, , the information stored in the selected TFT is not lost from the charge storage material (i.e., the charge confinement layer 231 in embodiments (EMB-1, EMB-2, and EMB-3)). Capacitor C is used to temporarily maintain the pre-charge voltage on N ⁺ sublayers 221 and 223 at one of the voltages V _ss , V _bl , V _progr , V _inhibit , or V _erase ; C is not used to store actual data for any of the non-volatile TFTs in the string. Pre-charge transistor 303 (FIG. 3A), controlled by word line 151n (208-CHG), is immediately activated momentarily, and then voltage V _b1 is connected to the board circuit (not shown) via connection 270. A read, program, program stop, or delete operation is performed by transferring data from the capacitor C of the sublayer 221 to the capacitor C of the sublayer 221. For example, the voltage (V _bl ) may be adjusted to precharge N ⁺ sublayer 221 to a virtual ground voltage of ~0V during read, or to connect both N ⁺ sublayers 221 and 223 to ~5V and ~0V during program stop. It can be set to ~0V, to pre-charge between 10V. The value of the cumulative capacitor (C) can be increased by extending the active string to accommodate thousands or more TFTs along each side of the string, which correspondingly increases the pre-charge voltage (N ⁺ V _ss on sublayer 221). ) increases the holding time. However, longer NOR strings suffer from increased resistance (R) as well as higher leakage current between N ⁺ sublayer 221 and N ⁺ sublayer 223; These leakage currents can interfere with the sensed current when reading one TFT being addressed with all the other TFTs in the "off" (but somewhat leaky) state. To accelerate pre-charging of the capacitance C of a long active strip, several pre-charged TFTs 303 are spaced along one side of the active strip (e.g., one every 128, 256 or more TFTs). each time) can be provided.

HIGHLY SCALED NON-VOLATILE MEMORY TFT WITH SHORT CHANNELS

The ultra-thin anti-diffusion layer 521-d reduces the thickness of the SAC1 material, thereby enabling highly scaled channel lengths in non-volatile memory TFTs (“ultra-short channel TFTs”; e.g., the TFT in Figure 5f ( T _R 585) enables channel length (L)). For example, a highly scaled channel length may be 40 nm, while the thickness of SAC1 material suitable for the P ^- sublayer 522 may be reduced to 20 nm or less. TFT channel scaling is improved by having an extremely thin P ^- sublayer 522, in the range of 3 to 10 nm, just enough to support the TFT channel inversion layer and thin enough to be consumed through the entire depth under an appropriate control gate voltage. do. Read operations for ultra-short channel TFTs require that the P ^- sublayer 522 be relatively heavily P ^- doped (eg, between 1×10 ¹⁷ /cm ³ and 1×10 ¹⁸ /cm ³ ). Shorter channel lengths result in higher read currents at lower drain voltages, thus reducing power dissipation for read operations. Highly scaled channels have the additional benefit of thinning the overall thickness of the active layer, thus making it easier to etch from the top active layer to the bottom active layer. Ultra-short channel TFTs can also be erased via a lateral-field-assisted charge-hopping and tunnel-erase mechanism, discussed below in conjunction with FIG. 7.

Exemplary operation for NOR strings of the present invention is described below.

read action

To read any one of the multiple TFTs along the NOR string, the TFTs on both sides of the active strip are non-conducting such that all global and local word lines in the selected block are initially held at 0 V. Alternatively, it is initially set to the “off” state. As shown in Figure 3A, an addressed NOR string (e.g., NOR string 202-1) may share sensing circuitry among several NOR strings via decoding circuitry within substrate 201, or Each NOR string can be connected directly to a dedicated sensing circuit so that multiple other addressed NOR strings sharing the same plane can be sensed in parallel. Each addressed NOR string has its source line (i.e., N ⁺ sublayer 221) initially set to V _ss -0V. (To simplify this discussion, in the context of FIGS. 3A-3C, N ⁺ sublayers 221 and 223 are referred to as source line 221 and bit line or drain line 223, respectively). In implementations using wired source connections, voltage V _ss is supplied from substrate 201 to source line 221 via wired connection 280 . Figure 3b shows a typical read cycle for a NOR string with source voltage (V _ss ) wired. Initially, all word lines are at 0V and the voltage on source line 221 is maintained at 0V through connection 280. Thereafter, the voltage on bit line 223 rises to V _bl -0.5 V to 2 V, which is supplied from the board through connection 270, which is also the voltage at the input to sense amplifier (V _SA ). After bit line 223 is raised to V _bl , the selected word line (word line 151a; denoted “WL-sel”) undergoes incremental stepped voltages (as shown in FIG. 3B). ) is ramped up, while all other unselected word lines (word line 151b; denoted “WL-nsel”) remain in the “off” state (0V). The voltage on the selected gate electrode begins to conduct after exceeding a threshold voltage programmed into the selected TFT (e.g., transistor 152-1 on strip 202-1), and thus the addressed string 202-1. ) begins to discharge the voltage (V _bl ) (event A in Figure 3b) detected by the sense amplifier connected to ).

An embodiment (EMB-1, EMB) employing pre-charging of the accumulated parasitic capacitance (C) (i.e., the total capacitance of all capacitors, denoted as 360 in each NOR string in Figure 3a) to the “virtual V _ss ” voltage. -2 and EMB-3), the pre-charge TFT 303 (FIG. 3B) shares the source line 221 and the bit line or drain line 223 of the NOR string (pre-charge TFT 303 is the memory TFT may have the same configuration as, but is not used as a memory transistor and may have a wider channel to provide higher current during the pre-charge pulse), and the bit line voltage ( It has its drain line 223 connected to V _bl ). In a typical pre-charge/read cycle (see Figure 3c), V _bl is initially set to 0V. The pre-charge word line 208-CHG of the TFT 303 transfers V _bl ~0V from the bit line 223 to the source line 221, bringing the "virtual V _ss " voltage on the source line 221 to ~0V. To establish, it is momentarily raised to about 3V. After the pre-charge pulse, bit line 223 is set to near V _bl ~2V via bit line connection 270. The V _bl voltage is also the voltage at the sense amplifier for the addressed NOR string. If a larger operating window is required between the cleared and programmed V _th voltages, while all other global word lines and their local word lines in the block are in the "off" state (0V), one selected global word line and all Its associated vertical local wordline 151a (denoted “WL-sel”) (i.e., slice 114 in Figure 1A-2) is stepped from 0V to typically 3V-4V (shown as a step voltage in Figure 3D). ), or higher. The selected TFT is in erased state (i.e. V _th = When at V _erase ~1V), the bit line voltage (V _bl ) begins discharging toward the source voltage (V _ss ) when its word line voltage rises above ~1V. If the selected TFT is programmed to V _th ~2V, the bit line voltage will begin discharging only when its word line voltage rises above ~2V. A voltage drop in voltage (V _bl ) (event B in FIG. 3C) occurs in the sense amplifier when the charge stored on bit line 223 begins to discharge through the selected TFT toward voltage (V _ss ) on source line 221. It is detected. All unselected word lines 151b (denoted “WL-nsel”) in the NOR string may contribute to the subthreshold leakage current between N ⁺ sublayer 223 and N ⁺ sublayer 221, respectively. Even if it is present, it is “off” at 0V. Therefore, it is important that the read operation closely follows the pre-charge pulse before the leakage current significantly degrades the V _ss charge on the NOR string's capacitor (C). The pre-charge phase typically depends on the distributed capacitance (C) and distributed resistance (R) of the N ⁺ sublayers 221 and 223, and the magnitude of the pre-charge current supplied through the pre-charge TFT 303. Depending, it has a duration of 1 to 10 ns. Pre-charging can be achieved by using some of the memory TFTs along the NOR string to temporarily pre-charge the transistors, although care must be taken to avoid driving the gate voltage high enough to cause a disturb condition for the programmed threshold voltage. It can be accelerated by increasing the current through the pre-charge TFT 303, which acts as a.

All TFTs 152-0 through 152-3 within slice 114 (FIG. 1A-2) have different active layers 202-0 through 152-3 when a read operation is initiated from the respective substrate circuitry via pre-charge TFT 303. If the active strips on 202-7) are all pre-charged (individually or simultaneously), and if the active strips on different active layers have dedicated sense amplifiers connected via their respective connections 270, then their local word lines 151a. TFTs on different active strips on (WL-sel) and therefore on different planes can be read simultaneously (i.e. in parallel) during a single read operation. This slice-oriented read operation increases the read bandwidth by a factor corresponding to the number of planes in the memory block 100.

Multibit (MLC), archival (ARCHIVAL), and analog thin-film transistor strings

In embodiments where MLC (i.e., a multi-level cell in which more than one bit of information is stored within the TFT) is used, the addressed TFT in the NOR string has several threshold voltages (e.g., For the four states, each representing two bits, can be programmed to be either 1V (for the erase state), 2V, 3V or 4V. The addressed global word line and its local word line can be raised in incremental voltage steps until conduction in the selected TFT is detected by the respective sense amplifier. Alternatively, a single wordline voltage (e.g. ~5V) and the discharge rate of the voltage (V _bl ) can be compared to the discharge rate of each of several programmable reference voltages representing the four voltage states of the two binary bits stored on the TFT. This approach can be extended to store 8 states (for an MLC TFT of 3 bits), 16 states, or a continuum of states, providing analog storage efficiently. The programmable reference voltage is stored on a reference NOR string, typically within the same block, preferably located in the same plane as the selected NOR string, in order to best track manufacturing variations among the active strips in different planes. For MLC applications, more than one programmable reference NOR string may be provided to detect each of the programmed states. For example, if 2 bits of MLC are used, three reference NOR strings could be used, one for each intermediate programmable threshold voltage (e.g., 1.5 V, 2.5 V, 3.5 V in the example above) . Since there may be thousands of activity strips on each plane in a block, the programmable reference NOR strings can be repeated, for example, one set shared between every eight or more NOR strings in a block.

Alternatively, the reference NOR string can be programmed to a first threshold voltage (e.g., ~1.5 V slightly above the erase voltage of ~1 V), such that the additional ~2.5 V and ~3.5 V reference programmed voltage levels are ~ This can be achieved by pre-charging the virtual source voltage (V _ss (source line 221)) of the reference NOR string with a step or ramp voltage starting from 0 V and ramping it up to ~4 V, while correspondingly higher than the V _ss voltage. Increase the voltage (V _bl ) on the reference NOR string bit line 223 to be ~0.5 V. The word line voltage applied to the reference TFT and the word line voltage applied to the memory TFT to be read are both the same global word. Since each reference NOR string can be easily set to its respective gate-source voltage, independently of all other NOR strings in the block, this "on-the-fly" operation of various reference voltages is identical throughout. (on the fly)" setting becomes possible.

The flexibility of setting the reference voltage for the reference NOR string, by adjusting its V _ss and V _bl voltages, instead of actually programming the reference TFT with any of the distinct threshold voltages, allows storage of the continuum of NOR voltages. Provides analog storage on each storage TFT in the string. As an example, during programming, the reference NOR string can be set to a target threshold voltage of 2.2V, when programming the storage TFT to ~2.2V. Then, during read, the voltages of the reference string (V _ss and V _bl ) are ramped across the word line at ~4V for the reference TFT and storage TFT in a sweep starting at ~0V and ending at ~4V. As long as the ramping reference voltage is below 2.2V, the signal from the reference TFT is stronger than that of the programmed memory TFT. When the reference TFT is ramped past 2.2V, the signal from the reference TFT becomes weaker compared to the signal from the storage TFT, which results in flipping of the output signal polarity from the differential sense amplifier, and the 2.2V programmed It is expressed as the stored value of TFT.

The NOR string of the present invention can be employed for archival storage of rarely changing data. Since archival storage requires the lowest possible cost per bit, selected archival blocks of the NOR string of the present invention can be programmed to store, for example, 1.5, 2, 3, 4 or more bits per TFT. For example, storing four bits per TFT requires 16 programmed voltages between ~0.5V and ~4V. The corresponding TFT in the reference NOR string can be programmed to ~0.5V while programming the storage TFT to the target threshold. During a read operation, the source and drain voltages (V _ss and V _bl ) of the reference string are ~ until the output polarity of the sense amplifier is flipped, which occurs when the signal from the reference NOR string becomes weaker than the signal from the store or program TFT. Increased in increments of .25V. Strong ECC in the system controller can correct any intermediate program state that drifts during long stores or after a significant number of reads.

Even when all TFTs in a NOR string are turned off, when a NOR string in a block experiences excessive source-to-drain leakage, this leakage substantially matches the leakage current of a non-reference NOR string in the same block. , the leakage current of the reference string can be substantially neutralized by a modified reference string by adjusting the voltages on its shared source (V _ss ) and shared drain (V _b1 ).

REVOLVING reference NOR string address position to extend cycle durability

In applications requiring a large number of write/erase operations, the threshold voltage window of operation for a TFT in a NOR string deviates from the threshold voltage window programmed into the TFT of a reference NOR string early in the life of the device, through cycling. You can drift. A mismatch that increases over time between the TFT on the reference NOR string and the TFT on the addressed memory NOR string can defeat the purpose of the reference NOR string if left empty. To overcome this drift, the reference NOR string in a block need not always be at the same physical address and need not be permanently programmed for the entire life of the device. Because the programmable reference NOR string is effectively identical to the memory NOR string sharing the same plane in the block, the reference NOR string need not be dedicated for that purpose in any memory array block. In fact, any one of the memory NOR strings can be set aside as a programmable reference NOR string. In fact, the physical address position of a programmable reference NOR string may be periodically rotated between multiple memory NOR strings to eliminate performance degradation of the memory NOR string and the reference NOR string as a result of excessive program/erase cycles (e.g. For example, it may change once every 100 times a block is deleted).

In accordance with the present invention, any NOR string can be periodically rotated to designate a programmable reference NOR string, and its address position can be stored inside or outside the addressed block. The stored address can be retrieved by the system controller when reading the NOR string. Under this scheme, rotation of the reference NOR string can be done either randomly (e.g., using a random number generator to specify new addresses) or systematically among the active memory NOR strings. Programming of a newly designated reference NOR string can be done as part of an erase sequence when all TFTs on a slice or block are erased together, followed by setting a new reference voltage for the newly designated setting of the reference NOR string. In this way, all active memory NOR strings and all reference NOR strings in a block can drift somewhat statistically simultaneously through extensive cycling.

Programmable Reference Slice

In some embodiments of the invention, a block may be divided into four equally sized quadrants, as shown in Figure 6A. FIG. 6A shows semiconductor structure 600, a three-dimensional representation of a memory array comprised of quadrants Q1 through Q4. In each quadrant, (i) a plurality of NOR strings (e.g., NOR strings 112) are each formed in an activity strip extending along the Y direction, and (ii) a page (e.g., page 113). extends along the (iii) a slice (e.g., slice 114) extending in both the (e.g., plane 110) extends along both the

6B shows a TFT in a programmable reference NOR string 112-Ref in quadrant Q4 and a TFT in NOR string 112 in quadrant Q2 connected to a sense amplifier SA(a) - Q2. and Q4 is the “mirror image quadrant”—illustrating structure 600 in FIG. 6A. Figure 6b also shows (i) a program in quadrant Q3 that similarly provides the corresponding reference TFT for slice 114 in mirror image quadrant Q1, sharing a sense amplifier SA(b); (ii) a reference TFT in plane 110 in the mirror image quadrant (Q1) sharing a possible reference slice (114-Ref) (indicated by region B), and (ii) a sense amplifier (SA(c)), the same It shows a programmable reference plane 110-Ref in quadrant Q2, which provides a corresponding reference TFT for a NOR string (e.g., NOR string 112) in that quadrant.

As shown in Figure 6B, a programmable reference NOR string 112Ref may be provided in each quadrant to provide a reference voltage for the memory NOR strings on the same plane within the same quadrant, in the manner already discussed above. Alternatively, a programmable reference slice (e.g., reference slice 114Ref) is provided on a mirror image quadrant for the corresponding memory slice. For example, reference slice 114Ref programmed in quadrant Q3 is simultaneously provided to sense amplifier 206 shared between quadrants Q1 and Q3 when reading a memory slice in quadrant Q1. Similarly, reference slice 114Ref in quadrant Q1 is provided to shared sense amplifier 206 when reading a memory slice in quadrant Q3. To partially accommodate the discrepancy in RC delay between the slice being read and its reference slice, there may be more than one reference slice distributed along the length of the NOR string 112. Alternatively, the system controller may calculate and apply a time delay between the global wordline of the addressed slice and that of the reference slice, based on its respective physical location along its respective NOR string. Where the number of planes is a high number (e.g., eight or more planes), one or more of the planes in the quadrant are either of the remaining planes (i.e., to replace any defective planes) or of the same global wordline conductor ( 208g-a) can be added to the top of the block to serve as a programmable reference page that provides a reference threshold voltage for the addressed pages sharing it. Because both pages are activated by the same global word line, the sense amplifier at the end of each NOR string receives the read signal from the addressed page at the same time as it receives the signal from the reference page at the top of the block.

In one embodiment, each memory block is comprised of two halves, for example, quadrants Q1 and Q2 are comprised of the “upper half” and quadrants Q3 and Q4 are comprised of the “lower half”. . In this example, each quadrant has 16 planes, 4096 (4K) NOR strings in each plane, and 1024 (1K) TFTs in each NOR string. It is customary to use the "K" unit, which is 1024. Adjacent quadrants (Q1 and Q2) have 1K global modules driving 2048 (2K) local word lines (208W) per quadrant (i.e., one local word line for each pair of TFTs from two adjacent NOR strings). A word line (e.g., global word line (208g-a)) is shared. The 4K TFT from quadrant Q1 and the 4K TFT from quadrant Q2 form an 8K bit page of TFTs. 16 pages form a slice of 128K bits, and a 1K slice is given as a half block, providing 256 Mbits of total storage per block (where 1 Mbit is 1K × 1 Kbit). The 4K strings in each plane of quadrants Q2 and Q4 share a substrate circuit 206, including a sense amplifier (SA) and a voltage source for voltage (V _bl ). Additionally, residual NOR strings are used as spares to replace defective NOR strings, as well as to store quadrant parameters such as program/erase cycle count, quadrant defect map, and quadrant ECC. This is included. This system data is accessible to the system controller. For blocks with a high plane coefficient, it may be desirable to add one or more planes to each block as an extra to replace defective planes.

Programmable reference plane, extra plane

The high-capacity storage system based on the array of NOR strings of the present invention provides the full potential for error-free, massively parallel erase, program and program halt, and read operations that can span thousands of "chips" containing hundreds of memory blocks. It requires a dedicated, intelligent, high-speed system controller to manage it. To achieve the necessary high speeds, off-chip system controllers typically rely on state machines or dedicated logic functions implemented in memory circuitry. In addition, each memory circuit stores system parameters and information related to files stored in the memory circuit. This system information is typically accessible to the system controller, but is not accessible by the user. It is advantageous for the system controller to quickly read information related to the memory circuit. For a binary memory system with 1 bit stored per TFT (e.g., in the block configuration of Figure 6A), the storage capacity in each block accessible to the user is 4 quadrants × 16 planes per block × plane per quadrant. It is given as 4K NOR strings × 1K TFTs per NOR string - equivalent to 256M bits.

A block under this configuration (i.e. 256 megabits) provides 2K slices. By including 4K blocks, a terabit memory circuit can be provided.

6A and 6B, in quadrants Q2 and Q4, the TFT has a voltage source (V _bl ), a sense amplifier (SA), a data register, an (I/O) terminal is shared. According to one configuration, FIG. 6A shows a NOR string 112, a quarter plane 110, a half slice 114, and a half page 113. Also shown is a pillar 290 that supplies a back bias voltage (V _bb ) from the substrate. Figure 6B shows an example of the positions of reference string 112 (Ref), reference slice 114 (Ref), and reference plane 110 (Ref). In the case of the reference string, the reference string 112 (Ref) in quadrant Q4 can serve as a reference string for the NOR string 112 on the same plane in quadrant Q2, and the two NOR strings are connected to the circuit ( 206) is provided to the shared differential sense amplifier (SA). Likewise, reference slice 114 Ref (zone A) in quadrant Q1 can serve as a reference for slices in quadrant Q3, while reference slice B in quadrant Q1 can serve as a reference for slices in quadrant Q1 and Q3) can serve for a slice in quadrant (Q3), again sharing the differential sense amplifier (SA) provided between them. The global word line (208g-a) is connected to the local word line (208W) and the local precharge word line (208-CHG). The substrate circuitry and input/output channels 206 are shared between TFTs in quadrants (Q2 and Q4). Under this arrangement, their physical location allows for cutting the resistance and capacitance of the NOR string 112 in half. Similarly, global wordline drivers 262 are shared between quadrants (Q1 and Q2) to halve the resistance and capacitance of the global wordlines, and pillars 290 (optional) drive the NOR string ( 112) P ^- connects the sublayers.

Because the real estate of silicon on an integrated circuit is expensive compared to adding a reference string or reference page to each plane, it may be advantageous for some or all of the reference strings or reference pages to be provided in one or more additional planes. there is. The additional plane or planes consume minimal additional silicon real estate, and the reference plane ensures that the addressed global word line 208g-a is positioned on any of the planes at the same address location along the activity string in the same quadrant. It has the advantage of accessing the reference page at the same time as accessing the page. For example, in Figure 6B, reference string 112Ref, shown as a dashed line in quadrant Q2, is in this example at reference plane 110Ref. NOR string 112Ref tracks which memory NOR string 112 is selected for read in the same quadrant, and the read signals from both NOR strings arrive at the differential sense amplifier (SA) for that quadrant virtually simultaneously. Although the reference plane 110Ref is shown in FIG. 6B as being provided at the top surface, any of the quadrants may be designated as the reference plane. In fact, not all NOR strings on a reference plane need to be reference strings; for example, each one of the eight NOR strings could be designated as a reference NOR string that is shared by the eight NOR strings in the other planes. The remainder of the NOR string in the reference plane can serve as an extra string to replace the defective string on another plane within the block.

Alternatively, one or more additional planes (e.g., plane 117 in Figure 6C) serve as extra memory resources to replace a faulty NOR string, faulty page, or faulty plane in the same quadrant. It can be set separately to do so.

With respect to an electrically programmable reference string, slice, page or plane, once set to a specified threshold voltage state, care must always be taken to prevent inadvertent programming or erasure of non-reference strings while programming, erasing or reading them. It must be tilted.

A very large storage system of 1 ^petabyte (8 am). This is a significant amount of data to be written (i.e. programmed) or read. Therefore, it is beneficial to program and read a significant number of blocks, slices, or pages at once on multiple chips in parallel, with minimal power loss at the system level. Additionally, it is advantageous to have terabit capacity memory chips have multiple input/output channels so that requested data can be streamed from and to multiple blocks in parallel. The time required to track the physical location of the most recent version of any given stored file or data set requires a significant amount of time for the system controller to maintain, such as translating the logical address to the most recent physical address. will be. Translation between logical and physical addresses would require, for example, a large centralized lookup FAT (file allocation table) to access the right slice within the right block on the right chip. This search may add significant read latency (e.g., in the range of 50 to 100 μs) that would defeat the goal of high-speed read access (e.g., less than 100 ns). Accordingly, one aspect of the present invention provides system-wide parallel on-chip rapid file searches to dramatically reduce the latency associated with large, centralized FATs, as described below. By introducing it, the search time is significantly reduced.

High-Speed Reads: PIPELINED STREAMING and Random Access

At system startup of the virgin multi-chip storage system of the present invention, all chips are erased and a reference string, reference slice or reference plane is programmed to its reference state. The system controller designates the memory slice that is physically closest to the sense amplifier and voltage source 206 (e.g., slice 116 in Figure 6C) as the cache store. Due to the RC delay along the length of each NOR string, the TFT in each string physically closest to substrate circuitry 206 will have its voltage (V _bl ) established several ns earlier than the TFT furthest from substrate circuitry 206. ) will have. For example, from the 1K slices in each quadrant, the first to 50 slices, etc. (shown as slices 116 in FIG. 6C) have the shortest latency and are responsible for the quadrant operating parameters, as well as files or data sets stored in the quadrant. It can be designated as a cache memory or storage that will be used to store information about. For example, each memory page (2 Along with the index number, it may have a unique identifier number assigned to it by the system controller.

Cache storage can be used to store on-chip resource management data, such as file management data. A file may be, for example, a “hot file” (i.e., associated with a high number of accesses or a “high cycle count”), a “cold file” (i.e., not changed for a long period of time, ready to be moved to slower storage or archival memory at a future time), “delete files” (i.e. ready for future deletion in background mode), “defective files” (i.e. ready to be skipped) ), or may be identified as a “replacement file” (i.e., replaces a defective file). Additionally, the identifier may include a timestamp indicating the last time and date the file associated with the identifier was placed in the quadrant. This unique identifier, typically between 32 and 128 bits long, may be written to one or more of the cache slices as part of the write of the file itself from the same half block to another memory slice. Files are written sequentially into the available cleared space, and identifiers can be assigned by incrementing the previous unique identifier, one for each new file written to memory. If desired, the new file may be recorded in partial slices, and the unwritten portion of the slice may be used for the recorded portion or the entirety of the next file, to avoid wasting storage space. Writing sequentially until the entire memory space of the system is used helps eliminate TFT wear-out throughout the system. Other on-chip resource management data includes chip, block, plane, slice, page, and string parameters, faulty strings and their replacement strings, and address locations of faulty pages, faulty planes, faulty slices, and faulty blocks. and its alternative replacements, file identifiers for all files within the block, lookup tables and link lists to skip unusable memory, block erase cycle coefficients, optimal voltage and pulse shape, and erase, program, program-stop, It may include periods for program scrub, read, margin read, read refresh, read scrub operation, error correction code and data recovery mode, and other system parameters.

Due to the modularity of each chip at the block level and the low-power operation involved in Fowler-Nordheim tunneling for program and erase, erasing of some blocks, programming in some other blocks, and reading one or more of the remaining blocks can be executed simultaneously. It is possible to design a chip to do so. The system controller can use that parallelism of operations at the block level to work in background mode; For example, the system controller may delete some blocks or entire chips (i.e., delete them to free space), defragment fragmented files into unified files, and file files that have been inactive for longer than a predetermined amount of time. , moving blocks or chips to slower or archival storage, or chips that group files together with nearby dates and timestamps, while storing the original file identifier with the most recent timestamp in cache storage for the next available physical block. It can be rewritten as (116).

To facilitate rapid retrieval of the location of the most recent version of any one file from the millions of such files on a petabyte storage system, a unique identifier for each file is stored by the system controller no matter where it is physically relocated. It is important to be able to access it quickly. According to one embodiment of the invention, the system controller broadcasts unique identifiers (i.e., words of 32 to 128 bits) for files that are retrieved simultaneously for some or all chips in the system. Each chip temporarily stores its identifier and, using an on-chip exclusive Or ( The controller is provided with a buffer memory for reporting with the location where the corresponding file is located. If more than one match is found, the system controller picks the identifier with the most recent timestamp. The search can be narrowed down to a few chips if the files being searched are recorded within the specified interval. For a 1 terabit chip, one 128 Kbit slice, or 16 × 8 Kb page, would be sufficient to store all 64-bit identifiers for all 2K slices in each block.

TFT pair for high-speed read cache memory

To reduce read latency to cache storage 116, TFTs in the NOR string physically closest to sense amplifier 206 may be arranged in pairs. For example, in an adjacent NOR string, two TFTs related by a common local word line can be shared to store a single data bit between them. For example, in embodiment EMB-3 (FIG. 2K), plane 202-7 includes a pair of TFTs that share a local wordline 208-W from an adjacent active strip (e.g. , TFT 281 on one NOR string may serve as a reference TFT for TFT 283 or vice versa). In a typical programming operation, the TFTs on both NOR strings are initialized to the erased state, and one of the TFTs (i.e., TFT 281) is programmed to a higher threshold voltage, while TFT 283 remains erased. To do this, the program is stopped. Both TFTs on adjacent active strips are simultaneously read by a differential sense amplifier in the substrate circuit when its shared local word line 208W is raised to the read voltage, and the first TFT that begins to conduct is either TFT 281 or TFT 283. ), depending on which of the TFTs is programmed, provides the sense amplifier in either state '0' or state '1' (tips).

This TFT pair method has the advantages of high-speed detection and higher durability because the TFTs of two adjacent NOR strings are almost perfectly matched, and even the small programmed voltage difference between the two TFTs read by the sense amplifier is correctly detected by the sense amplifier. This will be enough to make it trip. Additionally, because the threshold voltage of the programmable reference TFT may drift over multiple write/erase cycles over the life of the device, under this scheme, both the reference TFT and the read TFT are reset with each cycle. In fact, one of the two TFTs in the pair can serve as a reference TFT. To statistically ensure that two TFTs in a pair are randomly scrambled to invert or not invert data in each cycle, each TFT in each pair is the reference TFT for approximately the same number of cycles as the other TFT. plays the role of (Inverting/non-inverting code can be stored on the same page as the page being programmed to aid descrambling during read operations). Since the paired TFTs are in close proximity to each other, i.e. on two adjacent active strips on the same plane, the TFTs are designed to best neutralize (i.e. cancel) the strip leakage during read operations, or to They can best track each other for local changes in the process.

Alternatively, a TFT pairing scheme can be applied to TFTs on different planes where the pairs share a common vertical local word line. One drawback of this approach is that it reduces silicon efficiency by nearly 50%, since two TFTs are required to store one bit between them. For this reason, each block can be configured such that only a small percentage (e.g., 1% to 10%) of the blocks are used as high-speed dual TFT pairs, and the remainder of the blocks are operated as regular NOR strings and programmable reference TFT strings. The actual percentage set for the TFT pair method can be changed on the fly by the system controller, depending on the specific application. The high level of flexibility in operating the NOR string of the present invention provides that, unlike conventional NAND strings, the TFTs in a NOR string can be randomly addressed and operate independently of each other or of TFTs in other NOR strings. It results from the fact that

Many applications of data storage, such as video or high-resolution imaging, require data files occupying multiple pages or even many slices. These files can be accessed quickly in a pipelined manner, that is, the system controller stores the first page or first slice of the file in cache memory, while storing the remaining pages or slices of the file in low-cost memory, and pipes Streams data out in a line sequence. Thus, the pages or slices are linked in a continuous stream, so that the first page of the file is quickly read into the sense amplifier and passed to the data buffer shift register, in order to clock the first page from the block, in a pipelined sequence. They can be linked in a continuous stream to precharge and read the next slower page, thereby hiding the read access time of each page after the first page. For example, if a first page of 8Kbits stored in cache memory is read in 10 ns and clocked at 1 Gbit per second, then the full 8K bits will be clocked in more than enough time for the second page to be read from the slower, lower-cost pages. It will take almost 1 μs to complete clocking out. The flexibility provided by pre-charging randomly selected TFT strings allows their data strings to be routed on-chip to one or more data input/output ports, allowing more than one file from more than one block to be read together.

random access read

The pre-charge scheme of the present invention allows the data to be programmed to be clocked serially or accessed randomly, and similarly to be read serially in a stream or accessed randomly by word. For example, pages addressed in one plane can then be accessed randomly in 32-bit, 64-bit, or 128-bit words, one word at a time, for routing to the chip's input/output pads. , can be read in one or more operations on the sense amplifiers, registers, or latches of the addressed plane. In this way, the delay involved in stringing entire pages sequentially is avoided.

In all embodiments, for example in Figure 2H, only one TFT on either side of the activity strip can participate in either read operation; Every TFT on the other side of the activity strip must be set to the "off" state. For example, if TFT 285 is read, TFT 283 on the same active strip should be shut off. Other ways to read the correct state of a multi-state TFT are known to those skilled in the art.

Reading a TFT of the present invention requires that only the TFT to be read be "on", compared to a NOR string in which all TFTs in series with the one TFT being read must also be "on", compared to conventional NAND. It is significantly faster than reading flash memory cells. For a string with 1024 non-volatile TFTs on each side, an embodiment in which the metal sublayer 224 is not provided as an integral part of the active layer (see, e.g., memory structure 220a in Figure 2B-1). To provide an RC time delay of less than approximately 10 ns, the typical line resistance of each active strip is ∼500,000 ohms, and the typical capacitance of the active strip (e.g., capacitor 360 in FIG. 3A) is ~5 It is a femtofarad. If a metal sublayer 224 is provided to reduce the line resistance of the active strip, the line delay can be significantly reduced. To further reduce read latency, some or all planes in a selected memory block are kept pre-charged with their read voltages (V _ss (source line) and V _bl (bit line)), so that they immediately read the addressed TFT. It can be made ready for sensing (i.e., eliminating the time required for pre-charging right before the read operation). This ready-to-stand mode requires very low standby power because the current required to periodically recharge the capacitor 360 to compensate for charge leakage is very small. Within each block, all NOR strings on 8 or more planes can be pre-charged to be ready for high-speed reads; For example, after reading a TFT from the NOR string in plane 207-0 (FIG. 2A), the TFT from the NOR string in plane 207-1 will have its source and bit voltages (V _ss and V _bl ) undergo a read operation. Since it has already been set previously, it can be read immediately.

In memory block 100, only one TFT per NOR string can be read in a single operation. In a plane with 8,000 side-by-side NOR strings, 8,000 TFTs sharing a common global word line, with each NOR string connected to its own sense amplifier 206 at substrate 201 (FIG. 2C) They can all be read together. If each sense amplifier is shared between four NOR strings in the same plane, for example using a string decode circuit, then four read operations, each involving 2,000 TFTs, can be accomplished in four consecutive steps. It is required to be held. Each plane can be provided with its own set of dedicated sense amplifiers or alternatively one set of sense amplifiers can be shared between NOR strings in eight or more planes via a plane decoding selector. Additionally, one or more sets of sense amplifiers (see, e.g., sense amplifier (SA) 206 in FIGS. 6A, 6B and 6C) may be shared between NOR strings in a quadrant and its mirror image quadrant. Providing separate sense amplifiers for each plane allows simultaneous read operations of NOR strings in all planes, thereby improving read operation throughput. However, this higher data throughput comes at the cost of greater power dissipation and excess chip area required for additional sense amplifiers (although these may be within the substrate 201 below block 100). In practice, there is only one set of sense amplifiers per stack of NOR strings, with the first page in one plane being passed to a high-speed shift register with its sense amplifiers, while the first page in the second plane is connected to the second set of sense amplifiers. To be read as - the two sets share one set of input/output shift registers - data in and out of the memory block or pipeline clocking may suffice.

Parallel operation can also create excessive electrical noise through ground voltage bounce when too many TFTs are read all at once. This ground bounce is significantly suppressed in all embodiments that rely on pre-charge capacitor 360 to establish and temporarily maintain a virtual V _ss voltage for each active strip. In this case, the source voltage (V _ss ) of all NOR strings is not connected to the chip's V _ss ground wire, allowing any number of active strips to be sensed simultaneously without drawing charge from the chip ground supply.

Program (record) and program stop operations

There are several ways to program a TFT addressed in a NOR string to its intended threshold voltage. The most common method employed by industry over the past 40 years is by channel hot electron injection. Another commonly used method is by tunneling - direct tunneling or Fowler-Nordheim tunneling. One of these tunneling and charge confinement mechanisms is so efficient that very low current is required to program a TFT in a NOR string, allowing parallel programming of thousands of these TFTs with minimal power loss. For exemplary purposes, programming by tunneling involves applying a 20V pulse of 100 microsecond (μs) duration to the addressed word line (control gate) and 0V to the active strip (e.g., active layer 202-2 in FIG. 2A). It is assumed that the activity strip formed from 0) is requested to be authorized. Under these conditions, the N ⁺ sublayers 221 and 223 (FIG. 2B-1), which serve as the source and drain, respectively, are all set to 0V. The P ^- channel sublayer 222 of the TFT is inverted at the surface such that electrons tunnel into the corresponding charge confinement layer. TFT programming can be stopped by applying half the selection voltage (e.g., 10V in this example) between the local word line and the source and drain regions. A program stop can be achieved, for example, by maintaining the strip voltage at 0 V but lowering the word line voltage to 10 V, or by maintaining the word line voltage at 20 V but increasing the active strip voltage to 10 V, or some combination of the two. You can.

Only one TFT in an addressed activity strip can be programmed at a time, but TFTs in different activity strips can be programmed simultaneously during the same programming cycle. When programming one of a number of TFTs on one side edge of an addressed active strip (e.g. one TFT in an even addressed NOR string), all TFTs on the other side edge of the active strip (e.g. All TFTs in the NOR string that are addressed by an odd number (all other TFTs in the NOR string) are program stopped.

Once an addressed TFT is programmed to a target threshold voltage for its designated state, program stopping of that TFT is required when overshooting that target voltage places unnecessary stress on the TFT. When MLC is used, overshooting the target voltage can cause the TFT to overstep or merge the threshold voltage of the next higher target threshold voltage state, thus reaching its intended threshold voltage. The program must be stopped. It should be noted that all TFTs in adjacent active strips on the same plane that share the same global word line and their associated local word lines are exposed to a programming voltage of 20V and are required to be deprogrammed once they are programmed to their target threshold voltage. Additionally, TFTs that are in the erased state and remain in the erased state must be program stopped. Similarly, all TFTs (i.e., all TFTs in slice 114) that are within the same block and share the same global word line and its associated local word line - and thus are also exposed to a programming voltage of 20V - are also program halted. It is required to be possible. These program and program stop conditions are such that the even and odd sides of each active strip are controlled by different global word lines and their associated local word lines, and that the voltages on the shared source and bit lines of each active strip are the same regardless of their planes. Since it can be set independently of all other activity strips on one plane or another, all can be fulfilled for the memory block of the present invention.

In one example of a programming sequence, all TFTs in a block are first erased with a threshold voltage of approximately 1V. When the addressed TFTs are to be programmed, the voltage on the active strip of each addressed TFT is transferred (e.g., via precharge word line 208-CHG and connection 270, as shown in Figure 3A). or via wire connection 280) set to 0V; Otherwise, if left in an erased state (i.e., program stopped), the voltage on the shared source line of the active strip of the addressed TFT is set to ~10V. The global word line associated with the addressed TFT is then raised to ~20V in single or short steps of incrementally increasing voltage, starting at approximately 14V. These incremental voltage steps reduce the electrical stress across the charge confinement layer of the TFT and avoid overshooting the target programmed threshold voltage. All other global word lines in the block are set to half-selected 10V. All active strips on all planes that are not addressed within a memory block, as well as all active strips in addressed planes that are not individually addressed, are also set to 10V, as they are connected to the substrate circuits 206-0 and 206-1 of FIG. 2C. ) can be floated by ensuring that their access transistors (not shown) are off. Importantly, any of the active strips on all planes that are not addressed in a memory block, as well as all active strips within an address plane that are not individually addressed, are floated with that voltage set to ~0V, i.e., are not in program-stop mode. If not, it may be programmed incorrectly. These active strips are at 10V and are therefore strongly capacitively coupled to their local word lines, which float around 10V. Each of the incrementally higher voltage programming pulses is followed by a read cycle to determine whether the addressed TFT has reached its target threshold voltage. When the target threshold voltage is reached, the active strip voltage is raised to ~10V to stop further programming while continuing programming of other addressed strips on the sample plane that have not reached that target threshold voltage (alternatively, The strip floats and increases close to 10V when all addressed global word lines in the block except one rise to 10V). This program/read verify sequence read-verifies all addressed TFTs to ensure they are programmed correctly. All blocks on the chip that are dormant - ie they are not frequently accessed - should preferably be powered down, for example by setting the voltage on its active strips and conductors to ground potential.

When MLC is used, programming the correct one of multiple threshold voltage states can be accelerated in parallel by parallel programming of all target voltage states. First, the capacitor 360 of every addressed active strip (e.g., via connection 270 of FIG. 3A and precharge word line 208-CHG) is connected to one of several voltages (e.g., two voltages). When a bit of information is stored in each TFT, it is pre-charged (0, 1.5, 3.0 or 4.5V). A pulse of ~20 V is then applied to the addressed global word line, which causes the charge confinement layer of the TFT to change to a different effective tunneling voltage resulting in the correct one of the four threshold voltages being programmed in a single coarse programming step. (i.e., 20, 18.5, 17, or 15.5 V, respectively). Then, fine programming pulses can be applied at each TFT level.

Based on the inherent parasitic capacitance (C) of each active strip in a block, all active strips on all planes are properly activated (either in parallel or sequentially) before applying high voltage pulsing on the addressed global word lines. ) can have its pre-charge voltage state set. As a result, simultaneous programming of a significant number of TFTs can be achieved. For example, in Figures 1A-2, all TFTs within one page 113, or all pages within one slice 114, may be coarsely programmed in one high voltage pulsing sequence. Each read verification can then be performed and resetting the appropriately programmed activity strips to program stop mode where necessary. Pre-charging can be advantageous when the programming time is relatively long (e.g., about 100 μs), while pre-charging all capacitors 360 or read verifying the addressed TFT can be done 1,000 times faster, or about 100 μs. It can be performed over a time period of ns. Therefore, it is advantageous to program multiple TFTs with a single global wordline programming sequence, which is made possible because the programming mechanisms of direct tunneling or Fowler-Nordheim tunneling require only low current per TFT being programmed. Programming typically binds a hundred or fewer electrons in the charge confinement material to shift the TFT threshold by one or more volts, and these electrons become active in the string if the string has a sufficient number of TFTs contributing to the parasitic capacitance. It can easily be supplied from a reservoir of pre-charged electrons as a parasitic capacitor.

In order to properly shift the threshold voltage of a single TFT, programming the TFT with a conventional channel hot electron injection mechanism - which requires orders of magnitude more electrons compared to programming by tunneling - is less efficient than programming a single channel. Thermal electron injection is not suitable for use in embodiments that rely on pre-charging multiple active strips. Instead, channel hot electron injection programming requires wiring connections to the addressed source and drain regions during programming, severely limiting the ability to perform parallel programming.

delete action

Through some charge confinement layers, erasure is achieved through reverse-tunneling of bound electron charges, or through tunneling of holes to electrically neutralize the bound electrons. Erase is slow compared to programming and can require tens of ms of erase pulsing. Therefore, delete operations are often implemented in background mode, at block or multiple block levels. A block to be erased is tagged to be pre-charged to its predetermined erase voltage, subsequently erasing all tagged blocks together, continuing the erasure of other tagged blocks, while erasing those blocks that are verified to be properly erased. Stop. Typically, block erase is performed by maintaining all global word lines within the block at 0V, while maintaining the P-sub of each active strip through connections through filler 290 (FIGS. 3A, 4D, 2KA (FIG. 2K-1)). This can be done by applying ˜20V to layer 222 (FIG. 2B-1). However, since pillar 290 cannot be employed in embodiments in which metal sublayer 224 is used, there is no substrate contact to the P ^- channel 222, providing a path for excessive leakage between different planes. One alternative method for clearing all TFTs within a block ^is N ⁺ P ^- P - sub to a relatively high range of 1 × 10 ¹⁷ /cm ³ to 1 × 10 ¹⁸ /cm ³ to increase the reverse bias conduction characteristics. The layer 222 is doped. Then, when the N ⁺ sublayers 221 and 223 of all active strips to be removed are raised to ~20V (via substrate connection 206-0 ⁱⁿ Figure 2C), the reverse junction leakage is ) (channel region) is brought close to 20V, and tunnel erasure is initiated by releasing the electrons bound in the charge confined layer to the P ^- sublayer 222 for all TFTs through the local word line maintained at ~0V. .

Partial block deletion is also possible. For example, if only the TFTs on one or more selected slices 114 (FIG. 6B) are deleted, the filler 290, which is typically shared by all active strips in block 100, is the P ^- sublayer of all TFTs in the block. 222 (channel) is connected to a substrate circuit (e.g., substrate circuit 262-0 in FIG. 5B) to supply a high erase voltage (V _erase ). The global word lines of all slices in blocks other than the slice selected for erase are maintained at a half erase voltage of ~10V, or floated. One or more slices to be erased have their global wordlines brought to ˜0V during the period of the erase pulse. This method employs a high-voltage transistor that can withstand an erase voltage (V _erase ) of ~20V at its junction. Alternatively, pulse the addressed global word line with -20 V supplied from the board and charge all active strips within planes 202-0 through 202-7 to 0 V, while all but the addressed global word line are It is maintained at 0V. This method allows partial block erasure of one or more ZX slices 114 of all TFTs that share an addressed global wordline.

Other methods for partial block deletion may be possible. For example, if one or more selected Z-X slices will be deleted while all others are stopped for deletion; All global word lines within the block are first held at 0V, while all strings within the block are charged to half select voltage ~10V from the substrate and then isolated by switching off their access select transistors (not shown) at substrate 270. It remains in a floating state. Afterwards, all global word lines in the block are boosted to ~10V, increasing the voltage on all active strings to ~20V by capacitive coupling. Thereafter, the global word lines of one or more Z-X slices to be erased are brought to 0V, while the remaining global word lines remain at 10V for the duration of the erase pulse. To select an active strip for partial block erase, its access transistor in substrate 270 must be a high voltage transistor, capable of maintaining a charge of -20V on the active strip for a period of time beyond that required for a program or erase operation. The size and duration of the erase pulse should be such that most TFTs will be erased with a small enhancement mode threshold voltage between 0V and 1V. Some TFTs may overshoot and go into depletion mode (i.e., have a small negative threshold voltage). These TFTs are required to be soft programmed, as part of the erase sequence, to a lesser enhancement mode threshold voltage following the termination of the erase pulse.

FRINGING-FIELD ASSISTED LATERAL HOPPING TUNNEL ERASE IN HIGHLY SCALED SHORT-CHANNEL TFTs

As previously discussed in this disclosure, the active strip of the present invention can be produced with ultra-short channels (e.g., the P ^- sublayer of the TFT (T _R 585) of example (EMB-3A) in Figure 5G ( 522) can have an effective channel length (L) as short as 10 nm). 7 shows that the N ⁺ sub-layer 521 serves as a source, the N ⁺ sub-layer 523 serves as a drain, and the P ^- sub-layer 522 serves as a charge storage material 531 and a word line 208W. ) is a cross-section in the ZX plane of the active layer 502-7 of embodiment (EMB-3A), showing in more detail the single-channel TFT (T _R 585) of Figure 5g serving as a channel. FIG. 7 shows the N ⁺ sublayer ⁽ 521) and lateral hopping of the confined electron mechanism in the charge confinement material 531-CT (indicated by arrow 577), accompanied by electric field tunneling into the N ⁺ sublayer 523 (indicated by arrow 578). ) is used to delete a TFT with a sufficiently short channel length (L).

As shown in FIG. 7, the charge confinement layer 531 includes a tunnel dielectric sublayer 531-T, a charge confinement sublayer 531-CT (e.g., silicon-rich silicon nitride), and a blocking layer. It consists of a dielectric sublayer 531-B. Due to its very short channel length, the overlying channel (i.e. P- Sublayer 522) is defined by the fringing electric field between the local word line 208W and the N ⁺ sublayer 521 (source region) and N ⁺ sublayer 523 (drain region) (dotted ellipse 574 in FIG. 7 ) is strongly influenced by ).

During deletion, electrons (indicated by dashed lines 575) that are confined in the charge confinement sublayer 531-CT are transferred to the source region (N+ sublayer 521) and drain, respectively, as indicated by arrows 573 and 576. Areas (N ⁺ sublayer 523) - all of which are maintained at a high erase voltage (V _erase ) -20V - are erased by tunneling. In some circumstances, the voltage (V _erase ) on the P ^- channel 522 may be less than ~20V, especially if the P ^- pillar 290 is not provided, or the full ~20V cannot be supplied from the substrate, so that P ^- Tunnel erasure of electrons confined close to sublayer 522 may be less efficient. However, the fringing electric field 574 causes lateral migration of electrons (i.e., laterally, as indicated by arrow 577) in the silicon-rich silicon nitride of the charge confinement sublayer 531-CT. ) assists. This lateral movement is often referred to as hopping or Frankel-Poole conduction and results from electrons being pulled to ~20V on nearby source and drain regions. Once the electrons are moved close enough to the source and drain regions, they can tunnel out of the charge confinement sublayer 531-CT, as indicated by arrow 578. This fringing field assisted deletion mechanism will become increasingly efficient with shorter channel lengths (e.g., in the range of 5 nm to 40 nm) if source-drain leakage allows for short channels. For highly scaled channel lengths, the P ^- sublayer 522 should be made as thin as possible (e.g., 8 to within the 80 nm thickness range).

Pseudo-volatile random access TFT memory strings in three-dimensional arrays

The charge confinement materials described above (e.g., ONO laminates) have long data retention times (typically measured over several years), but have low durability. Endurance is a measure of the performance degradation of a storage transistor after a certain number of write-erase cycles. Endurances of less than about 10,000 cycles are considered too low for some storage applications that require frequent data rewriting. However, the NOR strings of embodiments of the invention (EMB-1, EMB-2, and EMB-3) substantially reduce retention time, but significantly increase durability (e.g., reduce retention time from years to minutes). or a charge confinement material that reduces durability to a few hours but increases durability from a thousand to thousands of write/erase cycles. For example, in ONO films or similar combinations of charge confinement layers, the tunnel dielectric layer - typically 5 to 10 nm of silicon oxide - is thinned to less than 3 nm, or is made of another dielectric (e.g., silicon nitride or SiN). It may be completely replaced by, or may not simply be removed. Similarly, the charge confinement material layer may be a more silicon-rich silicon nitride (eg, Si _1.0 N _1.1 ), which is richer in silicon than conventional Si ₃ N ₄ . Under a slightly positive control gate programming voltage, electrons (as distinct from Fowler-Nordheim tunneling, which typically requires higher voltages to program), connect a thinner tunnel dielectric layer to the silicon nitride charge confinement material layer. You can tunnel directly. Electrons can be temporarily confined in the silicon nitride charge confinement layer for minutes, hours, or days. A charge confining silicon nitride layer and a blocking layer (e.g., silicon oxide, aluminum oxide, or other high-K dielectric) prevent electrons from escaping into the control gate (i.e., word line). However, the bound electrons will eventually leak back into the N ⁺ sublayers 221 and 223 and P ⁻ sublayer 222 of the active strip, when the electrons become negatively charged and repel each other. Although the sub-3 nm tunnel dielectric layer breaks down locally after extended cycling, confined electrons are slow to escape from their confinement in the charge confinement material.

Other combinations of charge storage materials can also result in TFTs that are highly durable, but have short retention times (“semi-volatile” or “pseudo-volatile”). These TFTs may require periodic write refresh or read refresh to replenish lost charge. Because the TFTs of embodiments (EMB-1, EMB-2, and EMB-3) provide DRAM-like fast read access times with low latency by including any of the highly durable charge confinement layers in the TFTs, these TFTs A NOR string array with can be used in some applications that currently require DRAM. The advantages of these NOR string arrays over DRAM are: the cost per bit is very low since DRAM cannot be easily mounted in three-dimensional blocks, and refresh cycles occur on the order of every few minutes, compared to every ~64 ms required in current DRAM technology. Since it needs to be driven only once every hour or every few hours, it involves very little power loss. The quasi-volatile embodiment of the NOR string array of the present invention appropriately adjusts the program/read/erase conditions to incorporate periodic data refresh. For example, because each quasi-non-volatile TFT is frequently read-refreshed or program-refreshed, a large threshold voltage between the '0' and '1' states is typical for non-volatile TFTs, which require at least 10 years of data retention. To provide a window, it is not necessary to 'hard-program' the TFT. For example, the quasi-volatile threshold voltage window can be as small as 0.2V to 1V, compared to the typical 1V to 3V for a TFT supporting 10 year retention.

Read, program, MARGIN READ, and delete operations for pseudo-volatile NOR strings

The quasi-volatile NOR strings or slices of the present invention can be used in many memory applications, for example, in some or all memory devices supporting central processing unit (CPU) or microprocessor operation on a computer's main board ("motherboard"). It can be used as an alternative to DRAM. In these applications, memory devices are typically required to be capable of high-speed random read access and have very high cycle-endurance. At that capacitance, the quasi-volatile NOR string of the present invention employs a similar read/program/stop/erase sequence as the non-volatile NOR implementation. Additionally, because the charge stored on a programmed TFT leaks slowly, the lost charge must be replenished by reprogramming the TFT prior to a read error. To avoid read errors, if a program refresh operation is required, a "margin read" condition may be employed, as is well known to those skilled in the art. Margin read is an early detection mechanism that identifies when a TFT will soon become inoperable before it is too late to restore it to its correct program state. Quasi-volatile TFTs are typically programmed, program-stopped or erased with a reduced programming voltage (V _pgm ), program-stop voltage (V _inhibit ) or erase voltage (V _erase ), or programmed using shorter pulse periods. . Reduced voltage or shorter pulse duration results in reduced dielectric stress on the storage material, improving durability by orders of magnitude. Every slice within a block may require periodic reading under margin conditions to detect excessive threshold voltage shifts of the programmed TFT early due to charge leakage from its charge storage material. For example, the normal read voltage may be set to ~1V, the margin-read may be set to ~1.2V, the erase threshold voltage may be 0.5V ± 0.2V, and the programmed threshold voltage may be 1.5V ± 0.2V. there is. Any slice requiring a program refresh must be read and then properly reprogrammed into the same slice or an erased slice, either from the same block or from another previously erased block. Multiple reads of a quasi-volatile TFT may result in disturbance of the erase or program threshold voltage and require rewriting of the slice with another erased slice. Read disturbance is suppressed by lowering the voltage applied to the control gate, and source and drain regions during read. However, repeated reading can cause cumulative reading errors. These errors can be recovered by having the data encoded with error correcting codes (“ECC”).

One challenging requirement for proper operation of the quasi-volatile memory of the present invention is the ability to read and program-refresh a large number of TFTs, NOR strings, pages or slices. For example, a quasi-volatile 1 terabit chip has ~8,000,000 slices of 128K bits each. Assuming that 8 slices (~1 million) of a TFT can be program refreshed in parallel (one slice in each of 8 blocks) and the program refresh time is 100 μs, the entire chip can be program refreshed in ~100 seconds. there is. This massively parallel processing will be possible in the memory device of the present invention primarily due to two main factors; 1) Fowler-Nordheim tunneling, or direct tunneling, requires significantly lower programming current per TFT and allows new million or more TFTs to be programmed together without extending excessive power, and 2) the inherent power of long NOR strings. Parasitic capacitors make it possible to pre-charge and temporarily maintain the pre-charge voltage on multiple NOR strings. These characteristics allow multiple pages or slices on different blocks to be read first in margin-read mode to determine if a refresh is required, and if so, the pages or slices are individually pre-charged for program or program-stop before being read in a single parallel operation. Allow program refresh. Quasi-volatile memory with an average retention time of ~10 minutes or more will allow the system controller to have adequate time to properly refresh the program and maintain a low error rate that is fully within ECC recoverability. If a full 1 terabit chip is refreshed every 10 minutes, such a chip would consume significantly less current to operate, rivaling a typical 64 ms refresh DRAM chip, or a factor of over 1,000 times less frequently.

8A illustrates in simplified form a prior art storage system 800 in which a microprocessor (CPU) 801 communicates with a system controller 803 in a flash solid state drive (SSD) employing a NAND flash chip 804. It shows. SSD emulates a hard disk drive, and the NAND flash chip 804 does not communicate directly with the CPU 801 and has relatively long read latency. 8B shows that a non-volatile NOR string array 854 or a quasi-volatile NOR string array 855 (or both) can be connected directly by CPU 801 via one or more of the input/output (I/O) ports 861. A system architecture 850 using the memory device of the present invention, accessed with , is shown in simplified form. I/O port 861 is one or more high-speed serial ports for streaming data to or from NOR string arrays 854 and 855, or 8-, 16-, or 32-bit ports accessed randomly one word at a time. , may be 64 bits, 128 bits, or any appropriately sized wide word. Such access may be provided using, for example, DRAM-compatible DDR4, and future higher speed industry standard memory interface protocols, or other protocols for DRAM, SRAM or NOR flash memory. I/O port 862 processes storage system management instructions through flash memory controller 853, which translates CPU instructions for chip management operations and for inputting data to be programmed into memory chips. Additionally, CPU 801 can be configured to write and read files stored using one of several surface formats (e.g., PCIe, NVMe, eMMC, SD, USB, SAS, or multi-Gbit high data rate ports). I/O port 862 can be used. I/O port 862 communicates between the system controller 853 and the NOR string array in the memory chip.

Because each system controller typically manages multiple memory chips, the system is designed to be freed as much as possible from ongoing margin-read/program refresh operations that can be more efficiently controlled by simple on-chip state machines, sequences, or dedicated microcontrollers. It is advantageous for the controller (e.g., system controller 853 in Figure 8B) to turn off the memory chips. For example, a parity check bit (1-bit) or a more powerful ECC word (typically a few bits to more than 70 bits) can be checked by an off-chip controller or on-chip by a dedicated logic circuit or state machine. It can be stored as a page or slice that is created and programmed for incoming data. During a margin-read operation, the parity bits generated on the chip for the addressed page are compared to the stored parity bits. If the two bits do not match, the controller reads the addressed page again under a standard read (i.e., non-margin). Given a parity bit match, the controller reprograms the correct data into the page even if the data is not completely corrupted. If the parity bits do not match, dedicated on-chip ECC logic or an off-chip controller intervenes to detect and correct the bad bits, preferably rewrite the correct data to another available page or slice, and replace the faulty page or slice. It will be permanently disposed of. To accelerate the on-chip ECC operation, it is advantageous to have the on-chip exclusive Or or other logic circuitry find the ECC match quickly, without having to go off-chip. Alternatively, the memory chip may be one or more dedicated to communicating with a controller for ECC and other system management chores (e.g., dynamic fault management) so as not to interfere with the low-latency data I/O ports. It can be equipped with a high-speed I/O port. Because the frequency of read or program refresh operations can vary over the life of a memory chip due to TFT wear after excessive program/erase cycles, the controller determines the time between refresh operations for each block (preferably on a high-speed cache slice). A value representing the interval can be stored. This time interval tracks the cycle count of the block. Additionally, the chip or system may have temperature monitoring circuitry used to vary the refresh frequency at which output data is updated with the chip temperature. It should be clear that the example used herein is only one of several sequences that can achieve automatic program-refresh through rapid correction or replacement of faulty pages or slices.

In the example of a 1 terabit chip with no more than 0.2% of all blocks being refreshed at any one time, or only 8 blocks out of 4,000 blocks, the program refresh operation can be performed in background mode while all other blocks are refreshed in their dictionary. It can occur in parallel with charging, reading, program and erase operations. For address conflicts between 0.2% and 99.8% of blocks, the system controller arbitrates one of the more urgent accesses. For example, the system controller may interrupt a program refresh to take priority for a high-speed read and then return to complete the program refresh.

In summary, in the integrated circuit memory chip of the present invention, each active strip and its multiple associated conductive word lines are maintained in a semi-floating state (i.e., during read, program, program stop, or erase operations). It consists of a single-port isolated capacitor that can be charged to a predetermined voltage (which undergoes charge leakage through a string select transistor in the board circuit). The separate quasi-float capacitors in each active strip, coupled with the fairly low Fowler-Nordheim or direct tunneling currents required to program or erase a TFT in the NOR string associated with that active strip, allow a fairly large number of randomly selected blocks to be connected. Allows you to program, delete or read sequentially or together. Within an integrated circuit memory chip, one or more NOR strings of a first group of blocks are first pre-charged and then erased together, while NOR strings of one or more other groups of blocks are first pre-charged and then together programmed. It is written or read. Additionally, erasing the first group of blocks and programming or reading the second group of blocks may occur sequentially or together. Blocks that are dormant (e.g., blocks storing rarely changed archival data) are preferably kept in a quasi-floating state and are preferably isolated from the substrate after having their NOR strings and conductors set to ground potential. do. To take advantage of the massively parallel read and program bandwidth of these quasi-float NOR strings, it is advantageous for integrated circuit memory chips to include multiple high-speed I/O ports therein. Data can be stored, for example, for word-wide random access, or to provide multiple channels for serial data streams (reading) from or to the chip (programming or writing), They can be routed on the chip to or from their I/O ports.

The foregoing detailed description is provided to illustrate specific embodiments of the invention and is not intended to be limiting. Various variations and modifications are possible within the scope of the present invention. The invention is set forth in the accompanying claims.

Claims (15)

A three-dimensional array of NOR memory strings formed on a planar surface of a semiconductor substrate, each NOR memory string comprising a plurality of thin film storage transistors,
(i) the three-dimensional array is composed of a plurality of planes of NOR memory strings, and the NOR memory strings in each plane are located at substantially the same distance from the planar surface of the semiconductor substrate,
(ii) the storage transistors of the NOR memory string located in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel;
(iii) the storage transistors of the NOR memory string in the first group of the plane are configured in a plurality of sets and the storage transistors of the NOR memory string in the second group of the plane are also configured in the plurality of sets, Each set of storage transistors in a first group of NOR memory strings corresponds to a corresponding set of storage transistors in a second group of NOR memory strings in the plane, A three-dimensional array of NOR memory strings, wherein each set of storage transistors and a corresponding set of storage transistors in a second group of NOR memory strings in the plane are configured to be activated substantially simultaneously. According to paragraph 1,
A three-dimensional array of NOR memory strings, wherein the NOR memory strings located within each plane are further organized into blocks. According to paragraph 1,
(a) resource management data for each set of storage transistors in the NOR memory strings of the first group of the plane is maintained in the corresponding set of storage transistors in the NOR memory strings of the second group of the plane, and (b) ) each set of storage transistors holding the resource management data in the NOR memory strings of the second group of the plane, programming performed on a corresponding set of storage transistors in the NOR memory strings of the first group of the plane, A three-dimensional array of NOR memory strings configured to be read, stored, or updated with erase, program stop, or read operations. According to paragraph 3,
The above resource management data is:
File management data, configuration parameter values, mapping of addresses of defective storage transistors to addresses of alternative storage transistors, data identifiers, lookup tables, link lists, timestamps, error detection and error correction data, a first group of said planes. Program-erase cycle of storage transistors in NOR memory strings, optimal voltage and pulse shape, erase, program, program-stop, program scrub, read, margin read, read refresh, read scrub Actions, error correction codes, periods for data recovery modes, and other system parameters
A three-dimensional array of NOR memory strings, containing one or more of the following: According to paragraph 3,
A three-dimensional array of NOR memory strings, wherein the NOR memory strings in each plane are further organized into quadrants. According to paragraph 3,
A three-dimensional array of NOR memory strings, wherein the programming, deleting, deprogramming or read operations and storage and updating of the resource management data are performed under the control of an external controller. According to clause 5,
one or more types of circuitry for supporting programming, erasing, programming stop or read operations in a first group of storage transistors in the plane are formed in the planar surface of the semiconductor substrate;
A circuit of this type is a three-dimensional array of NOR memory strings, including one or more of a voltage source, a sense amplifier, a data register, an XOR gate, and an input/output (I/O) terminal. 8. The three-dimensional array of NOR memory strings of claim 7, wherein the NOR memory strings within each quadrant share a predetermined group of circuits to support program, erase, program stop, or read operations. According to paragraph 3,
A three-dimensional array of NOR memory strings, wherein within each NOR memory string, a first group of storage transistors is configured to be read within a shorter time period than a second group of storage transistors. According to clause 9,
A three-dimensional array of NOR memory strings, wherein in each NOR memory string in which resource management data is stored, the resource management data is stored in the first group of storage transistors. According to paragraph 3,
A three-dimensional array of NOR memory strings, wherein each set of storage transistors holding the resource management data shares the same wordline as a corresponding set of storage transistors in the NOR memory strings of the first group of the plane. According to paragraph 1,
A three-dimensional array of NOR memory strings, wherein the second group of NOR memory strings in the plane further provides a reference NOR memory string. According to paragraph 1,
wherein one or more NOR memory strings in the second group of planes serve as spare memory resources to replace defective NOR memory strings in the first group of planes. According to paragraph 1,
further comprising a plurality of conductors,
Each set of storage transistors in a NOR memory string in a first group of the plane and a corresponding set of storage transistors in a NOR memory string in the second group of the plane are connected by a corresponding one of the conductors. A three-dimensional array of memory strings. According to paragraph 1,
further comprising a plurality of groups of sense amplifiers,
Each group of sense amplifiers is formed in a region of the semiconductor substrate that does not overlap with a region of another group of sense amplifiers, and each set of storage transistors of a NOR memory string in a first group of said planes and a second group of said planes. A three-dimensional array of NOR memory strings, where corresponding sets of storage transistors located in a NOR memory string are read using corresponding groups of sense amplifiers.