TW201810433A - Double gate graphene field effect transistor and manufacturing method thereof - Google Patents

Abstract

A method for manufacturing a double gate graphene field effect transistor includes: providing a semiconductor substrate; forming a photoresist layer on the semiconductor substrate; performing carbon ion implantation to facilitate the semiconductor substrate to form two carbon ions Impurity region; removing the photoresist layer; selectively growing at least one graphene layer on the two doped regions; oxidizing the semiconductor substrate to form a dielectric layer; and respectively on the two doped regions Several high dielectric constant material regions are formed between the graphene layers and on the graphene layer, and the dielectric constant of the material in the high dielectric constant material region ranges from 2.0 to 30.

Description

Double-gate graphene field effect transistor and manufacturing method thereof

The invention relates to a semiconductor element and a manufacturing method thereof, in particular to a double-gate graphene field effect transistor and a manufacturing method thereof.

Because of its high mobility, graphene has been used in the manufacture of semiconductor devices by many industries. At present, the manufacturing method of graphene transistors is generally to form a graphene thin film on a glass substrate by a liquid-phase coating film or a transfer method. However, the disadvantage of this method is that the interface between the graphene film and the glass substrate is often contaminated, which seriously affects the performance of the graphene transistor. In addition, the current manufacturing method of graphene transistors is also difficult to meet the needs of large-scale applications due to complicated operations, high cost, and low yield. In view of this, there is currently a need to develop an improved method for manufacturing graphene transistors.

The invention provides a double-gate graphene field-effect transistor and a method for manufacturing the same, which can make the energy gap of the graphene nano-band greater than 300 mev and have a double-gate.

An embodiment of the present invention provides a method for manufacturing a double-gate graphene field effect transistor, including: providing a semiconductor substrate; forming a photoresist layer on the semiconductor substrate; and performing carbon ion implantation to facilitate the semiconductor substrate Forming two doped regions; removing the photoresist layer; selectively growing at least one graphene layer on the two doped regions, respectively; under a pure oxygen environment, conducting the semiconductor substrate through the graphene layers Oxidizing to form a dielectric layer under the graphene layers; and forming three high-dielectric-constant material structures on the dielectric layer and the graphene layer, respectively, and the high-dielectric-constant material structures The range of dielectric constant is 2.0 ~ 30.

An embodiment of the present invention provides a double-gate graphene field effect transistor, including: A semiconductor substrate; a dielectric layer, the dielectric layer being disposed on the semiconductor substrate; two graphene layers, the two graphene layers being disposed on the dielectric layer; a first high dielectric constant material Structure and a second high-dielectric-constant material structure respectively disposed on the two graphene layers: and a third high-dielectric-constant material structure disposed on the dielectric layer and the two graphites Between the olefin layers; and a first gate and a second gate, the first gate and the second gate are respectively disposed in the first high-dielectric constant material structure and the second high-dielectric constant material structure Above.

100‧‧‧ semiconductor substrate

102‧‧‧Photoresistive layer

104‧‧‧ the first carbon ion doped region

106‧‧‧Second carbon ion doped region

108‧‧‧ the first graphene layer

110‧‧‧second graphene layer

112‧‧‧ Silicon dioxide dielectric layer

114‧‧‧The first high dielectric constant material structure

116‧‧‧The second highest dielectric constant material structure

118‧‧‧ the third highest dielectric constant material structure

120‧‧‧first gate

122‧‧‧First source

124‧‧‧first drain

126‧‧‧Second gate

128‧‧‧Second Source

130‧‧‧Second Drain

FIG. 1 is a flowchart illustrating a method for manufacturing a double-gate graphene field effect transistor provided by the present invention.

FIG. 2A to FIG. 2H are cross-sectional views illustrating some steps of manufacturing a double-gate graphene field effect transistor.

The present invention is further described below with reference to the accompanying drawings and preferred embodiments of the specification, but the embodiments of the present invention are not limited thereto.

Referring to FIG. 1, a method for manufacturing a double-gate graphene field effect transistor according to an embodiment is provided, including the following steps:

S101: Provide a semiconductor substrate. In this embodiment, the semiconductor substrate is a silicon substrate.

S102: cleaning the semiconductor substrate in situ with ozone or silicon cobalt cobalt (SiCoNi).

S103: forming a photoresist layer on the semiconductor substrate

S104: Carbon ion implantation is performed, and two carbon ion doped regions are formed on a portion of the semiconductor substrate that is not provided with a photoresist layer. In this embodiment, the acceleration voltage of the cloth-valued carbon ions is between 1 keV and 100 keV, and the doping dose is between 10 ¹⁵ (number of carbon ions / cm ² ) to 10 ¹⁸ (number of carbon ions / cm ² ).

S105: Remove the photoresist layer on the surface of the semiconductor substrate.

S106: The semiconductor substrate is subjected to rapid thermal annealing. First, the semiconductor substrate is heated for 1 second to 1000 seconds, so that the semiconductor substrate is heated to 400 ° C to 1200 ° C, and then the semiconductor substrate is rapidly cooled.

S107: Selectively growing on the carbon ion doped regions of the semiconductor substrate (selective grow) at least one graphene layer. In this embodiment, a graphene layer is formed on each carbon ion doped region.

S108: In a pure oxygen environment, the semiconductor substrate is oxidized through the graphene layer to form a dielectric layer under the graphene layer, and a part of the dielectric layer overlaps the carbon ion doped region.

S109: Forming a plurality of high dielectric constant material structures on the dielectric layer and the graphene layer, respectively, and the dielectric constant of the high dielectric constant material structure ranges from 2.0 to 30. The high dielectric constant material may include silicon nitride, silicon oxynitride, aluminum oxide, zirconia, or hafnium dioxide. As for the method of forming a high-dielectric-constant material structure, there are Chemical Vapor Deposition, Atomic Layer Deposition, or Metal-Organic Chemical Vapor Deposition Epitaxy. .

In order to explain the manufacturing method of the double-gate graphene field-effect transistor in FIG. 1 in more detail, please refer to FIG. 2A to FIG. 2H, in order to provide a part of the graphene field-effect transistor provided by an embodiment of the present invention. Sectional view of steps.

Referring to FIG. 2A, a semiconductor substrate 100 is prepared. The semiconductor substrate 100 is a silicon substrate.

Referring to FIG. 2B, a photoresist layer 102 is formed on the semiconductor substrate 100.

Referring to FIG. 2C, a carbon ion distribution value is performed, and a first carbon ion doped region 104 and a second carbon ion doped region 106 are formed on portions of the semiconductor substrate 100 that are not provided with the photoresist layer 102, respectively.

Referring to FIG. 2D, the photoresist layer 102 previously disposed on the semiconductor substrate 100 is removed.

Referring to FIG. 2E, the first carbon ion doped region 104 and the second carbon ion doped region 106 of the semiconductor substrate 100 are selectively grown on the first graphene layer 108 and the second graphene layer 110, respectively.

Referring to FIG. 2F, in a pure oxygen environment, the semiconductor substrate 100 is oxidized through the first graphene layer 108 and the second graphene layer 110 so as to be below the first graphene layer 108 and the second graphene layer 110. And other areas not covered by the graphene layer form a silicon dioxide dielectric layer 112, and the formation of the silicon dioxide dielectric layer 112 consumes some or all of the first carbon The ion doped region 104 and the second carbon ion doped region 106.

Referring to FIG. 2G, a first high-k dielectric material structure 114 and a second high-k dielectric material structure 116 are deposited on the first graphene layer 108 and the second graphene layer 110, respectively, and on silicon dioxide. A third high-dielectric-constant material structure 118 is deposited on the dielectric layer and between the first graphene layer 108 and the second graphene layer 110.

Referring to FIG. 2H, a first gate electrode 120 is formed on top of the first high-dielectric-constant material structure 114, and a first gate electrode 120 is formed on both sides of the first high-dielectric-constant material structure 114 and on the first graphene layer 108, respectively. The first source electrode 122 and a first drain electrode 124. A second gate electrode 126 is formed on top of the second high-dielectric-constant material structure 116, and a second source electrode 128 is formed on both sides of the second high-dielectric-constant material structure 116 and on the second graphene layer 110. And a second drain electrode 130.

The double-gate graphene field effect transistor and the manufacturing method thereof provided by the present invention can clean the silicon substrate in-situ and graphically grow a graphene layer, which can make the energy gap of the graphene nano-band greater than 300 mev and have Double gate. In addition, compared with the current method of manufacturing graphene transistors, the method provided by the present invention has simpler operation, lower cost, and higher yield, so it can meet the needs of large-scale applications.

What has been disclosed above are only preferred embodiments of the present invention, and of course, the scope of rights of the present invention cannot be limited by this. Therefore, equivalent changes made according to the scope of patent application of the present invention still fall within the scope of the present invention.

Claims (13)

A method for manufacturing a double-gate graphene field effect transistor includes: providing a semiconductor substrate; forming a photoresist layer on the semiconductor substrate; and performing carbon ion implantation so that the semiconductor substrate forms two doped regions; Removing the photoresist layer; selectively growing at least one graphene layer on the two doped regions respectively; under a pure oxygen environment, oxidizing the semiconductor substrate through the graphene layers to the graphene A dielectric layer is formed under the layer; and a high-dielectric-constant material structure is formed on the dielectric layer and the graphene layer, respectively, and the dielectric coefficient ranges from 2.0 to 30. The method for manufacturing a double-gate graphene field effect transistor according to claim 1, further comprising, before forming the photoresist layer, cleaning the semiconductor substrate in situ with ozone or silicon nickel cobaltate. The method for manufacturing a double-gate graphene field effect transistor according to claim 1, further comprising performing rapid thermal annealing on the semiconductor substrate after removing the photoresist layer and before selectively growing the at least one graphene layer ( rapid thermal anneal). The method for manufacturing a double-gate graphene field effect transistor according to claim 3, wherein the step of rapid thermal annealing comprises first heating the semiconductor substrate to 400 ° to 1200 ° C, and then cooling the two semiconductor substrates. The method for manufacturing a double-gate graphene field-effect transistor according to claim 4, wherein the time for heating the semiconductor substrate is 1 second to 1000 seconds. The method for manufacturing a double-gate graphene field effect transistor according to claim 1, wherein a part of the dielectric layer and the two doped regions overlap each other. The method for manufacturing a double-gate graphene field effect transistor according to claim 1, wherein the materials of the high-dielectric-constant material structure include silicon nitride, silicon oxynitride, aluminum oxide, zirconia, or dioxide hafnium. The method for manufacturing a double-gate graphene field effect transistor according to claim 1, wherein the high-dielectric-constant material structure is formed by using a chemical vapor deposition method (Atomic Layer Deposition) and an atomic deposition method (Atomic Layer Deposition). Or metal-organic chemical vapor deposition epitaxy (Metal-Organic Chemical Vapor Deposition Epitaxy). The method for manufacturing a double-gate graphene field effect transistor according to claim 1, wherein the acceleration voltage when performing carbon ions is between 1 keV and 100 keV and the doping dose is between 10 ¹⁵ (number of carbon ions / cm ² ) To 10 ¹⁸ (number of carbon ions / cm ² ). The method for manufacturing a double-gate graphene field-effect transistor according to claim 1, further comprising forming the high-dielectric-constant material structures, and forming a first one on top of two of the high-dielectric-constant materials. A gate and a second gate. A double-gate graphene field effect transistor, comprising: a semiconductor substrate; a dielectric layer disposed on the semiconductor substrate; two graphene layers, the two graphene layers disposed on the semiconductor substrate; Over the dielectric layer; a first high-dielectric constant material structure and a second high-dielectric constant material structure, which are respectively disposed on the two graphene layers: and a third high-dielectric constant material structure, It is disposed on the dielectric layer and between the two graphene layers; and a first gate and a second gate, the first gate and the second gate are respectively disposed on the first high dielectric layer. The dielectric material structure and the second high-dielectric constant material structure. The dual-gate graphene field effect transistor according to claim 11, wherein the semiconductor substrate is further provided with two carbon ion doped regions, and a portion of the dielectric layer overlaps the two carbon ion doped regions. The double-gate graphene field-effect transistor according to claim 1, wherein the materials of the high-dielectric-constant material structure include silicon nitride, silicon oxynitride, aluminum oxide, zirconia, or hafnium dioxide.