CN102479819A - Field-effect transistor and its manufacturing method - Google Patents

Abstract

The invention discloses a field effect transistor and a preparation method thereof. The field effect transistor comprises an insulating substrate, a graphene channel region, a top gate region, a source contact electrode and a drain contact electrode, wherein: the graphene channel region is formed above the insulating substrate; the top gate region is formed above the graphene channel region; and the source contact electrode and the drain contact electrode are formed above the insulating substrate and on two sides of the graphene channel region, and are respectively contacted with the graphene channel region. Because the graphene material has huge carrier mobility, the speed of the field effect transistor can be greatly improved by using the graphene as the channel region material.

Description

Field-effect transistor and its manufacturing method

technical field

The invention relates to the technical field of microelectronics, in particular to a field effect transistor and a preparation method thereof.

Background technique

Graphene, which is composed of a single layer to a few layers of carbon atoms and has a two-dimensional honeycomb structure, was first discovered and prepared in 2004 by a research team led by Andre Geim, a professor of astrophysics at the University of Manchester. Published in "Science" [306, 666-669 (2004)], it is the thinnest material known in the world, its charge carrier shows inherent huge mobility, and suspended graphene has a high The intrinsic carrier mobility exceeds 200,000 cm ² /Vs (see "Solid State communication" [146, 351 (2008)]), and is considered to be the most promising new material to replace silicon semiconductors and continue Moore's Law.

In the process of realizing the present invention, the inventor realized that the prior art has the following defects: the field effect transistor using Si as the channel material cannot meet the demands for higher speed and smaller size.

Contents of the invention

(1) Technical problems to be solved

Aiming at the above-mentioned problems in the prior art, the present invention proposes a field effect transistor and a preparation method thereof, so as to improve the mobility of intrinsic carriers in the novel transistor.

(2) Technical solution

The invention discloses a field effect transistor, comprising: an insulating substrate; a graphene channel region formed above the insulating substrate; a top gate region formed above the graphene channel region; a source contact electrode and a drain contact The electrodes are formed above the insulating substrate, on both sides of the graphene channel region, and the source contact electrode and the drain contact electrode are respectively in contact with the graphene channel region.

In addition, the present invention also discloses a method for preparing a field effect transistor, comprising: preparing an insulating substrate; preparing graphene by a micromechanical method, and transferring the graphene to the insulating substrate to form a graphene channel region; Prepare a gate dielectric layer on the graphene channel region; prepare source/drain contact electrodes in contact with the graphene channel region on both sides of the graphene channel region on an insulating substrate; prepare a gate electrode layer above the gate dielectric layer .

(3) Beneficial effects

Since the graphene material has a huge carrier mobility, the field effect transistor using graphene as the material of the channel region can greatly increase the speed of the field effect transistor.

Description of drawings

Fig. 1 is the schematic diagram of the field effect transistor of the embodiment of the present invention;

2 is a schematic diagram of the sample structure after forming a silicon dioxide insulating layer in the method for preparing a field effect transistor according to an embodiment of the present invention;

Fig. 3 is the schematic diagram of the sample structure after forming the graphene channel region in the field effect transistor preparation method of the embodiment of the present invention;

4 is a schematic diagram of a sample structure after forming a gate dielectric in a method for manufacturing a field effect transistor according to an embodiment of the present invention;

Fig. 5 is the structure schematic diagram after homogenizing in the preparation method of the field effect transistor of the embodiment of the present invention;

6 is a structure diagram after exposure and development in the method for manufacturing a field effect transistor according to an embodiment of the present invention;

7 is a schematic diagram of a sample structure after etching a predetermined part of the gate dielectric in the method for manufacturing a field effect transistor according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a structural diagram after evaporation of metal in the method for manufacturing a field effect transistor according to an embodiment of the present invention;

9 is a schematic diagram of the sample structure after stripping off the metal above the channel region to form source-drain contact electrodes in the method for manufacturing a field-effect transistor according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a sample structure after forming a top gate electrode in a method for manufacturing a field effect transistor according to an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

The invention discloses a field effect transistor, comprising: an insulating substrate; a graphene channel region formed above the insulating substrate; a top gate region formed above the graphene channel region; a source contact electrode and a drain contact The electrodes are formed above the insulating substrate, on both sides of the graphene channel region, and the source contact electrode and the drain contact electrode are respectively in contact with the graphene channel region.

Since the graphene material has a huge carrier mobility, a transistor using graphene as a channel region material can greatly increase the speed of a field effect transistor.

In a further embodiment, the graphene channel region includes: single-layer graphene, the thickness of the single-layer graphene is between 0.35nm and 0.8nm; or double-layer graphene, the thickness of the double-layer graphene is between 0.8nm and 0.8nm. Between 1.2nm; or multilayer graphene, the thickness of multilayer graphene is between 1.2nm and 1.8nm. Graphene is prepared by micromechanical exfoliation and transferred to an insulating substrate. Preferably, the graphene is exfoliated from highly oriented pyrolytic graphite using adhesive tape and transferred to an insulating substrate.

FIG. 1 is a schematic diagram of a field effect transistor according to an embodiment of the present invention. As shown in FIG. 1 , a field effect transistor is composed of n-type or p-type silicon wafer 101 , silicon oxide 102 , graphene 103 , top gate dielectric 104 , source-drain contact electrode 105 and top gate electrode 106 . Specifically, a layer of silicon dioxide with a thickness of 10nm to 500nm is thermally grown on a silicon wafer, and then the graphene material that has been prepared is transferred to the silicon dioxide, and finally the photolithography and evaporation in the field of microelectronics are used to And lift-off and other processes to prepare source-drain metal contacts and top-gate electrodes. Silicon oxide silicon wafer is used as substrate support and device isolation insulating material, graphene is used as the conductive channel of this field effect transistor, the source and drain contact electrodes are directly in contact with the graphene channel, and the top gate dielectric is directly covered on the graphene channel. The top gate electrode covers the top gate dielectric to form a field effect transistor. The concentration and distribution of carriers in the graphene channel can be adjusted by applying different voltages on the top gate, thereby forming a field effect transistor structure.

The preparation method of the above-mentioned field effect transistor device also provided by the present invention comprises the following steps:

Step 1, preparing a highly doped n-type or p-type silicon substrate sample;

Step 2, taking the sample in step 1) into a superalloy furnace, and thermally growing silicon dioxide of 10nm to 500nm, as shown in Figure 2;

Step 3, use Scotch tape to peel off the graphene material to be used in the experiment from HOPG (highly oriented pyrolytic graphite);

Step 4, transfer the Graphene obtained in step 3) to the silicon dioxide substrate obtained in step 2) with Scotch adhesive tape, as shown in Figure 3;

Step 5, using atomic layer deposition (Atomic Layer Deposition, referred to as ALD) or chemical vapor deposition (Chemical Vapor Deposition, referred to as CVD) technology to deposit a layer of high-K gate dielectric with a thickness of 5nm to 300nm, such as aluminum oxide, hafnium oxide , titanium dioxide, etc., as shown in Figure 4;

Step 6, put the sample prepared in step 4) on a hot plate at 85°C and bake for 5 minutes;

Step 7, put the sample on the homogenizer and use the speed of 3000rpm to homogenize the glue for 1min;

In step 8, put the sample on a hot plate at 85° C. and bake for 4.5 minutes; as shown in FIG. 5 , 107 is photoresist.

Step 9, put the sample on the lithography machine and expose for 4s. The purpose of the exposure is to partially denature the photoresist irradiated by the light. During development, the denatured photoresist will be dissolved, and continue without denaturation. reserve;

In step 10, develop in positive-resist developing solution for 1 minute, and then put it in fixer solution for fixing for 1 minute; the pattern shown in Figure 6 is obtained.

Step 11, use wet etching or dry etching to etch the part of the high-K insulating top gate dielectric above the source and drain electrodes, preferably using buffer oxide etchant (Buffer Oxide Etch, referred to as BOE) to soak for a preset time , as shown in Figure 7;

Step 12, transfer the sample to an electron beam evaporation machine, and successively evaporate 5nm Cr and 50nm gold, as shown in Figure 8;

Step 13, after the vapor deposition, put the sample into acetone, alcohol and deionized water in sequence, and finally dry it with a nitrogen gun to obtain a source-drain contact electrode, as shown in Figure 9. After step 10, the source and drain contact areas are exposed, and other parts including the gate area are still covered with photoresist. When evaporating metal, all areas have chrome and gold, but after step 13, acetone turns the photoresist At the same time as the resist is dissolved, the gold chrome on the top of the gate area is stripped off, leaving the gold chromium in the source and drain contact area.

In step 14, repeat steps 6) to 10) and steps 12) to 13) to prepare a top gate electrode, as shown in FIG. 10 , so far, the preparation of the field effect transistor is completed.

The above specific embodiments have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., shall be included within the protection scope of the present invention.

Claims (11)

1. a field effect transistor, is characterized in that, comprises insulating substrate, graphene channel region, top gate region, source contact electrode and drain contact electrode, wherein: a graphene channel region formed above the insulating substrate; a top gate region formed above the graphene channel region; A source contact electrode and a drain contact electrode are formed above the insulating substrate and on both sides of the graphene channel region, and the source contact electrode and drain contact electrode are respectively in contact with the graphene channel region. 2. The field effect transistor according to claim 1, wherein the graphene channel region comprises: a single-layer graphene with a thickness between 0.35nm and 0.8nm; or a thickness between 0.8nm and 1.2nm nm between bilayer graphene; or multilayer graphene with a thickness between 1.2nm and 1.8nm. 3 . The field effect transistor according to claim 2 , wherein the graphene is prepared by micromechanical exfoliation and transferred to the insulating substrate. 4 . 4 . The field effect transistor according to claim 3 , wherein the graphene is peeled off from highly oriented pyrolytic graphite using an adhesive tape, and transferred to the insulating substrate. 5. The field effect transistor according to claims 1 to 4, characterized in that, The insulating substrate includes: an n-type or p-type silicon wafer; a silicon dioxide layer formed by thermal oxidation on the n-type or p-type silicon wafer; The top gate region includes: a high dielectric constant K gate dielectric formed above the graphene channel region; a metal gate electrode formed above the high K gate dielectric. 6. A method for preparing a field effect transistor, comprising: Prepare an insulating substrate; preparing graphene by micromechanical exfoliation, and transferring the graphene to the insulating substrate to form a graphene channel region; preparing a gate dielectric layer on the graphene channel region; On the insulating substrate, prepare source/drain contact electrodes in contact with the graphene channel region on both sides of the graphene channel region; A gate electrode layer is prepared on the gate dielectric layer. 7. The method for preparing a field effect transistor according to claim 6, wherein the graphene channel region comprises: a single-layer graphene with a thickness between 0.35nm and 0.8nm; or a thickness between 0.8nm Bilayer graphene between 1.2nm and 1.2nm; or multilayer graphene between 1.2nm and 1.8nm thick. 8 . The method for preparing a field effect transistor according to claim 7 , wherein the graphene is peeled off from highly oriented pyrolytic graphite using an adhesive tape, and transferred to the insulating substrate. 9 . 9. The field-effect transistor preparation method according to claim 8, wherein said preparation of an insulating substrate comprises: Put the highly doped n-type or p-type silicon wafer into the superalloy furnace; heating to thermally grow a 10 nm to 500 nm thick silicon dioxide layer on top of the silicon wafer. 10. field effect transistor preparation method according to claim 9, is characterized in that, described gate dielectric layer is high-K gate dielectric layer, described on insulating substrate, the both sides of graphene channel region preparation and described The source-drain contact electrodes contacted by the graphene channel region include: Bake the insulating substrate sample with the graphene channel region formed on a hot plate at 85°C for 5 minutes; Put the sample on the glue homogenizer at a speed of 3000rpm, and homogenize the glue for 1 minute; Bake the sample on a hot plate at 85°C for 4 minutes and 30 seconds; Expose the sample on the photolithography machine for 4 seconds; Develop the sample for 50 seconds in a positive photoresist developer; Soak the sample in a buffered oxide etchant solution, and the high-K gate dielectric layer at a preset position is etched; Evaporate chromium and gold, or nickel and gold, or titanium palladium gold in sequence on the sample with a preset thickness; Place the sample in acetone, alcohol and deionized water in sequence, and peel off the chromium and gold, or nickel and gold, or titanium palladium gold evaporated on the top of the channel region to obtain the source-drain contact electrodes. 11. The field-effect transistor preparation method according to claim 10, wherein said preparing a gate electrode layer above the high-K gate dielectric layer comprises: Bake the sample on a hot plate at 85°C for 5 minutes; Put the sample on the glue homogenizer at a speed of 3000rpm, and homogenize the glue for 1 minute; Bake the sample on a hot plate at 85°C for 4 minutes and 30 seconds; Expose the sample on an optical lithography machine for 4 seconds, or use electron beam direct writing technology to expose; Develop the sample for 50 seconds in a positive photoresist developer; Transfer the sample to the cavity of the electron beam evaporation machine, and sequentially evaporate the specified thickness of chromium and gold, or nickel and gold, or titanium palladium gold; Place the vapor-deposited sample in acetone, alcohol and deionized water in sequence, and peel off the chromium and gold, or nickel and gold, or titanium-palladium-gold vapor-deposited on the upper part of the source and drain regions to obtain a top gate electrode.

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