TW201818415A - Reading method for preventing read disturbance and memory using the same - Google Patents

Abstract

A reading method for preventing a read disturbance and a memory using the same are provided. The reading method includes the following steps: At least one of a plurality of string select lines is selected and a predetermined string select voltage is applied to the selected string select line. Only one of a plurality of ground select lines is selected and a predetermined ground select voltage is applied to the selected ground select line.

Description

Reading method for preventing read disturb and memory using the same

The present disclosure relates to a reading method and a memory applied thereto, and in particular to a reading method for preventing read disturb and a memory applied thereto.

With the development of storage technology, all kinds of memory are constantly being updated. The digital data can be written/programmed in the memory and the digital data can be read out.

However, as the number of uses increases, the method of reading the memory may affect the adjacent memory cells of the same memory block. This is called read disturb or read disturbance. To avoid the problem of read disturb, the controller can count the number of reads from the last erase action. When the number of readings exceeds a certain target threshold, the affected memory block will be copied its data to another memory block, and then the affected memory block will be erased. After the erase action, the affected memory block can be like new. However, the act of copying data is quite time consuming, and some of the data may have been lost when the number of reads did not exceed the target threshold.

The disclosure relates to a reading method for avoiding reading interference and a memory for applying the same. When the selected memory cell is read, only one of the ground selection lines is selected to apply a predetermined ground selection voltage. In each of the unselected memory cells, the voltage difference between the gate and the channel can be lowered. Therefore, reading interference can be effectively prevented.

According to an embodiment, a method of reading a memory that prevents read disturb is provided. The reading method includes the steps of selecting at least one of a plurality of string select lines and applying a predetermined string selection voltage to the selected string selection line. Only one of a number of ground select lines is selected and a predetermined ground selection voltage is applied to the selected ground selection line.

According to another embodiment, a memory is provided. The memory includes a plurality of serial selection lines and a plurality of ground selection lines. At least one of the series of select lines is selected by a decoder to apply a predetermined series select voltage. Only one serial select line is selected through the decoder to apply a predetermined ground selection voltage.

In order to better understand the above and other aspects of the present disclosure, the preferred embodiments are described below in detail with reference to the accompanying drawings.

Please refer to FIG. 1 , which illustrates a schematic diagram of a memory 100 according to an embodiment. The memory 100 can be a three-dimensional V-NAND flash memory. Memory 100 includes a number of strings. Each string includes several memory cells. The memory 100 includes a plurality of even bit lines BL1_even, a plurality of odd bit lines BL1_odd, a plurality of word lines WL1_n, WL1_n+1, ..., a plurality of strings. String select line SSL1_n, SSL1_n+1, SSL1_n+2, ..., several ground select lines GSL1_n, GSL1_n+1, GSL1_n+2, ..., and a common source line (common Source line) CSL1. One end of each string is connected to a common source line CSL1, and the other end of each string is connected to an even bit line BL1_even or an odd bit line BL1_odd.

The serial selection lines SSL1_n, SSL1_n+1, SSL1_n+2, ... are used to turn on or off the serial device selection switches (SSL devices) SD1_n, SD1_n+1, SD1_n+2, ..., respectively. The serial selection switch SD1_n is controlled by the serial selection line SSL1_n, the serial selection switch SD1_n+1 is controlled by the serial selection line SSL1_n+1, and the serial selection switch SD1_n+2 is connected by the serial selection line SSL1_n+2 Controlled, and so on. For example, if the serial selection switch SD1_n is turned on, the voltage supplied from the even bit line BL1_even (or the odd bit line BL1_odd) can be applied to the series connected to the string selection switch SD1_n.

The ground selection lines GSL1_n, GSL1_n+1, GSL1_n+2, ... are used to turn on or off the ground selection switches (GSL devices) GD1_n, GD1_n+1, GD1_n+2, ..., respectively. The ground selection switches GD1_n, GD1_n+1, GD1_n+2 are not controlled by the same ground selection line. Conversely, the ground selection switch GD1_n is controlled by the ground selection line GSL1_n, the ground selection switch GD1_n+1 is controlled by the ground selection line GSL1_n+1, and the ground selection switch GD1_n+2 is controlled by the ground selection line GSL1_n+2. So on and so forth. For example, if the ground selection switch GSL1_n is turned on, the voltage supplied from the common source line CSL1 can be applied to the series connected to the series selection switch GD1_n.

The character lines WL1_n, WL1_n+1, . . . located in each of the strings are connected to the memory cells of the respective strings.

In the present embodiment, each of the string selection lines SSL1_n, SSL1_n+1, SSL1_n+2, ... corresponds to each of the ground selection lines GSL1_n, GSL1_n+1, GSL1_n+2, . One of the serial selection lines SSL1_n, SSL1_n+1, SSL1_n+2, ... and one of the ground selection lines GSL1_n, GSL1_n+1, GSL1_n+2, ... can be selected by a decoder 110. In an embodiment, the ground selection lines GSL1_n, GSL_1n+1, GSL1_n+2, ... may each perform decoding selection. For example, the switch SW1 can be opened and the switch SW2 can be turned on to apply a predetermined series selection voltage Vss1 to the string selection line SSL1_n; the switch SW3 can be turned on and the switch SW4 can be turned off to apply a voltage of 0 volts To the serial selection line SSL1_n+1. The switch SW5 can be opened and the switch SW6 can be turned on to apply a predetermined ground voltage Vgs1 to the ground select line GSL1_n; the switch SW7 can be turned on and the switch SW8 can be turned off to apply a voltage of 0 volts to the ground select line GSL1_n+1.

Please refer to FIG. 2, which illustrates a voltage waveform of a forward read operation of the memory 100. The read operation includes a pre-on setup stage ST1 and a sense developing stage ST2. In the reading phase ST2, the reading method of the memory 100 includes the following steps. These steps can be performed simultaneously.

One of the word lines WL1_n, WL1_n+1, ... is selected. The selected word line is applied with a change in read voltage Vread; the unselected word line is applied with a pass voltage Vpass.

One of the serial selection lines SSL1_n, SSL1_n+1, SSL1_n+2, ... is selected. The selected tandem select line is applied with a predetermined string select voltage Vssl; the unselected tandem select line applies a voltage of 0 volts.

Only one ground selection line GSL1_n, GSL1_n+1, GSL1_n+2, ... is selected. The selected ground selection line is applied with a predetermined ground selection voltage Vgsl; the unselected ground selection line is applied with a voltage of 0 volts.

The common source line CSL1 is applied with a voltage of 0 volts. The even bit line BL1_even is selected, or the odd bit line BL1_odd is selected. The selected bit line is applied with a predetermined bit line voltage Vbl; the unselected bit line applies a voltage of 0 volts.

In this embodiment, not all of the ground selection lines GSL1_n, GSL1_n+1, GSL1_n+2, ... are applied with a predetermined ground selection voltage Vgs1. Therefore, not all of the ground selection switches GD1_n, GD1_n+1, GD1_n+2, ... are turned on, and not all of the strings are applied with a voltage of 0 volts from the common source line CSL1.

Please refer to FIG. 3, which is a schematic diagram showing the channel potential of the memory 100. In the third figure, the series S11, S12 are selected for reading, and the series S13, S14, S15, S16, ... are not selected. The unselected series S13, S14, S15, and S16 are floating. The channel potential of each of the strings S13, S14, S15, S16, ... is raised to a predetermined voltage level Vch. Therefore, the voltage difference between the unselected memory cells in the series S13, S14, S15, and S16 at the gate and the channel can be reduced from "the difference between the on-voltage Vpass and the 0 volt" to the "on-voltage Vpass and the predetermined voltage level Vch". Difference". Since the voltage difference of the unselected memory cells has been lowered, the occurrence of read disturb can be effectively prevented.

Please refer to FIG. 4, which illustrates a voltage waveform diagram of an all bit lines sensing operation of the memory 100. In another embodiment, all of the even bit lines BL1_even and the odd bit lines BL1_odd are selected to apply the predetermined bit line voltage Vbl. In this embodiment, the case of the channel potential is similar to the case of Fig. 3. The voltage difference between the gate and the channel of each of the unselected memory cells in the series S13, S14, S15, and S16 may also be reduced from "the difference between the on voltage Vpass and the 0 volt" to the "on voltage Vpass and the predetermined voltage level Vch". Difference". Since the voltage difference of the unselected memory cells has been lowered, the occurrence of read disturb can be effectively prevented.

Please refer to FIG. 5 , which illustrates a schematic diagram of a memory 200 according to another embodiment. Memory 200 can be a three dimensional SGVC memory. Memory 200 includes a number of strings. Each string includes several memory cells. The memory 200 includes a plurality of even bit lines BL2_even, a plurality of odd bit lines BL2_odd, a plurality of word lines, a plurality of string selection lines SSL2_n, SSL2_n+1, SSL2_n+2, SSL2_n+3, and a plurality of ground selections. Lines GSL2_n, GSL2_n+1, GSL2_n+2, GSL2_n+3, and a common source line CSL2.

Please refer to FIG. 6 , which illustrates a schematic diagram of the serial S21 to the serial S28 of the memory 200 . One end of each of the strings S21 to S28 is connected to the common source line CSL2, and the other end of each of the strings S21 to S28 is connected to the even bit line BL2_even or the odd bit line BL2_odd.

The serial selection lines SSL2_n, SSL2_n+1, SSL2_n+2, and SSL2_n+3 are used to turn on or off the serial selection switches SD2_n, SD2_n+1, SD2_n+2, and SD2_n+3, respectively. The serial selection switch SD2_n is controlled by the serial selection line SSL2_n, the serial selection switch SD2_n+1 is controlled by the serial selection line SSL2_n+1, and the serial selection switch SD2_n+2 is composed of the serial selection line SSL2_n+2. Controlled, and the serial selection switch SD2_n+3 is controlled by the serial selection line SSL2_n+3. For example, if the serial selection switch SD2_n is turned on, the voltage supplied from the odd bit line BL2_odd (or the even bit line BL1_even) can be applied to the string S21 (or the string S25) connected to the string selection switch SD2_n. .

The ground selection lines GSL2_n, GSL2_n+1, GSL2_n+2, and GSL2_n+3 are used to turn on or off the ground selection switches GD2_n, GD2_n+1, GD2_n+2, GSL2_n+3, respectively. The ground selection switches GD2_n, GD2_n+1, GD2_n+2, GSL2_n+3 are not controlled by the same ground selection line. Conversely, the ground selection switch GD2_n is controlled by the ground selection line GSL2_n, the ground selection switch GD2_n+1 is controlled by the ground selection line GSL2_n+1, and the ground selection switch GD2_n+2 is controlled by the ground selection line GSL2_n+2. The ground selection switch GD2_n+3 is controlled by the ground selection line GSL2_n+3. For example, if the ground selection switch GD2_n is turned on, the voltage supplied from the common source line CSL2 can be applied to the series S22, S25 connected to the ground selection switch GD2_n.

In the embodiment of the all bit lines sensing scheme, the series S22, S25 are regarded as one page, and the series S23, S26 are regarded as one page, and the series S24, S27 Considered as a page, the series S21, S28 are treated as one page.

In Fig. 6, the series S22, S25 are read. The series S23, S24, S27, and S28 are floating. The channel potentials of the series S23, S24, S27, S28 are raised to a predetermined voltage level Vch. Therefore, in the series S23, S24, S27, and S28, the voltage difference between each of the unselected memory cells in the gate and the channel can be reduced from "the difference between the on-voltage Vpass and the 0 volt" to the "on-voltage Vpass and the predetermined voltage level". The difference between Vch." Furthermore, the serial selection switch SD2_n is turned on by the string selection line SSL2_n such that the channel potential of the string S21 is raised to the predetermined bit line voltage Vbl supplied from the odd bit line BL2_odd. The string selection switch SD2_n+1 is turned on by the string selection line SSL2_n+1 such that the channel potential is raised to the predetermined bit line voltage Vbl supplied from the even bit line BL2_even. Therefore, the voltage difference between the unselected memory cells in the series S21 and S26 in the gate and the channel can be reduced from "the difference between the on-voltage Vpass and the 0 volt" to the difference between the on-voltage Vpass and the predetermined bit line voltage Vbl. "." Since the voltage difference of the unselected memory cells has been lowered, the occurrence of read disturb can be effectively prevented.

Please refer to Table 1, which shows the reading operation of the pages composed of the serials S22 and S25. In Table 1, the string selection lines SSL2_n, SSL2_n+1 are selected to apply the predetermined series selection voltage Vssl; the unselected series selection lines SSL2_n+2, SSL2_n+3 are applied with a voltage of 0 volts. The ground selection line GSL2_n is selected to apply a predetermined ground selection voltage Vgsl; the unselected ground selection lines GSL2_n+1, GSL2_n+2, GSL2_n+3 are applied with a voltage of 0 volts. The common source line CSL2 is applied with a voltage of 0 volts. All of the even bit lines BL2_even and the odd bit lines BL2_odd are selected to apply the predetermined bit line voltage Vbl. Table I

Please refer to Table 2, which shows the reading operation of the pages composed of the series S23 and S26. In Table 2, the string selection lines SSL2_n+1, SSL2_n+2 are selected to apply the predetermined series voltage Vssl; the unselected series selection lines SSL2_n, SSL2_n+3 are applied with a voltage of 0 volts. The ground selection line GSL2_n+1 is selected to apply a predetermined ground selection voltage Vgsl; the unselected ground selection lines GSL2_n, GSL2_n+2, GSL2_n+3 are applied with a voltage of 0 volts. The common source line CSL2 is applied with a voltage of 0 volts. All of the even bit lines BL2_even and the odd bit lines BL2_odd are applied with a predetermined voltage Vb1. Table II

Please refer to Table 3, which shows the reading operation of the page composed of the serial S24 and S27. In Table 3, the serial selection lines SSL2_n+2, SSL2_n+3 are selected to apply the predetermined series voltage Vssl; the unselected series selection lines SSL2_n, SSL2_n+1 are applied with a voltage of 0 volts. The ground selection line GSL2_n+2 is selected to apply a predetermined ground selection voltage Vgsl; the unselected ground selection lines GSL2_n, GSL2_n+1, GSL2_n+3 are applied with a voltage of 0 volts. The common source line CSL2 is applied with a voltage of 0 volts. All of the even bit lines BL2_even and odd bit lines BL2_odd are selected to apply a predetermined voltage Vbl. Table 3

Please refer to Table 4, which shows the reading operation of the page composed of the series S21, S28. In Table 4, the string selection lines SSL2_n+3, SSL2_n are selected to be applied with a predetermined series voltage Vssl; the unselected series selection lines SSL2_n+1, SSL2_n+2 are applied with a voltage of 0 volts. The ground selection line GSL2_n+3 is selected to apply a predetermined ground selection voltage Vgsl; the unselected ground selection lines GSL2_n, GSL2_n+1, GSL2_n+2 are applied with a voltage of 0 volts. The common source line CSL2 is applied with a voltage of 0 volts. All of the even bit lines BL2_even and the odd bit lines BL2_odd are applied with a predetermined voltage Vb1. Table 4

As described above, in the process of the all bit lines sensing scheme, the voltage difference between the gate and the channel of the unselected memory cell can be lowered to "the on-voltage Vpass and the predetermined voltage level Vch". "Poor" or "difference between the on-voltage Vpass and the predetermined bit line voltage Vbl". In this way, the occurrence of read disturb can be effectively prevented.

In the above, the disclosure has been disclosed in the above preferred embodiments, and is not intended to limit the disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the disclosure. Therefore, the scope of protection of this disclosure is subject to the definition of the scope of the appended claims.

100, 200‧‧‧ memory

110‧‧‧Decoder

BL1_even, BL2_even‧‧‧ even bit lines

BL1_odd, BL2_odd‧‧‧ odd bit lines

CSL1, CSL2‧‧‧ common source line

GD1_n, GD1_n+1, GD1_n+2, GD2_n, GD2_n+1, GD2_n+2, GD2_n+3‧‧‧ Ground selection switch

GSL1_n, GSL1_n+1, GSL1_n+2, GSL2_n, GSL2_n+1, GSL2_n+2, GSL2_n+3‧‧‧ Ground selection line

S11, S12, S13, S14, S15, S16, S21, S22, S23, S24, S25, S26, S27, S28‧‧‧ series

SD1_n, SD1_n+1, SD1_n+2, SD2_n, SD2_n+1, SD2_n+2, SD2_n+3‧‧‧ Serial selection switch

SSL1_n, SSL1_n+1, SSL1_n+2, SSL2_n, SSL2_n+1, SSL2_n+2, SSL2_n+3‧‧‧ Serial selection line

ST1‧‧‧ preparatory stage

ST2‧‧‧ reading phase

SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8‧‧‧ switch

Vbl‧‧‧predetermined bit line voltage

Vch‧‧‧predetermined voltage level

Vgsl‧‧‧predetermined ground voltage

Vpass‧‧‧ turn-on voltage

Vread‧‧‧ reading voltage

Vssl‧‧‧Predetermined tandem selection voltage

WL1_n, WL1_n+1, WL2‧‧‧ character lines

FIG. 1 is a schematic diagram of a memory according to an embodiment. FIG. 2 is a diagram showing a voltage waveform of a forward read operation of the memory. Figure 3 is a schematic diagram showing the channel potential of the memory. Figure 4 is a diagram showing voltage waveforms of an all bit lines sensing operation of the memory. FIG. 5 is a schematic diagram of a memory according to another embodiment. Figure 6 is a schematic diagram showing a plurality of serials of memory.

Claims (10)

A method of reading a memory for preventing read disturbance, the reading method comprising: selecting at least one of a plurality of string select lines and applying a predetermined string The column selects a voltage to the selected string select line; and selects only one of a plurality of ground select lines and applies a predetermined ground select voltage to the selected ground select line. The method of reading a memory according to claim 1, wherein the ground selection lines are not connected to each other. The method for reading a memory according to claim 1, wherein the memory comprises a plurality of strings, at least one of the strings is selected, and the series is selected to be connected to The serial selection line is selected and the ground selection line is selected. The method for reading a memory according to claim 1, further comprising: selecting a plurality of even bit lines or a plurality of odd bit lines to apply a predetermined bit Element voltage. The method of reading a memory according to claim 1, wherein in the step of selecting at least one of the series of selection lines, two of the series of selection lines are selected. A memory comprising: a plurality of string select lines, at least one of the series select lines being selected by a decoder to apply a predetermined series select voltage; and a plurality of ground select lines (ground select line), only one of the series select lines is selected through the decoder to apply a predetermined ground selection voltage. The memory of claim 6, wherein the ground selection lines are not connected to each other. The memory of claim 6, further comprising: a plurality of strings, wherein at least one of the series is selected, and the selected series is connected to the selected string selection line and Select the ground selection line. The memory of claim 6 further includes: a plurality of even bit lines and a plurality of odd bit lines, wherein the even bit lines or the plurality of bit lines An odd bit line is selected to apply a predetermined bit voltage. The memory of claim 6, wherein two of the series of selection lines are selected.