TWI766559B - Operation method for memory device - Google Patents

Abstract

An operation method of a memory device is provided. The memory device includes a P-type well, a common source line, a memory array, a plurality of word lines, and a serial selection line, a ground selection line, and at least one bit line. The word lines include a first word line and a second word line that are programmed and not adjacent to each other. The operation method includes the following steps. A read voltage is applied to a selected word line. A pass voltage is applied to unselected word lines, and the read voltage is less than the pass voltage. During a period when the pass voltage ramps down to a lower level before the end of a read operation, a channel potential of the memory string is down-coupled, a hole current is injected to flow from the P-type well to the memory string to neutralize the channel voltage in advance.

Description

How to operate a memory device

The present invention relates to an operating method of a memory device.

In a memory device, the read operation of a word line will increase the threshold voltage of adjacent word lines, which is called read disturbance.

For both 2D and 3D NAND flash memory, multiple dummy word lines have been used in NAND strings for different purposes. As arrays have grown in size and density, additional dummy wordlines have been incorporated to mitigate unwanted programming interference on wordline edges. In the absence of dummy word lines, the edge word lines of NAND strings are more susceptible to tunneling or hot carriers by Fowler-Nordheim (FN) because they are located in high electric field spaces. affected by the interference caused by the effect.

In addition, as technology nodes continue to shrink and the demand for multiple bits per cell increases, the number of programmed firings has greatly increased, making it almost impossible for cell transistors on word lines to avoid hot carrier effects and The related read disturbance needs to be further improved.

The present invention relates to an operating method of a memory device to avoid hot carrier effects and related read disturbances from affecting the read accuracy of adjacent word lines.

According to an aspect of the present invention, a method for operating a memory device is provided. The memory device includes a P-type well region, a common source line, a memory array, a plurality of word lines, a series of column select lines, a A ground select line and at least one bit line, wherein the word lines are connected to a memory string in the memory array, and the word lines are arranged between the string select line and the ground select line. The memory string is connected between the bit line and the common source line. The word lines include a first word line and a second word line that are programmed and not adjacent to each other. The operation method includes the following steps . A read voltage is applied to a selected word line. A pass voltage is applied to the unselected word lines, and the read voltage is less than the pass voltage. Before the end of the read operation, one of the ground selection transistors on the ground selection line is turned off in advance, so that the gate voltage of the ground selection transistor is reduced from the pass voltage to a lower level.

According to an aspect of the present invention, a method for operating a memory device is provided. The memory device includes a string select line, and the string select line has a channel potential coupled downward. The operation method includes the following steps. A read voltage is applied to the selected word line. A pass voltage is applied to the unselected word lines, and the read voltage is less than the pass voltage. Before the end of the read operation, a ground selection transistor is turned off in advance, so that the gate voltage of the ground selection transistor is reduced from the pass voltage to a lower level.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given and described in detail in conjunction with the accompanying drawings as follows:

100: Memory device

101: Memory Array

102: Memory string

T0,T1,T2: time

WL1,WLx,WLx-1: word line

SSL: Serial select line

GSL: Ground Selection Line

SSM: Serial Select Transistor

GSM: Ground Select Transistor

BL, BL1, BL2: bit lines

CSL: Common Source Line

MC: memory unit cell

Vch: channel potential

WLn: first word line

WLn+k: Second word line

PWI: Substrate (P-well area)

Vread: read voltage

VCSL, VPWI, VBL: Voltage

S110-S130: Steps

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a voltage waveform of the memory device during a read operation; FIG. 3 shows a schematic diagram of the channel voltage being coupled down between the first word line and the second word line before the read operation ends; FIG. 4 shows a memory device according to an embodiment of the present invention Figure 5 is a schematic diagram of the voltage waveform of the memory device during a read operation according to an embodiment of the present invention; Figure 6 is a schematic diagram of the channel voltage at the first word before the end of the read operation A schematic diagram showing no downward coupling between the line and the second word line; and FIG. 7 is a schematic diagram showing a voltage waveform of a memory device during a read operation according to another embodiment of the present invention.

The following examples are provided for detailed description, and the examples are only used as examples to illustrate, and are not intended to limit the scope of protection of the present invention. In the following, the same/similar symbols are used to represent the same/similar elements for description.

Please refer to FIGS. 1, 2 and 3, wherein FIG. 1 is a schematic diagram of a memory device 100 according to an embodiment of the present invention, and FIG. 2 is a schematic diagram of a voltage waveform of the memory device 100 during a read operation. FIG. 3 is a schematic diagram illustrating the downward coupling of the channel potential Vch between the first word line WLn and the second word line WLn+k before the end of the read operation.

Referring to FIG. 1, according to an embodiment of the present invention, the memory device 100 has multiple layers of word lines WL0 to WLx stacked in a vertical direction. The parallel strip-shaped string selection line SSL and the idle string selection line SSL dummy are arranged above the word line WLx, and the ground selection line GSL and the idle ground selection line GSL dummy are arranged on the word line Below WL0. The intersection of the bit lines BL1, BL2 and the serial selection line SSL/SSL dummy is a serial selection transistor (SSM), and the intersection of the bit lines BL1, BL2 and the ground selection line GSL/GSL dummy is Ground selection transistor GSM. A set of memory cells (MC) on the bit line BL1 and the word lines WL0 to WLx are connected in series to form a memory string 102 such that the memory string 102 is connected between the bit line BL1 and the common source between lines CSL. In addition, the bit line BL2 and another group of memory cells on the word lines WL0 to WLx are connected in series to form another memory string 102, so that the memory string 102 is connected between the bit line BL2 and the common source line CSL between.

That is, the memory string 102 is located between the P-type well region and the bit line BL and includes a plurality of memory cells MC. The memory unit cell MC is, for example, a unit unit cell, a multi-bit unit cell, or a three-bit unit cell, etc., which is not limited in the present invention. Taking the three-dimensional unit cell as an example, the memory unit cell can be programmed into 8 states, namely, erase state, A state, B state, C state, D state, E state, F state, and G state. The highest state is the G state, which has the highest threshold voltage. Wherein, two non-adjacent memory cells in the memory string 102 can be programmed to be in the G state (highest threshold voltage state), while the remaining memory cells can be in the erased state or lower state (eg, A status or B status). As shown in FIG. 3, the first word line WLn with a higher threshold voltage is not adjacent to the second word line WLn+k, where n is a positive integer, and k is a positive integer greater than 1, such as 2 to 10 any value in . In one embodiment, a downwardly coupled channel potential Vch may be formed between the first word line WLn and the second word line WLn+k.

Before the memory string 102 receives a programming operation, the memory string 102 may receive an erase operation. The voltage of the erase operation is, for example, the voltage applied to the substrate (P-well region) PWI through the local interconnect, the erase voltage is, for example, -2V, and the voltage of the program operation is applied to a select word line through the wire, for example The programming voltage on the gate of , and the pass voltage Vpass applied to an unselected word line. The pass voltage Vpass is less than the programming voltage applied to the gate of the selected word line, eg, the pass voltage Vpass is 10V, and the programming voltage is eg 20V.

When electrons are injected from the bit line BL into a channel of the memory string 102 due to the programming operation and flow to the gate of the selected word line, the electrons are stored in the charge trapping layer to increase the threshold voltage of the gate.

Next, referring to FIGS. 2 and 3, the selected word line can be programmed to perform a read operation or a verification operation. Before the read operation or the verification operation is completed, the pass voltage Vpass on the unselected word line ramps down During the period to a lower level (eg 0V), since the non-adjacent two word lines WLn and WLn+k have cells in a high threshold voltage state, when the selected word line is discharged, a downwardly coupled channel potential Vch is formed (eg -4V) will cause hot carriers (electrons e-) to easily move to the gates of adjacent word lines via the down-coupled channel, resulting in adjacent word lines WLn-1 and/or WLn +k+1 for read disturb issue.

Please refer to FIGS. 4 , 5 and 6, wherein FIG. 4 is a schematic diagram illustrating an operation method of the memory device 100 according to an embodiment of the present invention, and FIG. 5 is a schematic diagram illustrating the memory device 100 according to an embodiment of the present invention in Schematic diagrams of voltage waveforms during the read operation. FIG. 6 is a comparison diagram of the channel potential Vch without down-coupling before the end of the read operation and the channel potential down-coupling (indicated by dotted lines) in FIG. 3 .

The operation method includes the following steps. In step S110, a read voltage Vread is applied to a selected word line. In step S120, a pass voltage Vpass is applied to the unselected word line, wherein the read voltage Vread is lower than the pass voltage Vpass. In step S130, a hole current is injected into the memory string 102 from the P-well region to neutralize the channel potential Vch during the period when the pass voltage Vpass is ramped down to a lower level before the end of the read operation.

Next, referring to FIGS. 5 and 6, a method for injecting hole current into the memory string 102 from the P-type well region is, for example, to turn off one of the select transistors on the ground select line GSL and the GSL dummy to make its gate The voltage is lowered from the pass voltage Vpass to 0V in advance, and the P-type well region and the common source line CSL are maintained at 0.7V (VPWI=VCSL=0.7). That is, the potential of the P-well region is maintained to be greater than the channel potential Vch between the first word line WLn and the second word line WLn+k, so the hole current can be injected into the memory through the ground selection transistor GSM In the bulk string 102, the channel potential Vch that is coupled downward is neutralized. At this time, the gate voltage of one of the select transistors on the string select line SSL is still maintained at the pass voltage Vpass, until the read operation ends, and the gate voltage drops to 0V. Therefore, in this embodiment, the voltage of the ground select line GSL can be changed to Before the end of the read operation from T0 to T1, the hole current is injected into the memory string 102 from the P-type well region to 0V, so as to avoid a channel potential Vch of the memory string 102 from T1 to T2 In the case of downward coupling between the first word line WLn and the second word line WLn+k, it is thus avoided that hot carriers (electrons e ⁻ ) can easily move to adjacent words through the downwardly coupled channel The gate of the word line causes read disturbance of adjacent word lines.

In addition, please refer to FIG. 5, the bit line BL is maintained at a precharge voltage (eg 1.3V) during the read operation, and the voltage VBL of the bit line BL is at the pass voltage The pre-charge voltage drops to a lower level (eg, 0.7V) during the period T0 to T1 before Vpass ramps down. In addition, the common source line CSL is maintained at 0.7V during the read operation, and before the pass voltage Vpass is ramped down, the common source line CSL is coupled to the P-type well region to form an equipotential, so that the voltage in the P-type well region is The hole can easily be injected into the memory string 102 across the energy barrier of the ground select transistor GSM (GSL/GSL dummy). In this embodiment, in order to allow holes to remain in the channels of the memory string 102, the voltage of the bit line BL drops from the precharge voltage 1.3V to 0.7V during the period from T0 to T1 before the pass voltage Vpass ramps down, Equipotential is formed between the voltage of the bit line BL and the common source line CSL and the voltage VCSL/VPWI of the P-type well region, so that the injected holes can be prevented from leaking to the bit line through the string select line SSL/SSL dummy BL.

Please refer to FIG. 7 , which is a schematic diagram of voltage waveforms of the memory device 100 during a read operation according to another embodiment of the present invention. In another embodiment, the method of injecting hole current into the memory string 102 from the P-type well region is, for example, applying a negative voltage to one of the select transistors on the ground select line GSL/GSL dummy to make it gate The electrode voltage is lowered to a lower level (eg -1V to -4V) from the pass voltage Vpass in advance, and the P-type well region and the common source line CSL are maintained at 0.7V (VPWI=VCSL=0.7), therefore, the grounding selection The voltage of line GSL drops to a lower level (less than 0V) from T0 to T1 before the end of the read operation, so that more hole current can be injected into the memory string 102 through the ground select transistor GSM, so that the and the down-coupled channel potential Vch.

In addition, please refer to FIG. 7, the bit line BL is maintained at a precharge voltage (eg 1.3V) during the read operation, and the voltage of the bit line BL is in the period T0 to T1 before the pass voltage Vpass is ramped down from the precharge voltage to a lower level (eg 0.7V). In addition, the common source line CSL is maintained at 0.7V during the read operation, and before the pass voltage Vpass is ramped down, the common source line CSL is coupled to the P-type well region to form an equipotential, so that the voltage in the P-type well region is A hole can easily be injected into the memory string 102 across the energy barrier of the ground select transistor GSM. In this embodiment, in order to allow holes to remain in the channels of the memory string 102, the voltage of the bit line BL drops from the precharge voltage 1.3V to 0.7V during the period from T0 to T1 before the pass voltage Vpass ramps down, Equipotential is formed between the voltage of the bit line BL and the common source line CSL and the voltage VCSL/VPWI of the P-type well region, so that the injected holes can be prevented from leaking to the bit line through the string select line SSL/SSL dummy BL.

In one embodiment, the read operation method of FIG. 4 can be applied to a normal read operation or a program-verify operation, which are all within the scope of the present invention. In a not-shown embodiment, the memory device 100 may include a controller coupled to the memory array 101 (see FIG. 1 ). The controller can execute the operation methods described in the above embodiments, and details are not described herein again.

The operating method of the memory device according to the above embodiments of the present invention can effectively suppress the reading interference of adjacent word lines, so as to help correctly interpret the output data, thereby increasing the reading accuracy of the word lines.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

S110-S130: Steps

Claims (9)

A method of operating a memory device, the memory device comprising a P-type well region, a common source line, a memory array, a plurality of word lines, a string select line, a ground select line, and at least one bit element lines, wherein the word lines are connected to a memory string in the memory array, and the word lines are arranged between a string select line and a ground select line, the memory string is connected to the bit line and the common source line, the word lines include a first word line and a second word line that are programmed and not adjacent to each other, and the operation method includes: applying a read voltage to a selection apply a pass voltage to the unselected word line, the read voltage is lower than the pass voltage; and before the end of the read operation, turn off a ground select transistor on the ground select line in advance, so that the The gate voltage of the ground select transistor drops from the pass voltage to a lower level, the bit line is maintained at a precharge voltage during the read operation, and the bit line voltage ramps down from the pass voltage from the precharge voltage to a lower level during a previous period. The method of claim 1, wherein when the gate voltage of the ground select transistor drops from the pass voltage to the lower level, the potential of the P-well region is maintained greater than that of the first word line and the second A channel potential between word lines causes a hole current to be injected into the memory string from the P-well region to neutralize the channel potential. The method of claim 2, wherein the method for reducing the gate voltage of the ground select transistor from the pass voltage to the lower level includes applying a negative voltage to the ground select transistor on the ground select line, causing The gate voltage of the selection transistor is less than 0V. The method of claim 1, wherein the gate voltage of a select transistor on the string select line is maintained at the pass voltage until ramping down to 0V at the end of the read operation. The method of claim 1, wherein the common source line CSL is maintained at 0.7V during the read operation, and the common source line is coupled to the P-well during a period before the pass voltage ramps down region to form an equipotential. The method of claim 1, wherein before the pass voltage is ramped down to the lower level period, further comprising forming an equipotential between the bit line and the common source line, and the common source line coupled to the P-type well region. The method of claim 1, wherein the operating method applies to a normal read operation or a program-verify operation. An operation method of a memory device, the memory device includes a memory string, and the memory string has a channel potential coupled downward, the operation method includes: applying a read voltage to a selected word line; applying a pass voltage to unselected word lines, the read voltage being less than the pass voltage; and Before the end of the read operation, a negative voltage is applied to a ground selection transistor, so that the gate voltage of the ground selection transistor is reduced from the pass voltage to a level less than 0V. The method of claim 8, wherein when the gate voltage of the ground select transistor drops from the pass voltage to the lower level, a P-well potential is maintained greater than the channel potential, so that a hole current is reduced by A P-type well is injected into the memory string to neutralize the channel potential.

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