TW201814837A - Structure of resistive element and associated manufcturing method - Google Patents

Abstract

A structure of resistive element is connected between a first conductor and a second conductor. The structure of the resistive element includes a first via located above the first conductor; a first barrier layer formed on an inner surface of the first via and contacted to the first conductor; a first conductive plug filled in the first via and contacted to the first barrier layer; a second barrier layer located above the first via and contacted to the first conductive plug and the first barrier layer; a third conductor covered on the second barrier layer; a third barrier layer covered on the third conductor; a fourth barrier layer covered on the third barrier layer; a variable resistance layer covered on the fourth barrier layer, a fifth barrier layer covered on the variable resistance layer; a second via located above the fifth barrier layer; a sixth barrier layer formed on an inner surface of the second via and contacted to the fifth barrier layer; a second conductive plug filled in the second via and contacted to the sixth barrier layer; and the second conductor electrically contacted to the second conductive plug.

Description

 Structure and manufacturing method of resistive element  

The present invention relates to a semiconductive component and a method of fabricating the same, and more particularly to a structure and a method of fabricating a resistive component.

It is well known that non-volatile memory can continuously store its internal stored data when the power is turned off. For example, Resistive Random Access Memory (RRAM) is a resistive non-volatile memory.

There is a resistive element in the resistive non-volatile memory, which is a variable and reversible resistive element. The resistance value of the resistive element can be controlled to control the storage state of the resistive non-volatile memory.

Please refer to FIG. 1 , which is a schematic structural view of a conventional resistive element. The resistive element structure is disclosed in U.S. Patent No. 8,553,444, entitled "Variable resistance nonvolatile storage device and method of forming memory cell".

Memory cell 300 includes a transistor 317 and a resistive element. The transistor 317 is formed on the semiconductor substrate 301 and includes N-type diffusion layer regions 302a and 302b, a gate insulation film 303a, and a gate 303b.

Furthermore, the interconnection between the N-type diffusion region 302b and the third wiring layer 311 is a resistive element.

The resistive element structure includes: a first via 304, a first wiring layer 305, a second penetration hole 306, a second connection layer 307, and a third penetration hole 308. A variable resistance element 309, a fourth penetration hole 310, and a third connection layer 311.

Furthermore, the variable resistance element 309 is connected between the third penetration hole 308 and the fourth penetration hole 310. The variable resistance element 309 includes an upper electrode 309c, a variable resistance layer 309b, and a lower electrode 309a. In addition, the variable resistance layer 309b further includes a first oxygen-deficient tantalum oxide layer 309b-1 and a second oxygen atom-deficient tantalum oxide layer 309b-2.

The object of the present invention is to provide a structure and a manufacturing method of a newly constructed resistive element, which can simplify the process of resistive non-volatile memory and improve the yield of resistive non-volatile memory.

The present invention is a resistive element structure connected between a first conductor and a second conductor, the resistive element structure comprising: a first penetration hole above the first conductor; a first barrier layer Contacting the inner surface of the first penetration hole and the first conductor; a first conductive plug contacting the first barrier layer and filling the first penetration hole; and a second barrier layer located at the first a first through hole, contacting the first conductive plug and the first barrier layer; a third conductor covering the second barrier layer; a third barrier layer covering the third conductor; a fourth a barrier layer covering the third barrier layer; a variable resistance layer covering the fourth barrier layer; a fifth barrier layer covering the variable resistance layer; and a second penetration hole located at the fifth Above the barrier layer; a sixth barrier layer contacting the inner surface of the second penetration hole and the fifth barrier layer; and a second conductive plug contacting the sixth barrier layer and filling the second penetration a hole, wherein the second conductor is located above the second penetration hole and electrically connected to the hole Two conductive plugs.

The present invention is a method for fabricating a resistive element, comprising the steps of: forming a first dielectric layer on a first conductive layer, and forming a first through hole and a first in the first dielectric layer a through hole, wherein the first conductive layer includes a first conductor and a second conductor, the first penetration hole is located above the first conductor and the second penetration hole is located above the second conductor; forming a first barrier layer contacting the inner surface of the first penetration hole and the first conductor, and contacting the inner surface of the second penetration hole and the second conductor; forming a first conductive plug and a second a conductive plug, the first conductive plug contacts the first barrier layer and fills the first penetration hole, and the second conductive plug contacts the first barrier layer and fills the second penetration hole; Forming a second barrier layer, a second conductive layer, a third barrier layer, a fourth barrier layer, and a layer on the first dielectric layer, the first penetration hole and the second penetration hole a variable resistance layer and a fifth barrier layer; forming a first mask layer, exposing the second penetration hole The fifth barrier layer; etching the exposed fifth barrier layer and the variable resistance layer under the second barrier layer to expose the fourth barrier layer near the second penetration hole; removing the first cover Forming a second mask layer covering the fifth barrier layer near the first penetration hole and covering the fourth barrier layer near the second penetration hole; etching is not the second layer After the fifth barrier layer, the variable resistance layer, the fourth barrier layer, the third barrier layer, the second conductive layer and the second barrier layer covered by the mask layer, the first penetration hole Forming the stacked second barrier layer, a third conductor, the third barrier layer, the fourth barrier layer, the variable resistance layer and the fifth barrier layer, forming a stack above the second penetration hole The second barrier layer, a fourth conductor, the third barrier layer and the fourth barrier layer; removing the second mask layer; forming a second dielectric layer covering the first dielectric layer, the fifth a barrier layer and the fourth barrier layer, and forming a third penetration hole and a fourth penetration hole in the second dielectric layer Wherein the third penetration hole is located above the fifth barrier layer and the fourth penetration hole is located above the fourth barrier layer; forming a sixth barrier layer contacting the inner surface of the third penetration hole and the fifth a barrier layer, and contacting the inner surface of the fourth penetration hole and the fourth barrier layer; forming a third conductive plug and a fourth conductive plug, the third conductive plug contacting the sixth barrier layer and Filling the third penetration hole, the fourth conductive plug contacts the sixth barrier layer and fills the fourth penetration hole; and forms a fifth conductor and a sixth conductor, the fifth conductor is electrically Connected to the third conductive plug, the sixth conductor is electrically connected to the fourth conductive plug.

The present invention is a resistive element structure connected between a first conductor and a second conductor, the resistive element structure comprising: a first penetration hole above the first conductor; a first barrier layer Contacting the inner surface of the first penetration hole and the first conductor; a first conductive plug contacting the first barrier layer and filling the first penetration hole; and a second barrier layer located at the first a first conductive plug and a first barrier layer; a variable resistance layer covering the second barrier layer; a third barrier layer covering the variable resistance layer; a fourth barrier layer covering the third barrier layer; a third conductor covering the fourth barrier layer; a fifth barrier layer covering the third conductor; and a second penetration hole at the fifth Above the barrier layer; a sixth barrier layer contacting the inner surface of the second penetration hole and the fifth barrier layer; and a second conductive plug contacting the sixth barrier layer and filling the second penetration hole Wherein the second conductor is located above the second penetration hole and electrically connected to the Two conductive plugs.

The present invention is a method for fabricating a resistive element, comprising the steps of: forming a first dielectric layer on a first conductive layer, and forming a first through hole and a first in the first dielectric layer a through hole, wherein the first conductive layer includes a first conductor and a second conductor, the first penetration hole is located above the first conductor and the second penetration hole is located above the second conductor; forming a first barrier layer contacting the inner surface of the first penetration hole and the first conductor, and contacting the inner surface of the second penetration hole and the second conductor; forming a first conductive plug and a second a conductive plug, the first conductive plug contacts the first barrier layer and fills the first penetration hole, and the second conductive plug contacts the first barrier layer and fills the second penetration hole; Forming a second barrier layer, a variable resistance layer and a third barrier layer on the first dielectric layer, the first penetration hole and the second penetration hole; forming a first mask layer Exposing the third barrier layer near the second penetration hole; etching the exposed third barrier layer and The variable resistance layer is disposed such that the second barrier layer near the second penetration hole is exposed; the first mask layer is removed; and a fourth barrier layer is formed to cover the third barrier layer Exposing the second barrier layer; forming a second conductive layer covering the fourth barrier layer; forming a fifth barrier layer covering the second conductive layer; forming a second mask layer covering the first penetration layer a fifth barrier layer near the upper portion of the hole and covering the fifth barrier layer near the second penetration hole; etching the fifth barrier layer not covered by the second mask layer, the second conductive layer After the fourth barrier layer, the third barrier layer, the variable resistance layer, and the second barrier layer, the second barrier layer, the variable resistance layer, and the stacked layer are formed over the first penetration hole. a third barrier layer, a fourth barrier layer, a third conductor and the fifth barrier layer, and the second barrier layer, the fourth barrier layer, and the fourth conductor are stacked on the second penetration hole The fifth barrier layer; removing the second mask layer; forming a second dielectric layer covering the a dielectric layer, the fifth barrier layer, and a third penetration hole and a fourth penetration hole in the second dielectric layer, wherein the third penetration hole is above the first penetration hole And exposing the fifth barrier layer, and the fourth penetration hole is located above the second penetration hole and exposing the fifth barrier layer; forming a sixth barrier layer contacting the inner surface of the third penetration hole And the fifth barrier layer, and contacting the inner surface of the fourth penetration hole and the fifth barrier layer; forming a third conductive plug and a fourth conductive plug, the third conductive plug contacting the first a sixth barrier layer filling the third penetration hole, the sixth conductive plug contacting the sixth barrier layer and filling the fourth penetration hole; and forming a fifth conductor and a sixth conductor, the first The fifth conductor is electrically connected to the third conductive plug, and the sixth conductor is electrically connected to the fourth conductive plug.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

300‧‧‧ memory cells

302a, 302b‧‧‧N type diffusion zone

303a‧‧‧gate insulation

303b‧‧‧ gate

304, 306, 308, 310‧‧‧ penetration holes

305, 307, 311‧‧‧ connection layer

309‧‧‧Variable resistance components

309a, 309c‧‧ ‧ electrode layer

309b‧‧‧variable resistance layer

309b-1, 309b-2‧‧‧Oxygen atom defect ruthenium oxide layer

317‧‧‧Optoelectronics

601, 602, 605, 606, 701, 702, 705, 706‧‧‧ penetration holes

603, 604, 703, 704‧‧ ‧ cover layer

610a, 610b, 616a, 616b, 638a, 638b‧‧‧ conductor

710a, 710b, 716a, 716b, 738a, 738b‧‧‧ conductor

612, 615, 615a, 615b, 617, 617a, 617b‧‧ ‧ barrier layer

618, 632, 634, 637, 712, 715, 715a, 715b‧‧ ‧ barrier layer

717, 717a, 717b, 718, 732, 734, 737‧‧ ‧ barrier layer

614, 636, 714, 736‧‧‧ conductive plugs

620, 720‧‧‧resistive components

622, 722‧‧‧ transition layer

624, 724‧‧‧Oxygen capture layer

630, 630a, 630b, 630c, 730, 730a, 730b, 730c‧‧‧ dielectric layer

FIG. 1 is a schematic view showing the structure of a conventional resistive element.

Fig. 2 is a view showing the first embodiment of the structure of the resistive non-volatile memory of the present invention.

3A to 3H are schematic views showing the manufacturing process of the resistive non-volatile memory structure according to the first embodiment of the present invention.

Figure 4 is a diagram showing a second embodiment of the resistive non-volatile memory structure of the present invention.

5A to 5H are schematic views showing a manufacturing process of a resistive non-volatile memory structure according to a second embodiment of the present invention.

The invention discloses a structure and a manufacturing method of a resistive element, which can be applied to a process of a resistive non-volatile memory. Depending on the requirements, an internal connection with a variable resistance layer or an interconnected internal connection can be made between the two conductors.

Please refer to FIG. 2, which illustrates a first embodiment of a resistive element structure of the present invention. The first conductive layer has conductors 610a, 610b thereon, and the second conductive layer has conductors 638a, 638b thereon. Wherein, the inner connection between the conductor 610a and the conductor 638a has a variable resistance layer 620, which is the first embodiment of the resistive element structure of the present invention; the inner connection between the conductor 610b and the conductor 636b is a connection. In addition, the two internal connections are formed in the dielectric layer 630, and the dielectric layer 630 may be an inter-metal dielectric (IMD), and the material may be cerium oxide (SiO ₂ ). In addition, the conductors 610a, 610b, 638a, 638b may be metal wires, and the conductors 610a, 610b may be metal wires that are connected to each other or metal wires that are not connected to each other.

Furthermore, a penetration hole is formed above each of the conductors 610a, 610b. Furthermore, a barrier layer 612 is formed on the inner surfaces of the two penetration holes and the conductors 610a, 610b such that the barrier layers 612 are in contact with the conductors 610a, 610b, respectively. Furthermore, a conductive plug 614 contacts the barrier layer 612 and fills the two penetration holes. The conductive plug 614 is a metal plug.

Furthermore, the barrier layers 615a, 615b are in contact with the two conductive plugs 614, respectively. In addition, a stacked conductor 616a, a barrier layer 617a, a barrier layer 618, a variable resistance layer 620, and a barrier layer 632 are sequentially formed on the barrier layer 615a; and a stacked conductor 616b and a barrier layer 617b are sequentially formed on the barrier layer 615b. , barrier layer 618. In addition, the conductor 616b can also be regarded as another metal wire connected to the conductor 610b. Furthermore, the variable resistance layer 620 includes a transition layer 622 and an oxygen atom trap layer 624, and the positions of the transition layer 622 and the oxygen atom trap layer 624 may be interchanged.

According to the first embodiment of the present invention, the barrier layer 615a, the conductor 616a, the barrier layer 617a, the barrier layer 618, the variable resistance layer 620, and the barrier layer 632 have the same size and are aligned with each other. Moreover, the barrier layers 618, 632 are not limited to being composed of a single material layer, and the barrier layers 618, 632 may be stacked by a plurality of sub-barrier layers.

In addition, there is a penetrating hole above each of the barrier layer 632 and the barrier layer 618. The barrier layer 634 is formed on the inner surface of the penetration hole and the barrier layer 632, and the barrier layer 634 is formed on the inner surface of the other penetration hole and the barrier layer 618. Furthermore, the conductive plug 636 contacts the barrier layer 634 in the two penetration holes and fills the two penetration holes.

In addition, there are two penetration holes on the second conductive plug 636. The inner surface of the two penetration holes and the conductive plug 636 form a barrier layer 637, and the conductors 638a and 638b respectively contact the barriers in the two penetration holes. Layer 637 fills the two penetration holes. The conductors 638a, 638b are electrically connected to the conductive plugs 636, respectively.

According to the first embodiment of the present invention, the material of the conductors 610a, 610b, 638a, and 638b may be a metal material, an alloy material, a semiconductor, a metal silicide layer. The metal material may be aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta). The alloy material may be a combination of the above metal materials.

The transition layer 622 may be an oxide layer of hafnium (Hf), tantalum (Ta), titanium (Ti), aluminum (Al), niobium (Nb), hafnium (La), zirconium (Zr).

The oxygen atom trapping layer 624 may be a metal layer such as magnesium (Mg), zinc (Zn), titanium (Ti), hafnium (Hf), lanthanum (La), lanthanum (Ta), zirconium (Zr), or copper (Cu). Or an oxide layer of the above metal.

The barrier layers 612, 615a, 615b, 617a, 617b, 618, 632, 634 and the sub-male layer may be iridium (Ir), platinum (Pt), ruthenium (Ru), tungsten (W), titanium (Ti), ruthenium ( A metal layer such as Ta) or a nitride layer of the above metal, which is electrically conductive.

Please refer to FIG. 3A to FIG. 3H , which are schematic diagrams showing the manufacturing process of the first embodiment of the resistive component structure of the present invention.

As shown in FIG. 3A, a dielectric layer 630a is formed over the conductors 610a, 610b, and two penetration holes 601, 602 are formed in the dielectric layer 630a on the conductors 610a, 610b.

Next, as shown in FIG. 3B, a barrier layer 612 is formed on the inner surfaces of the penetration holes 601, 602 and the conductors 610a, 610b, and the conductive plugs 614 fill the two penetration holes 601, 602. The conductors 610a and 610b are aluminum-copper alloys (Al/Cu), the dielectric layer 630a is cerium oxide (SiO ₂ ), the barrier layer 612 is titanium nitride (TiN), and the conductive plug 614 is tungsten (W).

As shown in FIG. 3C, a stacked barrier layer 615, a conductive layer 616, a barrier layer 617, a barrier layer 618, a transition layer 622, an oxygen atom trap layer 624, and a barrier layer 632 are sequentially formed on the dielectric layer 630a. Thereafter, a first mask layer 603 is formed on the barrier layer 632, and the first mask layer 603 exposes only the region near the upper portion of the penetration hole 602. Next, an etching step is performed on the region not covered by the first mask layer 603, and the uncovered barrier layer 632, the oxygen atom capturing layer 624, and the transition layer 622 are etched to expose the barrier layer 618.

As shown in FIG. 3D, after the first mask layer 603 is removed, a second mask layer 604 is formed to cover the area near the upper portions of the penetration holes 601 and 602. Next, an etching step is performed on the region not covered by the second mask layer 603, and the uncovered barrier layer 632, the oxygen atom capturing layer 624, the transition layer 622, the barrier layer 618, the barrier layer 617, and the conductive layer 616 are etched. The barrier layer 615 is exposed until the surface of the dielectric layer 630a is exposed.

After the etching step is completed and the second mask layer 604 is removed, as shown in FIG. 3E. The original barrier layer 615 is separated into two barrier layers 615a, 615b, respectively contacting the second conductive plug 614; the original conductive layer 616 is separated into two conductors 616a, 616b, respectively contacting the second barrier layer 615a, 615b; the original barrier layer 617 is separated into two barrier layers 617a, 617b that are in contact with the two conductors 616a, 616b, respectively. Further, a stacked barrier layer 618, a transition layer 622, an oxygen atom trapping layer 624, and a barrier layer 632 are formed over the barrier layer 617a; and only the barrier layer 618 is formed over the barrier layer 617b. Wherein, the conductors 616a, 616b are aluminum-copper alloys (Al/Cu), the barrier layers 615a, 615b, 617a, 617b, 618, 632 are titanium nitride (TiN), the transition layer 622 is hafnium oxide (HfOx), and oxygen atoms. The capture layer 624 is titanium (Ti).

Next, a dielectric layer 630b is overlaid in the structure of FIG. 3E. Next, as shown in FIG. 3F, penetration holes 605, 606 are formed in the dielectric layer 630b, and the barrier layer 632 is exposed below the penetration hole 605, and the barrier layer 618 is exposed below the penetration hole 606. The dielectric layer 630b is cerium oxide (SiO ₂ ).

Next, as shown in FIG. 3G, a barrier layer 634 is formed on the inner surface of the penetration hole 605 and the barrier layer 632, and a barrier layer 634 is formed on the inner surface of the penetration hole 606 and the barrier layer 618. Next, a conductive plug 636 is formed to fill the two penetration holes 605, 606. Wherein, the barrier layer 634 is titanium nitride (TiN), and the conductive plug 636 is tungsten (W).

A dielectric layer 630c is further covered in the structure of FIG. 3G, and two penetration holes are formed in the dielectric layer 630c, and the conductive plugs 636 are exposed under the second penetration holes. Next, a barrier layer 637 is formed on the inner surface of the two penetration holes and the two conductive plugs 636. Thereafter, as shown in FIG. 3H, the conductors 638a and 638b are filled in the two penetration holes to contact the barrier layer 637. Therefore, an inner connection having a variable resistance layer is formed between the conductor 610a and the conductor 638a, which is the first embodiment of the resistive element structure of the present invention. A conductor internal connection is formed between the conductor 610b and the conductor 638b. Among them, the conductors 638a and 638b are aluminum-copper alloys (Al/Cu), and the barrier layer 637 is titanium nitride (TiN).

As apparent from the above description, the first embodiment of the present invention discloses that the etching step is used to form the barrier layer 615a, the conductor 616a, the barrier layer 617a, the barrier layer 618, the variable resistance layer 620, and the barrier ribs of the same size and aligned with each other. Layer 632.

Please refer to FIG. 4, which illustrates a second embodiment of the structure of the resistive element of the present invention. The first conductive layer has conductors 710a, 710b thereon, and the second conductive layer has conductors 738a, 738b thereon. Wherein, the inner connection between the conductor 710a and the conductor 738a has a variable resistance layer 720, which is the second embodiment of the resistive element structure of the present invention; the inner connection between the conductor 710b and the conductor 738b is a connection. In addition, the two inner connections are formed in the dielectric layer 730, and the dielectric layer 730 is an IMD, and the material thereof may be cerium oxide (SiO ₂ ). In addition, the conductors 710a, 710b, 738a, 738b may be metal wires, and the conductors 710a, 710b may be metal wires that are connected to each other or metal wires that are not connected to each other.

Furthermore, a penetration hole is formed above each of the conductors 710a, 710b. Furthermore, a barrier layer 712 is formed on the inner surfaces of the two penetration holes and the conductors 710a, 710b such that the barrier layers 712 are in contact with the conductors 710a, 710b, respectively. Furthermore, the conductive plug 714 contacts the barrier layer 712 and fills the two penetration holes. The conductive plug 714 is a metal plug.

Furthermore, the second barrier layer 718 is in contact with the second conductive plug 714, respectively. A stacked variable resistance layer 720, a barrier layer 732, a barrier layer 715a, a conductor 716a, and a barrier layer 717a are formed over one of the barrier layers 718; and a barrier layer 715b, a conductor 716b, and a barrier layer 717b are formed over the other barrier layer 718. . Alternatively, conductor 716b can also be considered as another metal wire that is connected to conductor 710b. Furthermore, the variable resistance layer 720 includes a transition layer 722 and an oxygen atom trap layer 724, and the positions of the transition layer 722 and the oxygen atom trap layer 724 may be interchanged.

According to the second embodiment of the present invention, the barrier layer 718, the variable resistance layer 720, the barrier layer 732, the barrier layer 715a, the conductor 716a, and the barrier layer 717a have the same size and are aligned with each other. Moreover, the barrier layers 718, 732 are not limited to being composed of a single material layer, and the barrier layers 718, 732 may be stacked by a plurality of sub-barrier layers.

In addition, there is a penetration hole above each of the barrier layers 717a, 717b. Wherein, a barrier layer 734 is formed on the inner surface of the penetration hole and the barrier layer 717a, and the barrier layer 734 is formed on the inner surface of the other penetration hole and the barrier layer 717b. Furthermore, the conductive plug 736 contacts the barrier layer 734 in the two penetration holes and fills the two penetration holes.

In addition, there are two penetration holes on the second conductive plug 736. The inner surface of the two penetration holes and the conductive plug 736 form a barrier layer 737, and the conductors 738a and 738b respectively contact the barrier layer in the two penetration holes. 737 and fill the two penetration holes. The conductors 738a, 738b are electrically connected to the conductive plugs 736, respectively.

According to a second embodiment of the present invention, the material of the conductors 710a, 710b, 738a, and 738b may be a metal material, an alloy material, a semiconductor, a metal silicide layer. The metal material may be aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta). The alloy material may be a combination of the above metal materials.

The transition layer 722 can be an oxide layer of hafnium (Hf), tantalum (Ta), titanium (Ti), aluminum (Al), niobium (Nb), hafnium (La), zirconium (Zr).

The oxygen atom trapping layer 724 may be a metal layer such as magnesium (Mg), zinc (Zn), titanium (Ti), hafnium (Hf), lanthanum (La), tantalum (Ta), zirconium (Zr), or copper (Cu). Or an oxide layer of the above metal.

The barrier layers 712, 715a, 715b, 717a, 717b, 718, 732, 734 and the sub-male layer may be iridium (Ir), platinum (Pt), ruthenium (Ru), tungsten (W), titanium (Ti), iridium ( A metal layer such as Ta) or a nitride layer of the above metal, which is electrically conductive.

Please refer to FIG. 5A to FIG. 5H , which are schematic diagrams showing the manufacturing process of the second embodiment of the resistive component structure of the present invention.

As shown in FIG. 5A, a dielectric layer 730a is formed over the conductors 710a, 710b, and two penetration holes 701, 702 are formed in the dielectric layer 730a above the conductors 610a, 610b.

Next, as shown in FIG. 5B, a barrier layer 712 is formed on the inner surfaces of the penetration holes 701, 702 and the conductors 710a, 710b, and the conductive plugs 714 fill the two penetration holes 701, 702. The conductors 710a and 710b are aluminum-copper alloys (Al/Cu), the dielectric layer 730a is cerium oxide (SiO ₂ ), the barrier layer 712 is titanium nitride (TiN), and the conductive plug 714 is tungsten (W).

Next, a stacked barrier layer 718, a transition layer 722, an oxygen atom trap layer 724, and a barrier layer 732 are sequentially formed on the dielectric layer 730a. Thereafter, a first mask layer 703 is formed on the barrier layer 632, and the first mask layer 703 exposes only the region near the upper portion of the penetration hole 702. Next, as shown in FIG. 5C, an etching step is performed on the region not covered by the first mask layer 703, and the uncovered barrier layer 732, the oxygen atom capturing layer 724, and the transition layer 722 are etched to expose the barrier layer. 718.

After the first mask layer 703 is removed, as shown in FIG. 5D, the barrier layer 715, the conductive layer 716, and the barrier layer 717 are sequentially covered. Next, a second mask layer 704 is further formed on the conductive layer 716 to cover the area near the upper holes 701 and 702.

Next, an etching step is performed on the region not covered by the second mask layer 704, and the uncovered barrier layer 717, the conductive layer 716, the barrier layer 715, the barrier layer 732, the oxygen atom capturing layer 724, the transition layer 722, The barrier layer 718 is exposed until the surface of the dielectric layer 730a is exposed. After the etching step is completed and the second mask layer 704 is removed, as shown in FIG. 5E. The original barrier layer 715 is separated into two barrier layers 715a, 715b that are in contact with the barrier layers 732, 718, respectively; the original conductive layer 716 is separated into two conductors 716a, 716b that are in contact with the barrier layers 715a, 715b, respectively. The original barrier layer 717 is separated into two barrier layers 717a, 717b that are in contact with the two conductors 716a, 716b, respectively. Furthermore, below the barrier layer 715a are a stacked barrier layer 718, a transition layer 722, an oxygen atom trapping layer 724, and a barrier layer 732; and below the barrier layer 715b, there is only a barrier layer 718. Wherein, the conductors 716a, 716b are aluminum-copper alloys (Al/Cu), the barrier layers 715a, 715b, 717a, 717b, 718, 732 are titanium nitride (TiN), the transition layer 722 is hafnium oxide (HfOx), and oxygen atoms. The capture layer 724 is titanium (Ti).

Next, a dielectric layer 730b is overlaid in the structure of FIG. 5E. Next, as shown in FIG. 5F, two penetration holes 705, 706 are formed in the dielectric layer 730b, and the barrier layers 717a, 717b are exposed under the penetration holes 705, 706, respectively. The dielectric layer 730b is cerium oxide (SiO ₂ ).

Next, as shown in FIG. 5G, a barrier layer 734 is formed on the inner surface of the penetration hole 705 and the barrier layer 717a, and a barrier layer 734 is formed on the inner surface of the penetration hole 706 and the barrier layer 717b. Next, a conductive plug 736 is formed to fill the two penetration holes 705, 706. The barrier layer 734 is titanium nitride (TiN) and the conductive plug 736 is tungsten (W).

A dielectric layer 730c is further covered in the structure of FIG. 5G, and two penetration holes are formed in the dielectric layer 730c, and the conductive plugs 736 are exposed under the two penetration holes. Next, a barrier layer 737 is formed on the inner surface of the two penetration holes and the two conductive plugs 736. Thereafter, as shown in FIG. 5H, the conductors 738a and 738b are filled in the two penetration holes to contact the barrier layer 737. Therefore, an inner connection having a variable resistance layer is formed between the conductor 710a and the conductor 738a, which is the second embodiment of the resistive element structure of the present invention. A conductor internal connection is formed between the conductor 710b and the conductor 738b. Among them, the conductors 738a and 738b are aluminum-copper alloys (Al/Cu), and the barrier layer 737 is titanium nitride (TiN).

As can be seen from the above description, it can be seen from the second embodiment of the present invention that the barrier layer 718, the variable resistance layer 720, the barrier layer 732, the barrier layer 715a, the conductive layer 716, and the same size and aligned with each other are formed by an etching step. Barrier layer 717a.

As can be seen from the above description, the present invention provides a structure of a resistive non-volatile memory, which has the advantage that the contact area between the variable resistance layers 620, 720 and the upper and lower barrier layers can be accurately controlled, and thus can be stably controlled. The resistance values of the variable resistance layers 620, 720 are increased, and the yield and the scalability of the resistive non-volatile memory are improved.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (14)

 a resistive component structure is connected between a first conductor and a second conductor, the resistive component structure comprising: a first penetration hole above the first conductor; a first barrier layer contacting the a first penetration hole inner surface and the first conductor; a first conductive plug contacting the first barrier layer and filling the first penetration hole; and a second barrier layer located at the first penetration hole Upper, contacting the first conductive plug and the first barrier layer; a third conductor covering the second barrier layer; a third barrier layer covering the third conductor; a fourth barrier layer covering The third barrier layer; a variable resistance layer covering the fourth barrier layer; a fifth barrier layer covering the variable resistance layer; and a second penetration hole located above the fifth barrier layer; a sixth barrier layer contacting the inner surface of the second penetration hole and the fifth barrier layer; and a second conductive plug contacting the sixth barrier layer and filling the second penetration hole; wherein The second conductor is located above the second penetration hole and electrically connected to the second conductive insertion .    The resistive element structure of claim 1, wherein the variable resistance layer comprises: a transition layer; and an oxygen atom trapping layer contacting the transition layer; wherein the fourth barrier layer and the first layer One of the five barrier layers is in contact with the transition layer, and the fourth barrier layer and the fifth barrier layer are in contact with the oxygen atom capture layer.    The resistive element structure of claim 1, wherein the fourth barrier layer or the fifth barrier layer comprises a plurality of stacked sub-barrier layers.    The resistive element structure of claim 1, wherein the second barrier layer, the third conductor, the third barrier layer, the fourth barrier layer, the variable resistance layer, and the fifth barrier layer have Same size and aligned with each other.    A method for fabricating a resistive component includes the steps of: forming a first dielectric layer on a first conductive layer, and forming a first through hole and a second through hole in the first dielectric layer The first conductive layer includes a first conductor and a second conductor, the first penetration hole is located above the first conductor and the second penetration hole is located above the second conductor; forming a first barrier a layer contacting the inner surface of the first penetration hole and the first conductor, and contacting the inner surface of the second penetration hole and the second conductor; forming a first conductive plug and a second conductive plug, The first conductive plug contacts the first barrier layer and fills the first penetration hole, and the second conductive plug contacts the first barrier layer and fills the second penetration hole; Forming a second barrier layer, a second conductive layer, a third barrier layer, a fourth barrier layer, and a variable resistance layer on the dielectric layer, the first penetration hole and the second penetration hole And a fifth barrier layer; forming a first mask layer, exposing the fifth portion near the second penetration hole a wall layer; etching the exposed fifth barrier layer and the variable resistance layer below the second barrier layer to be exposed near the second penetration hole; removing the first mask layer; forming a second mask layer covering the fifth barrier layer near the first penetration hole and covering the fourth barrier layer near the second penetration hole; etching is not performed by the second mask layer After the fifth barrier layer, the variable resistance layer, the fourth barrier layer, the third barrier layer, the second conductive layer and the second barrier layer are covered, a stack is formed over the first penetration hole The second barrier layer, a third conductor, the third barrier layer, the fourth barrier layer, the variable resistance layer and the fifth barrier layer form a stacked barrier layer above the second penetration hole a fourth conductor layer, the third barrier layer and the fourth barrier layer; removing the second mask layer; forming a second dielectric layer covering the first dielectric layer, the fifth barrier layer and the a fourth barrier layer, and forming a third penetration hole and a fourth penetration hole in the second dielectric layer, wherein the first a penetration hole is located above the fifth barrier layer and the fourth penetration hole is located above the fourth barrier layer; forming a sixth barrier layer contacting the inner surface of the third penetration hole and the fifth barrier layer, and Contacting the inner surface of the fourth penetration hole and the fourth barrier layer; forming a third conductive plug and a fourth conductive plug, the third conductive plug contacting the sixth barrier layer and filling the first a third penetration plug, the fourth conductive plug contacts the sixth barrier layer and fills the fourth penetration hole; and forms a fifth conductor and a sixth conductor, the fifth conductor is electrically connected to the first a third conductive plug electrically connected to the fourth conductive plug.    The method of fabricating a resistive element according to claim 5, wherein the variable resistance layer comprises: a transition layer; and an oxygen atom trapping layer contacting the transition layer; wherein the fourth barrier layer is One of the fifth barrier layers is in contact with the transition layer, and the fourth barrier layer and the fifth barrier layer are in contact with the oxygen atom capture layer.    The method of fabricating a resistive element according to claim 5, wherein the fourth barrier layer or the fifth barrier layer comprises a plurality of stacked sub-barrier layers.    a resistive component structure is connected between a first conductor and a second conductor, the resistive component structure comprising: a first penetration hole above the first conductor; a first barrier layer contacting the a first penetration hole inner surface and the first conductor; a first conductive plug contacting the first barrier layer and filling the first penetration hole; and a second barrier layer located at the first penetration hole Upper, contacting the first conductive plug and the first barrier layer; a variable resistance layer covering the second barrier layer; a third barrier layer covering the variable resistance layer; and a fourth barrier layer Covering the third barrier layer; a third conductor covering the fourth barrier layer; a fifth barrier layer covering the third conductor; and a second penetration hole above the fifth barrier layer; a sixth barrier layer contacting the inner surface of the second penetration hole and the fifth barrier layer; and a second conductive plug contacting the sixth barrier layer and filling the second penetration hole; wherein The second conductor is located above the second penetration hole and electrically connected to the second conductive insertion .    The resistive element structure of claim 8, wherein the variable resistance layer comprises: a transition layer; and an oxygen atom trapping layer contacting the transition layer; wherein the second barrier layer and the first layer One of the three barrier layers is in contact with the transition layer, and the second barrier layer and the third barrier layer are in contact with the oxygen atom capture layer.    The resistive element structure of claim 8, wherein the second barrier layer or the third barrier layer comprises a plurality of stacked sub-barrier layers.    The resistive element structure of claim 8, wherein the second barrier layer, the variable resistance layer, the third barrier layer, the fourth barrier layer, the third conductor, and the fifth barrier layer Having the same size and aligned with each other.    A method for fabricating a resistive component includes the steps of: forming a first dielectric layer on a first conductive layer, and forming a first through hole and a second through hole in the first dielectric layer The first conductive layer includes a first conductor and a second conductor, the first penetration hole is located above the first conductor and the second penetration hole is located above the second conductor; forming a first barrier a layer contacting the inner surface of the first penetration hole and the first conductor, and contacting the inner surface of the second penetration hole and the second conductor; forming a first conductive plug and a second conductive plug, The first conductive plug contacts the first barrier layer and fills the first penetration hole, and the second conductive plug contacts the first barrier layer and fills the second penetration hole; Forming a second barrier layer, a variable resistance layer and a third barrier layer on the dielectric layer, the first penetration hole and the second penetration hole; forming a first mask layer, exposing the The third barrier layer near the second penetration hole; etching the exposed third barrier layer and the underlying layer Changing the resistance layer such that the second barrier layer near the second penetration hole is exposed; removing the first mask layer; forming a fourth barrier layer covering the third barrier layer and exposing the first layer a second barrier layer; forming a second conductive layer covering the fourth barrier layer; forming a fifth barrier layer covering the second conductive layer; forming a second mask layer covering the vicinity of the first penetration hole a fifth barrier layer covering the fifth barrier layer near the second penetration hole; etching the fifth barrier layer not covered by the second mask layer, the second conductive layer, the fourth Forming the second barrier layer, the variable resistance layer, and the third barrier layer over the first penetration hole after the barrier layer, the third barrier layer, the variable resistance layer, and the second barrier layer a fourth barrier layer, a third conductor, and the fifth barrier layer, and the second barrier layer, the fourth barrier layer, a fourth conductor, and the fifth barrier formed over the second penetration hole a layer; removing the second mask layer; forming a second dielectric layer overlying the first dielectric layer a fifth barrier layer and a third penetration hole and a fourth penetration hole in the second dielectric layer, wherein the third penetration hole is located above the first penetration hole and exposes the first a fifth barrier layer, and the fourth penetration hole is located above the second penetration hole and exposes the fifth barrier layer; forming a sixth barrier layer contacting the inner surface of the third penetration hole and the fifth barrier a layer, and contacting the inner surface of the fourth penetration hole and the fifth barrier layer; forming a third conductive plug and a fourth conductive plug, the third conductive plug contacting the sixth barrier layer and filling Full of the third penetration hole, the sixth conductive plug contacts the sixth barrier layer and fills the fourth penetration hole; and forms a fifth conductor and a sixth conductor, and the fifth conductor is electrically connected The sixth conductive plug is electrically connected to the fourth conductive plug.    The method of fabricating a resistive element according to claim 12, wherein the variable resistance layer comprises: a transition layer; and an oxygen atom trapping layer contacting the transition layer; wherein the second barrier layer is One of the third barrier layers is in contact with the transition layer, and the second barrier layer and the third barrier layer are in contact with the oxygen atom capture layer.    The method of fabricating a resistive element according to claim 12, wherein the second barrier layer or the third barrier layer comprises a plurality of stacked sub-barrier layers.