CN106159084A - Damascene process for resistive random access memory top electrode - Google Patents

Abstract

The invention provides a manufacturing method of a memory. An insulating layer is formed over the array of interlayer conductors, and the insulating layer is etched to define a first opening corresponding to a first interlayer conductor in the array, wherein the etching stops at a first upper surface of the first interlayer conductor. A metal oxide layer is formed on the first upper surface. And depositing a first barrier material layer which is conformal with and in contact with the metal oxide layer and the surface of the first opening. The insulating layer is then etched to define a second opening corresponding to a second interlayer conductor in the array, wherein the etching stops at a second upper surface of the second interlayer conductor. A second barrier material layer is deposited conformal to and in contact with the first barrier material layer in the first opening. The first opening is filled with a conductive material.

Description

Damascene Technology of Top Electrode of Resistive Random Access Memory

technical field

The present invention relates to metal oxide based memory devices and methods of manufacturing the same.

Background technique

Resistive Random Access Memory (RRAM) is a type of non-volatile memory that offers the following advantages: small memory cell size, scalability, ultra-high-speed operation, low-power operation, high endurance , good retention, large switching ratio and CMOS compatibility. One type of RRAM includes a metal oxide layer that can be created to vary the resistance between two or more stable resistance ranges by applying electrical pulses of varying degrees suitable for implementation in integrated circuits.

As integrated circuit fabrication technology scales down, damascene processes for forming the top electrodes of RRAMs become more suitable than line patterning. The RRAM memory cell may include an access device having a first terminal and a second terminal, a first plug contacting the first terminal, and a second plug contacting the second terminal. The access device can be a transistor or a diode. A metal oxide layer contacts the top surface of the first plug and serves as a memory element in the RRAM memory cell. An insulating layer is disposed on the first plug and the second plug, and has a first opening and a second opening corresponding to the first plug and the second plug. A first top electrode and a second top electrode may be disposed in the first opening and the second opening, and the first top electrode and the second top electrode are respectively connected to a bit line and a source line.

In the manufacturing method of the RRAM memory unit, for example, before forming respective top electrodes in the openings, the upper surfaces of the first plug and the second plug are oxidized to form a metal oxide layer. When the second plug is designed to electrically connect the second terminal of the access device to the source line, the metal oxide layer on the upper surface of the second plug will be etched. However, etching the metal oxide layer of the upper surface of the second plug located in the second opening may cause damage to the second plug, resulting in higher resistance in the second plug. Furthermore, the sidewalls of the second opening in the insulating layer may be contaminated. For example, if the second plug includes copper (Cu) and the metal oxide layer includes copper oxide (CuO _x ), when etching the metal oxide layer in the second opening, copper may be sputtered onto the second plug. on the side wall of the opening.

In addition, when etching the metal oxide layer in the second opening, a photoresist mask is used to protect the metal oxide layer in the first opening. After etching, the photoresist mask is stripped, which may damage the metal oxide layer in the first opening.

Therefore, in order to provide a cost-effective manufacturing method, it is desirable to provide a memory cell and a manufacturing method thereof that can eliminate the possibility of damage to the plug connected to the source line by etching the metal oxide layer and by removing the possibility of damage to the metal oxide layer. Possibility of damage due to mask lift-off of the layer where the metal oxide layer acts as a programmable resistive element.

Contents of the invention

The invention provides a method for manufacturing a memory. The present invention defines a first opening corresponding to a first interlayer conductor (also called a plug), a metal oxide layer is formed on the upper surface of the first interlayer conductor in the first opening, and the definition corresponds to a second interlayer A first barrier material layer is deposited in the first opening before the second opening of the conductor. Therefore, this method eliminates the possibility of damage to the second interlayer conductor caused by etching the metal oxide layer in the second opening and damage to the insulating layer caused by etching the metal oxide layer in the second opening in the prior art. The possibility of contamination of the sidewalls of the second opening and the possibility of damage to the metal oxide layer in the first opening by mask lift-off.

In an embodiment, an insulating layer is formed over the array of interlayer conductors. The insulating layer is etched to define a first opening corresponding to a first interlevel conductor in the array, wherein the etch stops at a first upper surface of the first interlevel conductor. A metal oxide layer is formed on the first upper surface of the first interlayer conductor in the first opening. A diffusion barrier layer may be formed between the upper surface of the array of interlevel conductors and the insulating layer, the diffusion barrier layer contacting the upper surface to prevent diffusion from the interlevel conductors and to stop the first opening located on the upper surface of the array of interlevel conductors with etching of the second opening. A first barrier material layer is deposited conformal to and in contact with the surface of the metal oxide layer and the first opening, the metal oxide layer being on the first interlayer conductor. The first barrier material layer can protect the metal oxide layer from potential damage through subsequent fabrication steps to form and then remove the etch mask on the metal oxide layer, thereby providing a better interface between the metal oxide layer and the top electrode. A width of the first opening may be greater than a width of the first interlayer conductor. The insulating layer is etched after depositing the first barrier material layer to define a second opening in the array corresponding to the second interlevel conductor, wherein the etching stops at the second upper surface of the second interlevel conductor. A second layer of barrier material is deposited conformal to and in contact with the first layer of barrier material in the first opening. The first opening is filled with a conductive material. The first and second interlayer conductors are respectively connected to the first and second terminals of the access device.

When etching to define the first opening, a first etching mask can be used on the insulating layer, wherein the first etching mask has a mask area corresponding to the second interlayer conductor and a spacer area corresponding to the first opening. When etching to define the second opening, a second etching mask can be used on the insulating layer, wherein the second etching mask has a mask area corresponding to the first opening and a spacer area corresponding to the second opening.

Depositing a second layer of barrier material conformal to and in contact with the second upper surface of the second interlayer conductor in the second opening and in contact with the surface of the second opening, the second opening may also be filled with a conductive material, wherein the metal oxide layer is absent Between the second upper surface and the second barrier material layer.

A first access line electrically connected to the metal oxide layer and serving as a bit line can be formed. A second access line electrically connected to the second interlayer conductor and serving as a source line may be formed.

An array of access devices coupled to the array of interlayer conductors may be formed, the array of access devices comprising the aforementioned first access device. The aforementioned first access means may include diodes or transistors. In the foregoing embodiment in which the first access means comprises a transistor, a third access line electrically connected to the gate terminal of the transistor may be formed.

The metal oxide layer can be characterized as having a programmable resistance. The first interlayer conductor may substantially consist of metal, and the metal oxide layer may include metal oxide. The first interlayer conductor may consist essentially of transition metals, and the metal oxide layer may include oxides of transition metals.

Description of drawings

1 shows a cross-sectional view of a memory cell according to an embodiment;

2-8 illustrate exemplary steps in fabricating the memory cell shown in FIG. 1;

9 shows a circuit diagram of a resistive random access memory (Resistive Random Access Memory, RRAM) array according to an embodiment;

Figure 10 shows a simplified design diagram of a memory cell according to the embodiment shown in Figure 9;

FIG. 11 shows a circuit diagram of an RRAM array according to a second embodiment;

Fig. 12 shows a simplified design diagram of a memory cell according to the second embodiment shown in Fig. 11;

FIG. 13 shows a circuit diagram of an RRAM array according to a third embodiment;

Fig. 14 shows a simplified design diagram of a memory cell according to the third embodiment shown in Fig. 13;

Figure 15 shows a circuit diagram of an RRAM array according to an embodiment using diodes as access devices;

FIG. 16 shows a simplified layout diagram of a memory cell according to the embodiment shown in FIG. 15 using diodes as access devices;

Figure 17 shows a simplified flowchart of an embodiment of a method for fabricating a memory device.

[Description of Reference Signs]

100: storage unit

111: first terminal

112: second terminal

120: dielectric layer

131, 941M, 1141M, 1341M: first interlayer conductor

131T: first upper surface

132, 941A, 941B, 1141A, 1141B, 1341A: second interlayer conductor

132T: second upper surface

140: Diffusion barrier

150: insulating layer

161: First opening

162: second opening

170: metal oxide layer

180: first barrier layer

181: first barrier material layer

182: second layer of barrier material

185: Conductive material

310: first etch mask

610: Second etch mask

900, 1100, 1300, 1500: RRAM array

901, 902, 903, 904, 1101, 1102, 1103, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1544: storage unit

901A, 1101A: first transistor

901B, 1101B: second transistor

901M, 1101M, 1301M, 1541M, 1542M, 1543M, 1544M: storage elements

911, 912, 913, 1111, 1112, 1113, 1311, 1312, 1313, 1314: the first access line

921, 922, 923, 1121, 1122, 1123, 1321, 1322, 1323, 1324: the second access line

931, 932, 933, 934, 935, 936, 1131, 1132, 1133, 1134, 1135, 1136, 1331, 1332, 1333, 1334: the third access line

1301A: Transistor

1511, 1512, 1513, 1514: bit lines

1531, 1532, 1533, 1534: word lines

1544D: Diode

1510: Bitline Decoder

1530: word line decoder

1551, 1552, 1553, 1554: contacts

1701, 1702, 1703, 1704, 1705, 1706, 1707: steps

W1, W2: Width

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

It should be understood that there is no intent to limit the invention to the specific disclosed embodiments and methods and that other features, elements, methods and embodiments may be used to practice the invention. The preferred embodiments are described to illustrate the invention, not to limit its scope, which is defined by the claims. Those skilled in the art to which this invention pertains will appreciate various equivalent changes to the following description. Like elements in various embodiments generally have like reference numerals.

FIG. 1 illustrates a cross-sectional view of a memory cell (eg, 100 ) according to an embodiment. A patterned insulating layer (eg, 150) is disposed on the array of interlayer conductors (eg, 131, 132). The patterned insulating layer (eg 150) includes a first opening (eg 161) corresponding to a first interlayer conductor (eg 131) in the array and a second opening (eg 161) corresponding to a second interlayer conductor (eg 132) in the array 162). The first opening and the second opening extend through the patterned insulating layer and stop at the first upper surface (eg 131T) of the first interlayer conductor (eg 131 ) and the second upper surface of the second interlayer conductor (eg 132 ). (eg 132T).

The first interlayer conductor (such as 131 ) and the second interlayer conductor (such as 132 ) include conductive elements. For example, the interlayer conductor may be selected from titanium (Ti), tungsten (W), molybdenum (Mo), aluminum (Al), hafnium (Hf), tantalum (Ta), copper (Cu), platinum (Pt), One or more elements and combinations thereof in the group consisting of iridium (Ir), lanthanum (La), nickel (Ni), nitrogen (N), oxygen (O) and ruthenium (Ru), in some implementations Examples may include more than one layer. In one embodiment, the first and second interlayer conductors may consist essentially of metal, and the metal oxide layer may include metal oxide. In another embodiment, the first and second interlayer conductors may consist essentially of transition metals, and the metal oxide layer may include oxides of transition metals.

A metal oxide layer (such as 170) is disposed on the first upper surface (such as 131T) of the first interlayer conductor (such as 131), while the metal oxide layer does not exist on the second surface of the second interlayer conductor (such as 132). surface (eg 132T). The metal oxide layer can be characterized as having a programmable resistance such that the metal oxide layer is programmable to at least two resistance states. For example, the metal oxide layer may include one or more tungsten-oxygen compounds ( _WOX ), such as one or more of WO ₃ , W ₂ O ₅ , WO ₂ . The metal oxide layer may have a gradient pattern including WO ₃ , W ₂ O ₅ and WO ₂ such that the proportion of oxygen in the metal oxide layer decreases from the first opening (eg 161 ) to the first interlayer conductor (eg 131 ).

As shown in the embodiment, the metal oxide layer 170 formed by oxidizing the upper surface of the first interlayer conductor 131 may be a single layer, so the metal oxide layer 170 is self-aligned to the first interlayer conductor 131 . The metal oxide layer may protrude from the first upper surface of the first interlayer conductor to the first opening due to volume expansion during the formation of the metal oxide layer. In alternative embodiments, metal oxide layer 170 may comprise other metal oxides, for example selected from the group consisting of nickel oxide, aluminum oxide, magnesium oxide, cobalt oxide, titanium oxide, titania-nickel oxide, zirconium oxide, and copper oxide. group of metal oxides.

A diffusion barrier layer (eg, 140 ) may be disposed between the upper surface of the array of interlayer conductors and the patterned insulating layer. A diffusion barrier (eg, 140) can prevent diffusion from interlevel conductors. For example, interlayer conductors may include highly diffusive materials such as copper (Cu), which may cause reliability issues. The diffusion barrier layer (eg, 140 ) may include silicon nitride (SiN). On the upper surface of the array of interlayer conductors, the diffusion barrier layer (eg, 140 ) can also stop the etching of the first opening and the second opening. A thicker diffusion barrier may increase the capacitance of the RRAM memory cell, while a thinner diffusion barrier may not sufficiently prevent diffusion from the interlevel conductor or may not stop the etching of the first and second openings on the upper surface of the interlevel conductor . In one embodiment, in the range of 10 nanometers (nm) to 100 nm, the diffusion barrier layer (eg, 140) may have a thickness of about 30 nm to prevent diffusion from interlayer conductors without causing excessive capacitance.

On the first interlayer conductor and on the surface of the first opening, a first barrier layer (such as 180) conformal to and in contact with the metal oxide layer (such as 170) is disposed, wherein the surface of the first opening includes the side surfaces of the first opening with the underside. The first barrier layer (eg, 180) may include a first layer of barrier material (eg, 181) and a second layer of barrier material (eg, 182) that conforms to and contacts the first layer of barrier material. In one embodiment, the first barrier material layer (eg 181 ) and the second barrier material layer (eg 182 ) of the first barrier layer may have a thickness of about 10 nm in the range of 1 nm to 50 nm.

The second barrier layer may include a second barrier material layer (eg, 182) configured in the second opening to conform to and contact a second upper surface (eg, 132T) of a second interlayer conductor (eg, 132), And the second barrier layer is configured to be conformal and in contact with the side surface and the bottom surface of the second opening. The thickness of the second barrier layer is smaller than the thickness of the first barrier layer 180 . In an embodiment, the second barrier layer including the second barrier material layer (eg, 182 ) is in the range of 1 nm to 50 nm, and may have a thickness of about 10 nm.

The first opening is filled with a conductive material (eg 185 ), where the conductive material (eg 185 ) contacts the first barrier layer (eg 180 ). The second opening is filled with a conductive material (eg 185 ), where the conductive material (eg 185 ) contacts the second barrier layer. The first barrier material layer (such as 181) and the second barrier material layer (such as 182) may include one or more layers of different materials, and the different materials include titanium (Ti), titanium nitride (TiN), tungsten (W) , aluminum copper alloy (AlCu), tantalum nitride (TaN), copper (Cu), hafnium (Hf), tantalum (Ta), gold (Au), platinum (Pt), silver (Ag) and other CMOS compatible and One or more elements of the group consisting of metals that do not contribute to the variable resistance properties of the metal oxide layer.

The first interlayer conductor (eg 131 ) and the second interlayer conductor (eg 132 ) are respectively connected to the first terminal (eg 111 ) and the second terminal (eg 112 ) of the access device. The first terminal and the second terminal of the access device are disposed on one side of the dielectric layer opposite to the first opening and the second opening.

An array of interlayer conductors extends through the dielectric layer (eg, 120). The dielectric layer (eg, 120) may include oxide materials such as plasma enhanced (PE) oxide, plasma enhanced tetraethyl orthosilicate (PETEOS) oxide, low pressure tetraethoxysilane (low pressure tetraethyl orthosilicate, LPTEOS) oxide, high density plasma (high density plasma, HDP) oxide, borophosphosilicate glass film (BPSG), phosphosilicate glass film (PSG) , fluorosilicate glass film (fluorosilicate glass film, FSG), low dielectric constant (low k) materials, etc.

For example, the first access line (not shown) can be electrically connected to the metal oxide layer through the conductive material filled in the first opening, and the first access line can be used as a bit line of the memory cell. For example, the second access line (not shown) can be electrically connected to the second interlayer conductor through the conductive material filled in the second opening, and the second access line can be used as the source line of the memory cell. The first access line and the second access line may include one or more elements including titanium (Ti), tungsten (W), aluminum (Al), copper (Cu), platinum (Pt), nitride Tantalum (TaN), Hafnium (Hf), Tantalum (Ta), and Nickel (Ni). The first access line may comprise the same or a different material than the second access line. The conductive material filled in the first opening (eg 161) and the second opening (eg 162) can be formed in metal layer 1 (ML1), and the first and second access lines can be formed in metal layers 2, 3, 4 or n (ML2, ML3, ML4 or ... MLn). Furthermore, the first and second access lines can be formed on different metal layers. For example, a first access line can be formed on metal layer 3 (ML3), and a second access line can be formed on metal layer 4 (ML4).

The access means may comprise diodes or transistors. In an embodiment where the access device includes a transistor, a third access line (not shown) may be electrically connected to the gate terminal of the transistor, and the third access line may serve as a word line of the memory cell.

During operation, a voltage applied between the first access line and the first interlayer conductor 131 through the metal oxide layer 170 and the first barrier layer 180 will cause current to flow between the first access line and the first layer. between conductors 131. This current can cause a programmable change in the resistance of metal oxide layer 170 , which represents the data value stored in memory cell 100 . In some embodiments, the metal oxide layer 170 of the memory cell 100 may store two or more bits of data.

2-8 illustrate example steps in fabricating the memory cell shown in FIG. 1 . 2 shows in cross-section the result of forming an array of interlayer conductors extending through a dielectric layer and forming an insulating layer (e.g., 150) over the array of interlayer conductors, wherein the interlayer conductors include a first interlayer conductor (e.g., 131 ) and the second interlayer conductor (such as 132). In an embodiment, a diffusion barrier layer (eg, 140) may be formed between the insulating layer and the dielectric layer, and contact the upper surface (eg, 131T, 132T) of the array of interlayer conductors to stop at the upper surface of the array of interlayer conductors. The etching of the first opening and the second opening protects the upper surface of the interlayer conductor from oxidation. The dielectric layer may include silicon dioxide. The insulating layer will be patterned to form the top electrodes of the memory cells. The first and second interlayer conductors are connected to the first terminal and the second terminal (for example, 111 and 112 in FIG. 1 ) of the access device, wherein the first terminal and the second terminal are located on the dielectric layer relative to the insulating layer. side.

FIG. 3 illustrates etching the insulating layer to define a first opening (eg, 161 ) in the array corresponding to a first interlevel conductor (eg, 131 ), wherein the etch stops at a first upper surface (eg, 131T) of the first interlevel conductor. In embodiments where the diffusion barrier layer is formed, the etch used to define the first opening also etches through the diffusion barrier layer and stops at the upper surface of the first interlayer conductor in the first opening. In this manufacturing step, openings corresponding to second interlayer conductors in the array of interlayer conductors do not exist in the insulating layer. For example, when etching to define the first opening, a first etch mask (eg, 310) such as a photoresist mask may be used on the insulating layer, wherein the first etch mask has a corresponding mask for the second interlayer conductor area and a spacer corresponding to the first opening (eg 161 ).

FIG. 4 illustrates the formation of a metal oxide layer on the first upper surface (eg, 131T) of the first interlayer conductor in the first opening. Various deposition and oxidation techniques can be used to form metal oxide layers, such as rapid thermal oxidation (Rapid Thermal Oxidation, RTO), photo-oxidation (photo-oxidation), direct plasma oxidation, blown plasma (down-stream oxidation) oxidation , sputtering and reactive sputtering. For example, using RTO to oxide tungsten (tungsten, W) or copper (copper, Cu), the temperature can be from 200°C to 1100°C in an oxygen or oxygen/nitrogen environment, and the processing time can be from 5 seconds to 500 seconds, Typically 30 seconds to 60 seconds. In embodiments where the first interlayer conductor comprises tungsten (W), plasma oxidation can result in a gradient W _X O _Y with a tungsten-oxygen compound concentration profile that varies with distance from the surface exposed to oxidation. . For example, the metal oxide (eg 170) can have a gradient pattern comprising WO ₃ , W ₂ O ₅ , WO ₂ such that the proportion of oxygen in the metal oxide layer goes from the first opening (eg 161 ) to the first interlayer The conductor (eg 131) is lowered. The metal oxide layer may protrude from the first upper surface of the first interlayer conductor to the first opening due to volume expansion during the formation of the metal oxide layer.

In embodiments using RTO oxidation techniques, the metal oxide layer may have a thickness of about 50 nm in the range of 1 nm to 300 nm. In another embodiment using plasma oxidation techniques, the metal oxide layer may have a thickness of about 5 nm in the range of 1 nm to 50 nm.

5 shows the result of depositing a first barrier material layer (eg 181) in a first opening (eg 161), the first barrier material layer is conformal to and in contact with the metal oxide layer, and the first barrier material layer is in contact with the first opening. The sides and the bottom surface of the first interlayer conductor are conformal and in contact, wherein the metal oxide layer is located on the first upper surface of the first interlayer conductor. In one embodiment, the first barrier material layer (eg 181 ) is in the range of 1 nm to 50 nm, and may have a thickness of about 10 nm. The first barrier material layer (e.g., 181) may include one or more layers of different materials, including materials selected from the group consisting of titanium, titanium nitride, tungsten, aluminum copper alloys, tantalum nitride, copper, hafnium, tantalum, gold, platinum, One or more elements in the group consisting of silver and other CMOS compatible metals that do not contribute to the variable resistance properties of the metal oxide layer. The first barrier material layer can protect the metal oxide layer from potential damage through subsequent fabrication steps to form and then remove the etch mask on the metal oxide layer, thereby providing a better interface between the metal oxide layer and the top electrode.

The minimum width of the first opening is based on manufacturing technology. The width (eg W1 ) of the first opening (eg 161 ) may be greater than the width (eg W2 ) of the first interlayer conductor (eg 131 ). For example, if the first interlayer conductor includes tungsten (W) and has a width of about 100 nm, the first opening may have a width greater than 120 nm.

6 illustrates etching an insulating layer (eg, 150) to define a second opening (eg, 162) corresponding to a second interlevel conductor (eg, 132) in an array of interlevel conductors, wherein the etch stops at the second interlevel conductor's second opening (eg, 132). Two upper surfaces (eg 132T). This etching step to define the second opening is performed after depositing the first layer of barrier material as shown in FIG. 5 and etches through the first layer of barrier material (eg 181 ). In an embodiment where the diffusion barrier layer is formed, the etch used to define the second opening also etches through the diffusion barrier layer and stops at the top surface of the second interlayer conductor in the second opening. In one embodiment, the width of the second opening (eg, 162 ) can match the width of the first opening (eg, 161 ).

In the conventional method of forming a metal oxide layer on the second upper surface of the second interlayer conductor, the metal oxide layer needs to be removed by a process such as sputtering, which may cause contamination of the sidewall of the second opening in the insulating layer. For example, if the second interlayer conductor includes copper (Cu) and the metal oxide layer includes copper oxide (CuO _x ), copper may be sputtered onto the sidewall of the second opening when the metal oxide layer is removed.

In an embodiment of the present invention, because the metal oxide layer does not exist on the second upper surface (eg 132T) of the second interlayer conductor (eg 132) and the etch stops at the second upper surface (eg 132) of the second interlayer conductor (eg 132) Second upper surface (eg 132T), contamination of the sidewalls of the second opening in the insulating layer that may occur with existing methods can be minimized.

In the manufacturing step for defining the second opening, a second etch mask (eg, 610) such as a photoresist mask can be used on the insulating layer (eg, 150) and the first barrier material layer (eg, 181), wherein the second The etch mask has a mask area corresponding to the first opening (eg 161 ) and a spacer area corresponding to the second opening (eg 162 ). Thus, in this fabrication step, the metal oxide layer (eg 170 ) in the first opening is protected by the first barrier material layer and the masked area in the second etch mask.

FIG. 7 shows the result of stripping the second etch mask (eg, 610 ) as shown in FIG. 6 after using the second etch mask to define the second opening (eg, 162 ). During the lift-off process, the metal oxide layer (eg 170 ) in the first opening is protected by the first barrier material layer (eg 181 ).

In preparation for depositing the second layer of barrier material, plasma cleaning may be used to remove impurities, contamination, substances and natural oxides. For example, the gaseous species can include argon, and the plasma clean can etch from a depth of about 1 nm to 20 nm. During the plasma cleaning process, the metal oxide layer (eg 170 ) in the first opening is protected by the first barrier material layer (eg 181 ).

FIG. 8 shows the result of depositing a second layer of barrier material (eg, 182 ) in the first and second openings. The second barrier material layer in the first opening conforms to and contacts the first barrier material layer (eg, 181), the second barrier material layer in the second opening is in contact with the second upper surface of the second interlayer conductor (eg, 132T). conformal and in contact, and the second barrier material layer is conformal and in contact with the sides and the bottom of the second opening. In one embodiment, the second barrier material layer (eg, 182 ) is in the range of 1 nm to 50 nm, and may have a thickness of about 10 nm. The first barrier material layer (such as 181) and the second barrier material layer (such as 182) may include one or more layers of different materials, and the different materials include titanium, titanium nitride, tungsten, aluminum copper alloy, tantalum nitride, One or more elements from the group consisting of copper, hafnium, tantalum, gold, platinum, silver, and other CMOS-compatible metals that do not cause the variable resistance properties of the metal oxide layer.

Then a conductive material (such as 185 ) can be filled in the first opening and the second opening. For example, a first access line (not shown) electrically connected to the metal oxide layer can be formed by the conductive material filled in the first opening, and the first access line can be used as a bit line of the memory cell. For example, a second access line (not shown) electrically connected to the second interlayer conductor can be formed by filling the conductive material in the second opening, and the second access line can serve as the source of the memory cell Wire. The conductive material filled in the first opening (eg 161) and the second opening (eg 162) can be formed in metal layer 1 (ML1), and the first and second access lines can be formed in metal layers 2, 3, 4 or n (ML2, ML3, ML4 or ... MLn). Furthermore, the first and second access lines can be formed on different metal layers. For example, a first access line can be formed on metal layer 3 (ML3), and a second access line can be formed on metal layer 4 (ML4).

FIG. 9 shows a circuit diagram of a resistive random access memory (RRAM) array according to an embodiment. RRAM array 900 includes columns and columns of memory cells (e.g., 901, 902, 903), where each memory cell includes a first transistor (e.g., 901A), a second transistor (e.g., 901B), and a storage element (e.g., 901M) connected to a bit line. ). The first and second transistors may be N-type metal oxide semiconductor (NMOS) transistors. The memory element may include a metal oxide layer 170 as shown in FIG. 8 . The memory cell may include a first barrier material layer 181 and a second barrier material layer 182 on the metal oxide layer 170 as shown in FIG. 1 . First terminals of the first and second transistors in the memory cell are connected to one terminal of the memory element in the memory cell. The three memory cells 901, 902, and 903 shown represent a small block of a memory array, which may include thousands or millions of memory cells.

A plurality of first access lines (eg, 911 , 912 and 913 ) extend along a first direction and are in electrical communication with bit line decoders (not shown) and storage elements of the memory cells. Through the first interlayer conductor (such as 941M) arranged under the storage element (such as 901M), one end of the storage element in the memory unit is connected to a first access line among the plurality of first access lines, and the other end is connected to to the first terminals of the first and second transistors in the memory cell. A cross-sectional view of the first interlayer conductor (eg, 131 ) is shown in FIG. 8 . The plurality of first access lines may serve as bit lines.

A plurality of second access lines (eg 921 , 922 and 923 ) extend along the first direction and terminate at a source line termination circuit (not shown). A second access line (eg, 921 ) is in electrical communication with second terminals of first and second transistors (eg, 901A and 901B) in the memory cell through a second interlevel conductor (eg, 941A and 941B). A cross-sectional view of a second interlayer conductor (eg, 132 ) is shown in FIG. 8 . A plurality of second access lines may serve as source lines.

A plurality of third access lines (eg, 931 to 936 ) extend along a second direction orthogonal to the first direction. The third access line is in electrical communication with a word line decoder (not shown) and may function as a word line. The gate terminals of the first and second transistors (eg, 901A and 901B) in the memory cell are each connected to the third access line. The bit line decoder and the word line decoder may include complementary metal oxide semiconductor (CMOS) circuits.

FIG. 10 shows a simplified layout of a memory cell according to the embodiment shown in FIG. 9 . Like elements in FIG. 10 are denoted by like reference numerals as in FIG. 9 . The layout of memory cells can be repeated vertically and horizontally. For simplicity, the insulating material, for example, the insulating material between the first, second and third access lines is not shown.

This design diagram shows that the first access lines 911 and 912 are used as bit lines (Bit Lines, BL), the second access lines 921 and 922 are used as source lines (Source Lines, SL), and the third access lines 931, 932 and 933 as word lines (Word Lines, WL). In one embodiment, the first access line and the second access line may be configured in the metal layer 1 . The first, second and third access lines are connected to memory cells (eg, 901 and 904 ), as described in FIG. 9 . The memory cell includes a memory element (such as 901M), and the memory element may include a metal oxide layer 170 as shown in FIG. 8 . The memory cell may include a first barrier material layer 181 and a second barrier material layer 182 on the metal oxide layer as shown in FIG. 1 .

FIG. 11 shows a circuit diagram of a resistive random access memory (Resistive Random Access Memory, RRAM) array according to the second embodiment. RRAM array 1100 includes columns and columns of memory cells (eg, 1101, 1102, and 1103), where each memory cell includes a first transistor (eg, 1101A), a second transistor (eg, 1101B), and a memory element (eg, 1101M). The first and second transistors may be N-type metal oxide semiconductor (NMOS) transistors. The memory cell may include a first barrier material layer 181 and a second barrier material layer 182 on the memory element as shown in FIG. 1 . The memory element may include a metal oxide layer 170 as shown in FIG. 8 . First terminals of the first and second transistors in the memory cell are connected to one terminal of the memory element in the memory cell, and second terminals of the first and second transistors in the memory cell are connected to a source line (eg, 1121 ). The three memory cells 1101, 1102, and 1103 shown represent a small block of a memory array, which may include thousands or millions of memory cells.

A plurality of first access lines (eg, 1111, 1112, and 1113) extend along a first direction and are in electrical communication with a bit line decoder (not shown). The plurality of first access lines may serve as bit lines. A plurality of second access lines (eg, 1121 , 1122 and 1123 ) extend along a second direction orthogonal to the first direction and terminate at source line termination circuits (not shown). A plurality of second access lines may serve as source lines.

The memory cell includes a first interlayer conductor (such as 1141M) disposed under the memory element (such as 1101M), and the first interlayer conductor (such as 1141M) connects the memory element (such as 1101M) to the first and second transistors (such as 1101A and 1101B), and a second interlayer conductor (eg, 1141A and 1141B) connects the second terminals of the first and second transistors to the source line (eg, 1121). The cross-sectional view of the first interlayer conductor (such as 131 ) and the second interlayer conductor (such as 132 ) is shown in FIG. 8 .

A plurality of third access lines (eg, 1131 to 1136 ) extend along the first direction. The third access line is in electrical communication with a word line decoder (not shown) and may function as a word line. The gate terminals of the first and second transistors (eg, 1101A and 1101B) in the memory cell are each connected to a third access line. The bit line decoder and the word line decoder may include complementary metal oxide semiconductor (CMOS) circuits.

FIG. 12 shows a simplified layout of a memory cell according to the second embodiment shown in FIG. 11 . Like elements in FIG. 12 are denoted by like reference numerals as in FIG. 11 . The layout of memory cells can be repeated vertically and horizontally. For simplicity, the insulating material, for example, the insulating material between the first, second and third access lines is not shown.

This design diagram shows that the first access line (such as 1111) is used as the bit line (Bit Lines, BL), the second access line (such as 1121, 1122 and 1123) is used as the source line (Source Lines, SL), and the third The access lines (such as 1131, 1132 and 1133) serve as word lines (WL). In one embodiment, the second access line can be arranged in the metal layer 1 , and the first access line can be arranged in the metal layer 2 on the metal layer 1 . The first, second and third access lines are connected to memory cells (eg, 1101, 1102 and 1103), as depicted in FIG. 11 . The memory cell includes a memory element (eg, 1101M), which may include a metal oxide layer 170 as shown in FIG. 8 . The memory cell may include a first barrier material layer 181 and a second barrier material layer 182 on the metal oxide layer as shown in FIG. 1 .

FIG. 13 shows a circuit diagram of a resistive random access memory (Resistive Random Access Memory, RRAM) array according to a third embodiment. RRAM array 1300 includes columns and columns of memory cells (eg, 1301, 1302, 1303, 1304, 1305, 1306, 1307, and 1308), where each memory cell includes a transistor (eg, 1301A) and a memory element (eg, 1301M). The transistor may be an N-type metal oxide semiconductor (NMOS) transistor. The memory element may include a metal oxide layer 170 as shown in FIG. 8 . The memory cell may include a first barrier material layer 181 and a second barrier material layer 182 on the metal oxide layer 170 as shown in FIG. 1 . A first terminal of a transistor in the memory cell is connected to one terminal of a storage element in the memory cell. The memory cells shown represent a small block of a memory array, which may include thousands or millions of memory cells.

A plurality of first access lines (eg, 1311, 1312, 1313, and 1314) extend along a first direction and are in electrical communication with a bit line decoder (not shown), the plurality of first access lines are connected to the storage element The second end of the second end is opposite to the end connected to the first terminal of the transistor in the memory cell. The plurality of first access lines may serve as bit lines. The memory cell may include a first interlayer conductor (eg, 1341M) disposed under the memory element (eg, 1301M), the first interlayer conductor (eg, 1341M) connecting the memory element to a first terminal of the transistor (eg, 1301A). A cross-sectional view of the first interlayer conductor (eg, 131 ) is shown in FIG. 8 .

A plurality of second access lines (eg, 1321, 1322, 1323, and 1324) extend along a second direction orthogonal to the first direction and terminate at source line termination circuits (not shown). A plurality of second access lines may serve as source lines. The memory cell may include a second interlayer conductor (eg, 1341A) connecting the second terminal of the transistor to a source line (eg, 1321). A cross-sectional view of a second interlayer conductor (eg, 132 ) is shown in FIG. 8 .

A plurality of third access lines (eg, 1331 to 1334 ) extend along the first direction. The third access line is in electrical communication with a word line decoder (not shown) and may function as a word line. The gate terminals of the transistors (eg, 1301A) in the memory cells are each connected to a third access line. The bit line decoder and the word line decoder may include complementary metal oxide semiconductor (CMOS) circuits.

FIG. 14 shows a simplified layout of a memory cell according to the third embodiment shown in FIG. 13 . Like elements in FIG. 14 are denoted by like reference numerals as in FIG. 13 . The layout of memory cells can be repeated vertically and horizontally. For simplicity, the insulating material, for example, the insulating material between the first, second and third access lines is not shown.

This design diagram shows that the first access lines 1311 and 1312 are used as bit lines (Bit Lines, BL), the second access lines 1321, 1322 and 1323 are used as source lines (Source Lines, SL), and the third access line 1331 and 1132 as word lines (Word Lines, WL). In one embodiment, the second access line can be disposed in the metal layer 1 , and the first access line can be disposed in the metal layer 2 on the metal layer 1 . The first, second and third access lines are connected to memory cells (eg, 1301 to 1303 and 1305 to 1306 ), as described in FIG. 13 . The memory cell includes a memory element (eg, 1301M), which may include a metal oxide layer 170 as shown in FIG. 8 . The memory cell may include a first barrier material layer 181 and a second barrier material layer 182 on the metal oxide layer as shown in FIG. 1 .

FIG. 15 shows a circuit diagram of an RRAM array according to an embodiment using diodes as access devices. Memory array 1500 includes a matrix of memory cells, a plurality of word lines (eg, 1531, 1532, 1533, and 1534), and a plurality of bit lines (eg, 1511, 1512, 1513, and 1514). Each memory cell (eg, 1544) in the example memory array 1500 includes an access diode (eg, 1544D) and a storage element (eg, 1544M) in sequence between a corresponding word line (eg, 1534) and a corresponding bit line (eg, 1511). . Each storage element is electrically coupled to a corresponding access diode.

The memory cells in the memory array 1500 may include a first barrier material layer 181 and a second barrier material layer 182 on the memory element as shown in FIG. 1 . The memory element in the memory cell includes a metal oxide layer 170 in the memory cell as shown in FIG. 8 .

A plurality of bit lines including bit lines 1511, 1512, 1513 and 1514 extend in parallel along the first direction. The bit lines are in electrical communication with the bit line decoder 1510 . The memory element may be connected between the anode or cathode of the diode and the bit line. For example, memory element 1544M is connected between the cathode of diode 1544D and bit line 1511 . A plurality of word lines including word lines 1531, 1532, 1533 and 1534 extend in parallel along the second direction. The word lines 1531 , 1532 , 1533 and 1534 are in electrical communication with the word line decoder 1530 . The anode or cathode of the diode can be connected to the word line. For example, the anode of diode 1544D is connected to word line 1534 . The bit line decoder and the word line decoder may include complementary metal oxide semiconductor (CMOS) circuits. It should be noted that the 16 memory cells in Figure 15 are shown as such for ease of discussion, however in practice a memory array may include thousands or millions of such memory cells.

FIG. 16 shows a simplified layout of a memory cell according to the embodiment shown in FIG. 15 using diodes as access devices. Like elements in FIG. 16 are denoted by like reference numerals as in FIG. 15 . The layout of memory cells can be repeated vertically and horizontally. For simplicity, the insulating material, for example, the insulating material between the first, second and third access lines is not shown.

This design diagram shows the first access lines 1511, 1512, 1513 and 1514 as bit lines (BitLines, BL), and the second access lines 1531, 1532, 1533 and 1534 as word lines (Word Lines, WL). The second access line in the memory cell may include an active area for a diode (eg, 1544D), and the second access circuit may be connected to contacts (eg, 1551, 1552, 1553, and 1554) for wordline pickup. In one embodiment, bit lines may be disposed in the metal layer 1, and the bit lines located on the word lines may include polysilicon. The first and second access lines are connected to memory cells (eg, 1544 ), as depicted in FIG. 15 . The memory cells include memory elements (eg, 1541M, 1542M, 1543M, and 1544M), and the memory elements may include a metal oxide layer 170 as shown in FIG. 8 . The memory cell may include a first barrier material layer 181 and a second barrier material layer 182 on the memory element as shown in FIG. 1 .

Figure 17 shows a simplified flowchart of an embodiment of a method for fabricating a memory device. At step 1701, an insulating layer is formed over the array of interlayer conductors. A diffusion barrier layer may be formed between the upper surface of the array of interlayer conductors and the insulating layer, the diffusion barrier layer being in contact with the upper surface. In step 1702, the insulating layer is etched to define a first opening corresponding to a first interlevel conductor in the array, wherein the etch stops at a first upper surface of the first interlevel conductor. When etching to define the first opening, a first etch mask (eg, 310) can be used on the insulating layer, wherein the first etch mask has a mask area corresponding to the second interlayer conductor and a corresponding first opening (eg, 161 ) spacer.

In step 1703, a metal oxide layer is formed on the first upper surface of the first interlayer conductor in the first opening. The metal oxide layer can be characterized as having a programmable resistance. At step 1704, a first layer of barrier material conformal to and in contact with the metal oxide layer and the surface of the first opening is deposited, the metal oxide layer being on the first interlayer conductor. The first barrier material layer can protect the metal oxide layer from potential damage through subsequent fabrication steps to form and then remove the etch mask on the metal oxide layer, thereby providing a better interface between the metal oxide layer and the top electrode.

In step 1705, the insulating layer is etched after depositing the first barrier material layer to define a second opening in the array corresponding to the second interlayer conductor, wherein the etching stops at the second upper surface of the second interlayer conductor. When etching to define the second opening, a second etching mask can be used on the insulating layer, wherein the second etching mask has a mask area corresponding to the first opening and a spacer area corresponding to the second opening. At step 1706, a second layer of barrier material is deposited conformal to and in contact with the first layer of barrier material in the first opening. For example, a second barrier material layer conformal to and in contact with the second upper surface of the second interlayer conductor in the second opening and the surface of the second opening may also be deposited in the same step.

At step 1707, the first opening is filled with a conductive material. For example, the second opening can also be filled with a conductive material in the same step, wherein the metal oxide layer does not exist between the second upper surface and the second barrier material layer. A width of the first opening may be greater than a width of the first interlayer conductor.

The first and second interlayer conductors may be connected to first and second terminals of the access device, respectively. The access means may comprise diodes or transistors. An array of access devices may be formed coupled to an array of interlevel conductors including first and second interlevel conductors.

It will be understood that the memory array is not limited to the array structure shown in FIG. 12 , and additional array structures may be used along with the memory cells including the above-mentioned top electrode layer. Furthermore, in some embodiments, instead of MOS transistors, bipolar transistors or diodes may be used as access devices.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the present invention.

Claims (22)

1. A method of manufacturing a memory, comprising: forming an insulating layer over an array of interlayer conductors; etching the insulating layer to define a first opening corresponding to a first interlayer conductor in the array, the etching stopping at a first upper surface of the first interlayer conductor; forming a metal oxide layer on the first upper surface of the first interlayer conductor in the first opening; depositing a first barrier material layer conformal to and in contact with the metal oxide layer on the first interlayer conductor, and the first barrier material layer conformal to surfaces of the first opening and contacting, wherein the width of the first opening is greater than the width of the first interlayer conductor; The insulating layer is etched to define a second opening after depositing the first barrier material layer, the second opening corresponds to a second interlayer conductor in the array, and the etching stops at a second interlayer conductor of the second interlayer conductor. upper surface; depositing a second layer of barrier material conformal to and in contact with the first layer of barrier material in the first opening; and filling the first opening with a conductive material; Wherein the first interlayer conductor and the second interlayer conductor are respectively connected to a first terminal and a second terminal of an access device. 2. The method of claim 1, further comprising: A diffusion barrier layer is formed between upper surfaces of the array of interlayer conductors and the insulating layer, the diffusion barrier layer contacts the upper surfaces. 3. The method of claim 1, wherein the step of etching to define the first opening comprises: A first etching mask is used on the insulating layer, the first etching mask has a mask area corresponding to the second opening and a spacer area corresponding to the first opening. 4. The method of claim 1, wherein the step of etching to define the second opening comprises: A second etching mask is used on the insulating layer, the second etching mask has a mask area corresponding to the first opening and a spacer area corresponding to the second opening. 5. The method according to claim 1, wherein the step of depositing the second barrier material layer comprises: depositing the second barrier material layer, the second barrier material layer conforming to and in contact with the second upper surface of the second interlayer conductor in the second opening, and the second barrier material layer being in contact with the second opening Multiple surfaces of are conformal and in contact; and The second opening is filled with the conductive material. 6. The method of claim 1, comprising: forming a first access line electrically connected to the metal oxide layer; and A second access line is formed, and the second access line is electrically connected to the second interlayer conductor. 7. The method of claim 1, comprising: An array of access devices is formed, the array is coupled to the array of said interlevel conductors, and the array of said access devices includes the access device mentioned for the first time. 8. The method of claim 1, wherein the first-mentioned access device comprises a diode. 9. The method of claim 1, wherein the access device mentioned for the first time comprises a transistor comprising: A third access line is formed, and the third access line is electrically connected to a gate terminal of the transistor. 10. The method of claim 1, wherein the metal oxide layer is characterized by a programmable resistance. 11. The method of claim 1, wherein the first interlayer conductor consists essentially of a metal, and the metal oxide layer comprises an oxide of the metal. 12. The method of claim 1, wherein the first interlayer conductor consists essentially of a transition metal, and the metal oxide layer comprises an oxide of the transition metal. 13. A memory comprising: A patterned insulating layer is located on an array of a plurality of interlayer conductors, the patterned insulating layer includes a first opening and a second opening, the first opening corresponds to a first interlayer conductor in the array, the The second opening corresponds to a second interlayer conductor in the array; a metal oxide layer on a first upper surface of the first interlayer conductor; a first barrier layer conformal to and in contact with the metal oxide layer on the first interlayer conductor, and the first barrier layer conformal to and in contact with surfaces of the first opening, wherein the first opening having a width greater than the width of the first interlayer conductor; a second barrier layer over the second opening, wherein the thickness of the second barrier layer is less than the thickness of the first barrier layer; and a conductive material filled in the first opening; Wherein the first interlayer conductor and the second interlayer conductor are respectively connected to a first terminal and a second terminal of an access device. 14. The memory of claim 13, further comprising: A diffusion barrier layer is located between the upper surfaces of the array of interlayer conductors and the patterned insulating layer, and the diffusion barrier layer contacts the upper surfaces. 15. The memory of claim 13, further comprising: the second barrier layer conforms to and contacts a second upper surface of the second interlayer conductor in the second opening, and the second barrier layer conforms to and contacts surfaces of the second opening; as well as The conductive material fills the second opening. 16. The memory of claim 13, further comprising: a first access line electrically connected to the metal oxide layer; and A second access line is electrically connected to the second interlayer conductor. 17. The memory of claim 13, further comprising: An array of access devices is coupled to the array of interlevel conductors, and the array of access devices includes the first-mentioned access device. 18. The memory of claim 13, wherein the first-mentioned access means comprises a diode. 19. The memory of claim 13, wherein the access device mentioned for the first time comprises a transistor, and the memory comprises: A third access line is electrically connected to a gate terminal of the transistor. 20. The memory of claim 13, wherein the metal oxide layer is characterized by a programmable resistance. 21. The memory device of claim 13, wherein the first interlayer conductor consists essentially of a metal, and the metal oxide layer comprises an oxide of the metal. 22. The memory device of claim 13, wherein the first interlayer conductor consists essentially of a transition metal, and the metal oxide layer comprises an oxide of the transition metal.