TW201606977A - Method of manufacturing electronic package module and structure of electronic package module - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000465 moulding Methods 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 7
- 238000001746 injection moulding Methods 0.000 claims description 4
- 238000007789 sealing Methods 0.000 claims description 4
- 238000005507 spraying Methods 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 3
- 238000001721 transfer moulding Methods 0.000 claims description 3
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 claims description 2
- 239000003292 glue Substances 0.000 claims description 2
- 238000012545 processing Methods 0.000 claims description 2
- 229920002379 silicone rubber Polymers 0.000 claims description 2
- 239000004945 silicone rubber Substances 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 1
- 239000012778 molding material Substances 0.000 description 4
- 239000007769 metal material Substances 0.000 description 3
- 229920001296 polysiloxane Polymers 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 229920006336 epoxy molding compound Polymers 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000009415 formwork Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 235000013824 polyphenols Nutrition 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
本發明係關於一種電子封裝模組之製造方法及其結構,特別係指一種利用兩階段模封以及利用兩階段屏蔽的電子封裝模組製造方法及其結構。 The present invention relates to a method and a structure for manufacturing an electronic package module, and more particularly to a method and a structure for manufacturing an electronic package module using two-stage mold sealing and using two-stage shielding.
目前電子封裝模組通常包括一電路板與多個裝設在電路板上的電子元件(electronic component)。這些電子元件例如是晶片封裝體(chip package)或被動元件(passive component)等。此外,大多數的電子封裝模組通常更包括模封塊(molding compound),其用以包覆(encapsulating)上述電子元件,以保護電子元件。 At present, an electronic package module generally includes a circuit board and a plurality of electronic components mounted on the circuit board. These electronic components are, for example, a chip package or a passive component. In addition, most electronic packaging modules generally include a molding compound for encapsulating the above electronic components to protect the electronic components.
電子元件日益複雜,而使用者對於加快處理速度(processing speed)與縮小元件尺寸的需求也日益增加。現今的電子產品講求輕薄短小,使得電子元件與線路的分布密度過高,這增加了一些問題,例如電磁干擾(Electromagnetic interference,EMI)。尤其,如何在電子元件與線路分布密集的電路板上形成多區塊的電磁屏蔽結構,亦即,形成多個電磁屏蔽隔間,成為現有通訊產品的需求。 Electronic components are becoming more complex, and users are increasingly demanding faster processing speeds and smaller component sizes. Today's electronic products are light and short, which makes the distribution density of electronic components and circuits too high, which increases some problems, such as electromagnetic interference (EMI). In particular, how to form a multi-block electromagnetic shielding structure on a circuit board with dense electronic components and line distribution, that is, to form a plurality of electromagnetic shielding compartments, becomes a requirement of existing communication products.
一種習知技術是先在電路板上大面積地形成模封塊,然後在模封塊上挖槽,再於槽內填入金屬材料以形成隔間。然而,此等製程容易因挖槽的深寬比造成填入槽內的金屬材料無法均勻地分布於槽內,例如,填入槽內的金屬材料無法接觸挖槽底部的線路基板,或者具有孔隙、空氣間隔等。因此,以此所形成的金屬 隔間容易有導電不良或導電不均的問題,並且,金屬隔間的尺寸受限於挖槽的深寬比,難以縮小。 One conventional technique is to first form a mold block on a large area on a circuit board, then dig a groove in the mold block, and then fill the groove with a metal material to form a compartment. However, these processes are prone to the fact that the metal material filled in the groove cannot be uniformly distributed in the groove due to the aspect ratio of the groove. For example, the metal material filled in the groove cannot contact the circuit substrate at the bottom of the groove, or has a pore. , air separation, etc. Therefore, the metal formed by this The compartment is prone to problems of poor conduction or uneven conductivity, and the size of the metal compartment is limited by the aspect ratio of the trench and is difficult to reduce.
此外,美國專利公開文件US2008/0055878號,揭露了一種具有電磁屏蔽結構的電子元件,其不具有金屬隔間的屏蔽結構,且該電子元件的厚度受限於模封材料的厚度而難以降低。 In addition, U.S. Patent Publication No. US 2008/0055878 discloses an electronic component having an electromagnetic shielding structure which does not have a shielding structure of a metal compartment, and the thickness of the electronic component is limited by the thickness of the molding material and is difficult to reduce.
本發明提供一種電子封裝模組之製造方法,能兩階段模封以及兩階段鍍覆以形成屏蔽,而無需受限於屏蔽層的深寬比,可完整防護電子元件間的電磁干擾。 The invention provides a method for manufacturing an electronic package module, which can form a shield in two stages and two-stage plating to form a shield without completely limiting the aspect ratio of the shield layer, thereby completely protecting electromagnetic interference between the electronic components.
一種電子封裝模組之製造方法,包括以下步驟:提供一線路基板,線路基板具有組裝平面與至少一接地墊,多個電子元件設置於組裝平面上;形成至少一第一模封體包覆部份電子元件;形成第一屏蔽層,覆蓋第一模封體並接觸該線路基板;形成第二模封體覆蓋第一模封體、電子元件、組裝平面;移除部分第一模封體以及部分第二模封體,以暴露部分第一屏蔽層;以及形成第二屏蔽層,覆蓋該第一模封體、該第二模封體,並電性連接該第一屏蔽層。 A method for manufacturing an electronic package module, comprising the steps of: providing a circuit substrate having an assembly plane and at least one ground pad, wherein the plurality of electronic components are disposed on the assembly plane; and forming at least one first cavity covering portion a first shielding layer covering the first molding body and contacting the circuit substrate; forming a second molding body covering the first molding body, the electronic component, assembling the plane; removing part of the first molding body and Part of the second molding body to expose a portion of the first shielding layer; and forming a second shielding layer covering the first molding body, the second molding body, and electrically connecting the first shielding layer.
一種電子封裝模組結構,包括:線路基板,該線路基板具有組裝平面與接地墊;電子元件設置於組裝平面上;第一模封體以及一第二模封體分別包覆一部份電子元件;第一屏蔽層順形覆蓋第一模封體並電性連接接地墊,而第一模封體與第二模封體以第一屏蔽層相隔離;以及第二屏蔽層,覆蓋第一模封體並電性連接第一屏蔽層;其中,第一屏蔽層在形成該第二模封體之前先製作完成。 An electronic package module structure includes: a circuit substrate having an assembly plane and a ground pad; the electronic component is disposed on the assembly plane; and the first mold body and the second mold body respectively cover a part of the electronic component The first shielding layer conforms to the first molding body and electrically connects to the grounding pad, and the first molding body and the second molding body are separated by the first shielding layer; and the second shielding layer covers the first mode The first shielding layer is sealed and electrically connected; wherein the first shielding layer is completed before forming the second molding body.
為了能更進一步瞭解本發明所採取之技術、方法及功效,請參閱以下有關本發明之詳細說明、圖式,相信本發明的特徵與特點,當可由此得以深入且具體之瞭解,然而所附圖式與附件僅提供參考與說明用,並非用來對本發明加以限制者。 For a better understanding of the techniques, methods and efficacies of the present invention, reference should be made to the detailed description and drawings of the invention, The drawings and the annexed drawings are for the purpose of illustration and description only
1‧‧‧電子封裝模組結構 1‧‧‧Electronic package module structure
11‧‧‧線路基板 11‧‧‧Line substrate
111‧‧‧組裝平面 111‧‧‧ Assembly plane
12‧‧‧接地墊 12‧‧‧ Grounding mat
131‧‧‧第一電子元件 131‧‧‧First electronic components
132、132’‧‧‧第二電子元件 132, 132'‧‧‧ second electronic components
141’‧‧‧第一初始模封體 141'‧‧‧First initial molded body
141‧‧‧第一模封體 141‧‧‧First molded body
151‧‧‧第一屏蔽層 151‧‧‧First shield
161’‧‧‧第二初始模封體 161'‧‧‧Second initial molded body
161‧‧‧第二模封體 161‧‧‧Second formwork
171‧‧‧第二屏蔽層 171‧‧‧Second shield
181‧‧‧犧牲層 181‧‧‧ sacrificial layer
191‧‧‧底部填充膠 191‧‧‧ underfill
2‧‧‧遮罩 2‧‧‧ mask
S1~S6‧‧‧步驟 S1~S6‧‧‧Steps
圖1是本發明一實施例之電子封裝模組結構的剖面示意圖。 1 is a cross-sectional view showing the structure of an electronic package module according to an embodiment of the present invention.
圖2至圖8顯示圖1中電子封裝模組結構在製造過程中的剖面示意圖。 2 to 8 are schematic cross-sectional views showing the structure of the electronic package module of FIG. 1 during the manufacturing process.
圖9是本發明一實施例之電子封裝模組之製造方法之流程圖。 9 is a flow chart of a method of manufacturing an electronic package module according to an embodiment of the present invention.
本文中可能使用術語第一、第二、第三等來描述各種元件,但此等元件不應受此等術語限制。此等術語乃用以區分一元件與另一元件。因此,下文論述之第一元件可稱為第二元件而不偏離本發明概念之教示。 The terms first, second, third, etc. may be used herein to describe various elements, but such elements are not limited by the terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the inventive concept.
請參考圖1,圖1是本發明一實施例之電子封裝模組結構的剖面示意圖。本發明實施例提供了一種電子封裝模組結構1,電子封裝模組結構1包括線路基板11、多個電子元件(例如第一電子元件131、第二電子元件132、132’)、第一屏蔽層151、第二屏蔽層171、第一模封體141以及相鄰於第一模封體141的第二模封體161。線路基板11具有組裝平面111,組裝平面111包括第一區域(圖未繪示)以及第二區域(圖未繪示)。線路基板11還包括多個接地墊12,其中部份接地墊12裸露於線路基板11的組裝平面111,部份接地墊12可依設計需求選擇性設置並裸露於線路基板11的側邊。 Please refer to FIG. 1. FIG. 1 is a cross-sectional view showing the structure of an electronic package module according to an embodiment of the present invention. The embodiment of the present invention provides an electronic package module structure 1. The electronic package module structure 1 includes a circuit substrate 11, a plurality of electronic components (for example, the first electronic component 131, the second electronic component 132, 132'), and a first shield. The layer 151, the second shield layer 171, the first mold body 141, and the second mold body 161 adjacent to the first mold body 141. The circuit substrate 11 has an assembly plane 111. The assembly plane 111 includes a first area (not shown) and a second area (not shown). The circuit substrate 11 further includes a plurality of ground pads 12, wherein a portion of the ground pads 12 are exposed on the assembly plane 111 of the circuit substrate 11, and some of the ground pads 12 are selectively disposed and exposed on the side of the circuit substrate 11 according to design requirements.
第一電子元件131是位於組裝平面111的第一區域,第二電子元件132、132’位於組裝平面111的第二區域。第一模封體141是位於第一區域並包覆第一電子元件131;第二模封體161是位於模封體141之外的組裝平面111上。第一屏蔽層151電性連接線路基板11的接地墊12,而第一模封體141與第二模封體161是以第一屏蔽層151相隔離。第二屏蔽層171全面性地形成於線路基板11的上方,以覆蓋第一模封體141、第二模封體161、組裝平面111以及部份第二電子元件,並直接接觸於第一屏蔽層 151。第二屏蔽層171還可直接電性連接至接地墊12,甚至包含裸露於線路基板11側邊的接地墊12。在其它實施例中,第一電子元件也可能自第一模封體141裸露出來而直接接觸第二屏蔽層171。 The first electronic component 131 is in a first region of the assembly plane 111 and the second electronic component 132, 132' is located in a second region of the assembly plane 111. The first molding body 141 is located in the first region and covers the first electronic component 131; the second molding body 161 is located on the assembly plane 111 outside the molding body 141. The first shielding layer 151 is electrically connected to the ground pad 12 of the circuit substrate 11 , and the first molding body 141 and the second molding body 161 are separated by the first shielding layer 151 . The second shielding layer 171 is formed over the circuit substrate 11 to cover the first molding body 141, the second molding body 161, the assembly plane 111, and a portion of the second electronic component, and directly contacts the first shielding layer. Floor 151. The second shielding layer 171 can also be directly electrically connected to the ground pad 12, and even includes the ground pad 12 exposed on the side of the circuit substrate 11. In other embodiments, the first electronic component may also be exposed from the first molding body 141 to directly contact the second shielding layer 171.
上述以對應形成第一模封體所在區域為第一區域、對應形成第二模封體所在區域為第二區域,以方便說明與理解,並非用以限定第一區域以及第二區域的解釋,例如第一模封體也可以是積體電路封裝(IC package)的封裝材。因此若第二電子元件132’為積體電路封裝(IC package)的電子元件,或者是半導體晶片堆疊並以覆晶接合的方式裝設於線路基板11上,未被第二模封體所覆蓋,則其所在區域也可稱為第一區域。 The area corresponding to the area where the first molding body is formed is the first area, and the area corresponding to the second molding body is the second area, which is convenient for explanation and understanding, and is not intended to limit the interpretation of the first area and the second area. For example, the first mold body may also be a package material of an IC package. Therefore, if the second electronic component 132' is an electronic component of an IC package, or a semiconductor wafer is stacked and mounted on the circuit substrate 11 by flip-chip bonding, it is not covered by the second molding body. , the area in which it is located may also be referred to as the first area.
以下將透過實施例來解釋本發明之一種電子封裝模組之製造方法。請參考圖2至圖8,圖2至圖8顯示圖1中電子封裝模組結構在製造過程中的剖面示意圖。 Hereinafter, a method of manufacturing an electronic package module of the present invention will be explained by way of embodiments. Please refer to FIG. 2 to FIG. 8 . FIG. 2 to FIG. 8 are schematic cross-sectional views showing the structure of the electronic package module of FIG. 1 during the manufacturing process.
如圖1所示,首先,提供一線路基板11,線路基板11具有一組裝平面111(例如線路基板11的上表面)。組裝平面111包括第一區域以及第二區域(圖未繪示)。 As shown in FIG. 1, first, a circuit substrate 11 having an assembly plane 111 (for example, an upper surface of the wiring substrate 11) is provided. The assembly plane 111 includes a first area and a second area (not shown).
線路基板11並具有多個預先設置的接地墊12與線路層(未繪示)。接地墊12是導電材料所製成,以電性連接至導電線路(未繪示)或是接地面(未繪示)。其中,接地墊12與線路層皆位於組裝平面111上或埋入基板,接地墊12進一步裸露於線路基板11的側邊。 The circuit substrate 11 has a plurality of pre-set ground pads 12 and circuit layers (not shown). The ground pad 12 is made of a conductive material and is electrically connected to a conductive line (not shown) or a ground plane (not shown). The ground pad 12 and the circuit layer are both located on the assembly plane 111 or buried in the substrate, and the ground pad 12 is further exposed on the side of the circuit substrate 11.
接著,將電子元件裝設於線路基板11上,其組裝方式可利用表面粘著技術(Surface Mount Technology,SMT)進行,但不以此為限。 Next, the electronic component is mounted on the circuit board 11, and the assembly method can be performed by Surface Mount Technology (SMT), but not limited thereto.
請參圖3,接著,於第一區域提供第一初始模封體141’,以包覆第一電子元件131。第一初始模封體141’例如是以模封材料(molding material)對第一區域進行一封膠製程所形成,且第 一初始模封體141’是包覆第一電子元件131以及第一電子元件131周圍的一部分組裝平面111。需要注意的是,本實施例中,在所述提供第一初始模封體141’的步驟完成之後,鄰近第一電子元件131的至少一個接地墊12有至少一部分是裸露於組裝平面111,而沒有被第一初始模封體141’所覆蓋。本案封膠製程例如採用壓注成型、模穴注膠成形(mold chase)、覆蓋成形製程(over-molding process)、轉移成形方式(transfer molding)、頂模塑封製程(top-gate molding)、點膠機(dispenser)。而所用於形成模封體的材質例如為環氧樹脂、塑封材(molding compound)、環氧模封化合物(Epoxy Molding Compound,EMC)、聚醯亞胺(Polyimide,PI)、酚醛樹脂(Phenolics)、矽膠或是矽樹脂(Silicones)等。 Referring to Fig. 3, next, a first initial mold body 141' is provided in the first region to cover the first electronic component 131. The first initial mold body 141' is formed, for example, by a molding process on a first region by a molding material, and An initial molding body 141' is a portion of the assembly plane 111 surrounding the first electronic component 131 and the first electronic component 131. It should be noted that, in this embodiment, after the step of providing the first initial molded body 141 ′ is completed, at least a portion of the at least one ground pad 12 adjacent to the first electronic component 131 is exposed to the assembly plane 111 , and Not covered by the first initial molded body 141'. The sealing process in this case is, for example, injection molding, mold chase, over-molding process, transfer molding, top-gate molding, and point. Dispenser. The materials used to form the mold body are, for example, epoxy resin, molding compound, Epoxy Molding Compound (EMC), polyimide (PI), and phenolic resin (Phenolics). , silicone or silicone resin (Silicones).
此外,於上述封膠製程的步驟中,可同時提供底部填充膠191包覆第二電子元件132’的外露導電接腳,以保護這些導電接腳並使這些導電接腳與後續形成的第一屏蔽層151(圖5)電性隔絕。 In addition, in the step of the above-mentioned encapsulation process, the underfill 191 may be simultaneously provided to cover the exposed conductive pins of the second electronic component 132' to protect the conductive pins and to form the first and subsequent conductive pins. The shield layer 151 (Fig. 5) is electrically isolated.
接著,如圖4所示,提供犧牲層181包覆部份第二電子元件132。舉例而言,可透過具有圖案設計的遮罩2對線路基板11進行犧牲層181塗佈製程,依遮罩2的圖案提供犧牲層181包覆部份第二電子元件132以及部分組裝平面111。犧牲層181是用以移除後續製程形成於犧牲層181上方的物質,並保護犧牲層181所包覆的部份第二電子元件132。犧牲層181的材料可1包含壓克力(acrylic)膠或矽膠。於另一實施例中,犧牲層181的材料可包含感光固化性樹酯或熱固化性樹酯組成的油墨,例如液態感光型油墨,且可藉由使用有機溶劑被簡單移除,但不以此為限。 Next, as shown in FIG. 4, a sacrificial layer 181 is provided to cover a portion of the second electronic component 132. For example, the sacrificial layer 181 coating process can be performed on the circuit substrate 11 through the mask 2 having a pattern design, and the sacrificial layer 181 is provided to cover a portion of the second electronic component 132 and the partial assembly plane 111 according to the pattern of the mask 2. The sacrificial layer 181 is for removing a substance formed on the sacrificial layer 181 by a subsequent process, and protecting a portion of the second electronic component 132 covered by the sacrificial layer 181. The material of the sacrificial layer 181 may include an acrylic glue or silicone. In another embodiment, the material of the sacrificial layer 181 may comprise an ink composed of a photosensitive curable resin or a thermosetting resin, such as a liquid photosensitive ink, and may be simply removed by using an organic solvent, but not This is limited.
然後,形成第一屏蔽層151。第一屏蔽層151可作為不同電子元件間在垂直方向上的金屬屏蔽,意即隔絕相鄰電子元件間的電磁干擾。如圖5所示,整面且順形地(conformal)形成第一屏蔽層151,以覆蓋第一初始模封體141’、犧牲層181、第二電子元 件132’、底部填充膠191,以及部分組裝平面111,並接觸線路基板11的接地墊12以電性連接至接地墊12。形成第一屏蔽層151的方法例如噴鍍(spray coating)、電鍍(electroplating)、無電鍍(electrolessplating)、蒸鍍或濺鍍(sputtering)等。本技術領域具有通常知識者可知,順形(conformal)是指其所形成之物與其所覆蓋者的外輪廓具有大致相同的形狀,以圖5實施例而言,即第一屏蔽層151的外輪廓與第一初始模封體141’、犧牲層181、第二電子元件132’的外輪廓相同。 Then, a first shield layer 151 is formed. The first shielding layer 151 can serve as a metal shield in the vertical direction between different electronic components, that is, to isolate electromagnetic interference between adjacent electronic components. As shown in FIG. 5, the first shielding layer 151 is formed integrally and conformally to cover the first initial molding body 141', the sacrificial layer 181, and the second electron element. The piece 132', the underfill 191, and the partially assembled plane 111 are in contact with the ground pad 12 of the circuit substrate 11 to be electrically connected to the ground pad 12. A method of forming the first shield layer 151 is, for example, spray coating, electroplating, electroless plating, evaporation, or sputtering. It is known to those skilled in the art that conformal means that the object formed has substantially the same shape as the outer contour of the person it covers, in the embodiment of Fig. 5, that is, outside the first shielding layer 151. The outline is the same as the outer contour of the first initial cavity 141', the sacrificial layer 181, and the second electronic component 132'.
接著,如圖6所示,將犧牲層181移除,以移除犧牲層181上方所覆之第一屏蔽層151,並使第二電子元件132暴露出來。如此,可以隔絕電子封裝模組結構1內電子元件131、132、132’之間的電磁干擾。 Next, as shown in FIG. 6, the sacrificial layer 181 is removed to remove the first shield layer 151 overlying the sacrificial layer 181 and expose the second electronic component 132. Thus, electromagnetic interference between the electronic components 131, 132, 132' in the electronic package module structure 1 can be isolated.
上述圖4-6搭配圖案化的犧牲層181以形成第一屏蔽層151的方法,也可以改用圖案化的遮罩(mask)遮蓋整個組裝平面,再進行金屬噴塗(spray coating)並加以固化而形成第一屏蔽層151。 4-6 above, in conjunction with the patterned sacrificial layer 181 to form the first shielding layer 151, a patterned mask may be used instead to cover the entire assembly plane, followed by spray coating and curing. The first shield layer 151 is formed.
接著,如圖7所示,於組裝平面111提供第二初始模封體161’,以包覆第一初始模封體141’、第二電子元件132、132’、第一屏蔽層151以及部份組裝平面111。其中第一初始模封體141’與第二初始模封體161’之間是以第一屏蔽層151相互隔離,也就是說,第一屏蔽層151是埋設於模封材料中。第二初始模封體161’例如是以模封材料對整個組裝平面111進行一封膠製程所形成,所述封膠製程例如採用覆蓋成型、一般轉注成型、壓注成型或是模穴注膠成形(mold chase)的方式,而第二初始模封體161’的材質可以與第一初始模封體141’的材質相同,例如為環氧樹脂或矽膠。 Next, as shown in FIG. 7, a second initial molding body 161' is provided on the assembly plane 111 to cover the first initial molding body 141', the second electronic component 132, 132', the first shielding layer 151, and the portion. Assembly plane 111. The first initial molding body 141' and the second initial molding body 161' are separated from each other by the first shielding layer 151, that is, the first shielding layer 151 is embedded in the molding material. The second initial molding body 161 ′ is formed, for example, by a molding process of the entire assembly plane 111 by using a molding material, for example, by overmolding, general transfer molding, injection molding or cavity injection molding. The material of the second initial mold body 161 ′ may be the same as the material of the first initial mold body 141 ′, for example, epoxy resin or silicone rubber.
接著,如圖8所示,移除部分第一初始模封體141’以及部分第二初始模封體161’,以暴露一部分的第一屏蔽層151,同時形成如圖1的第一模封體141以及第二模封體161。例如利用 研磨(grinding)或是雷射加工處理(Laser trimming)等方式,削除部份第一初始模封體141’與部份第二初始模封體161’,藉此降低電子封裝模組結構1整體的高度。第一模封體141的高度可小於第一初始模封體141’的高度,且第二模封體161的高度可小於第二初始模封體161’的高度,第一模封體141的上表面可切齊於第二模封體161的上表面。同時,一部分的第一屏蔽層151也一併被移除,未被移除的第一屏蔽層151在電子元件131、132之間形成具有一定高度的屏蔽結構。 Next, as shown in FIG. 8, a portion of the first initial mold body 141' and a portion of the second initial mold body 161' are removed to expose a portion of the first shield layer 151 while forming the first mold seal of FIG. The body 141 and the second mold body 161. For example Grinding or laser trimming, etc., part of the first initial molding body 141' and part of the second initial molding body 161' are removed, thereby reducing the overall structure of the electronic package module 1. the height of. The height of the first molding body 141 may be smaller than the height of the first initial molding body 141 ′, and the height of the second molding body 161 may be smaller than the height of the second initial molding body 161 ′, the first molding body 141 The upper surface may be aligned with the upper surface of the second mold body 161. At the same time, a part of the first shielding layer 151 is also removed together, and the unshielded first shielding layer 151 forms a shielding structure with a certain height between the electronic components 131, 132.
接著,形成第二屏蔽層171,如圖1所示,本實施例中,可整面性地形成第二屏蔽層171,以覆蓋第一模封體141、第二模封體161以及第二電子元件132’上表面。第二屏蔽層171並可完整包覆線路基板11的側邊並電性連接側邊的接地墊12。形成第二遮蔽層的製程可採用例如金屬噴塗(Spray coating)、無電鍍製程(electroless plating)或濺鍍製程(Sputtering)等常見的金屬塗佈製程,也可採用黏貼導電膠帶等方式,但不以此為限。 Next, a second shielding layer 171 is formed. As shown in FIG. 1 , in the embodiment, the second shielding layer 171 can be formed in a full surface to cover the first molding body 141 , the second molding body 161 , and the second layer. The upper surface of the electronic component 132'. The second shielding layer 171 can completely cover the side edges of the circuit substrate 11 and electrically connect the ground pads 12 on the side. The process for forming the second shielding layer may be a common metal coating process such as a spray coating, an electroless plating or a sputtering process, or a conductive tape, but not This is limited to this.
上述實施例可歸納出本發明一實施例之電子封裝模組之製造方法,請參照圖9。步驟S1,提供線路基板,線路基板具有組裝平面與接地墊,多個電子元件設置於該組裝平面上;步驟S2,形成第一模封體包覆部份電子元件;步驟S3,形成第一屏蔽層,覆蓋第一模封體並接觸組裝平面上的接地墊;步驟S4,形成第二模封體覆蓋第一模封體及組裝平面上未被模封體覆蓋的電子元件;步驟S5,移除部分模封體並暴露部分第一屏蔽層;步驟S6,形成第二屏蔽層,覆蓋整個模封體外表面並電性連接第一屏蔽層。 The above embodiment can be summarized as a method of manufacturing an electronic package module according to an embodiment of the present invention. Please refer to FIG. 9. In step S1, a circuit substrate is provided. The circuit substrate has an assembly plane and a ground pad, and a plurality of electronic components are disposed on the assembly plane; in step S2, a first mold body is formed to cover a portion of the electronic component; and in step S3, a first shield is formed. a layer covering the first mold body and contacting the ground pad on the assembly plane; in step S4, forming a second mold body covering the first mold body and the electronic component not covered by the mold body on the assembly plane; step S5, shifting Part of the molding body is exposed and a portion of the first shielding layer is exposed; in step S6, a second shielding layer is formed to cover the entire outer surface of the molding body and electrically connect the first shielding layer.
在另一實施例中,上述形成形成第二屏蔽層171之前,在移除部分第一初始模封體141’以及部分第二初始模封體161’的步驟時,利用模封體不同高度的落差所產生的區域提供其它電子元件或電子模組做立體堆疊與電性連接。詳細而言,可以預先將 較高度較低的元件設計在一個區域而較高的元件設計在另一區域,如此後續形成的模封體,其頂部距離較低電子元件的距離較另一距離較高電子元件的距離為大,因此高度較低的元件區域上方的模封體可削除得較多,以形成模封體具有不同高度的區域。可先在高度較低的元件區域的模封體中依設計形成導電結構以連接電子元件、線路基板11的接地墊12或線路層,或在模封體上方形成線路佈局,再電性連接堆疊置放其上的電子元件或電子模組,最後再形成第二屏蔽層171電性連接接地墊12。實際作法例如:形成多個孔洞於模封體中,其中各孔洞暴露出接地墊或是電子元件的電性連接端;形成多個金屬柱於孔洞中,並且形成第一金屬圖案層於模封體以及金屬柱上方,其中各金屬柱電性連接接地墊或是電子元件之電性連接端。接著,再堆疊電子元件或電子模組於模封體上方,並電性連接於第一金屬圖案層或金屬柱。之後,形成模封體全面覆蓋組裝平面上方,包括堆疊後的電子元件或電子模組、已形成的模封體。 In another embodiment, before the forming of the second shielding layer 171, the step of removing a portion of the first initial molding body 141' and a portion of the second initial molding body 161' is performed by using different heights of the molding body. The area created by the drop provides other electronic components or electronic modules for stereoscopic stacking and electrical connection. In detail, you can pre- The lower-level components are designed in one area and the higher-level components are designed in another area, such that the subsequently formed molded body has a larger distance from the top of the lower electronic component than the distance of the other higher-distance electronic component. Therefore, the molding body above the lower-element component region can be removed more to form regions of the molding body having different heights. The conductive structure may be formed in the mold body of the lower-level component region to connect the electronic component, the ground pad 12 or the circuit layer of the circuit substrate 11, or form a line layout over the mold body, and then electrically connect the stack. The electronic component or the electronic module is placed thereon, and finally the second shielding layer 171 is electrically connected to the ground pad 12. The actual method is as follows: forming a plurality of holes in the mold body, wherein each hole exposes a ground pad or an electrical connection end of the electronic component; forming a plurality of metal pillars in the hole, and forming a first metal pattern layer on the mold seal Above the body and the metal column, each of the metal posts is electrically connected to the ground pad or the electrical connection end of the electronic component. Then, the electronic component or the electronic module is stacked on the mold body and electrically connected to the first metal pattern layer or the metal pillar. Thereafter, the molding body is formed to cover the entire assembly plane, including the stacked electronic components or electronic modules, and the formed molding body.
本發明利用兩階段分別形成第一屏蔽層、第二屏蔽層,以及利用兩階段模封,在個別電子元件間選擇性形成垂直方向上的金屬屏蔽,此方法所形成的金屬屏蔽隔間不會有習知金屬屏蔽隔間深寬比所產生的導電不良或不均的問題,繼之搭配模封體頂部的第二屏蔽層後,可完整地保護電子元件免於受到電磁干擾。並且,透過削除部份模封體,可以同時降低電子封裝模組結構整體高度。再者,電子封裝模組結構1可有效利用電子元件間的高度差,而提供可供立體堆疊的結構。因而本發明可提供具有較小厚度的構形因子(form factor)。 The invention utilizes two stages to respectively form a first shielding layer, a second shielding layer, and a two-stage molding to selectively form a metal shielding in a vertical direction between individual electronic components, and the metal shielding compartment formed by the method does not There is a problem of poor conductivity or unevenness caused by the known aspect ratio of the metal shielding compartment, and then the second shielding layer on the top of the molding body can completely protect the electronic components from electromagnetic interference. Moreover, by cutting off part of the mold body, the overall height of the electronic package module structure can be reduced at the same time. Furthermore, the electronic package module structure 1 can effectively utilize the height difference between the electronic components, and provides a structure for three-dimensional stacking. Thus the present invention can provide a form factor having a small thickness.
以上所述僅為本發明的實施例,其並非用以限定本發明的專利保護範圍。任何熟習相像技藝者,在不脫離本發明的精神與範圍內,所作的更動及潤飾的等效替換,仍為本發明的專利保護範圍內。 The above is only an embodiment of the present invention, and is not intended to limit the scope of the invention. It is still within the scope of patent protection of the present invention to make any substitutions and modifications of the modifications made by those skilled in the art without departing from the spirit and scope of the invention.
S1~S6‧‧‧步驟 S1~S6‧‧‧Steps
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| TWI676259B (en) * | 2016-09-02 | 2019-11-01 | 矽品精密工業股份有限公司 | Electronic package and method for fabricating the same |
| CN111158521A (en) * | 2019-12-30 | 2020-05-15 | 合肥微晶材料科技有限公司 | Anti-interference touch control induction layer and touch screen based on same |
| CN111584374A (en) * | 2020-05-21 | 2020-08-25 | 徐彩芬 | Packaging method of semiconductor device |
| CN112563155A (en) * | 2019-09-26 | 2021-03-26 | 伟创力有限公司 | Method of forming exposed cavities in a molded electronic device |
| CN113990812A (en) * | 2020-07-27 | 2022-01-28 | 华为技术有限公司 | Electronic packaging module and preparation method thereof |
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| KR102449619B1 (en) * | 2017-12-14 | 2022-09-30 | 삼성전자주식회사 | Semiconductor package and semiconductor module including same |
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| US8004860B2 (en) * | 2006-08-29 | 2011-08-23 | Texas Instruments Incorporated | Radiofrequency and electromagnetic interference shielding |
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| TWI472007B (en) * | 2010-12-28 | 2015-02-01 | 財團法人工業技術研究院 | Encapsulation structure of embedded electronic components |
| TWI502733B (en) * | 2012-11-02 | 2015-10-01 | 環旭電子股份有限公司 | Electronic package module and method of manufacturing the same |
| TWI553825B (en) * | 2013-01-11 | 2016-10-11 | 日月光半導體製造股份有限公司 | Stacked package module and manufacturing method thereof |
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| TWI676259B (en) * | 2016-09-02 | 2019-11-01 | 矽品精密工業股份有限公司 | Electronic package and method for fabricating the same |
| CN112563155A (en) * | 2019-09-26 | 2021-03-26 | 伟创力有限公司 | Method of forming exposed cavities in a molded electronic device |
| CN111158521A (en) * | 2019-12-30 | 2020-05-15 | 合肥微晶材料科技有限公司 | Anti-interference touch control induction layer and touch screen based on same |
| CN111158521B (en) * | 2019-12-30 | 2022-03-11 | 合肥微晶材料科技有限公司 | Anti-interference touch control induction layer and touch screen based on same |
| CN111584374A (en) * | 2020-05-21 | 2020-08-25 | 徐彩芬 | Packaging method of semiconductor device |
| CN111584374B (en) * | 2020-05-21 | 2023-08-22 | 深圳市鸿润芯电子有限公司 | Packaging method of semiconductor device |
| CN113990812A (en) * | 2020-07-27 | 2022-01-28 | 华为技术有限公司 | Electronic packaging module and preparation method thereof |
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