TWI472007B - Encapsulation structure of embedded electronic components - Google Patents

Description

Encapsulation structure of embedded electronic components

The present invention relates to an electronic component package structure, and more particularly to a buried electronic component package structure.

In view of the electromagnetic interference (EMI) of current electronic products, the performance of the electronic device or the overall circuit is reduced. The common method is to add an extra shielding plate or a cover-type metal cover to the externally disposed package on the substrate as electromagnetic interference. Prevention and treatment. When considering the overall thickness of an electronic device or package, it is necessary to investigate the manner in which the embedded electronic components are mounted.

The present invention provides an electronic component package having at least a first electronic component, a first shielding layer, and a first dielectric structure. The first electronic component is disposed on a substrate and electrically connected to the substrate. The first shielding layer is disposed on the substrate and covers at least the upper surface of the first electronic component and at least one side surface and a portion of the substrate. The first dielectric structure is disposed on the first shielding layer and the substrate and covers the first electronic component.

The invention provides a buried electronic component package having at least one electronic component, a shielding layer and a gel. The electronic component is disposed on a stack and electrically connected to the stack, and the stack has at least one dielectric structure and a metal pattern structure disposed under the dielectric structure. The shielding layer is disposed on the laminate and covers at least the upper surface of the electronic component and the at least one side surface and the portion of the metal pattern structure of the laminate. The encapsulant is disposed on the laminate and encapsulates the electronic component and the shielding layer.

Based on the above, the electronic component package of the present invention is formed by covering at least one shielding layer above or/and around the electronic component before or during lamination.

In order to make the above-described features of the present invention more comprehensible, the following detailed description of the embodiments will be described in detail below.

In the process of the embedded electronic component packaging process, the invention synchronously forms an architecture that can achieve EMI shielding. The utility model mainly covers at least one metal film above or/and around the buried electronic component, so that the electronic component is covered by the metal film and is free from electromagnetic interference, and the heat conduction and heat dissipation effect of the electronic component can also be enhanced.

In the present invention, a metal film can be attached to the embedded electronic component by electroplating, or by adhesive film bonding or by patterned interface lamination. The metal film can be designed in different patterns to improve the protection effect and increase the adhesion, or reduce the possibility of bubble generation during the metal film attachment process.

1A-1F are schematic cross-sectional views showing a manufacturing process of an electronic component package structure according to an embodiment of the invention. It must be noted here that the electronic component can be a semiconductor wafer or a semiconductor component, such as an active component such as a transistor, a diode, a light emitting diode (LED) or a passive component such as a resistor, a capacitor or an inductor component. Wait.

Referring first to FIG. 1A, first, a substrate 100 is provided having a stack 101 of at least one dielectric film 102 and an adhesive layer 104. The material of the dielectric film 102 is, for example, polyimide or benzocyclobutene (BCB), or ABF, and the material of the adhesive layer 104 is, for example, a thermosetting adhesive or a thermoplastic adhesive. Next, the electronic components 106a/106b/106c are sequentially disposed on the adhesive layer 104 face-down. In this embodiment, the electronic component 106a is, for example, an IC chip, the electronic component 106b is, for example, a passive component, and the electronic component 106c is, for example, a radio frequency (RF) chip. By "face down" is meant contacting the contact end 105 of the electronic component with the upper surface of the adhesive layer 104. However, the types, relative positions, or numbers of actual electronic components are not limited to those described in this case, and may be adjusted or changed depending on actual needs of the product.

Next, referring to FIG. 1B, a shielding layer 110 is formed on the upper surface of the adhesive layer 104 to cover the electronic components 106a/106b/106c. The material of the shielding layer 110 is, for example, aluminum or copper metal. The method of forming the shielding layer 110 is, for example, electroplating or sputtering to plate aluminum or copper or other metal such as a silver (Ag) nickel (Ni) film, or a plurality of metal films onto the surface of the electronic component, or a copper tape. Or a non-metallic conductive carbon tape attached to the surface of the electronic component. The masking layer 110 may further include an adhesive layer (not shown) to help flatten the attachment to the surface of the electronic component.

The shielding layer 110 covers at least the upper surface and the partial side surface of the electronic component 106a/106b/106c and the partial laminate 101. Although the masking layer 110 is represented by a "layer", it may actually be a discontinuous, discrete metal pattern block rather than a continuous film layer. In general, corresponding to different electronic components, the shielding layer 110 includes different pattern blocks, but the pattern blocks are at least larger than the corresponding electronic components, so as to cover at least the upper surface of the corresponding electronic components. With partial side surfaces (or even partial adhesive layer surfaces). In other words, the shielding layer 110 is preferably capable of completely covering the electronic component 106 to provide electromagnetic interference shielding, or at least cover the entire upper surface and at least one surface of the corresponding electronic component 106 to provide electromagnetic interference shielding. efficacy. Moreover, in other embodiments, the masking layer 110 may have a different pattern design depending on the frequency of the desired masking.

2A-2E are schematic top views of a pattern block included in a portion of the masking layer to show different pattern designs of the masking layer corresponding to different electronic components. Referring to the cross-shaped metal pattern 210 shown in FIG. 2A, the dotted line area indicates the size of the upper surface of the electronic component, and the shielding layer (the cross-shaped metal pattern 210) completely covers the upper surface and the four side surfaces of the electronic component. With respect to FIG. 2A, it can be seen that the metal pattern 210 of FIG. 2B is designed to have uniformly distributed holes 21a, and the shape, size, and distribution density of the holes can be changed by the frequency of the desired shielding. The metal pattern 210 of Figures 2C-2D is designed with equidistantly distributed, staggered grid-like gaps 21b/21c, but the grid-like gaps are designed differently. The T-shaped metal pattern 210 shown in FIG. 2E is composed of an equidistantly distributed, staggered mesh metal stripe 21d (which can also be regarded as having a checkerboard space), and the dotted line area indicates the surface size of the electronic component, and The T-shaped metal pattern 210 can completely cover the upper surface of the electronic component and the three side surfaces. The ratio of the width d of the metal stripe 21d to the spacing D of the stripe 21d can be more dynamically designed depending on the frequency of the desired shading. 2A and 2E can be viewed as two different shapes and sizes of holes.

Here, since the shielding layer completely covers the upper surface of the electronic component and the at least one side surface, the electromagnetic interference shielding effect of the electronic component is provided, and the electromagnetic interference of the electronic component is reduced. At the same time, the metal material of the shielding layer also has a good heat dissipation and heat dissipation effect, and is used as a heat sink.

Next, referring to FIG. 1C, a glue process is performed to form an encapsulant 120 disposed on the stack 101 and the substrate 100, and the electronic component 106 (106a/106b/106c), the shielding layer 110, and the covering layer are covered. Part of the adhesive layer 104. In the encapsulation process, the model is generally used to facilitate the injection of the encapsulant at a specific location, and after the encapsulant is solidified to form the encapsulant 120, the model is removed. The sealant is, for example, a thermosetting polymer, an epoxy resin, a polyimide or a benzocyclobutene (BCB).

Next, referring to FIG. 1D, after removing the substrate 100, a dicing process trimming layer 101 is performed to align the sides thereof with the encapsulant 120, and the whole structure is inverted upside down, that is, the encapsulant 120 is located below, and the dielectric film is 102 is at the top.

Referring to FIG. 1E, the dielectric film 102 and the adhesive layer 104 are patterned to form a patterned stack 101a including openings V that expose the contact ends 105 of the electronic components 106. Thereafter, the conductive pattern 130 is formed on the patterned dielectric film 102a and covers the opening V to be in contact with the contact end 105 of the electronic component 106. Therefore, the different electronic components can be electrically connected to each other through the conductive pattern 130. Here, the patterned laminate 101a and the conductive pattern 130 may be regarded as one of a laminate of a built-up substrate. The laminated or laminated substrate is, for example, a printed circuit board substrate of two laminated layers, four layers or eight laminated layers.

Referring to FIG. 1F, another patterned layer 140 and conductive pattern 150 are formed on the patterned layer stack 101a and the conductive pattern 130 as another layer of a built-up substrate. The encapsulant 120 constitutes the electronic component package 10 together with the coated electronic components and the laminated structures 101a/130/140/150 thereon. Here, only two layers of the laminated substrate are formed on the sealant 120. However, the scope of the present invention is not limited thereto, and the above steps may be repeated several times to form a multilayer laminated substrate.

3A-3E are schematic cross-sectional views showing a manufacturing process of an electronic component package structure according to another embodiment of the present invention.

Referring to FIG. 3A, a substrate 300 is provided. The substrate 300 can be a laminate substrate, for example, a two-layer laminated printed circuit board substrate. The substrate 300 can be regarded as a so-called first stack, and the first dielectric layer 304, the lower first metal layer 302 and the upper second metal layer 306 are alternately stacked, and are transmitted through the plurality of first via holes. (vias) 308 electrically connects the upper and lower metal layers 306, 302. Next, the electronic component 310 is sequentially disposed on the substrate 300 face-down. The electronic component 310 can be electrically connected to the substrate 300 through a flip chip bonding technique. The first and second metal layers 302, 306 include different wiring patterns and contact pads or pads.

Referring to FIG. 3B, a laminate layer 311 having a third metal layer 312 and a second dielectric layer 314 is provided. The third metal layer 312 may include continuous or discrete metal pattern blocks having a position corresponding to the position of the electronic component 310 thereunder. Next, as shown in FIG. 3C, the pressing layer 311 is pressed onto the first laminate 300 by a thermal pressing technique, and the metal pattern block position of the third metal layer 312 corresponds to the electronic component during the pressing process. The position of the third metal layer 312 covers the upper surface and the side surface of the electronic component 310, and even covers a portion of the second metal layer 306 of the first laminate 300 to electrically connect to the first stack. Layer 300 (ground).

In this embodiment, the third metal layer 312 can be regarded as a shielding layer of the electronic component, completely covering the upper surface of the electronic component and the at least one side surface, thereby providing a good electromagnetic interference shielding effect of the electronic component and reducing the electromagnetic of the electronic component. interference. In addition, the third metal layer 312 covers a portion of the substrate and can be directly grounded. Although, in this embodiment, all of the electronic components on the third metal layer are coated on the substrate, the process or electronic component functional configuration may be used to cover only certain electronic components.

In the packaging process of the embedded electronic component, the metal film is pressed and attached, and the embedded component is covered by the metal film to provide multiple protection functions.

Then, referring to FIG. 3D, a plurality of second via holes 316 are formed in the second dielectric layer 314, and a fourth metal layer 318 is formed on the second dielectric layer 314. The fourth metal layer 318 and the second metal layer 306 can be electrically connected through the second via 316. The second dielectric layer 314, the fourth metal layer 318 and the second via 316 form a so-called second stack 320.

The materials of the first, second and fourth metal layers may be the same or different and may comprise copper, aluminum or tungsten. The material of the third metal layer is, for example, aluminum or copper metal. The materials of the first and second dielectric layers may be the same or different, and may include organic compounds, such as polyimide, benzocyclobutene (BCB), polyarylene ether (parylene), etc. Things.

Referring to FIG. 3E, a plurality of solder balls 330 are directly formed on the pads 302a of the first metal layer 302.

4 is a cross-sectional view showing an electronic component package structure according to still another embodiment of the present invention. Referring to FIG. 4 , in the embodiment, the electronic component package 40 includes a substrate 400 , a plurality of electronic components 410 , a first shielding layer 412 , a dielectric structure 414 , a metal wiring structure 416 , and a second The shielding layer 418, a top dielectric structure 420, and a plurality of vias 422. The substrate 400 can be a laminated substrate, such as a two-layer laminated printed circuit board substrate. The electronic component 410 is, for example, a high power wafer and is connected to the substrate 400 in a flip chip manner. The electronic component 410 is disposed on the upper surface of the substrate 400 or on the upper surface of the intermediate dielectric structure 414. The first shielding layer 412 is disposed on and covers the upper surface of the substrate 400 and covers part or all of the four or at least one sidewall of the electronic component 410 and/or a portion or all of the upper surface. The material of the first shielding layer 412 and the second shielding layer 418 may be, for example, copper, aluminum or copper aluminum alloy, and the materials of the first shielding layer 412 and the second shielding layer 418 may be the same or different. The second shielding layer 418 is located on the inter-dielectric structure 414 and the metal wiring structure 416, covering part or all of the four or at least one sidewall of the electronic component 410 and/or part or all of the upper surface and covering the portion thereof. Metal line structure 416. The first and second shielding layers 412, 418 and the metal wiring structure 416 may be insulated to obtain a desired electrical connection function. In addition, the plurality of vias 422 formed in the inter-dielectric structure 414 electrically connect the metal line structure 416 and the substrate 400. The first or second shielding layer can be grounded depending on the product design. In addition, the electronic component package 40 of the present embodiment further includes a plurality of solder balls 424 located on the back surface of the substrate 400, which can serve as contacts for electrical connection with the outside.

In the electronic component package of the embodiment, the first or second shielding layer can be regarded as an EMI shield, which can protect the electronic component from electromagnetic interference radiation from an external or internal radiation source. Therefore, compared with the conventional electronic component package, the electronic component package of the embodiment does not need to be added with an additional metal cover plate outside the package, and is directly integrated into the package structure, which not only has a simple process, but also provides a A thinner package. In addition, for multi-chip package structures, this design can improve the performance of electromagnetic interference shielding of electronic component packages. In particular, the shielding layer can selectively cover specific electronic components, or elastically design multiple shielding layers to match the multi-layer packaging structure, covering different layers of electronic components, and enhancing the electromagnetic interference shielding effectiveness of specific blocks of the electronic component package.

In this embodiment, the electronic component package 100 can be a stacked package structure or a part of a system-in-package structure.

In summary, since the shielding layer covering the surface and the side of the electronic component can effectively shield the external electromagnetic interference radiation, the effectiveness of the electromagnetic interference shielding of the chip package of the present invention can be improved. The electronic component package of the present invention is fabricated by attaching the shielding layer to the surface of the electronic component before or during lamination, so that it is compatible with the existing packaging process.

The design of the above embodiment covers a metal film above or/and around the electronic component, so that the electronic component is covered by the metal film, thereby generating an electromagnetic interference shielding effect, and also has a good heat dissipation effect.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 40. . . Electronic component package

100, 300, 400. . . Substrate

101, 140, 320. . . Lamination

102. . . Dielectric film

104. . . Adhesive layer

105. . . Contact end

106, 106a, 106b, 106c, 310, 410. . . Electronic component

110. . . Masking layer

120. . . Sealant

130, 150. . . Conductive pattern

210. . . Metal pattern

21a. . . Hole

21b, 21c. . . Mesh gap

21d. . . Mesh metal stripe

302. . . First metal layer

302a. . . Solder pad

304. . . First dielectric layer

306. . . Second metal layer

308. . . First via

311. . . Press layer

312. . . Third metal layer

314. . . Second dielectric layer

316. . . Second via

318. . . Fourth metal layer

412. . . First shielding layer

414. . . Dielectric structure

416. . . Metal circuit structure

418. . . Second shielding layer

420. . . Top dielectric structure

422. . . Via

330, 424. . . Solder balls

V. . . Opening

1A-1F are schematic cross-sectional views showing a manufacturing process of an electronic component package according to an embodiment of the invention.

2A-2E are schematic top views of a pattern block included in a portion of the masking layer.

3A-3E are schematic cross-sectional views showing a manufacturing process of an electronic component package structure according to another embodiment of the present invention.

4 is a cross-sectional view showing an electronic component package structure according to still another embodiment of the present invention.

40. . . Electronic component package

400. . . Substrate

410. . . Electronic component

412. . . First shielding layer

414. . . Dielectric structure

416. . . Metal circuit structure

418. . . Second shielding layer

420. . . Top dielectric structure

422. . . Via

424. . . Solder balls

Claims (18)

An electronic component package includes: a substrate; at least one first electronic component disposed on the substrate and electrically connected to the substrate; a first shielding layer disposed on the substrate and covering at least the first a portion or all of the upper surface of the electronic component and a portion or all of the at least one side of the substrate; and a first dielectric structure disposed on the first shielding layer and the substrate and covering the first electron Part or all of the component. The electronic component package of claim 1, further comprising a metal circuit structure disposed on the first dielectric structure, wherein the first dielectric structure further has a plurality of via holes electrically connected to the first dielectric structure Metal lines and the substrate. The electronic component package of claim 2, further comprising: at least one second electronic component disposed on the substrate, the second electronic component being electrically connected to the metal wiring structure; and a second shielding layer And disposed on the substrate, and covering at least part or all of the upper surface of the second electronic component and at least one side of the metal wiring structure; and a second dielectric structure disposed on the substrate The second shielding layer is on the first dielectric structure and covers part or all of the second electronic component. Electronic component according to any one of claims 1-3 The package further includes a plurality of solder balls disposed under the substrate. The electronic component package of any one of claims 1-3, wherein the first electronic component is a radio frequency chip or a high power wafer. The electronic component package of claim 3, wherein the second electronic component is a passive component. The electronic component package of claim 3, wherein the second electronic component is a semiconductor wafer. The electronic component package according to any one of claims 1 to 3, wherein the material of the first shielding layer comprises copper or aluminum or other metal, and may be a non-metallic conductive material such as carbon tape, and the first A masking layer has a plurality of holes or has a grid-like gap. The electronic component package of claim 3, wherein the material of the second shielding layer comprises copper or aluminum or other metal, which may also be a non-metallic conductive material such as carbon tape, and the second shielding layer has a plurality of The hole may have a grid-like gap. An embedded electronic component package includes: a laminate having at least one dielectric structure and a metal pattern structure disposed under the dielectric structure; at least one electronic component disposed on the laminate and electrically connected to the a masking layer disposed on the layer and covering at least part or all of the upper surface of the electronic component and a portion or all of the at least one side surface and the portion of the metal pattern structure laminated; A glue is disposed on the laminate and encloses part or all of the electronic component and part or all of the shielding layer. The embedded electronic component package according to claim 10, further comprising a plurality of solder balls disposed under the laminate. The embedded electronic component package of claim 10, wherein the electronic component is a radio frequency chip, a high power chip or a passive component. The embedded electronic component package of claim 10, wherein the material of the shielding layer comprises copper or aluminum or other metal or non-metal conductive material such as carbon tape, and the shielding layer covers the electronic component. Part or all of at least one of the upper surfaces and at least one of the four sides and the shielding layer is designed to have a plurality of holes. The embedded electronic component package of claim 10, wherein the material of the shielding layer comprises copper or aluminum, and the shielding layer covers part or all of the upper surface of the electronic component and four sides. Part or all of at least one side and the shielding layer is designed to have a grid-like gap. A method for fabricating an electronic component package, comprising: providing a substrate; providing a first electronic component disposed on the substrate and electrically connected to the substrate; providing a first shielding layer disposed on the substrate, and at least Coating a portion or all of the upper surface of the first electronic component with a portion or all of the at least one side surface and a portion of the substrate; and providing a first dielectric structure disposed on the first shielding layer and the substrate The board covers and covers part or all of the first electronic component. The method of fabricating the electronic component package of claim 15, further comprising providing a metal circuit structure disposed on the first dielectric structure, and having a plurality of via holes in the first dielectric structure, Electrically connecting the metal line to the substrate. The method of manufacturing the electronic component package of claim 16, further comprising: providing at least one second electronic component, disposed on the substrate, and electrically connecting the second electronic component to the metal circuit structure Providing a second shielding layer disposed on the substrate and covering at least part or all of the upper surface of the second electronic component with at least one side of the surface and a portion of the metal wiring structure; And a second dielectric structure disposed on the second shielding layer and the first dielectric structure and covering part or all of the second electronic component. A method of fabricating a buried electronic component package includes: providing a laminate having at least one dielectric structure; providing a metal pattern structure disposed under the dielectric structure; providing at least one electronic component disposed on the laminate And electrically connected to the laminate; providing a shielding layer disposed on the laminate, and covering at least part or all of the upper surface of the electronic component and a portion or all of the at least one side of the laminate And the metal pattern structure; and providing a gel, disposed on the laminate and enclosing part or all of the electronic component and part or all of the shielding layer.