TW201338106A - Semiconductor package structure - Google Patents
Semiconductor package structure Download PDFInfo
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- TW201338106A TW201338106A TW101107558A TW101107558A TW201338106A TW 201338106 A TW201338106 A TW 201338106A TW 101107558 A TW101107558 A TW 101107558A TW 101107558 A TW101107558 A TW 101107558A TW 201338106 A TW201338106 A TW 201338106A
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- semiconductor package
- package structure
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- end portion
- lead frame
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- H10W90/726—
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- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
本發明係有關於一種半導體封裝結構，特別係有關於一種具有抗導電膜之半導體封裝結構。
The present invention relates to a semiconductor package structure, and more particularly to a semiconductor package structure having an anti-conductive film.
習知為了防止導線架與多餘之電子元件電性連接造成短路，因此常利用半蝕刻方式將導線架之引腳前半段厚度變薄，使導線架之引腳前半段得以被封膠體包覆以降低與其他電子元件接觸之機率，但此種導線架結構與晶片結合時，由於引腳前半段之厚度無法支撐晶片接合時之壓力而容易導致封裝結構變形。
In order to prevent short circuit between the lead frame and the redundant electronic components, the thickness of the first half of the lead of the lead frame is often thinned by half etching, so that the first half of the lead of the lead frame can be covered by the sealing body. The probability of contact with other electronic components is reduced. However, when the leadframe structure is bonded to the wafer, the thickness of the first half of the lead cannot support the pressure at the time of wafer bonding, and the package structure is easily deformed.
本發明之主要目的係在於提供一種半導體封裝結構，其包含一導線架、至少一晶片、一封膠體以及一抗導電膜，該導線架係具有複數個引腳，各該引腳係具有一第一端部、一第二端部及一連接該第一端部及該第二端部之半蝕刻部，該第一端部係具有一第一上表面及一第一下表面，該第二端部係具有一第二上表面及一第二下表面，該半蝕刻部係具有一第三上表面及一第三下表面，該晶片係設置於該些引腳上方，該晶片係具有一主動面及複數個設置於該主動面之凸塊，該主動面係朝向該些第一端部之該些第一上表面且該些凸塊係電性連接於該導線架，該封膠體係包覆該晶片及該些引腳，且該封膠體係顯露出各該第一端部之該第一下表面及各該第二端部之該第二下表面，該抗導電膜係覆蓋各該引腳之該第一端部之該第一下表面。由於該導線架之該些第一端部未經半蝕刻處理，因此可增加該導線架與該晶片對接時之支撐強度，且該抗導電膜係覆蓋各該引腳之該第一端部之該第一下表面，進而增加該半導體封裝結構之可靠度，此外，該導線架之該些第二端部之該些第二下表面係為裸露，提高該半導體封裝結構導電性及導熱性，也可與其他半導體封裝結構或電子元件相互堆疊並形成電性連接。
The main purpose of the present invention is to provide a semiconductor package structure including a lead frame, at least one wafer, a gel, and an anti-conductive film. The lead frame has a plurality of pins, each of which has a first An end portion, a second end portion, and a half etching portion connecting the first end portion and the second end portion, the first end portion having a first upper surface and a first lower surface, the second portion The end portion has a second upper surface and a second lower surface. The half etched portion has a third upper surface and a third lower surface. The wafer is disposed above the pins, and the wafer has a An active surface and a plurality of bumps disposed on the active surface, the active surface facing the first upper surfaces of the first ends and the bumps are electrically connected to the lead frame, the sealing system Coating the wafer and the leads, and the encapsulation system exposes the first lower surface of each of the first ends and the second lower surface of each of the second ends, the anti-conductive film covering each The first lower surface of the first end of the pin. Since the first ends of the lead frame are not half-etched, the support strength of the lead frame when the wafer is docked with the wafer is increased, and the anti-conductive film covers the first end of each of the leads. The first lower surface further increases the reliability of the semiconductor package structure, and the second lower surfaces of the second ends of the lead frame are exposed to improve conductivity and thermal conductivity of the semiconductor package structure. It is also possible to stack and form electrical connections with other semiconductor package structures or electronic components.
請參閱第1及2圖，其係本發明之一較佳實施例，一種半導體封裝結構100係包含一導線架110、至少一晶片120、一封膠體130、一抗導電膜140以及複數個銲料150，該導線架110係具有複數個引腳111，各該引腳111係具有一第一端部112、一第二端部113及一連接該第一端部112及該第二端部113之半蝕刻部114，該第一端部112係具有一第一上表面112a及一第一下表面112b，該第二端部113係具有一第二上表面113a及一第二下表面113b，該半蝕刻部114係具有一第三上表面114a及一第三下表面114b，該晶片120係設置於該些引腳111上方，該晶片120係具有一主動面121、複數個設置於該主動面121之凸塊122及一背面123，該主動面121係朝向該些第一端部112之該些第一上表面112a且該些凸塊122係電性連接於該導線架110，在本實施例中，該些凸塊122之材質係可選自於金、銅、銅/鎳、銅/鎳/金或非金屬凸塊其中之一，該封膠體130係包覆該晶片120及該些引腳111，且該封膠體130係顯露出各該第一端部112之該第一下表面112b及各該第二端部113之該第二下表面113b，該抗導電膜140係覆蓋各該引腳111之該第一端部112之該第一下表面112b以防止短路之情形發生，進而提高該半導體封裝結構之可靠度。
請再參閱第1及2圖，在本實施例中，該抗導電膜140之材質係為高阻抗高分子材料，該抗導電膜140係具有一顯露面141，各該第一端部112之該第一上表面112a至該顯露面141之間係具有一第一高度H1，各該第二端部113之該第二上表面113a至該第二下表面113b之間係具有一第二高度H2，該第一高度H1係大於該第二高度H2，該半蝕刻部114之該第三上表面114a至該第三下表面114b之間係具有一第三高度H3，該第三高度H3係小於該第二高度H2，該些銲料150係電性連接該些凸塊122及該導線架110，此外，該半導體封裝結構100係另包含有一接合層160，該接合層160係形成於該些第一端部112之該些第一上表面112a、該些第二端部113之該些第二上表面113a及該些半蝕刻部114之該些第三上表面114a，該接合層160之材質係可選自於鎳/鉛/金、銀或錫銀其中之一。由於該導線架110之該些第一端部112未經半蝕刻處理，因此可增加該導線架110與該晶片120對接時之支撐強度，且該晶片120及該導線架110之間係藉由該些銲料150及該接合層160直接電性連接，使得該半導體封裝結構100製程簡便，此外，該導線架110之該些第二端部113之該些第二下表面113b係為裸露，提高該半導體封裝結構100導電性及導熱性，也可與其他半導體封裝結構或電子元件相互堆疊並形成電性連接。
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。
Referring to FIGS. 1 and 2, a semiconductor package structure 100 includes a lead frame 110, at least one wafer 120, a gel 130, an anti-conductive film 140, and a plurality of solders. The lead frame 110 has a plurality of pins 111. Each of the pins 111 has a first end portion 112, a second end portion 113, and a first end portion 112 and a second end portion 113. The first end portion 112 has a first upper surface 112a and a first lower surface 112b. The second end portion 113 has a second upper surface 113a and a second lower surface 113b. The semi-etched portion 114 has a third upper surface 114a and a third lower surface 114b. The wafer 120 is disposed above the pins 111. The wafer 120 has an active surface 121, and a plurality of the active surfaces 121 are disposed on the active surface. a bump 122 and a back surface 123 of the surface 121, the active surface 121 is opposite to the first upper surfaces 112a of the first ends 112, and the bumps 122 are electrically connected to the lead frame 110. In an embodiment, the material of the bumps 122 may be selected from gold, copper, copper/nickel, copper/nickel/gold or non-metallic convex. The sealant 130 covers the wafer 120 and the pins 111, and the sealant 130 exposes the first lower surface 112b of each of the first ends 112 and each of the second ends. The second lower surface 113b of the 113, the anti-conductive film 140 covers the first lower surface 112b of the first end portion 112 of the pin 111 to prevent a short circuit, thereby improving the reliability of the semiconductor package structure. degree.
Referring to FIGS. 1 and 2 again, in the embodiment, the material of the anti-conductive film 140 is a high-resistance polymer material, and the anti-conductive film 140 has a display surface 141, and each of the first ends 112 The first upper surface 112a and the exposed surface 141 have a first height H1, and the second upper surface 113a of the second end 113 has a second height between the second lower surface 113a and the second lower surface 113b. H2, the first height H1 is greater than the second height H2, and the third height H3 is between the third upper surface 114a and the third lower surface 114b of the half etching portion 114, and the third height H3 is The solder package 150 is electrically connected to the bumps 122 and the lead frame 110. The semiconductor package structure 100 further includes a bonding layer 160. The bonding layer 160 is formed on the solder bumps 160. The first upper surface 112a of the first end portion 112, the second upper surface 113a of the second end portions 113, and the third upper surfaces 114a of the half etching portions 114, the bonding layer 160 The material may be selected from one of nickel/lead/gold, silver or tin-silver. Since the first ends 112 of the lead frame 110 are not half-etched, the support strength of the lead frame 110 when the wafers are docked with the wafers 120 can be increased, and the wafer 120 and the lead frame 110 are separated by The solder 150 and the bonding layer 160 are directly electrically connected, so that the semiconductor package structure 100 is simple in process, and the second lower surfaces 113b of the second ends 113 of the lead frame 110 are exposed. The semiconductor package structure 100 has electrical and thermal conductivity, and can also be stacked with other semiconductor package structures or electronic components to form an electrical connection.
The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .
100．．．半導體封裝結構100. . . Semiconductor package structure
110．．．導線架110. . . Lead frame
111．．．引腳111. . . Pin
112．．．第一端部112. . . First end
112a．．．第一上表面112a. . . First upper surface
112b．．．第一下表面112b. . . First lower surface
113．．．第二端部113. . . Second end
113a．．．第二上表面113a. . . Second upper surface
113b．．．第二下表面113b. . . Second lower surface
114．．．半蝕刻部114. . . Half etching
114a．．．第三上表面114a. . . Third upper surface
114b．．．第三下表面114b. . . Third lower surface
120．．．晶片120. . . Wafer
121．．．主動面121. . . Active surface
122．．．凸塊122. . . Bump
123．．．背面123. . . back
130．．．封膠體130. . . Sealant
140．．．抗導電膜140. . . Anti-conductive film
141．．．顯露面141. . . Revealed face
150．．．銲料150. . . solder
160．．．接合層160. . . Bonding layer
H1．．．第一高度H1. . . First height
H2．．．第二高度H2. . . Second height
H3．．．第三高度H3. . . Third height
第1圖：依據本發明之一較佳實施例，一種半導體封裝結構之截面示意圖。
第2圖：依據本發明之一較佳實施例，該半導體封裝結構之底視圖。
Figure 1 is a cross-sectional view showing a semiconductor package structure in accordance with a preferred embodiment of the present invention.
2 is a bottom view of the semiconductor package structure in accordance with a preferred embodiment of the present invention.
100．．．半導體封裝結構100. . . Semiconductor package structure
110．．．導線架110. . . Lead frame
111．．．引腳111. . . Pin
112．．．第一端部112. . . First end
112a．．．第一上表面112a. . . First upper surface
112b．．．第一下表面112b. . . First lower surface
113．．．第二端部113. . . Second end
113a．．．第二上表面113a. . . Second upper surface
113b．．．第二下表面113b. . . Second lower surface
114．．．半蝕刻部114. . . Half etching
114a．．．第三上表面114a. . . Third upper surface
114b．．．第三下表面114b. . . Third lower surface
120．．．晶片120. . . Wafer
121．．．主動面121. . . Active surface
122．．．凸塊122. . . Bump
123．．．背面123. . . back
130．．．封膠體130. . . Sealant
140．．．抗導電膜140. . . Anti-conductive film
141．．．顯露面141. . . Revealed face
150．．．銲料150. . . solder
160．．．接合層160. . . Bonding layer
H1．．．第一高度H1. . . First height
H2．．．第二高度H2. . . Second height
H3．．．第三高度H3. . . Third height
Claims (6)
一導線架，其係具有複數個引腳，各該引腳係具有一第一端部、一第二端部及一連接該第一端部及該第二端部之半蝕刻部，該第一端部係具有一第一上表面及一第一下表面，該第二端部係具有一第二上表面及一第二下表面，該半蝕刻部係具有一第三上表面及一第三下表面；
至少一晶片，其係設置於該些引腳上方，該晶片係具有一主動面及複數個設置於該主動面之凸塊，該主動面係朝向該些第一端部之該些第一上表面且該些凸塊係電性連接於該導線架；
一封膠體，其係包覆該晶片及該些引腳，且該封膠體係顯露出各該第一端部之該第一下表面及各該第二端部之該第二下表面；以及
一抗導電膜，其係覆蓋各該引腳之該第一端部之該第一下表面。A semiconductor package structure comprising at least:
a lead frame having a plurality of pins, each of the leads having a first end portion, a second end portion, and a half etching portion connecting the first end portion and the second end portion The first end portion has a first upper surface and a first lower surface, the second end portion has a second upper surface and a second lower surface, the semi-etched portion has a third upper surface and a first surface Three lower surfaces;
At least one wafer is disposed above the pins, the wafer has an active surface and a plurality of bumps disposed on the active surface, the active surface facing the first ends of the first ends a surface and the bumps are electrically connected to the lead frame;
a colloid covering the wafer and the leads, and the encapsulation system reveals the first lower surface of each of the first ends and the second lower surface of each of the second ends; An anti-conductive film covering the first lower surface of the first end of each of the pins.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101107558A TWI459515B (en) | 2012-03-06 | 2012-03-06 | Semiconductor package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101107558A TWI459515B (en) | 2012-03-06 | 2012-03-06 | Semiconductor package structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201338106A true TW201338106A (en) | 2013-09-16 |
| TWI459515B TWI459515B (en) | 2014-11-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW101107558A TWI459515B (en) | 2012-03-06 | 2012-03-06 | Semiconductor package structure |
Country Status (1)
| Country | Link |
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| TW (1) | TWI459515B (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI317991B (en) * | 2003-12-19 | 2009-12-01 | Advanced Semiconductor Eng | Semiconductor package with flip chip on leadframe |
| KR101146973B1 (en) * | 2005-06-27 | 2012-05-22 | 페어차일드코리아반도체 주식회사 | Package frame and semiconductor package using the same |
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| Publication number | Publication date |
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| TWI459515B (en) | 2014-11-01 |
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