TWI620258B - Package structure and its process - Google Patents

Abstract

The invention provides a packaging process, which includes the following steps: stacking a plurality of wafers on a carrier board; forming a packaging layer on the carrier board to cover the plurality of wafers; forming a plurality of contact openings separated from each other in the packaging layer, and A plurality of contact conductors are formed in the plurality of contact openings of the packaging layer, wherein the plurality of contact conductors are separated from each other and are electrically connected to the corresponding wafers respectively; the circuit substrate is connected to the packaging layer and the plurality of contact conductors, where the circuit substrate includes A plurality of connection pads, and the plurality of connection pads are separated from each other and are respectively electrically connected to corresponding contact conductors. In addition, the present invention also provides a packaging structure.

Description

Packaging structure and process

The invention relates to a semiconductor structure and a manufacturing process thereof, and more particularly to a packaging structure and a manufacturing process thereof.

In the existing multi-chip package structure, a plurality of chips stacked on a circuit substrate are usually passed through a plurality of bonding wires to electrically connect the chip to the circuit substrate. Generally speaking, a slender solder wire formed by a wire bonder usually faces a problem of high resistance value, which affects the overall performance of the package structure. In addition, in order to protect the bonding wire, it is usually necessary to form an encapsulation layer covering the wafer and the bonding wire on the circuit carrier board. In the process of forming the packaging layer, the longer bonding wire will face serious wire sweeping problems. , And the problem of dumping is easy to cause disconnection, collapse, short circuit and other phenomena. Furthermore, in order to prevent the bonding wires from being exposed outside the packaging structure, the packaging layer must have a certain thickness, making it difficult to reduce the volume of the packaging structure. Therefore, how to improve the reliability of the packaging structure and reduce the volume of the packaging structure is really one of the issues that researchers currently need to solve.

The invention provides a packaging structure with good reliability and a manufacturing process thereof.

An embodiment of the present invention provides a packaging process, which includes the following steps. Multiple wafers are stacked on a carrier board. An encapsulation layer is formed on a carrier board to cover a plurality of wafers. A plurality of contact openings separated from each other are formed in the packaging layer, and a plurality of contact conductors are formed in the plurality of contact openings of the packaging layer. The plurality of contact conductors are separated from each other and are electrically connected to the corresponding wafers, respectively. The circuit substrate is connected to the packaging layer and the plurality of contact conductors. The circuit substrate includes a plurality of connection pads, and the plurality of connection pads are separated from each other and electrically connected to the corresponding contact conductors, respectively.

Another embodiment of the present invention provides a packaging structure including a circuit substrate, a plurality of chips, a packaging layer, and a plurality of contact conductors. The circuit substrate includes a plurality of connection pads. A plurality of wafers are stacked on the circuit substrate, and each wafer includes a bonding pad. The packaging layer is located on the circuit substrate and covers a plurality of chips. A plurality of contact conductors are located in the packaging layer, wherein the plurality of contact conductors are separated from each other and are electrically connected to the corresponding connection pads and the corresponding solder pads, respectively, and the active surfaces of the plurality of chips face the circuit substrate.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

FIG. 1 is a top view of a wafer disposed on a carrier board according to an embodiment of the present invention. 2A to 2E are schematic cross-sectional views of a packaging process according to an embodiment of the present invention. Referring to FIG. 1, a plurality of wafers 102 are stacked on a carrier board 100, wherein each wafer 102 includes a bonding pad 104. In this embodiment, there are alignment points 100a and 100b on the carrier board 100, so that the wafer 102 can be accurately set on the carrier board 100, but the invention is not limited thereto. Referring to FIG. 2A, the wafers 102 are stacked on the carrier board 100 in the first direction D1, and among the two adjacent wafers 102, the wafers 102 on the upper layer are offset by a distance S in the second direction D2, so that The pads 104 of the lower wafer 102 are exposed. In an embodiment, the offset distance S is, for example, greater than the width W of the bonding pad 104, but the present invention is not limited thereto, as long as the offset distance S is sufficient to expose the bonding pad 104.

The material of the carrier plate 100 is, for example, glass, polyimide (PI), or a combination thereof. The material of the bonding pad 104 is, for example, a metal, such as copper, aluminum, gold, silver, nickel, palladium, or a combination thereof.

In addition, in order to improve the adhesion between the wafer 102 and the carrier board 100, before the plurality of wafers 102 are stacked on the carrier board 100, the carrier board 100 may be surface-treated to increase the surface roughness of the carrier board 100 so that the carrier board 100 The friction coefficient of the plate 100 can be improved, so the wafer 102 contacting the carrier plate 100 can be stably fixed on the carrier plate 100 without fixing the wafer 102 to the carrier plate 100 with an additional sticky crystal material. on. For example, the surface of the carrier board 100 may be surface-treated by a plasma to appropriately improve the surface roughness of the carrier board 100.

In addition, in order to improve the adhesion between two adjacent wafers 102, an adhesive layer 106 may be provided between the two adjacent wafers 102 so that the wafers 102 can be stably stacked on the carrier board 100. In one embodiment, an adhesive layer 106 is formed on the back surface 102B of the wafer 102 far from the carrier board 100 between two adjacent wafers 102, and the adhesive layer 106 is partially Covered on the active surface 102A of the wafer 102 near the carrier board 100 so that the bonding pad 104 is not covered by the adhesive layer 106. The adhesive layer 106 is, for example, a die attach film (DAF), but the invention is not limited thereto. The back surface 102B of the wafer 102 described above faces the active surface 102A of the wafer 102.

Referring to FIG. 2B, an encapsulation layer 108 is formed on the carrier board 100 to cover a plurality of wafers 102. In one embodiment, the encapsulation layer 108 includes a first portion 108a and a second portion 108b connected to the first portion 108a. For example, the boundary line X divides the packaging layer 108 into a first portion 108 a covering the active surface 102A of the chip 102 and a second portion 108 b located between the carrier board 100 and the chip 102. In other words, the first portion 108 a of the encapsulation layer 108 covers the bonding pad 104 of the chip 102; and the second portion 108 b of the encapsulation layer 108 and the carrier board 100 cover the back surface 102B of the chip 102. A method of forming the encapsulation layer 108 is, for example, an over mold. The material of the encapsulation layer 108 is, for example, epoxy or other suitable dielectric materials.

Then, a plurality of contact openings 110 separated from each other are formed in the encapsulation layer 108 to expose the bonding pads 104 of each wafer 102. In other words, the contact opening 110 is formed in the first portion 108 a of the encapsulation layer 108. In some embodiments, the contact opening 110 is formed in the first portion 108 a of the encapsulation layer 108 by laser drilling, for example. In other embodiments, the contact opening 110 may also be formed in the first portion 108 a of the encapsulation layer 108 in a transfer molding manner.

Referring to FIG. 2C, a plurality of contact openings 110 are filled with a conductive material to form a plurality of contact conductors 112, wherein the contact conductors 112 are respectively electrically connected to corresponding wafers 102. That is, the contact conductors 112 are embedded in the first portion 108 a of the encapsulation layer 108 separately from each other, and are respectively electrically connected to the corresponding pads 104 of the chip 102. In some embodiments, the method of forming the contact conductor 112 is, for example, filling a conductive material into the contact opening 110 by physical vapor deposition (PVD) to form the contact conductor 112. In other embodiments, the method of forming the contact conductor 112 may be, for example, forming a seed layer (not shown) before the surface of the contact opening 110, and then performing plating (for example, electroplating or electroplating) Electroless plating, etc.) or sputtering, a conductive material is formed on the seed layer and filled into the contact opening 110 to form the contact conductor 112. The material of the contact conductor 112 is, for example, copper, but the invention is not limited thereto.

Referring to FIG. 2D, the circuit substrate 114 is connected to the encapsulation layer 108 and the contact conductor 112. The circuit substrate 114 includes a plurality of connection pads 116. The connection pads 116 are separated from each other and are electrically connected to the corresponding contact conductors 112, respectively. A packaging structure 118 is formed on the carrier board 100. In other words, the contact conductor 112 in the package structure 118 can be electrically connected to the chip 102 and the circuit substrate 114 stably, so that the package structure 118 has good reliability. In one embodiment, the active surface 102A of the chip 102 faces the circuit substrate 114 so that the length L of the contact conductor 112 can be optimized. In this way, the package structure 118 not only has good electrical performance, but also achieves a miniaturized design. For example, the contact conductor 112 may be a conductive pillar perpendicular to the circuit substrate 114 and the carrier board 100, so that the package structure 118 has good electrical performance and miniaturization size. The length L of the above-mentioned contact conductor 112 is the length L of the contact conductor 112 extending along the first direction D1, wherein according to the distance between the bonding pad 104 of each chip 102 and the connection pad 116 of the corresponding circuit substrate 114, each contact The conductors 112 will have different lengths L.

Referring to FIG. 2E, the plurality of wafers 102 and the packaging layer 108 are separated from the carrier board 100 so that the wafer 102 farthest from the circuit substrate 114 is exposed. Then, the package structure 118 is transposed. In one embodiment, the back surface 102B of the wafer 102 farthest from the circuit substrate 114 is exposed, so that the package structure 118 has better heat dissipation effect. In other words, in this embodiment, the wafer 102 farthest from the circuit substrate 114 can be exposed without an additional grinding process. Therefore, damage to the wafer 102 due to excessive grinding or poor heat dissipation due to insufficient grinding can be avoided. Problems, making the package structure have good reliability.

Please continue to refer to FIG. 2E, the package structure 118 includes a circuit substrate 114, a plurality of chips 102, a package layer 108, and a plurality of contact conductors 112. The circuit substrate 114 includes a plurality of connection pads 116. The wafers 102 are stacked on the circuit substrate 114, wherein each wafer 102 includes a bonding pad 104. The encapsulation layer 108 is located on the circuit substrate 114 and covers the wafer 102. The contact conductors 114 are located in the encapsulation layer 108. The plurality of contact conductors 114 are separated from each other and are electrically connected to the corresponding connection pads 116 and the corresponding solder pads 104. The active surface 102A of the chip 102 faces the circuit substrate 114. In one embodiment, the encapsulation layer 108 includes a first portion 108a and a second portion 108b connected to the first portion 108a. The first portion 108a is located between the wafer 102 and the circuit carrier board 114, and the second portion 108b covers the wafer 102, and the contact conductor 112 is embedded in the first portion 108a.

To sum up, the package structure and the manufacturing process described in the above embodiments are formed by forming a packaging layer covering a plurality of wafers on a carrier board, and then forming a contact conductor in the packaging layer, so that the contact conductor can be stably formed in the package. Layer, so the package structure has good reliability. Moreover, in the package structure described in the above embodiment, the active surface of the chip faces the circuit substrate, so that the length of the contact conductor can be optimized. Therefore, the package structure not only has good electrical performance, but its size can also be miniaturized. design.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100‧‧‧ Carrier Board

100a, 100b‧‧‧

102‧‧‧Chip

102A‧‧‧ Active side

102B‧‧‧Back

104‧‧‧pad

106‧‧‧ Adhesive layer

108‧‧‧ Packaging

108a‧‧‧Part I

108b‧‧‧Part II

110‧‧‧ contact opening

112‧‧‧contact conductor

114‧‧‧circuit board

116‧‧‧Connecting pad

118‧‧‧Packaging Structure

D1‧‧‧ first direction

D2‧‧‧ Second direction

S‧‧‧distance

W‧‧‧Width

L‧‧‧ length

X‧‧‧ dividing line

FIG. 1 is a top view of a wafer disposed on a carrier board according to an embodiment of the present invention. 2A to 2E are schematic cross-sectional views of a packaging process according to an embodiment of the present invention.

Claims (8)

A packaging process includes: stacking a plurality of wafers on a carrier board; forming a packaging layer on the carrier board to cover the plurality of wafers; forming a plurality of contact openings separated from each other in the packaging layer; and A plurality of contact conductors are formed in the plurality of contact openings of the packaging layer, wherein the plurality of contact conductors are separated from each other and are respectively electrically connected to corresponding chips; and a circuit substrate is connected to the packaging layer and the On the plurality of contact conductors, wherein the circuit substrate includes a plurality of connection pads, the plurality of connection pads are separated from each other and are electrically connected to the corresponding contact conductors, respectively. The packaging process according to item 1 of the patent application scope further includes separating the plurality of chips and the packaging layer from the carrier board. The packaging process according to item 1 of the scope of patent application, wherein the method of forming the plurality of contact conductors comprises: forming the plurality of contact openings in the packaging layer by means of laser drilling; and A conductive material is filled in the plurality of contact openings to form the plurality of contact conductors. According to the packaging process described in item 1 of the patent application scope, before the plurality of wafers are stacked on the carrier board, the carrier board further includes a surface treatment. A packaging structure includes: a circuit substrate including a plurality of connection pads; A plurality of wafers stacked on the circuit substrate, wherein each wafer includes a bonding pad; a packaging layer located on the circuit substrate and covering the plurality of wafers; and a plurality of contact conductors located in the packaging layer Wherein the plurality of contact conductors are separated from each other and are electrically connected to the corresponding connection pads and corresponding solder pads, respectively, wherein the active surfaces of the plurality of wafers face the circuit substrate, and the plurality of contact conductors Includes multiple conductive posts. The package structure according to item 5 of the patent application scope, wherein the packaging layer includes a first portion and a second portion connected to the first portion, and the first portion is located between the plurality of chips and the circuit carrier board. Meanwhile, the second portion covers the plurality of wafers, wherein the plurality of contact conductors are embedded in the first portion. The package structure described in item 5 of the patent application scope further includes a plurality of adhesive layers located between two adjacent chips. The package structure according to item 5 of the scope of patent application, wherein a wafer farthest from the circuit substrate of the plurality of wafers is exposed.