TW201203559A - Pixel structure and method for forming the same - Google Patents

Abstract

A pixel structure comprises at least one transistor, a first storage capacitor, a first conductive layer, an interlayer dielectric layer, a second conductive layer, a passivation layer and a third conductive layer. The first storage capacitor is electrically connected to the transistor. The interlayer dielectric layer having at least one first opening covers the first conductive layer. The second conductive layer is formed on part of the interlayer dielectric layer and is electrically connected to the first conductive layer through the first opening. The passivation layer having at least one second opening covers the transistor and the second conductive layer. The third conductive layer is formed on part of the passivation layer and is electrically connected to the transistor through the second opening. The third conductive layer, the passivation layer and the second conductive layer form the first storage capacitor.

Description

201203559

1 W3530FA-D VI. Description of the Invention: [Technical Field] The present invention relates to a halogen structure and a method of forming the same, and in particular to a halogen structure having a storage capacitor. [Prior Art] Please refer to Fig. 1, which shows a cross-sectional view of a conventional halogen structure. The pixel structure 100 has a substrate 109. A semiconductor layer 120 is formed on the substrate 109. The semiconductor layer 120 and the substrate 109 are covered with an insulating layer 150. A gate 116 is formed on the insulating layer 150 and is covered with an inner dielectric layer 190 on the gate 116. The insulating layer 150 and the inner dielectric layer 190 have two openings 162 to expose the semiconductor layer 120. A source 114, a drain 112, and a capacitor electrode 101 are formed on the inner dielectric layer 190. The source 114 and the drain 112 are electrically connected to the semiconductor layer 120 via the opening 162. A protective layer 102 is formed on the inner dielectric layer 190 and covers the source 114, the drain 112 and the capacitor electrode 101, and has a contact hole 163 to expose the source 114. The pixel electrode 103 is formed on the protective layer 102 and electrically connected to the source 114 via the contact hole 163. The capacitor electrode 101 of the halogen structure 100 is a conductive material, and the protective layer 102 is a dielectric material. The storage capacitor Cs1 is formed between the capacitor electrode 101 and the halogen electrode 103. However, due to the coverage of the protective layer 102, a short circuit is likely to occur between the pixel electrode 103 and the capacitor electrode 101 due to process problems. Although the thickness of the protective layer 102 can be increased to solve the above-mentioned problems, the storage capacitor Csl is relatively reduced. 201203559 1 vv j-uur/Λ,-Ο In addition, the capacitor electrode 101 is generally made of an opaque material and is located in the visible region of the halogen structure 100 (not shown), so that even the halogen electrode 103 is transparent. The material of light. However, this design method tends to reduce the aperture ratio of the pixel structure 100 as the storage capacity of the storage capacitor Cs1 (e.g., the area of the storage capacitor Cs1 in the visible area) increases. As a result, the display brightness of the panel is lowered. In addition, this problem is more apparent in panels of the same size and higher resolution. SUMMARY OF THE INVENTION The present invention relates to a halogen structure and a method of forming the same, which can increase the aperture ratio without changing the capacitance value. According to a first aspect of the invention, a halogen structure is proposed. The halogen structure comprises at least one transistor, a first storage capacitor, a first conductive layer, an inner dielectric layer, a second conductive layer, a protective layer and a third conductive layer. The first storage capacitor is electrically connected to the transistor. The inner dielectric layer covers the first conductive layer and has at least one first opening. The second conductive layer is formed on the portion of the inner dielectric layer and electrically connected to the first conductive layer via the first opening. The protective layer covers the transistor and the second conductive layer and has at least one second opening. The third conductive layer is formed on the partial protective layer and electrically connected to the transistor via the second opening. The first storage capacitor is composed of a third conductive layer, a protective layer and a second conductive layer. According to a second aspect of the present invention, a method of forming a pixel structure is proposed. The halogen structure has at least one transistor and a first storage capacitor. The first storage capacitor is electrically connected to the transistor. This formation method includes the following steps 201203559

1 WJ^iUJ^A-D Step: First, a first conductive layer is formed. Next, an inner dielectric layer is overlaid on the first conductive layer and has a first opening. Then, a second conductive layer is formed on the portion of the inner dielectric layer, and is electrically connected to the first conductive layer via the first opening. Next, a protective layer is covered on the transistor and the second conductive layer, and has a second opening. Finally, a third conductive layer is formed on the portion of the protective layer and electrically connected to the transistor via the second opening. The first storage capacitor is composed of a third conductive layer, a protective layer and a second conductive layer. In order to make the above description of the present invention more comprehensible, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. The invention is to provide at least one storage capacitor between the conductive materials. The pixel structure. The conductive material includes a light transmissive material, a reflective material, or a combination thereof. Embodiments of the present invention are described in detail by taking a pixel structure of a display panel in an optoelectronic device as an example. Further, the illustration of the embodiments is to omit certain elements in order to clearly show the technical features of the present invention. First Embodiment Referring to Fig. 2A, there is shown a top view of a pixel structure of a first embodiment of the present invention. This embodiment is exemplified by a pixel structure 200 of a display panel in an optoelectronic device. As shown in Fig. 2A, the data line DT2 and the scan line SC2 are electrically connected to the halogen structure 200, respectively. Please refer to FIG. 2B, which is a cross-sectional view showing the structure of the halogen in FIG. 2A. Fig. 2B is a cross-sectional view taken along line 2B-2B' of Fig. 2A. The halogen structure 200 includes 201203559 241/1 mark), a first storage capacitor cs21, a first conductive layer and a germanium dielectric layer 290, a second conductive layer 242, a protective layer 280, and a layer 243. Preferably, the pixel structure 20 〇 selectively broadcasts an H-light pattern layer (not shown) 'located and parallel to the side of at least one of the data lines DT2 and 'to prevent the data line DT2 and the line from being smashed. At least - the edge of the person produces light leakage. The 9(10) fee-f• storage capacitor is electrically connected to the transistor. The inner layer has a wide dielectric = on the first conductive layer 241, and it has an opening. The first layer 242 is formed on a portion of the inner dielectric layer 29, and is connected to the first conductive layer 241 through the opening. The protective layer 280 overlies the electro-crystalline conductive layer 242 and has an opening 282. The third conductive layer 243 is formed on the partial protective layer 280 and is electrically connected to the electrical body via the opening. The first storage capacitor cs2 is composed of a third conductive layer 243, a protective layer 280, and a second conductive layer 242. Referring to Figs. 3A to 3F, the machine diagram of the method for forming the halogen structure of Fig. 2B is shown. The formation method of the halogen structure 2 is as follows: As shown in Fig. 3, a semiconductor layer 22 is formed on the substrate 209, and then an insulating layer 250 is overlaid on the semiconductor layer 22A. The semiconductor layer 22 includes a small number of doped regions 224a, 224b and an intrinsic region 222. In general, the intrinsic region 222 is located between the two doped regions 224a, 22 servants. Preferably, the embodiment of the present invention can selectively add at least one additional doping region between the at least one of the intrinsic product 222 and the two doped regions 224a, 22 and the doped region. The doping concentration is less than the two doping regions 224:, and the intrinsic region 222 may be doped or undoped. If doped, this 201203559

The polarity of the i w^^jur/\-D sign region 222 is preferably substantially different from the polarity of the _ doped region. The doped regions 224a, 224b and the additional intrinsic regions 222 and/or the other two doped positive portions 224a, 224b, the conductor layer 220, or different germanium shapes + may also be selectively formed simultaneously on the material of the semiconductor layer 220. A single f semiconductor layer 220 is included. Furthermore, 'semi-crystalline, polycrystalline cut material, non-S8^ containing bismuth material, microcrystalline stone-containing material, its material, or a combination of the above. When the (4), bismuth-containing material, or layer thereof is formed, as shown in Fig. 3B, the formation of the first conductive layer is increased. At this time, the gate 216 of the transistor is also formed at the same time. The material of the conductive layer 241 is made of a reflective material (such as gold, tin, lead, cadmium, molybdenum, tungsten, titanium, titanium, tantalum, niobium, or 2 materials, or the above oxide, or the above nitride). Or the above-mentioned compound (the above-mentioned alloy, or a combination thereof) is an embodiment, but is not limited thereto. A transparent material (eg, indium tin oxide, samarium oxide, and tin oxide) may also be selectively used. A combination of a material, an indium zinc oxide, a tin oxide, or a tantalum material thereof, or a combination thereof, or a transparent material and a reflective material. In addition, the first conductive layer 241 is connected to an electrode line having a level, for example: \ common electrode line Vcom2, or a portion of the electrode line having a level can be selectively used, for example, a common electrode line 乂_2 The first conductive layer 241 is formed (as shown in FIG. 2A). In this embodiment, the electrode line, for example, the common electrode line Vconi2 is made of a reflective material (eg, gold, silver, copper, iron, tin, lead, cadmium, molybdenum, tungsten, titanium, titanium, tantalum,铪, or other materials, or the above oxides, or the above-described nitrides, or the above-described nitrogen oxides, or the above-described alloys, or a combination thereof, are examples, but are not limited thereto, and also 8 201203559 Λ ** ^ ^ \f L· i &~ can selectively use transparent materials (such as: indium tin oxide, aluminum zinc oxide, aluminum tin oxide, indium zinc oxide, cadmium tin oxide, or other materials, or Combination of the above, or a combination of a transparent material and a reflective material. In other words, the first conductive layer 241 is connected to the electrode lines. For example, the common electrode lines VCQm22 are substantially the same or different in material. Preferably, the two are substantially the same to reduce process complexity. Next, as shown in FIG. 3C, the inner dielectric layer 290 is covered on the insulating layer 250, and an opening 292 is formed in the inner dielectric layer 290 and the two openings 231a and 231b in the inner dielectric layer 290 and the insulating layer 250, respectively. Then, as shown in FIG. 3D, the second conductive layer 242 is formed on a portion of the inner dielectric layer 290, and electrically connected to the first conductive layer 241 and the semiconductor layer 220 via the openings 292, 231a, and 231b, respectively. The second conductive layer 242 electrically connected to the semiconductor layer 220 via the openings 231a, 231b serves as one of the gates 212 and a source 214 of the transistor. In this embodiment, the second conductive layer 242 is made of a reflective material (eg, gold, silver, copper, iron, tin, ship, mine, molybdenum, crane, titanium, titanium, group, feed, or other materials, Or the above-mentioned oxide, or the above-mentioned nitride, or the above-mentioned nitrogen oxide, or the above-mentioned alloy, or a combination thereof, is an embodiment, but is not limited thereto, and a transparent material (for example, indium may be selectively used). Tin oxide, inscription oxide, aluminum tin oxide, indium oxide, cadmium tin oxide, or other materials, or a combination thereof, or a combination of a transparent material and a reflective material. Furthermore, one of the source 214 and the drain 212 of the transistor is electrically connected to the data line DT2 (as shown in FIG. 2A), and the gate 216 of the transistor is electrically connected to the scan line SC2 (eg, Figure 2A shows). It should be noted that the openings 231a, 231b and 292 of the embodiment 201203559 i wjD^urA-ΰ are formed at different times, but are not limited thereto. Alternatively, masks having different transmittances may be selectively used. The yellow light process 'e.g., a half dimming mask, a diffractive reticle, a grid pattern mask, or other reticle, or a combination thereof,' forms openings 231a, 231b, and 292 at the same time. Next, as shown in FIG. 3E, the protective layer 280 is covered on the transistor and the second conductive layer 242, and the protective layer 280 has an opening 282. Finally, as shown in Fig. 3F, a third conductive layer 243 (also referred to as a germanium electrode) is formed on a portion of the protective layer 280, and is electrically connected to the transistor via the opening 282. Wherein the opening 282 is selectively substantially aligned or misaligned with the opening 231b. In this way, the overall pixel structure 2 is as shown in Figure 3F. In this embodiment, the material of the third conductive layer 243 is made of a transparent material (eg, indium tin oxide, aluminum zinc oxide, aluminum tin oxide, indium zinc oxide, cadmium tin oxide, or other materials, Or a combination of the above), but is not limited thereto, and may also selectively use a reflective material (eg, gold, silver, steel, iron, tin, ship, town, molybdenum, crane, record, titanium, group, give) Or other materials, or the above-mentioned oxides, or the above-mentioned nitrides, or the above-mentioned nitrogen oxides, or the above-mentioned alloys, or a combination thereof, or a combination of a transparent material and a reflective material. In the present embodiment, since the first conductive layer 241 and the second conductive layer 242 have a common potential resistance, that is, a parallel design, the electrode lines, for example, the load p of the common electrode line Vc 〇 m2 and the resistance can be reduced. In this way, the cross-talk of the display panel in the photovoltaic device when the display screen is displayed can be avoided. 201203559 Further, at least one of the insulating layer 250, the inner dielectric layer 290, and the protective layer 280 is made of an inorganic material (eg, oxidized ash, nitrite, oxynitride, oxidized, nitriding, carbonized) ;6 eve, or other materials, or a combination of the above), organic materials (such as: photoresist, polyarylene ether (PAE), polyfluorenes, polyesters, polyalcohols, polyolefins, stupid Benzene cycline (BCB), HSQ (hydrogen silsesquioxane), MSQ (methyl silesquioxane), oxime oxycarbide (SiOC-H), or other materials, or a combination thereof, or a combination thereof. The second conductive layer 242 of this embodiment can be selectively made of a reflective bismuth material, a light transmissive material, or a combination thereof. The second conductive layer 242 of the second drawing is an embodiment of the reflective material. Referring to Figure 4, there is shown a cross-sectional view of another pixel structure of the first embodiment. The pixel structure 3gg includes a third conductive layer 343. The second conductive layer 342 is formed on the vine layer 380 and -390 and is electrically connected via the opening 392 to the second conductive layer conductive layer (4) of the inner dielectric layer. The material of the second conductive layer 342 of FIG. 4 is an example of implementation, but is not limited thereto. The above content is described by the light-transmissive material, and the formation method of the alizarin structure 3 is the same as that of the example 200, so it is not: the method and the alizarin structure are, the alizarin structure 200 The second conductive layer 242 is described. However, it is worth noting that the material of the two conductive layers 342 is different from the material: the structure of the halogen structure 300, and the halogen structure 3G〇$ has the above-mentioned embodiment. The same way. And because of the morpheme (not labeled), the -th storage capacitor Cs3i, a first conductive layer (4), the inner dielectric layer 390, the second conductive layer 342, 390 2B, and the 11th 201203559 i wjDJur/ The second conductive layer 342 of the \-0 structure 300 is an embodiment of the light transmissive material, so the halogen structure 300 can be used to match different application embodiments. SECOND EMBODIMENT Referring to Fig. 5A, there is shown a top view of a pixel structure of a second embodiment of the present invention. This embodiment is exemplified by a pixel structure 400 of a display panel in an optoelectronic device. As shown in FIG. 5A, the data lines DT41, DT42 and the scan line SC4 are electrically connected to the halogen structure 400, respectively. Please refer to FIG. 5B, which shows a cross-sectional view of the pixel structure of FIG. 5A. Fig. 5B is a cross-sectional view taken along line 5B-5B' of Fig. 5A. The pixel structure 400 includes a transistor (not labeled), a first storage capacitor Cs41, a first conductive layer 441, an inner dielectric layer 490, a second conductive layer 442, a protective layer 480, and a third conductive layer. Layer 443 and a fourth conductive layer 444. Preferably, the halogen structure 400 can selectively include a light shielding pattern layer located at a side parallel to at least one of the data line DT4 DT42 and the scan line SC4 to prevent the data lines DT41, DT42 and the scan line SC4. Leakage occurs at the edge of at least one of them. The first storage capacitor Cs41 is electrically connected to the transistor. The inner dielectric layer 490 covers the first conductive layer 441 and has an opening 492. The second conductive layer 442 is formed on the portion of the inner dielectric layer 490 and electrically connected to the first conductive layer 441 via the opening 492. The protective layer 480 covers the electromorph and the second conductive layer 442 and has an opening 482. The third conductive layer 443 is formed on the partial protective layer 480 and electrically connected to the transistor via the opening 482. The fourth conductive layer 444 covers the second conductive layer 442 and the portion 12 201203559 TT / I - inner dielectric layer 490, such that the first storage capacitor Cm 丨 is composed of the third conductive layer 443, the protective layer 480, and the fourth The conductive layer 444 and the second conductive layer 442 are formed. Referring to Figures 6A to 6G, there is shown a flow chart of a method of forming the pixel structure of Figure 5B. The pixel structure 400 is formed as follows: As shown in Fig. 6A, a semiconductor layer 420 is formed on the substrate 409, and then an insulating layer 450 is overlaid on the semiconductor layer 420. The semiconductor layer 420 includes at least one dummy region 424a, 424b and an intrinsic region 422. Typically, the intrinsic region 422 is located between the two doped regions 424a, 424b. Preferably, the embodiment of the present invention selectively adds at least another doped region between at least one of the intrinsic region 422 and the two doped regions 424a, 42. The concentration is substantially smaller than the at least one of the two doped regions 42 and the intrinsic region 422 can travel to the polar spot of the sigma θ θ region 422 - or do not push the impurity, if doped, the polarity of the present The essence is pure; ^ H4 is called, 424b and the doped area of the material is intrinsic... or another heterogeneous zone - ^ 420 in the conductor layer or different sputum formations simultaneously formed in the semi-conductive layer 42 〇 When the film is formed into a semiconductor layer. Furthermore, tantalum, polycrystalline cut material, amorphous = stone-containing material, microcrystalline cut material, its material, or a combination of the above. The material of the eve, the material containing the error, or it, then, as shown in Figure 6, layer 450. At this time, one of the 1 crystals is closed with the second conductive layer 441. In the insulating embodiment, the first conductive layer 441 416 is also formed at the same time. In this silver, steel, iron, tin, lead, koi from the culvert, crane, money, 〖, wrong, cake, / quality is reflective material (such as: gold, or titanium, group, give 13 201203559

1 wjjjur / \-D other materials, or the above oxides, or the above nitrides, or the above II oxides, or the above alloys, or a combination thereof, are examples, but are not limited thereto, and may be selected Use transparent materials (such as: indium tin oxide, Cui Lu zinc oxide, Ming tin oxide, indium zinc oxide, tin oxide, or other materials, or a combination of the above), or transparent and reflective materials The combination. In addition, the first conductive layer 441 is connected to a level electrode line, for example, the common electrode line Vcom4 (as shown in FIG. 5A), but is not limited thereto, and some partially-positioned electrodes may be selectively used. A line, for example, a common electrode line VC() m4 is regarded as the first conductive layer 441. In this embodiment, the electrode wire, for example, the common electrode wire Vcom4 is made of a reflective material (eg, gold, silver, copper, iron, tin, erroneous, braided, copper, crane, tantalum, titanium, group,铪, or other materials, or the above oxides, or the above-described nitrides, or the above-described nitrogen oxides, or the above-described alloys, or a combination thereof, are examples, but are not limited thereto, and may be selectively used. A transparent material (such as indium tin oxide, is zinc oxide, tin oxide, indium zinc oxide, tin oxide, or other materials, or a combination thereof), or a combination of a transparent material and a reflective material. In other words, the first conductive layer 441 is connected to the electrode lines. For example, the materials of the common electrode lines VC() m4 are substantially the same or different, and preferably, they are substantially the same to reduce the process complexity. Next, as shown in FIG. 6C, the inner dielectric layer 490 is covered on the insulating layer 450, and an opening 492 is formed in the inner dielectric layer 490 and the two openings 431a and 431b in the inner dielectric layer 490 and the insulating layer 450, respectively. Then, as shown in FIG. 6D, the second conductive layer 442 is formed on a portion of the inner dielectric layer 490, and is electrically connected to the first conductive layer 441 and the semiconductor layer via openings 492, 431a, and 431b, respectively. 420. The second conductive layer 442 electrically connected to the semiconductor layer 42A via the openings 43,1a, 431b is used as a crystal cell and a source. In the present embodiment, the material of the second conductive layer 442 is a reflective material (eg, gold, silver, copper, iron, tin, lead, cadmium, molybdenum, tungsten, titanium, titanium, button, bismuth, or other material). Or the above-mentioned oxide, or the above-mentioned nitride, or the above-mentioned gas oxide, or the above-mentioned alloy, or a combination thereof, is an embodiment, but is not limited thereto, and a transparent material (eg, indium may also be selectively used). Tin oxide, zinc oxide, aluminum tin oxide, indium zinc oxide, cadmium tin oxide, or other materials, or a combination thereof, or a combination of a transparent material and a reflective material. Furthermore, one of the drain 412 and the source 414 of the transistor is electrically connected to the data lines DT41 and DT42 (as shown in FIG. 5A), and the gate 416 of the transistor is electrically connected to the scan line sc4 ( As shown in Figure 5A). It should be noted that 'the openings 431a, 431b, and 492 of the present embodiment are formed at different times, but are not limited thereto, and a mask having different transmittances may be selectively used (eg, a half dimming cover, The yellow light process of the diffractive reticle, the grid pattern mask, or other reticle, or a combination thereof, forms openings 431a, 431b, and 492 at the same time. Next, as shown in FIG. 6E, the fourth conductive layer 444 is covered on the second conductive layer 442 and a portion of the inner dielectric layer 490. In the present embodiment, the material of the fourth conductive layer 444 is a light-transmitting material as an embodiment. However, the present invention is not limited thereto, and a reflective material or a combination of a light-transmitting material and a reflective material may be selectively used. In addition, since the second conductive layer 441, the second conductive layer 442, and the fourth conductive layer 444 are electrically connected to each other, the first conductive layer 441, 15 201203559 I ^353ϋ^Α-0 the second conductive layer 442 and the fourth conductive The level of layer 444 is substantially the same. The levels of the first conductive layer 441, the second conductive layer 442, and the fourth conductive layer 444 include, for example, a common level. In addition, in this embodiment, the first parasitic capacitance is between the drain 412 and the scan line SC4, and the sum of the capacitances between the drain 412 and the data lines DT41 and DT42 is substantially a second parasitic capacitance. . In addition, a pixel capacitor (not shown) is disposed between the pixel electrode of the pixel structure 400 and the common electrode (not shown). The halogen capacitor of the halogen structure 400 is substantially equal to the sum of the liquid crystal capacitance and the first storage capacitor Cs41. The area of the fourth conductive layer 444 is determined by the ratio of the first parasitic capacitance to the pixel capacitance, the ratio of the second parasitic capacitance to the pixel capacitance, and the ratio of the first storage capacitor Cs41 to the liquid crystal capacitance. The area of the fourth conductive layer 444 in the present embodiment is preferably substantially larger than the area of the second conductive layer 442, but is not limited thereto, and the fourth conductive layer 444 may be selectively changed according to design requirements. The area is, for example, substantially smaller than the area of the second conductive layer 442, substantially equal to the area of the second conductive layer 442, or a combination thereof. Then, as shown in FIG. 6F, the protective layer 480 is overlaid on the transistor and the second conductive layer 442, and the protective layer 480 has an opening 482. Finally, as shown in Fig. 6G, a third conductive layer 443 (also referred to as a germanium electrode) is formed on a portion of the protective layer 480, and is electrically connected to the transistor via the opening 482. Therein, the opening 482 can selectively substantially align or misalign the opening 431b. As a result, the overall pixel structure 400 is as shown in Fig. 6G. In this embodiment, the material of the third conductive layer 443 is made of a transparent material (eg, indium tin oxide, zinc oxide, tin oxide, indium 201203559 扈«) zinc oxide, tin tin oxide, Or other materials, or a combination thereof, is an example, but is not limited thereto, and a reflective material may also be selectively used (eg, gold, silver, copper, iron, tin, wrong, recorded, scorpion, crane, Syria, Chin) , a group, a feed, or another material, or an oxide of the above, or a nitride as described above, or an oxynitride as described above, or an alloy of the foregoing, or a combination thereof, or a combination of a transparent material and a reflective material. In the embodiment, the fourth conductive layer 444 is made of a light-transmitting material. Therefore, the pixel structure 400 can increase the aperture ratio without changing the capacitance value, but is not limited thereto, and a reflective material or a light-transmitting material can also be used. A combination of reflective materials. In addition, the fourth conductive layer 444 can selectively overlap with any gate line or data line, thereby reducing the load on the gate color or data line, but is not limited thereto, and can also be selectively partially overlapped. Furthermore, the first conductive layer 441, the second conductive layer 442, and the fourth conductive layer 444 have a common potential resistance, that is, a parallel design, so that the load impedance of the electrode line, for example, the common electrode line Vcom4 can be reduced. In this way, the crosstalk phenomenon occurs when the display panel of the optoelectronic device is displayed on the display screen. Further, the material of at least one of the insulating layer 450, the inner dielectric layer 490 and the protective layer 480 includes an inorganic material (eg: Cerium oxide, tantalum nitride, niobium oxynitride, antimony oxide, tantalum nitride, tantalum carbide, or other materials, or a combination thereof, organic materials (eg, photoresist, polystyrene ether (PAE)) , polyfluorenes, polyesters, polyalcohols, polyolefins, benzocyclclobutene (BCB), HSQ (hydrogen silsesquioxane), MSQ (methyl silesquioxane), shixi oxygenation 17 201203559

i wj^jur/\-D (SiOC-H), or other materials, or a combination thereof, or a combination thereof. THIRD EMBODIMENT Referring to Fig. 7A, there is shown a top plan view of a halogen structure of a third embodiment of the present invention. This embodiment is exemplified by a pixel structure 500 of a display panel in an optoelectronic device. As shown in Fig. 7A, the data line DT5 and the scan line SC5 are electrically connected to the pixel structure 500, respectively. Please refer to FIG. 7B, which shows a cross-sectional view of the pixel structure of FIG. 7A. Fig. 7B is a cross-sectional view taken along line 7B-7B' in Fig. 7A. The halogen structure 500 includes a transistor (not labeled), a first storage capacitor Cs51, a second storage capacitor Cs52, a third storage capacitor Cs53, a first conductive layer 541, an inner dielectric layer 590, and a first The second conductive layer 542, an insulating layer 550, a semiconductor layer 520, a protective layer 580, and a third conductive layer 543. Preferably, the halogen structure 500 can optionally include a light shielding pattern layer (not shown) located at a side parallel to at least one of the data line DT5 and the scan line SC5 to prevent the data line DT5 and the scan line. Light leakage occurs at the edge of at least one of the SC5. The first storage capacitor Cs51 is electrically connected to the transistor. The inner dielectric layer 590 covers the first conductive layer 541 and has an opening 592. The second conductive layer 542 is formed on the portion of the inner dielectric layer 590 and is electrically connected to the first conductive layer 541 via the opening 592. The protective layer 580 covers the electromorph and the second conductive layer 542 and has an opening 582. The third conductive layer 543 is formed on the partial protective layer 580 and electrically connected to the transistor via the opening 582. The first storage capacitor Cs51 is composed of a third conductive layer 543, a protective layer 201203559 580, and a second conductive layer 542. The second storage capacitor Cs52 is composed of a first conductive layer 541, an insulating layer 550, and a portion of the semiconductor layer 520. The third storage capacitor Cs53 is composed of a second conductive layer 542, an inner dielectric layer 590, an insulating layer 550, and a portion of the semiconductor layer 520. Please refer to Figs. 8A to 8F for a flow chart showing a method of forming the pixel structure of Fig. 7B. The pixel structure 500 is formed by forming a semiconductor layer 520 on the substrate 509 as shown in Fig. 8A, and then covering an insulating layer 550 on the semiconductor layer 520, respectively. The semiconductor layer 52A includes at least two doped regions 524a, 524b and an intrinsic region 522. The doped region 524a of this embodiment extends below the first metal layer 541 as an example embodiment. In general, the intrinsic region 522 is located between the two doped regions 524 & 524b. Preferably, in the embodiment of the present invention, at least one additional doping region is selectively added between at least one of the intrinsic region 522 and the two doping regions 524a, 524b, and the doping of the additional doping region is selectively performed. The concentration is substantially less than at least one of the two doped regions 524a, 524b, and the intrinsic region 522 can be doped: undoped, if doped, the polarity of the intrinsic region 522 and the two doped regions 52, 2 Preferably, the polarity of the additional doped regions is substantially different from the doped regions 524a, 164, and/or additional regions, and may also be formed on the semiconductor layer 52. Medium or not at the same time: guide. Furthermore, the material of the semiconductor layer 52G includes a single crystal containing a cut material, a microcrystalline cut material, a polycrystalline cut material, and an amorphous one.

Quality, inclusion material, or other materials, or a combination of the above. S then, as shown in Figure 8B, on layer 550. At this time, one of the transistors forms the first conductive layer 541 at the same time as the insulating gate 516. Yu Ben 201203559

1 wjjjur/\-D In the embodiment, the material of the first conductive layer 541 is made of reflective material (such as: gold, silver, copper, iron, tin, wrong, braided, key, crane, titanium, chin, group, give, Or other materials, or the above-mentioned oxides, or the above-mentioned nitrides, or the above-mentioned nitrogen oxides, or the above-mentioned alloys, or a combination thereof, are examples of 'but are not limited thereto, and transparent materials may be selectively used. (eg, indium tin oxide, zinc oxide, sulphur oxide, indium zinc oxide, tin oxide, or other materials, or combinations thereof) or a combination of transparent and reflective materials. In addition, the first conductive layer 541 is connected to a level electrode line, for example, the common electrode line Vcom5 (as shown in FIG. 7A), but is not limited thereto, and some partially-positioned electrodes may be selectively used. A line, for example, a common electrode line 乂(3)(10) is regarded as the first conductive layer 541. In this embodiment, the material of the common electrode line VC()m5 is a reflective material (eg, gold, silver, copper, iron, tin, erroneous, tin, key, crane, Syria, titanium, group, 铪, Or other materials, or the above oxides, or the above-mentioned nitrides, or the above-mentioned nitrogen oxides, or the above-mentioned alloys, or a combination thereof, are examples, but are not limited thereto, and transparent materials may be selectively used. (eg, indium tin oxide, zinc oxide, sulphur oxide, indium oxide, cadmium tin oxide, or other materials, or combinations thereof), or a combination of transparent materials and reflective materials. In other words, the first conductive layer 541 is connected to the electrode lines. For example, the materials of the common electrode lines Vccm5 are substantially the same or different, and preferably, they are substantially the same to reduce the process complexity. As described above, the doping region 524a of the semiconductor layer 520 of the present embodiment extends below the first metal layer 541 as an example. Therefore, the second storage capacitor Cs52 is composed of the first conductive layer 541, the insulating layer 550, and the partial semiconductor layer 520. It should be noted that the semiconductor layer 520 extending below the first metal layer 541 201203559 1 yy may also selectively connect the semiconductor layer 520 under the gate 516 through a connection layer (not shown). The semiconductor layer 520 extending below the first metal layer 541 includes at least one of at least one doped region 524a/524b, at least one other doped region, and at least one intrinsic region 522. The material of the connection layer may use at least one of the first conductive layer 541, the second conductive layer 542, the third conductive layer 543, and the semiconductor layer 520. Next, as shown in FIG. 8C, the inner dielectric layer 590 is covered on the insulating layer 550, and an opening 592 is formed in the inner dielectric layer 590 and the two openings 531a and 531b in the inner dielectric layer 290 and the insulating layer 550, respectively. Then, as shown in FIG. 8D, the second conductive layer 542 is formed on a portion of the inner dielectric layer 590, and electrically connected to the first conductive layer 541 and the semiconductor layer 520 via openings 592, 531a, and 531b, respectively. The second conductive layer 542 electrically connected to the semiconductor layer 520 via the openings 531a, 531b serves as one of the gates 512 and a source 514 of the transistor. In this embodiment, the second conductive layer 542 is made of a reflective material (eg, gold, silver, copper, iron, tin, boat, braid, molybdenum, tungsten, ruthenium, titanium, group, feed, or other materials, Or the above-mentioned oxide, or the above-mentioned nitride, or the above-mentioned nitrogen oxide, or the above-mentioned alloy, or a combination thereof, is an embodiment, but is not limited thereto, and a transparent material (for example, indium may be selectively used). Tin oxide, zinc oxide, aluminum tin oxide, indium zinc oxide, cadmium tin oxide, or other materials, or a combination thereof, or a combination of a transparent material and a reflective material. Furthermore, one of the source 514 and the drain 512 of the transistor is electrically connected to the data line DT5 (as shown in FIG. 7A), and the gate 516 of the transistor is electrically 21 201203559 1 wj3^urA-0 Connected to the line SC5 (as shown in Figure 7A). It should be noted that the openings 531a, 531b, and 592 of the embodiment are formed at different times, but are not limited thereto, and a mask having different transmittances may be selectively used (eg, a half dimming cover, The yellow light process of the diffractive reticle, the grid pattern mask, or other reticle, or a combination thereof, forms openings 531a, 531b, and 592 at the same time. Next, as shown in FIG. 8E, the protective layer 580 is covered on the transistor and the second conductive layer 542, and the protective layer 580 has an opening 582. Finally, a third conductive layer 543 (also referred to as a pixel electrode) is formed on a portion of the protective layer 580 as shown in FIG. 8F, and is electrically connected to the transistor via the opening 582. Therein, the opening 582 can selectively substantially align or misalign the opening 531b. The third storage capacitor CS53 is composed of a second conductive layer 542, an inner dielectric layer 590, an insulating layer 550, and a portion of the semiconductor layer 520. As a result, the overall pixel structure 500 is as shown in Fig. 8F. In this embodiment, the material of the third conductive layer 543 is made of a transparent material (eg, indium tin oxide, aluminum zinc oxide, aluminum tin oxide, indium zinc oxide, cadmium tin oxide, or other materials, Or a combination of the above) is an embodiment, but is not limited thereto. A reflective material (eg, gold, silver, steel, iron, tin, lead, cadmium, molybdenum, tungsten, titanium, titanium, tantalum, etc.) may also be selectively used. A combination of a material or a material, or an oxide of the above, or a nitride of the above, or an oxynitride of the above, or an alloy of the above, or a combination thereof, or a transparent material and a reflective material. In the present embodiment, the first conductive layer 541 and the second conductive layer 542" are a common-potential resistor', that is, a parallel design', thereby reducing the load impedance of the electrode lines, for example, the common electrode line Vcom5. In this way, you can avoid 22 201203559 1 WJJJUrM-L) The display panel in the optoelectronic device generates crosstalk when displaying the kneading surface. In addition, the doped region 524a of the semiconductor layer 520 of the present embodiment extends to the lower side of the first conductive layer 541 as an example to further form the second storage valley CS52 and the second storage capacitor CS53. Furthermore, at least one of the insulating layer 550, the inner dielectric layer 590 and the protective layer 580 is made of an inorganic material (eg, cerium oxide, tantalum nitride, lanthanum oxynitride, cerium oxide, tantalum nitride, tantalum carbide, Or other materials, or a combination of the above, organic materials (such as: photoresist, polyacrylic acid ether (PAE), polystyrene, polyester, polyalcohol, polyene, benzo ring Benzocycline (BCB), HSQ (hydrogen silsesquioxane), MSQ (methyl silesquioxane), Shihe oxygen hydrocarbon (SiOC-H), or other materials, or a combination thereof, or a combination thereof. The second conductive layer 542 of this embodiment can be selectively made of a reflective material, a light transmissive material, or a combination thereof. The second conductive layer 542 of FIG. 7B is an embodiment of a reflective material. Referring to Figure 9, there is shown a cross-sectional view of another pixel structure of the third embodiment. The halogen structure 600 includes a transistor (not labeled), a first storage capacitor Cs6i, a second storage capacitor cs62, a third storage capacitor Cs63, a first conductive layer 641, an inner dielectric layer 690, and a first The second conductive layer 642, a semiconductor layer 620, an insulating layer 650, a protective layer 680, and a third conductive layer 643. The second conductive layer 642 is formed on the portion of the inner dielectric layer 690 and is electrically connected to the first conductive layer 641 via the opening 692. The material of the second conductive layer 542 in FIG. 7B is a reflective material, and the material of the second conductive layer 642 in FIG. 9 is a light-transmitting material, but is not limited thereto. The above content is based on the picture. 23 201203559

The i wj^jupa-D structure 500 is an example for explaining the formation method thereof, and the method of forming the pixel structure 600 is the same as the method of forming the pixel structure 500, and therefore, the description will not be repeated. It should be noted, however, that the material of the second conductive layer 542 of the halogen structure 500 and the second conductive layer 642 of the halogen structure 600 is a different example of the material. Similarly, the halogen structure 600 also has the above-described manner. Moreover, since the second conductive layer 642 of the pixel structure 600 is an example of a light transmissive material, the halogen structure 600 can be used to suit different application implementations. Fourth Embodiment Referring to Fig. 10A, there is shown a top view of a pixel structure of a fourth embodiment of the present invention. This embodiment is exemplified by a pixel structure 700 of a display panel in an optoelectronic device. As shown in Fig. 10A, the data lines DT7, DT72, and the scan lines SC7 are electrically connected to the halogen structure 700, respectively. Please refer to FIG. 10B, which is a cross-sectional view showing the structure of the halogen in FIG. 10A. Fig. 10B is a cross-sectional view taken along line 10B-10B' of Fig. 10A. The pixel structure 700 includes a transistor (not labeled), a first storage capacitor Cs71, a second storage capacitor Cs72, a third storage capacitor Cs73, a first conductive layer 741, an inner dielectric layer 790, and a first The second conductive layer 742, the semiconductor layer 720, the insulating layer 750, a protective layer 780, a third conductive layer 743, and a fourth conductive layer 744. Preferably, the halogen structure 700 can selectively include a light shielding pattern layer (not shown) located at a side parallel to at least one of the data lines DT71, DT72 and the scan line SC7 to prevent the data line DT71, The edge of at least one of DT72 and scan line SC7 produces light leakage. 201203559 Image. The first storage capacitor Cm is electrically connected to the transistor. The inner dielectric layer 790 overlies the first conductive layer 741 and has an opening 792. The first conductive layer 742 is formed on the portion of the inner dielectric layer 790 and is electrically connected to the first conductive layer 741 via the gate 792. The protective layer 78 is on the body and the second conductive layer 742 and has an opening 782. The third conductive layer 743 is formed on a portion of the protective layer 780 and is electrically connected to the transistor via the opening 782. The fourth conductive layer 744 covers the second conductive layer 742 and the portion of the inner dielectric layer 790 such that the first storage capacitor 〇 is still replaced by the third conductive layer 743, the protective layer 780, the fourth conductive layer 744, and the second The conductive layer 742 is formed. The second storage capacitor CS72 is composed of a first conductive layer 741, an insulating layer 75A, and a portion of the semiconductor layer 720. The third storage capacitor 〇 (7) is composed of a second conductive layer 742, a fourth conductive layer 744, an inner dielectric layer 79, a second edge layer, a 75 Å layer, and a portion of the semiconductor layer 720. Please refer to the 11A-11G diagram, which shows the flow chart of the method of the 昼素社=成成. A method of forming the halogen structure 7 (8): as shown in the lower drawing, a semiconductor layer 72 is formed on the substrate 709, and a germanium-insulating layer 750 is formed on the semiconductor layer 72. The semiconductor layer 72 includes a doped region 724a, 724b and an intrinsic region 722. In this embodiment, the 724a' is extended below the first metal layer % for the implementation of the first embodiment. The 'intrinsic region 722 is located in the two doped regions, and the other is doped. In the embodiment of the present invention, the present invention can be selected. Sexually adding at least one less one... between the intrinsic area 722 and the two holding areas 72, 72, and the doping concentration of the other doped regions is substantially less than two pushes 25 201203559

1 W3^JUKA-D at least one of the 724a, 724b, and the "intrinsic region 722 may or may not be doped with another doping" 'the polarity of the 722 and the two doped regions 724a, 724b The polarity is preferably different from true f. In addition, two dopings 724a, 724b, intrinsic region 722, and/or alternatively formed simultaneously in the semiconductor layer 720 are formed in two 720. 'Semiconductor layer 72 is formed in the +conductor layer crystallites containing the tree, multi-day ~ (four) single crystal cut material, wrong material, or its material: then as shown in Figure 11B, forming the first conductive layer 74i is on the second 750. At this time, the gate-gate μ of the transistor is also formed at the same time. In the present invention, the material of the first conductive layer 741 is made of anti-gold, its ruthenium material, or the above oxide. Or the above, the sub-oxygen oxide, or the alloy described above, or a combination thereof, may also optionally use a transparent material (eg, indium tin di-zinc oxide, aluminum tin oxide, indium zinc) Oxidizing other materials, or a combination of the above, & 'smoke, or a combination of 1 and a reflective material. = First conductive layer 741 is connected to one The electrode wire with a standard position is as shown in the figure, but is not limited to = Π use some electrode wire with a standard position, for example: common electricity:: two widely used as the first conductive layer 541. Among them, in this implementation In the example, electric: .. The material of the common electrode line Vcom7 is a reflective material (such as: life:, steel, iron, kick, wrong, mine, crane, Syria, titanium, group, gold, other materials f, Or the above-mentioned oxide, or the above-mentioned nitride, or the above-mentioned alloy, or the above-mentioned alloy, or a combination thereof, is an example, but is not limited thereto, and a transparent material may be selectively used ( Such as: indium tin oxide, smectite oxide, tin oxide, indium zinc oxide, tin oxide, or other materials, or a combination of the above, or a combination of transparent and reflective materials. In other words, the first The conductive layer 741 is connected to the electrode lines. For example, the materials of the common electrode lines Vcom7 are substantially the same or different. Preferably, the two are substantially the same to reduce the process complexity. As described above, the semiconductor layer 720 of the present embodiment is doped. The impurity region 724a extends to the first metal layer 741 The second storage capacitor Cs72 is composed of a first conductive layer 741, an insulating layer 750, and a portion of the semiconductor layer 720. It should be noted that the semiconductor layer 720 extending below the first metal layer 741 may also be Optionally, the semiconductor layer 720 under the gate 716 is connected through a connection layer (not shown), wherein the semiconductor layer 720 or the block extending below the first metal layer 741 includes at least one doped region 724a/724b At least one of another doped region and at least one intrinsic region 722. The material of the connecting layer may be a first conductive layer 741, a second conductive layer 742, a third conductive layer 743, and a semiconductor layer 720. At least one of them. Next, as shown in FIG. 11C, the inner dielectric layer 790 is covered on the insulating layer 750, and an opening 792 is formed in the inner dielectric layer 790 and the two openings 731a and 731b in the inner dielectric layer 790 and the insulating layer 750, respectively. Then, as shown in FIG. 11D, the second conductive layer 742 is formed on a portion of the inner dielectric layer 790, and electrically connected to the first conductive layer 741 and the semiconductor layer 720 via the openings 792, 731a, and 731b, respectively. The second conductive layer 27 201203559 742 electrically connected to the semiconductor layer 720 via the openings 731a, 731b serves as one of the transistor 712 and a source 714. In this embodiment, the material of the second conductive layer 742 is made of a reflective material (eg, gold, silver, copper, iron, recorded, ship, recorded, molybdenum, crane, Syrian, Chin, group, give, or other materials, Or the above-mentioned oxide, or the above-mentioned nitride, or the above-mentioned nitrogen oxide, or the above-mentioned alloy, or a combination thereof, is an embodiment, but is not limited thereto, and a transparent material (eg, indium may also be selectively used). Tin oxide, aluminum zinc oxide, aluminum tin oxide, indium zinc oxide, cadmium tin oxide, or other materials, or a combination thereof, or a combination of a transparent material and a reflective material. One of the drain 712 and one source 714 of the transistor is electrically connected to the semiconductor layer 720 by openings 731a, 731b. Furthermore, one of the source 714 and the drain 712 of the transistor is electrically connected to the data line DT7 DT72 (as shown in FIG. 10A), and the gate 716 of the transistor is electrically connected to the scan line SC7 ( As shown in the figure ι〇Α). It should be noted that the openings 731a, 731b, and 792 of the embodiment are formed at different times, but are not limited thereto, and a mask having different transmittances may be selectively used (eg, a half dimming cover, The yellow light process of the diffractive reticle, the grid pattern mask, or other reticle, or a combination thereof, forms openings 731a, 731b, and 792 at the same time. Next, as shown in FIG. 11E, the fourth conductive layer 744 is covered on the second conductive layer 742 and a portion of the inner dielectric layer 79. In the present embodiment, the material of the fourth conductive layer 744 is a light-transmitting material as an embodiment. However, the present invention is not limited thereto, and a reflective material or a combination of a light-transmitting material and a reflective material may be selectively used. In addition, since the first conductive layer 741, the second conductive layer 742, and the fourth conductive layer 744 are electrically connected to each other, the levels of the first conductive layer 741, the second conductive layer 742, and the fourth conductive layer 744 are substantially the same. . 28 201203559 a ι-ν-ό and the levels of the first conductive layer 741, the second conductive layer 742, and the fourth conductive layer 744 include 'for example, a common level. In addition, in the present embodiment, the first parasitic capacitance is between the drain 712 and the scan line SC7, and the sum of the capacitances between the drain 712 and the data line DT7 and DT72 is substantially a second parasitic capacitance. . In addition, a pixel capacitor (not shown) is disposed between the pixel electrode of the pixel structure 700 and the common electrode (not shown). The pixel capacitance of the halogen structure 700 is substantially equal to the sum of the liquid crystal capacitance and the first storage capacitance Cs71. The area of the fourth conductive layer 744 is determined by the ratio of the first parasitic capacitance to the pixel capacitance, the ratio of the second parasitic core to the halogen electrode, and the ratio of the first storage capacitor Cs7i to the liquid crystal capacitance. The area of the fourth conductive layer 744 in the present embodiment is preferably substantially larger than the area of the first conductive layer 742, but is not limited thereto, and the fourth conductive layer 744 may be selectively changed according to design requirements. The area 'is, for example, actually smaller than the area of the first conductive layer 742, which is substantially equal to the area of the second conductive layer 74: or a combination thereof. The cover protective layer 780 is shown on the transistor and the H-th layer 742, and the protective layer _ is opened. After the break, if the first solid layer _ 昼 电 电 彳 彳 彳 , , , , , , , , 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三The opening 73lb, the middle opening 782 can selectively substantially align or not the dielectric layer 790, the third storage capacitor Cs73 is formed by the second conductive layer 742, the inner layer 750 and the partial semiconductor layer 720 In this embodiment, the flute structure is as shown in the UG diagram. The material of the conductive layer 743 is made of a transparent material (eg, indium 29 201203559).

1 WJ^JOPA-D tin oxide, sulphur oxide, sulphur tin oxide, indium zinc oxyoxide, or other materials, or a combination of the above) is an example, but not limited thereto, and optionally Using a reflective material (eg, gold, silver, steel, iron, tin, lead, cadmium, molybdenum, tungsten, titanium, titanium, niobium, tantalum, or oxides thereof, or nitrides thereof, or nitrogen oxides as described above) In the present embodiment, the fourth conductive layer 744 is made of a light material, and the pixel structure 700 can be used without changing the capacitance value, in the embodiment, the transparent material and the reflective material. Add this to the 'reflective material, or light-transmitting material and reflective material: combination. In addition, the fourth conductive layer 744 can be mass-produced to the m. The selected ground does not overlap with any of the gate lines. Therefore, the gate line load can be reduced, but it is not limited thereto, and may also be selected. Partially overlapping. And * the first conductive layer 741, the second conductive ^742 layer 744 is a common potential resistor, and the fourth conductive electrode line, for example: the common electrode line ν #δ and 6 ten, so the power can be reduced to avoid _ - II I: load impedance. So - come, like. In the device, when the panel is displayed, the crosstalk is generated to the doped region 724a of the semiconducting layer 720, and the lower portion of the *-conducting layer 741 is taken as an example to further shape the first storage capacitor cS72. And the third storage capacitor Cs73 ^ to 丨 'insulating layer 750, the inner dielectric layer 79 〇 and the protective layer of oxygen cut, quality, including inorganic materials (such as: oxidized hair, nitride dream, nitrogen, yttrium oxide, tantalum nitride) , carbon cut, or other materials f, or the combination of 201203559 tr\m0), organic materials (such as: photoresist, polyarylene ether (PAE), polyfluorenes, polyesters, polyols, poly Alkene, benzocyclclobutene 'BCB, HSQ (hydrogen silsesquioxane), MSQ (methyl silesquioxane), oxygenated hydrocarbon (SiOC-H), or other materials, or a combination thereof, or The combination. The halogen structure disclosed in the above embodiment of the present invention has at least one storage capacitor between the conductive materials. In the above embodiments, the application of the conductive material includes a light transmitting material, a reflective material, or a combination thereof. For example, since the fourth conductive layers 444 and 744 in the embodiment are made of a light-transmitting material, the halogen structures 400 and 700 can maintain the original capacitance value and further increase the aperture ratio. In addition, the arrangement of the fourth conductive layers 444, 744 can be selectively overlapped with any gate lines or data lines, so that the arrangement of the fourth conductive layers 444, 744 can reduce the gates in addition to the above advantages. The load on the line or data line, but not limited to this, may also be partially partially overlapped. Further, since the first, second, fourth, and fifth embodiments are the first and second conductive layers having a common potential resistance, that is, a parallel design, the first and third embodiments of the third and sixth embodiments are The second and fourth conductive layers are also designed in parallel, so the application of these embodiments can reduce the load impedance of the electrode lines. In this way, crosstalk can be avoided when the display panel in the optoelectronic device displays the kneading surface. In addition, the electrode line having the level as described in the above embodiment of the present invention is a common electrode line (Vc〇m) having a common level, but is not limited thereto, and may have a variable level. Electrode wire or its level electricity 31 201203559

TVV353WA-D pole line (eg: gate level, or other level). Figure 12 is a schematic view of the photovoltaic device of the present invention. The photovoltaic device 8 is a pixel structure 2 〇〇 to 700 which is described in the above embodiment. The optoelectronic device 800 further has an electronic component 82 connected to the display panel 810, such as: a control component, an operation component, a processing component, an input component, a memory component, a driving component, a light emitting component, a protection component, a sensing component, and a detecting component. , or other functional elements, or a combination of the above. Plastic devices such as optoelectronic devices include portable products (such as mobile phones, cameras, cameras, notebook computers, game consoles, watches, music players, electronic photos, e-mail transceivers, map navigators or similar products). ), audio and video products (such as audio and video projectors or similar products), screens, televisions, indoor or outdoor billboards, panels in projectors, etc. In addition, the display panel 810 includes a liquid crystal display panel (eg, a transmissive panel, a transflective panel, a reflective panel, a double-sided display panel, a vertical alignment panel (VA), a horizontal switching panel (IPS), and more Domain Vertical Alignment Panel (MVA), Twisted Nematic Panel (TN), Super Twisted Nematic Panel (STN), Pattern Vertical Alignment Panel (pvA), Super Pattern Vertical Alignment Panel (S-PVA), Advanced Large viewing angle panel (ASV), edge electric field switching panel (FFS), continuous flame-like array panel (CPA), axisymmetric array of microcell panels (ASM), optically compensated curved array panel (〇CB), super level Switching Panel (S-IPS), Advanced Super Horizontal Switching Panel (AS-IPS), Extreme Edge Electric Field Switching Panel (UFFS), Polymer Stabilized Alignment Panel (PSA) 'Double Viewing Panel (dual-view) , a triple-view, or a color filter integrated into a matrix (c〇1〇r filter on array; COA) type panel, or a matrix integrated on a color filter 32 201203559 1 τν (array on color filter; AOC) type panel, or other type of panel Or a combination of the above.), an organic electroluminescent display panel, depending on at least one of a pixel electrode and a drain electrode in the panel, such as a liquid crystal layer or an organic light-emitting layer (eg, a small molecule, A polymer, or a combination thereof, or a combination thereof. In the above, the present invention has been disclosed in the above preferred embodiments, but it is not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. [Simple description of the drawing] Fig. 1 is a cross-sectional view showing the structure of a conventional halogen element. Fig. 2A is a schematic view showing the structure of the halogen element of the first embodiment of the present invention. Fig. 2B is a cross-sectional view showing the structure of the halogen in Fig. 2A. 3A to 3F are flow charts showing a method of forming a halogen structure in Fig. 2B. Fig. 4 is a cross-sectional view showing another pixel structure of the first embodiment. Fig. 5A is a schematic view showing the pixel structure of the second embodiment of the present invention. Fig. 5B is a cross-sectional view showing the pixel structure of Fig. 5A. Figs. 6A to 6G are views showing a flow chart of a method of forming a halogen structure in Fig. 5B. 33 201203559

1 W3!) 3UPA-D Fig. 7A is a view showing the pixel structure of the third embodiment of the present invention. Fig. 7B is a cross-sectional view showing the pixel structure of Fig. 7A. Figs. 8A to 8F are views showing a flow chart of a method of forming a halogen structure in Fig. 7B. Figure 9 is a cross-sectional view showing another unitary structure of the third embodiment. Fig. 10A is a top plan view showing the pixel structure of the fourth embodiment of the present invention. Fig. 10B is a cross-sectional view showing the structure of the halogen in Fig. 10A. 11A to 11G are flowcharts showing a method of forming the halogen structure of Fig. 10B. Figure 12 is a schematic view of the photovoltaic device of the present invention. [Description of main component symbols] 100, 200, 300, 400, 500, 600, 700: Alizarin structure 101: Capacitance electrodes 102, 280, 380, 480, 580, 680, 780: Protective layer 103: pixel electrode 109, 209, 409, 509 '709: substrate 112, 212, 412, 512, 712: drain 114, 214 ' 414, 514, 714: source 116, 216, 416, 516, 716: gate 120, 220, 420 , 520, 620, 720: semiconductor layers 150, 250, 450, 550, 650, 750: insulating layer 34

201203559 1 WJ 162, 231a, 231b, 282, 292, 431a, 431b, 482, 492, 531a, 531b, 582, 592, 692, 731a, 731b, 782, 792: open σ 163: contact holes 190, 290, 390 490, 590, 690, 790: inner dielectric layers 222, 422, 522, 722: intrinsic regions 224a, 224b, 424a, 424b, 524a, 524b, 624a, 724a, 724b: doped regions 241, 341, 441 , 541, 641, 741: first conductive layer 242, 342, 442, 542, 642, 742: second conductive layer 243, 343, 443, 543, 643, 743: third conductive layer 444, 744: fourth conductive Layer 8: Optoelectronic device 81 〇: Display panel 820: Electronic component Csl: Storage capacitors CS21, CS31, CS41, Cs51, Cs61, CS71: First storage capacitor CS52, CS62, CS72: Second storage capacitor

Cs53, Cs63, Cs73: third storage capacitor DT2, DT41, DT42, DT5, DT71, DT72: data line SC2, SC4, SC5, SC7: scan line

Vc〇m2, Vcom4, "Vcom5, Vc〇m7 ·Common electrode line 35

Claims (1)

201203559 I W3y3UPA-0 VII. Patent application scope: h—a species of halogen structure comprising: at least one transistor; a first storage capacitor electrically connected to the transistor; a first conductive layer; an inner dielectric layer Covering the first conductive layer and having at least one first opening; η a second conductive layer formed on a portion of the inner dielectric layer and electrically connected to the first via a conductive layer covering the transistor and the second conductive layer and having at least one second opening; a third conductive portion formed on the protective layer and via the second The opening is electrically connected to the transistor, wherein the first storage capacitor is composed of the second conductive layer, the protective layer and the second conductive layer; a semiconductor layer; an insulating layer covering the semiconductor layer, and The method has at least two third openings; and a first to second storage capacitor formed by the first conductive layer, the insulating layer and a portion of the semiconductor layer. 2. The pixel structure of claim 2, wherein the material of at least one of the second conductive layer and the third conductive layer comprises a light transmissive material, a reflective material, or a combination thereof. 3. The pixel structure as claimed in claim 1, further comprising: a third storage capacitor, the second conductive layer, the inner dielectric layer, the insulating layer and the semiconductor layer and the semiconductor layer and the inner dielectric layer, 36 201203559 i vvjjjvrrv-i) Part of the semiconductor layer is formed. 4. The valence structure according to claim 1, wherein the semiconductor layer comprises at least one doped region, at least one intrinsic region, or a combination thereof. 5. The halogen structure according to claim 1, wherein the first conductive layer and the second conductive layer have substantially the same level. 6. The pixel structure of claim 1, wherein the levels of the first conductive layer and the second conductive layer comprise a common level. 7. The halogen structure according to claim 1, wherein the material of the first conductive layer comprises a reflective material. 8. The halogen structure according to claim 1, wherein the first conductive layer is connected to a common electrode line. 9. The halogen structure as claimed in claim 1, further comprising: a data line electrically connected to one of a source and a drain of the transistor; and a scan line, electrical Connected to one of the gates of the transistor. 10. A display panel comprising a plurality of halogen structures as described in claim 1 of the scope of the patent application. An optoelectronic device comprising the display panel as described in claim 10 of the patent application. A method for forming a pixel structure, the halogen structure having at least one transistor, a first storage capacitor and a second storage capacitor electrically connected to the transistor, the forming method comprising: forming a first conductive layer Covering an inner dielectric layer on the first conductive layer, and having an opening of a 37th 201203559 1 wjjjur/\-D; forming a first conductive layer on a portion of the inner dielectric layer, and via the The first opening is electrically connected to the first conductive layer; covering a protective layer on the transistor and the second conductive layer, and having a second opening; and forming a second conductive layer on the protective layer And the first storage capacitor is formed by the first conductive layer, the protective layer and the second conductive layer; wherein the forming method further comprises: forming a a semiconductor layer; and an insulating layer over the semiconductor layer, and having at least two third openings, wherein the second storage capacitor is composed of the first conductive layer, the insulating layer and a portion of the semiconductor layer13. The method according to claim 12, wherein the material of at least one of the second conductive layer and the third conductive layer comprises a light transmissive material, a reflective material, or a combination thereof. 14. The method according to claim 12, wherein the halogen structure further comprises a third storage capacitor, the second conductive layer, the inner dielectric layer, the insulating layer and a portion of the semiconductor layer . 15. The method of forming of claim 12, wherein the semiconductor layer comprises at least one doped region, at least one intrinsic region, or a combination thereof. The method of forming the method of claim 12, wherein the first conductive layer and the second conductive layer have substantially the same level. 17. The method according to claim 12, wherein the level of the first conductive layer and the second conductive layer comprises a common level. 18. The method according to claim 12, wherein the material of the first conductive layer comprises a reflective material. 19. The method of forming of claim 12, wherein the first conductive layer is connected to a common electrode line. 20. The method of forming the method of claim 12, further comprising: forming a data line electrically connected to one of a source and a drain of the transistor; and forming a scan line, the electricity It is connected to one of the gates of the transistor. A method of forming a display panel comprising the method of forming a halogen structure as described in claim 12 of the patent application. A method of forming a photovoltaic device, comprising the method of forming a display panel as described in claim 21 of the patent application. 39