TWI361493B - Pixel structure and method for forming the same - Google Patents

Description

1361493

TW3530PA-D VI. Description of the Invention: [Technical Field] The present invention relates to a pixel structure and a method of forming the same, and in particular to a pixel structure having a storage capacitor. [Prior Art] Referring to Fig. 1, a cross-sectional view showing a conventional pixel structure is shown. The pixel structure 100 has a substrate 109. A semiconductor layer 120 is formed on the substrate 109. The semiconductor layer 120 and the substrate 109 are covered with an insulating layer 150. A gate 116 is formed on the insulating layer 150 and is covered with an inner dielectric layer 190 on the gate 116. The insulating layer 150 and the inner dielectric layer 190 have two openings 162 to expose the semiconductor layer 120. A source 114, a drain 112, and a capacitor electrode 101 are formed on the inner dielectric layer 190. The source 114 and the drain 112 are electrically connected to the semiconductor layer 120 via the opening 162. A protective layer 102 is formed on the inner dielectric layer 190 and covers the source 114, the drain 112 and the capacitor electrode 101, and has a contact hole 163 to expose the source 114. The halogen electrode 103 is formed on the protective layer 102 and electrically connected to the source 114 via the contact hole 163. The capacitor electrode 101 of the halogen structure 100 is a conductive material, and the protective layer 102 is a dielectric material. The storage capacitor Cs1 is formed between the capacitor electrode 101 and the pixel electrode 103. However, due to the coverage of the protective layer 102, short circuits may occur between the germanium electrode 103 and the capacitor electrode 101 due to process problems. Although the thickness of the protective layer 102 can be increased to solve the above-mentioned problems, the storage capacitor Csl is relatively reduced. 1361493 * ·

TW3530PA-D In addition, the capacitor electrode 101 is generally made of an opaque material and is located in the visible region of the pixel structure 100 (not shown). Therefore, even if the pixel electrode 103 is made of a light transmissive material. However, this design approach tends to reduce the aperture ratio of the structure 100, which decreases as the storage capacity of the storage capacitor Cs1 (e.g., the area of the storage capacitor Cs1 in the visible area) increases. As a result, the display brightness of the panel is lowered. In addition, this problem is more apparent in panels of the same size and higher resolution. SUMMARY OF THE INVENTION The present invention relates to a halogen structure and a method of forming the same, which can increase the aperture ratio without changing the capacitance value. According to a first aspect of the invention, a halogen structure is proposed. The halogen structure comprises at least one transistor, a first storage capacitor, a first conductive layer, an inner dielectric layer, a second conductive layer, a protective layer and a third conductive layer. The first storage capacitor is electrically connected to the transistor. The inner dielectric layer covers the first conductive layer and has at least one first opening. The second conductive layer is formed on the portion of the inner dielectric layer and electrically connected to the first conductive layer via the first opening. The protective layer covers the transistor and the second conductive layer and has at least one second opening. The third conductive layer is formed on the partial protective layer and electrically connected to the transistor via the second opening. The first storage capacitor is composed of a third conductive layer, a protective layer and a second conductive layer. According to a second aspect of the present invention, a method of forming a halogen structure is proposed. The halogen structure has at least one transistor and a first storage capacitor. The first storage capacitor is electrically connected to the transistor. This formation method includes the following steps 5 1361493

TW3530PA-D Step: First, a first conductive layer is formed. Next, an inner dielectric layer is overlaid on the first conductive layer and has a first opening. Then, a second conductive layer is formed on the portion of the inner dielectric layer, and is electrically connected to the first conductive layer via the first opening. Next, a protective layer is covered on the transistor and the second conductive layer, and has a second opening. Finally, a third conductive layer is formed on the portion of the protective layer and electrically connected to the transistor via the second opening. The first storage capacitor is composed of a third conductive layer, a protective layer and a second conductive layer. In order to make the above-mentioned contents of the present invention more comprehensible, the preferred embodiments are described below, and the detailed description is as follows: [Implementation] The present invention proposes to have at least one storage capacitor for a conductive material. The structure of the prime. The conductive material includes a light transmissive material, a reflective material, or a combination thereof. Embodiments of the present invention are described in detail by taking a pixel structure of a display panel in an optoelectronic device as an example. Further, the illustration of the embodiments is to omit certain elements in order to clearly show the technical features of the present invention. First Embodiment Referring to Figure 2A, there is shown a top plan view of a halogen structure of a first embodiment of the present invention. This embodiment is exemplified by a pixel structure 200 of a display panel in an optoelectronic device. As shown in Fig. 2A, the data line DT2 and the scan line SC2 are electrically connected to the halogen structure 200, respectively. Please refer to FIG. 2B, which shows a cross-sectional view of the pixel structure of FIG. 2A. Fig. 2B is a cross-sectional view taken along line 2B-2B' of Fig. 2A. Alizarin structure 200 contains 1361493

TW3530PA-D a transistor (not labeled), a flute ^ ^ first - storage capacitor cs21, a first conductive layer 241, an inner dielectric layer 29 〇, β - i two ^ second conductive layer 242, a protection Layer 280 ys 43. Preferably, the pixel structure 2 〇〇 can selectively s the light-shielding pattern layer (not shown in green), and is located parallel to at least one side of the data line and the scan line SC2 to prevent the data line DT2 And at least one of the scan lines SC2 goes to the edge of the Wang ^ test to produce light leakage. The first storage valley Cs21 is electrically connected to the transistor 290 and covers the first conductive 屛μ + 曰

The power storage layer 241 has an opening 292. The second conductive layer 242 is formed on the portion of the inner dielectric layer 290 and electrically connected to the first conductive layer 241 via the opening 292. The protective layer 28G covers the electromorph and the first conductive layer 242, and has an opening 282. The third conductive layer 243 is formed on the adjacent damage protection layer 280 and electrically connected to the transistor via the opening 282. The first storage capacitor Cs21 is composed of a third conductive layer 243, a protective layer 280, and a second conductive layer 242. Referring to Figures 3A to 3F, a flow chart showing a method of forming the pixel structure of Figure 2B is shown. The halogen structure 200 is formed as follows: As shown in Fig. 3A, a semiconductor layer 22 is formed on the substrate 2, and then an insulating layer 250 is overlaid on the semiconductor layer 220. The semiconductor layer 220 includes at least two doped regions 224a, 224b and an intrinsic region 222. In general, the intrinsic region 222 is located between the two doped regions 224a, 224b. Preferably, in an embodiment of the present invention, at least one additional doping region may be selectively added between the intrinsic region 222 and the two doped regions 224a, 224b, at least one of which is doped The impurity concentration is substantially less than at least one of the two doped regions 224a, 224b, and the intrinsic region 222 can be doped or undoped.

The polarity of the TW3530PA-D sign region 222 is substantially different from the two doped regions 2243, 224b and the additional intrinsic region 222 and/or the other regions. Further, the material 1 in which the two doping regions 22, 22, the conductor layer 220, or the n-doped region' are selectively formed simultaneously on the semiconductor layer 220 is formed in the semiconductor layer 220. Furthermore, the semi-mass and polycrystalline stone-bearing material ^ single crystal contains ♦ material, microcrystalline stone-bearing material, its material, or the above-mentioned bond. The enamel, or it is then formed on the first conductive layer 250 as shown in Fig. 3. At this time, the Thunder 0th 』01/: 士于,, 邑 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施 实施The material of the conductive layer 241 of the present layer is a reflective material (such as: gold, silver, copper, iron, tin, lead, cadmium, molybdenum, tungsten, tantalum, titanium, button, bismuth: other materials, or the above oxides) Or the above-mentioned nitride, or the above 5 oxynitride, or the above-mentioned alloy, or a combination thereof, is not limited thereto. Alternatively, a transparent material may be selectively used (for example, indium tin oxide, not aluminum zinc oxide) a substance, aluminum tin oxide, indium zinc oxide, cadmium tin oxide, bismuth other material, or a combination thereof, or a combination of a transparent material and a reflective material. Further, the first conductive layer 241 is connected to a level. The electrode line, the second example; the common electrode line Vcom2' or alternatively the partially-positioned electrode line 'for example: the common electrode line vcom2 is regarded as the first conductive layer 241 (as shown in FIG. 2A). Wherein in the present embodiment, the electrode lines are, for example, a common electrode line ν. - the material is a reflective material (such as: gold, silver, copper, iron tin, lead, cadmium, molybdenum, tungsten, titanium, titanium, tantalum, niobium, or other materials, niobium oxide, or the above nitrogen The compound, or the above-mentioned bismuth vapor, the alloy of the above, or a combination thereof, is an embodiment of the invention 'but is not limited thereto, and is also 1361493

TW3530PA-D can selectively use transparent materials (such as: indium tin oxide, zinc oxide, aluminum tin oxide, indium oxide, cadmium tin oxide, or other combinations of the above), or transparent materials and reflection (4) The combination '. The conductive layer 24i is connected to the electrode lines, for example, the common electrode lines; the materials are substantially the same or different, preferably, the two are: low process complexity. ^ Next 'as shown in FIG. 3C, covering the inner layer The dielectric layer 29 is disposed on the insulating layer 250, and respectively forms an opening 292 in the inner dielectric layer 29 and two openings 231a, 231b in the inner dielectric layer 29 and the insulating layer 25A. Then, as shown in FIG. 3D *, the second conductive layer 242 is formed on a portion of the inner dielectric layer 290, and is electrically connected to the first conductive layer 241 and the semiconductor layer 22 via the openings 292, 23U, 23, wherein via the openings 231a, 231b The second conductive layer M2 electrically connected to the semiconductor layer 22 is used as one of the gates 212 and one source 214. In the present embodiment, the material of the second conductive layer 242 is a reflective material (such as : gold, silver, Lu, iron, tin, lead, cadmium, molybdenum, tungsten, niobium, titanium, niobium, tantalum, or other materials, or the above oxides, or the above-mentioned nitrides, or the above-mentioned nitrogen oxides Or the alloy described above, or a combination thereof, is an example, but is not limited to Alternatively, a transparent material (eg, indium tin oxide, aluminum zinc, oxide, aluminum tin oxide, indium zinc oxide, cadmium tin oxide, or other materials, or a combination thereof) or transparent may be used. A combination of a material and a reflective material. Further, one of the source 214 and the drain 212 of the transistor is electrically connected to the data line DT2 (as shown in FIG. 2), and the gate 216 of the transistor is electrically connected. On scan line SC2 (as shown in Figure 2A). It must be noted that this is 9 1361493

TW3530PA-D The openings 231a, 231b and 292 of the embodiment are formed at different times, but are not limited thereto, and masks having different transmittances can be selectively used (for example, a half dimming mask, a diffractive mask) The yellow light process of the grid pattern mask, or other reticle, or a combination thereof, forms openings 231a, 231b, and 292 at the same time. Next, as shown in FIG. 3E, the protective layer 280 is covered on the transistor and the second conductive layer 242, and the protective layer 280 has an opening 282. Finally, as shown in Fig. 3F, a third conductive layer 243 (also referred to as a germanium electrode) is formed on a portion of the protective layer 280, and is electrically connected to the transistor via the opening 282. Therein, the opening 282 can selectively substantially align or misalign the opening 231b. As a result, the overall pixel structure 200 is as shown in Fig. 3F. In this embodiment, the material of the third conductive layer 243 is made of a transparent material (eg, indium tin oxide, aluminum zinc oxide, aluminum tin oxide, indium zinc oxide, cadmium tin oxide, or other materials, Or a combination of the above), but is not limited thereto, and may also selectively use a reflective material (eg, gold, silver, copper, iron, tin, wrong, tin, molybdenum, tungsten, condensed, chin, group, give) Or a combination of other materials, or the above-mentioned oxides, or the above-mentioned II compounds, or the above-mentioned nitrogen oxides, or the above-mentioned alloys, or a combination thereof, or a transparent material and a reflective material. In the present embodiment, since the first conductive layer 241 and the second conductive layer 242 have a common potential resistance, that is, a parallel design, the electrode lines, for example, the load impedance of the common electrode line Vcom2 can be reduced. In this way, the cross-talk of the display panel in the optoelectronic device when the display surface is displayed can be avoided. 1361493

TW3530PA-D Further, at least one of the insulating layer 250, the inner dielectric layer 290 and the protective layer 280 is made of an inorganic material (eg, cerium oxide, tantalum nitride, cerium oxynitride, cerium oxide, tantalum nitride, Tantalum carbide, or other materials, or a combination of the above, organic materials (such as: photoresist, poly ary lene ether (PAE), polyfluorenes, polyesters, polyalcohols, polyolefins, Benzocyclobutene (BCB), HSQ (hydrogen silsesquioxane), MSQ (methyl silesqui〇xane), hydrogenated hydrogenated hydrocarbon (SiOC-H), or other materials, or combinations thereof, or combination. The second conductive layer 242 of this embodiment can be selectively made of a reflective material, a light transmissive material, or a combination thereof. The second conductive layer 242 of FIG. 2B is an embodiment of a reflective material. Please refer to FIG. 4, which illustrates a cross-sectional view of another pixel structure of the first embodiment. The β pixel structure includes a transistor (not labeled), a first storage valley Cs, and a first conductivity. The layer 341, an inner dielectric layer 390, a second conductive layer 342, a protective layer 38A, and a second conductive layer 343. The second conductive layer 342 is formed on the portion of the inner dielectric layer 430, and the material of the second conductive layer 242 electrically connected to the first conductive layer via the opening 392 is a reflective material as an example. The material of the second conductive layer 342 is made of a light transmissive material. The example is 'but is not limited thereto. The above description is based on the example of the formation of the halogen structure 2 〇 昼, and the formation method of the ruthenium structure 3 盥昼 is the same as the formation method of the 盥昼 钍 200, and therefore will not be repeated. However, it is worthwhile, the main thing is that the material of the pixel structure 2 〇〇 < the second guide (four) 242 and the second conductive layer 342 of the halogen structure is a different example of the material. Similarly, the pixel structure 300 also has the above-described manner. And because of 昼素壮 1361493

The second conductive layer 342 of the TW3530PA-D structure 300 is an example of a light transmissive material, and thus the pixel structure 300 can be used to match different application embodiments. SECOND EMBODIMENT Referring to Figure 5A, there is shown a top view of a pixel structure of a second embodiment of the present invention. This embodiment is exemplified by a pixel structure 400 of a display panel in an optoelectronic device. As shown in FIG. 5A, the data lines DT41, DT42 and the scan line SC4 are electrically connected to the halogen structure 400, respectively. Please refer to FIG. 5B, which shows a cross-sectional view of the pixel structure of FIG. 5A. Fig. 5B is a cross-sectional view taken along line 5B-5B of Fig. 5A. The halogen structure 400 includes a transistor (not labeled), a first storage capacitor Cs/n, a first conductive layer 44, an inner dielectric layer 49, a second conductive layer 442, a protective layer 480, and a The third conductive layer 443 and a fourth conductive layer 444. Preferably, the pixel structure 4 〇〇 selectively includes a light shielding pattern layer located at and parallel to the side of at least one of the data lines DT4 DT42 and the scan lines SC4 to prevent the data lines DT41, DT42 and scanning. Light leakage occurs at the edge of at least one of the lines SC4. The first storage capacitor Cs41 is electrically connected to the transistor. The inner dielectric layer 90 covers the first conductive layer 441 and has an open peach. The first electrical layer 442 is formed on the portion of the inner dielectric layer 490 and is connected to the first conductive layer 441 via an opening. The protective layer is overlaid on the electro-optic layer 442 and has an opening 482. The third conductive layer 443 is formed on the portion of the protective layer 48 and is electrically connected via the opening 2; the H conductive layer 444 covers the second conductive layer 442 and the portion 1361493

The TW3530PA-D inner dielectric layer 490 is such that the first storage capacitor CM1 is composed of the third conductive layer 443, the protective layer 480, the fourth conductive layer 444, and the second conductive layer 4?. Please refer to the figure 6A~6G, which shows the structure of the pixel structure of FIG. 5B.

A flow chart of the method. The pixel structure 400 is formed by forming a semiconductor layer 42 on the substrate 409 as shown in Fig. 6A, and then covering an insulating layer 450 on the semiconductor layer 420. The semiconductor layer 420 includes to the second doped regions 424a, 424b and an intrinsic region 422. General and ancient —. The intrinsic region 422 is located between the two doped regions 424a, 424b. Preferably, in an embodiment of the invention, at least one additional doping region is selectively added to the outside of the wood region 422 and the two doped regions 424a, 424b. Two doped regions 424;: one of the eves, the intrinsic region 422 can be replaced by μ7# λα · the sign of the region 422 (four) two doping or undoping, if doping, the polarity of the present Preferably, the regions are substantially free of 424a, 424b and additional doped regions intrinsic regions 4U and/or otherwise. . In addition, the two doped regions 424a, 424b, the conductor layer 420 or the different " miscellaneous regions, or the material of the semiconductor layer 420 may be selectively formed in the semiconductor layer 420. Furthermore, the semi-quality 'polycrystalline yttrium-containing material ^ ^ crystal yttrium-containing material, the microcrystalline yttrium-containing material thereof, or the above-mentioned group of amorphous yttrium-containing materials, yttrium-containing materials, or The 6th figure factory, layer 450. At this time, the Thunder does not form the first conductive layer 441. In the insulating embodiment, the first conductive layer opening 416 is also formed at the same time. In this silver, copper, iron, tin, the material is a reflective material (such as: gold, molybdenum, Syrian, Chin, 钽, 铪, or 13 1361493

TW3530PA-D other materials, or the above oxides, or the above-mentioned nitrides, or the above-mentioned nitrogen oxides, or the above-mentioned alloys, or a combination thereof, are examples of 'but are not limited thereto, and may be selectively used. Transparent material (such as: indium tin oxide, zinc oxide, tin oxide, indium zinc oxide, tin tin oxide, or other materials, or a combination of the above), or a combination of transparent and reflective materials. In addition, the first conductive layer 441 is connected to a level electrode line, for example, the common electrode line Vcom4 (as shown in FIG. 5A), but is not limited thereto, and some partially-positioned electrodes may be selectively used. A line such as a common electrode line Vc 〇 m4 is regarded as the first conductive layer 441. In this embodiment, the electrode line, for example, the material of the common electrode line Vc〇m4 is made of a reflective material (eg, gold, silver, copper, iron, tin, ship, knitting, key, crane, convergence, Qin, The group, the dosing, or other materials, or the above oxides, or the above-mentioned nitrides, or the above-mentioned nitrogen oxides, or the above-mentioned alloys, or a combination thereof, are examples of 'but are not limited thereto, and may also be optional. Use a transparent material (such as: indium tin oxide, zinc oxide, tin oxide, indium zinc oxide, tin oxide, or other materials, or a combination of the above), or a combination of transparent and reflective materials . In other words, the first conductive layer 441 is connected to the electrode lines. For example, the materials of the common electrode lines Vcom4 are substantially the same or different, and preferably, the two are substantially the same to reduce the process complexity. Next, as shown in FIG. 6C, the inner dielectric layer 490 is covered on the insulating layer 450, and an opening 492 is formed in the inner dielectric layer 490 and the two openings 431a and 431b in the inner dielectric layer 490 and the insulating layer 450, respectively. Then, as shown in FIG. 6D, a second conductive layer 442 is formed on a portion of the inner dielectric layer 490, and via openings 492, 431a, 431b, respectively, 1361493

The TW3530PA-D is electrically connected to the first conductive layer 441 and the semiconductor layer 42G. The second conductive layer 442 electrically connected to the semiconductor layer 42 via the openings 431a, 431b serves as one of the gates 412 and a source 414 of the transistor. In the present embodiment, the material of the second conductive layer 442 is a reflective material (such as: gold, silver, copper, iron, tin, wrong, recorded, turned, crane, Syrian, Chin, group, give, or other materials). Or the above-mentioned oxide, or the above-mentioned nitride, or the above-mentioned nitrogen oxide or the above-mentioned alloy, or a combination thereof, is an embodiment, but is not limited thereto, and a transparent material (eg, indium may be selectively used). Tin oxide, aluminum zinc oxide, aluminum tin vapor, germanium oxide, cadmium tin oxide, or other materials, or combinations thereof, or a combination of a transparent material and a reflective material. Furthermore, one of the drain 412 and the source 414 of the transistor is electrically connected to the data lines DT41 and DT42 (as shown in FIG. 5A), and the gate 416 of the transistor is electrically connected to the scan line SC4 ( As shown in Figure 5A). It should be noted that the openings 431a, 431b, and 492 of the present embodiment are opened at different times, but are not limited thereto, and a mask having different transmittances may be selectively used (for example, semi-dimming) The yellow light process of the cover, the diffractive reticle, the grid pattern mask, or other reticle, or a combination thereof, forms openings 431a, 431b, and 492 6 at the same time, and then 'as shown in FIG. 6E, covering The fourth conductive layer 444 is on the second conductive layer 442 and a portion of the inner dielectric layer 490. In the present embodiment, the material of the fourth conductive layer 444 is a light-transmitting material as an embodiment. However, the present invention is not limited thereto. A reflective material or a combination of a light-transmitting material and a reflective material may be selectively used. In addition, since the first conductive layer 441, the second conductive layer 442, and the fourth conductive layer 444 are electrically connected to each other, the first conductive layer 441, 15 1361493

The levels of the second conductive layer 442 and the fourth conductive layer 444 of the TW3530PA-D are substantially the same. The levels of the first conductive layer 441, the second conductive layer 442, and the fourth conductive layer 444 include, for example, a common level. In addition, in this embodiment, the first parasitic capacitance is between the drain 412 and the scan line SC4, and the sum of the capacitances between the gate 412 and the data lines dt4 1 and DT42 is substantially a second parasitic. capacitance. In addition, there is a liquid B solar valley (not shown) between the pixel electrode of the halogen structure 400 and the common electrode (not shown). The pixel capacitance of one of the halogen structures 400 is substantially equal to the sum of the liquid crystal capacitance and the first storage capacitance Cw. The area of the fourth conductive layer 444 is determined by the ratio of the first parasitic capacitance to the pixel capacitance, the ratio of the second parasitic capacitance to the halogen capacitance, and the ratio of the first storage capacitor Csw to the liquid crystal capacitance. The area of the fourth conductive layer 444 in the present embodiment is preferably substantially larger than the area of the second conductive layer 442, but is not limited thereto, and the fourth conductive layer 444 may be selectively changed according to design requirements. The area is, for example, substantially smaller than the area of the second conductive layer 442, substantially equal to the area of the second conductive layer 442, or a combination thereof. Then, as shown in FIG. 6F, the protective layer 480 is overlaid on the transistor and the second conductive layer 442, and the protective layer 480 has an opening 482. Finally, as shown in Fig. 6G, a third conductive layer 443 (also referred to as a germanium electrode) is formed on a portion of the protective layer 480, and is electrically connected to the transistor via the opening 482. Therein, the opening 482 can selectively substantially align or misalign the opening 431b. As a result, the overall pixel structure is as shown in Figure 6G. In this embodiment, the material of the third conductive layer 443 is made of a transparent material (eg, indium tin oxide, aluminum zinc oxide, aluminum tin oxide, indium 1361493).

TW3530PA-D zinc oxide, cadmium tin oxide, or other materials, or a combination thereof, is an example, but is not limited thereto, and a reflective material (such as: • gold, silver, copper, iron, or the like) may be selectively used. Tin, lead, recorded, molybdenum, tungsten, tantalum, titanium, ruthenium, tin, or other materials, or oxides thereof, or nitrides thereof, or the above-described nitrogen oxides, or alloys thereof, or Combination), or a combination of a transparent material and a reflective material. In the embodiment, the fourth conductive layer 444 is made of a light-transmitting material, so the halogen structure 400 can increase the aperture ratio without changing the capacitance value, but the invention is not limited thereto, and a reflective material or a light-transmitting material can also be used. And a combination of reflective materials. In addition, the fourth conductive layer 444 can selectively overlap with any gate line or data line, thereby reducing the load on the gate line or the data line, but is not limited thereto, and may be selectively partially overlapped. Further, the first conductive layer 441, the second conductive layer 442, and the fourth conductive layer 444 have a common potential resistance, that is, a parallel design, so that the electrode line, for example, the load impedance of the common electrode line Vc 〇 m4 can be reduced. In this way, the material of the at least one of the insulating layer 450, the inner dielectric layer 490 and the protective layer 480 which is generated by the display panel in the photoelectric device when the display surface is displayed can be avoided, and the inorganic material is included (for example: Cerium oxide, tantalum nitride, niobium oxynitride, antimony oxide, tantalum nitride, tantalum carbide, or other materials, or a combination thereof, organic materials (eg, photoresist, poly(fluorene ether) (PAE) ), polyfluorenes, polyesters, polyalcohols, polyolefins, benzocyclclobutene (BCB), HSQ (hydrogen silsesquioxane), MSQ (methyl silesquioxane), hydrogenated hydrocarbons 17 1361493

TW3530PA-D (SiOC-H), or other materials, or a combination thereof, or a combination thereof. THIRD EMBODIMENT Referring to Fig. 7A, there is shown a top plan view of a halogen structure of a third embodiment of the present invention. This embodiment is exemplified by a pixel structure 500 of a display panel in an optoelectronic device. As shown in Fig. 7A, the data line DT5 and the scan line SC5 are electrically connected to the halogen structure 500, respectively. Please refer to FIG. 7B, which shows a cross-sectional view of the pixel structure of FIG. 7A. Fig. 7B is a cross-sectional view taken along line 7B-7B' in Fig. 7A. The halogen structure 500 includes a transistor (not labeled), a first storage capacitor Cs51, a second storage capacitor Cs52, a third storage capacitor Cs53, a first conductive layer 541, an inner dielectric layer 590, and a first The second conductive layer 542, an insulating layer 550, a semiconductor layer 520, a protective layer 580, and a third conductive layer 543. Preferably, the halogen structure 500 can optionally include a light shielding pattern layer (not shown) located at a side parallel to at least one of the data line DT5 and the scan line SC5 to prevent the data line DT5 and the scan line. Light leakage occurs at the edge of at least one of the SC5. The first storage capacitor Cs51 is electrically connected to the transistor. The inner dielectric layer 590 covers the first conductive layer 541 and has an opening 592. The second conductive layer 542 is formed on the portion of the inner dielectric layer 590 and is electrically connected to the first conductive layer 541 via the opening 592. The protective layer 580 covers the electromorph and the second conductive layer 542 and has an opening 582. The third conductive layer 543 is formed on the partial protective layer 580 and electrically connected to the transistor via the opening 582. The first storage capacitor Cs51 is composed of a third conductive layer 543 and a protective layer 1361493

The TW3530PA-D 580 and the second conductive layer 542 are formed. The second storage capacitor Cs52 is composed of a first conductive layer 541, an insulating layer 550, and a portion of the semiconductor layer 520. The second storage valley Cs53 is composed of a first conductive layer 542, an inner dielectric layer 59, an insulating layer 550, and a portion of the semiconductor layer 520. Referring to Figures 8A to 8F, a flow chart showing a method of forming the pixel structure of Fig. 7B is shown. The halogen structure 500 is formed as follows: As shown in Fig. 8A, a semiconductor layer 52 is formed on the substrate 509, and then an insulating layer 550 is overlaid on the semiconductor layer 520, respectively. The semiconductor layer 52A includes at least two doped regions 524a, 524b and an intrinsic region 522. The doped region 524a' of this embodiment extends below the first metal layer 541 as an example embodiment. In general, the intrinsic region 522 is located between the two doped regions 524 & Preferably, an embodiment of the present invention is selectively added to the other doped region in the intrinsic region 522 and the two doped regions, between the brothers and the servants, and the doping of the additional doping region The concentration is substantially less than at least one of the two doped regions 524a, 524b, and the intrinsic ^ ^ ^ is not doped. If doped, the polarity of the intrinsic region 522 can be doped or the polarity of the 5 ice and the additional doped regions. Preferably, the doped regions are doped, the doped regions 524a, 524b, and the intrinsic region 522 are replaced. Alternatively, two selectively formed simultaneously in the semiconductor layer 52G, and the region may be in the coffee. The semiconductor layer is formed in a semi-conducting material containing a dream material, a polycrystalline sand-containing enamel =: crystal: containing a stone cerium material, or other materials, or a combination thereof. Then, as shown in Fig. 8B, a first conductive layer is formed on the second layer 550. At this time, one of the gates of the transistor, the conductive layer 541, is also formed at the insulating electric pole 516. In this 1361493

In the embodiment of the TW3530PA-D, the material of the first conductive layer 541 is made of a reflective material (such as gold, silver, copper, iron, tin, erbium, tin, key, tungsten, sigma, chin, group, give, or other materials). Or the above-mentioned oxide, or the above-mentioned nitride, or the above-mentioned nitrogen oxide, or the above-mentioned alloy, or a combination thereof, is an embodiment, but is not limited thereto, and a transparent material may be selectively used (for example: Indium tin oxide, aluminum zinc oxide, aluminum tin oxide, indium zinc oxide, cadmium tin oxide, or other materials, or a combination thereof, or a combination of a transparent material and a reflective material. In addition, the first conductive layer 541 is connected to a level electrode line, for example, the common electrode line Vcom5 (as shown in FIG. 7A), but is not limited thereto, and some partially-positioned electrodes may be selectively used. Line, for example: common electrode line, . . ...as the first conductive layer 541. In this embodiment, the material of the common electrode line VCC)m5 is a reflective material (eg, gold, silver, copper, iron, tin, erroneous, recorded, turned, tungsten, arsenic, titanium, group, given, or Other materials, or the above oxides, or the above-described nitrides, or the above-described nitrogen oxides, or the above-described alloys, or a combination thereof, are examples, but are not limited thereto, and transparent materials may be selectively used ( Such as: indium tin oxide, inscription oxide, Ming tin oxide, indium zinc oxide, cadmium tin oxide, or other materials, or a combination of the above, or a combination of transparent materials and reflective materials. In other words, the first conductive layer 541 is connected to the electrode lines. For example, the materials of the common electrode lines Vc 〇 m5 are substantially the same or different, and preferably, the two are substantially the same to reduce the process complexity. As described above, the doping region 524a of the semiconductor layer 520 of the present embodiment extends below the first metal layer 541 as an example. Therefore, the second storage capacitor Cs52 is composed of the first conductive layer 541, the insulating layer 550, and the partial semiconductor layer 520. It must be noted that it extends to the first metal layer 541 1361493 »

The semiconductor layer 520 under the TW3530PA-D can also be selectively connected to the semiconductor layer 520 under the gate 516 through a connection layer (not shown). The semiconductor layer 520 extending below the first metal layer 541 includes at least one doped region 524a/524b, at least one other doped region, and at least one intrinsic region 522. The material of the connection layer may use at least one of the first conductive layer 541, the second conductive layer 542, the third conductive layer 543, and the semiconductor layer 520. Next, as shown in FIG. 8C, the inner dielectric layer 590 is covered on the insulating layer 550, and openings 592 are formed in the inner dielectric layer 590 and the two openings 531a and 531b in the inner dielectric layer 290 and the insulating layer 550, respectively. . Then, as shown in FIG. 8D, the second conductive layer 542 is formed on a portion of the inner dielectric layer 590, and electrically connected to the first conductive layer 541 and the semiconductor layer 520 via openings 592, 531a, and 531b, respectively. The second conductive layer 542 electrically connected to the semiconductor layer 520 via the openings 531a, 531b serves as one of the gates 512 and a source 514 of the transistor. In this embodiment, the material of the second conductive layer 542 is made of a reflective material (eg, gold, silver, copper, iron, tin, writh, tin, bismuth, crane, strontium, titanium, group, give, or other materials). Or the above-mentioned oxide, or the above-mentioned nitride, or the above-mentioned nitrogen oxide, or the above-mentioned alloy, or a combination thereof, is an embodiment, but is not limited thereto, and a transparent material may be selectively used (for example: Indium tin oxide, aluminum zinc oxide, aluminum tin oxide, indium zinc oxide, cadmium tin oxide, or other materials, or a combination thereof, or a combination of a transparent material and a reflective material. Furthermore, one of the source 514 and the drain 512 of the transistor is electrically connected to the data line DT5 (as shown in FIG. 7A), and the gate 516 of the transistor is electrically 1361493.

The TW3530PA-D is connected to the scan line SC5 (as shown in Figure 7A). The openings 531a, 531b, and 592 of the embodiment must be described in the present invention, but are not limited thereto, and may be selectively used with a half dimming cover, a diffractive reticle, and a grid pattern. ^ Yellow light process with different transmittance masks (such as the combination described) at the same time, or other reticle, or 531b and 592. 3, the opening 53a is formed, and then, as shown in Fig. 8E, the second conductive layer 542 is covered, and the protective layer θ 580 is on the transistor and finally, as shown in Fig. 8F, the first f-opening 582 is formed. The magnetic electrode is disposed on a portion of the protective layer 580, and a conductive layer 543 (also referred to as a transistor). The opening 582 is optionally pendulum = electrically connected to the quasi-opening 531b by the opening 582. The third storage capacitor Cs53 In essence, the dielectric layer 590, the insulating layer 550 and the partial semi-i conductive layer 542, and the inner layer are substantially aligned with the monolithic structure 5, that is, the t-gate body / 520. As in the embodiment, The material of the third conductive layer 543 is shown in Fig. 8F. The present oxide, the zinc oxide, and the IS tin oxide are two transparent materials (such as indium tin oxide, or other materials, or a combination thereof; , xixi oxygen, ^ 〇) for the example of implementation, but not limited to, or above, can also selectively use reflective materials (such as: gold and silver, copper and iron, lead, recorded, molybdenum, tungsten, Syria, titanium, tantalum a combination of an oxide of a material, or another material, or a nitride of the above, or an oxynitride of the above, or an alloy of the above, or a combination thereof, or a combination of a transparent material and a reflective material. The first conductive layer 541 and the second conductive layer 542 are common-potential resistors, that is, Therefore, the electrode line can be lowered, for example, the load resistance of the common electrode line Vcom5. Thus, it can be avoided 22 1361493 • »

In the TW3530PA-D optoelectronic device, the display panel generates crosstalk when it is displayed on the kneading surface. In addition, the doped region 524a of the semiconductor layer 520 of the present embodiment extends to the lower side of the first conductive layer 541 as an embodiment to further form the second storage capacitor Cs52 and the third storage capacitor Cs53. Furthermore, at least one of the insulating layer 550, the inner dielectric layer 590 and the protective layer 580 is made of an inorganic material (for example, cerium oxide, cerium nitride, oxynitride), cerium oxide, cerium oxide, cerium nitride, Carbide, or other materials, or a combination of the above, organic materials (such as photoresist, poly(p-lyarylene ether; PAE), polyfluorenes, polyesters, polyols, polyolefins, Benzocyclobutene (BCB), HSQ (hydrogen silsesquioxane), MSQ (methyl silesquioxane), Shihe oxygen hydrocarbon (SiOC-H), or other materials, or a combination thereof, or a combination thereof. The second conductive layer 542 of this embodiment can be selectively made of a reflective material, a light transmissive material, or a combination thereof. The second conductive layer 542 of FIG. 7B is an embodiment of a reflective material. Referring to Figure 9, there is shown a cross-sectional view of another unitary structure of the third embodiment. The pixel structure 600 includes an electro-crystal (not labeled), a first storage capacitor (: (6), a second storage capacitor c, s 6 2 - a third storage capacitor Cs63, a first conductive layer 641, an inner layer The dielectric layer 690, a second conductive layer 642, a semiconductor layer 620, an insulating layer 65, a protective layer 680, and a third conductive layer 643. The second conductive layer 642 is formed on a portion of the inner dielectric layer 690. And the material of the second conductive layer 542 electrically connected to the first conductive layer 641 via the opening 692 is a reflective material, and the material of the second conductive layer 642 of FIG. 9 is transparent. The material is an example of implementation, but it is not limited to this. The above content is based on the 昼素会士23 1361493

The TW3530PA-D structure 500 is used as an example to describe the method of forming the pixel structure 600. The method of forming the pixel structure 600 is the same as the method of forming the pixel structure 500, and therefore, the description will not be repeated. It should be noted, however, that the material of the second conductive layer 542 of the halogen structure 500 and the second conductive layer 642 of the halogen structure 600 is a different example of the material. Similarly, the pixel structure 600 also has the above-described manner. Because the second conductive layer 642 of the halogen structure 600 is a light-transmitting material, the halogen structure 600 can be used to cooperate with different application embodiments. The fourth embodiment is shown in FIG. 10A, which illustrates the present invention. A top view of the halogen structure of the fourth embodiment. This embodiment is exemplified by a pixel structure 700 of a display panel in an optoelectronic device. As shown in FIG. 10A, the data lines DT71, DT72 and the scan line SC7 are electrically connected to the halogen structure 700, respectively. Please refer to FIG. 10B, which shows a cross-sectional view of the pixel structure of FIG. 10A. Fig. 10B is a cross-sectional view taken along line 10B-10B' of Fig. 10A. The halogen structure 700 includes a transistor (not labeled), a first storage capacitor Cs71, a second storage capacitor Cs72, a third storage capacitor Cs73, a first conductive layer 741, an inner dielectric layer 790, and a a second conductive layer 742, a semiconductor layer 720, an insulating layer 750, a protective layer 780, a third conductive layer 743, and a fourth conductive layer 744. Preferably, the pixel structure 700 can optionally include a light shielding pattern layer (not shown) located at a side parallel to at least one of the data lines DT71, DT72 and the scan line SC7 to prevent data lines. Leakage at the edge of at least one of DT71, DT72 and scan line SC7 is now 24 1361493 « »

TW3530PA-D

The first storage capacitor cs71 is electrically connected to the transistor. The inner dielectric layer 790 overlies the first conductive layer 741 and has an opening 792. The first conductive layer 742 is formed on the portion of the inner dielectric layer 790 and electrically connected to the first conductive layer 741 via the opening 792. The protective layer 78 is covered on the electromorph and the first conductive layer 742 and has an opening 782. The third conductive layer 743 is formed on the partial protective layer 780 and electrically connected to the electric beta body via the opening 782. The fourth conductive layer 744 covers the second conductive layer 742 and the portion of the inner dielectric layer 790 such that the first storage capacitor c (7) is composed of the third conductive layer 743, the protective layer 780, the fourth conductive layer 744, and the second conductive layer. The second storage capacitor Cs72 is formed by the first conductive layer 741 and the insulating layer 75. The semiconductor layer 720 is formed. The third storage capacitor Cs73 is composed of a second conductive layer 742, a fourth conductive layer 744, an inner dielectric layer 79, an insulating layer 75A, and a portion of the semiconductor layer 720. / Referring to Figures 11A to 11G, there is shown a flow chart of the method of forming the pixel structure of Figure 10B. The pixel structure is formed by the following method: a semiconductor layer 72 is formed on the substrate 7A, and an insulating layer 750 is overlying the semiconductor layer 72A. The semiconductor layer 72 is wrapped around a doped region 724a, 724b and an intrinsic region 722. This embodiment: doping, 72, 'extending to the lower side of the first metal layer 741 is generally the embodiment, the intrinsic region 722 is located in the two doped regions 724a, 724b. Further preferably, the implementation of the present invention For example, at least one less impurity region may be selectively added between the intrinsic region 722 and the two doped regions ^, Wei Zhizhi' and the doping concentration of the additional doping region is substantially less than two for 25 1361493

TW3530PA-D == The polarity of the sign region 722 can be doped or not doped = / / / Μ 2 and the polarity of the two doped regions W, 724b and the additional doped regions are preferably substantially different from the region L intrinsic region 722 and / or alternatively = simultaneously formed in the semiconductor layer 720 or different two = Z 曰 ° = ' semiconductor layer 720 material including single crystal containing stone eve material, wrong: quality: material ί crystal: "material, Amorphous cut material, containing (four) shell 4 or its tantalum material, or a combination of the above. The layer is η'211 shown in the figure 'forming the first conductive layer 741 in the insulating embodiment, the first conductive silver, copper, iron, tin Other materials, or the above-mentioned oxide lanthanum, or oxynitride, or nitrogen, or the above, is not limited thereto, also L σ , or a combination thereof, is an example, but the zinc oxide is selectively transparent. Material f (such as: indium tin oxide, other materials, Amin tin oxide, steel oxide, tin oxide, or in addition, the combination of the above) or the combination of the Japanese tree and the reflection (four). Electric _ν ^ has the electrode line of the material, for example: the sleeve is from his m C°m7 as shown in the figure, but is not limited to this, Select the electrode line of the V part, for example: the common electrode line v com7, the first track • the conductive layer 541. In this embodiment, the electrodes a, L are the material of the common electrode line Vc 〇 m7. Is a reflective material (such as: gold, other materials iron. Tin, lead, cadmium, molybdenum, tungsten, tantalum, titanium, niobium, nitrile, or eight or above oxides, or the above-mentioned nitrides, or the above 26 1361493 • »

TW3530PA-D oxynitride, or the above alloy, or a combination thereof, is an example, but is not limited thereto, and a transparent material (eg, indium tin oxide, . A combination of an oxide, indium zinc oxide, pot tin oxide, or other materials, or a combination thereof, or a transparent material and a reflective material. In other words, the first conductive layer 741 is connected to the electrode lines. For example, the materials of the common electrode lines Vccm7 are substantially the same or different, and preferably, they are substantially the same to reduce the process complexity. As described above, the doped region 724a of the semiconductor layer 720 of the present embodiment extends below the first metal layer 741. • For the sake of example, the second storage capacitor Cs72 is composed of the first conductive layer 741, the insulating layer 750, and a portion of the semiconductor layer. 720 is composed. It should be noted that the semiconductor layer 720 extending below the first metal layer 741 may also selectively connect the semiconductor layer 720 under the gate 716 through a connection layer (not shown). The semiconductor layer 720 or block extending below the first metal layer 741 includes at least one of at least one doped region 724a/724b, at least one other doped region, and at least one intrinsic region 722. The material of the connection layer may be at least one of the first conductive layer 741, the second conductive layer 742, the third conductive layer 743, and the semiconductor layer 720. Next, as shown in FIG. 11C, the inner dielectric layer 790 is covered on the insulating layer 750, and an opening 792 is formed in the inner dielectric layer 790 and the two openings 731a and 731b in the inner dielectric layer 790 and the insulating layer 750, respectively. Then, as shown in FIG. 11D, the second conductive layer 742 is formed on a portion of the inner dielectric layer 790, and electrically connected to the first conductive layer 741 and the semiconductor layer 720 via the openings 792, 731a, and 731b, respectively. Wherein, the second conductive layer electrically connected to the semiconductor layer 720 via the openings 731a, 731b 27 1361493

The TW3530PA-D 742 is one of the transistors and the pole 712 and a source 714. In this embodiment, the second conductive layer 742 is made of a reflective material (eg, gold, silver, copper, iron, tin, lead, cadmium, molybdenum, tungsten, tantalum, titanium, niobium, tantalum, or other materials, Or the above-mentioned oxide, or the above-mentioned nitride, or the above-mentioned nitrogen oxide, or the above-mentioned alloy, or a combination thereof, is an embodiment but is not limited thereto and may be selectively transparent (4) (eg, secret oxidation) A combination of a material, an inscription oxide, a tin oxide, an indium zinc oxide, a tin oxide, or other material, or a combination thereof, or a transparent material and a reflective material. One of the drain 712 and one source 714 of the transistor is electrically connected to the semiconductor layer 720 by openings 731a, 731b φ. Furthermore, one of the source 714 and the drain 712 of the transistor is electrically connected to the data line DT7b DT72 (as shown in FIG. 10A), and the gate 716 of the transistor is electrically connected to the scan line SC7 (eg, Figure 10A)). It should be noted that the openings 731a, 73lb, and 792 of the embodiment are formed at different times, but are not limited thereto, and a mask having different transmittances may be selectively used (eg, a half dimming cover, Openings 731a, 731b, and 792 are formed at the same time by a dimming process of a diffractive reticle, a grid pattern mask, or other reticle, or a combination thereof. _ Next, as shown in FIG. 11E, the fourth conductive layer 744 is overlaid on the second conductive layer 742 and a portion of the inner dielectric layer 790. In the present embodiment, the material of the fourth conductive layer 744 is a light-transmitting material as an embodiment. However, the present invention is not limited thereto, and a reflective material or a combination of a light-transmitting material and a reflective material may be selectively used. In addition, since the first conductive layer 741, the second conductive layer 742, and the fourth conductive layer 744 are electrically connected to each other, the levels of the first conductive layer 741, the first conductive 742, and the fourth conductive layer 744 are substantially the same. . 28 1361493 * t

TW3530PA-D and the levels of the first conductive layer 741, the second conductive layer 742, and the fourth conductive layer 744 include, for example, a common level. In addition, in this embodiment, a first parasitic capacitance is between the drain 712 and the scan line SC7, and the sum of the capacitances between the drain 712 and the data lines DT71 and DT72 is substantially a second. Parasitic capacitance. In addition, there is a liquid crystal capacitor (not shown) between the halogen electrode of the germanium structure 700 and the common electrode (not shown). One of the halogen elements 700 has a pixel capacitance substantially equal to the sum of the liquid crystal capacitance and the first storage capacitance Cs71. The surface _ product of the fourth conductive layer 744 is determined by the ratio of the first parasitic capacitance to the pixel capacitance, the ratio of the second parasitic capacitance to the pixel electrode, and the ratio of the first storage capacitor Cs71 to the liquid crystal capacitance. The area of the fourth conductive layer 744 in the present embodiment is preferably substantially larger than the area of the second conductive layer 742, but is not limited thereto, and the fourth conductive layer 744 may be selectively changed according to design requirements. The area is, for example, substantially smaller than the area of the second conductive layer 742, substantially equal to the area of the second conductive layer 742, or a combination thereof. Then, as shown in Fig. 11F, the protective layer 780 is overlaid on the transistor and the second conductive layer 742, and the protective layer 780 has an opening 782. Finally, as shown in Fig. 11G, a third conductive layer 743 (also referred to as a halogen electrode) is formed on a portion of the protective layer 780, and is electrically connected to the transistor via the opening 782. Therein, the opening 782 can selectively align substantially or not the opening 731b. The third storage capacitor Cs73 is composed of a second conductive layer 742, an inner dielectric layer 790, an insulating layer 750, and a portion of the semiconductor layer 720. As a result, the overall pixel structure 700 is as shown in FIG. 11G. In this embodiment, the material of the third conductive layer 743 is made of a transparent material (eg, indium 29 1361493

TW3530PA-D tin oxide, zinc oxide, tin oxide, indium zinc vapor, mineral tin oxide, or other materials, or a combination thereof, is an example, but not limited thereto' Use reflective materials (such as: gold, silver, copper, iron, . tin, wrong, recorded, Yan, crane, Syrian, Chin, group, give, or other materials, or the above oxides, or the above nitrides, or In the present embodiment, the fourth conductive layer 744 is made of a light-transmitting material, so that the pixel structure 700 can be used or not. When the capacitance value is changed, the aperture ratio is increased, but φ is not limited to this. A reflective material or a combination of a light-transmitting material and a reflective material may be used. In addition, the fourth conductive layer 744 can be selectively overlapped with any of the gate lines or data lines. Thus, the load on the gate lines or data lines can be reduced, but is not limited thereto, and can be selectively partially overlapped. Furthermore, the first conductive layer 741, the second conductive layer 742, and the fourth conductive layer 744 have a common potential resistance, that is, a parallel design, thereby reducing the load impedance of the electrode lines, for example, the common electrode lines Vc 〇 m7. In this way, it is possible to prevent the display panel of the optoelectronic device from generating a crosstalk when the display panel is displayed. In addition, the doped region 72A of the semiconductor layer 720 of the present embodiment extends to the lower side of the first conductive layer 741 as an embodiment to further form the second storage capacitor cS72 and the third storage capacitor Cs73. Furthermore, at least the insulating layer 750, the inner dielectric layer 79 and the protective layer 78 are made of an inorganic material (eg, oxidized hair, oxidized oxynitride, cerium oxide, tantalum nitride, carbon). Cut, or other material, or above 30 1361493 » >

TW3530PA-D combination), organic materials (such as: photoresist, polyarylene ether (PAE), polyfluorenes, polyesters, polyalcohols, polyolefins, benzocyclobutene (BCB) ), HSQ (hydrogen silsesquioxane), MSQ (methyl silesquioxane), Shihe oxygen hydrocarbon (SiOC-H), or other materials, or a combination thereof, or a combination thereof. The halogen structure disclosed in the above embodiment of the present invention has at least one storage capacitor between the conductive materials. In the above embodiments, the application of the conductive material includes a light transmitting material, a reflective material, or a combination thereof. For example, since the fourth conductive layers 444 and 744 in the embodiment are made of a light-transmitting material, the pixel structures 400 and 700 can maintain the original capacitance value and further increase the aperture ratio. In addition, the arrangement of the fourth conductive layers 444, 744 can be selectively overlapped with any gate lines or data lines, so that the arrangement of the fourth conductive layers 444, 744 can reduce the gates in addition to the above advantages. The load on the line or data line, but not limited to this, may also be partially partially overlapped. Furthermore, since the first and second second conductive layers of the first, second, fourth, and fifth embodiments are common potential resistors, that is, parallel designs, and the first and third embodiments of the third and sixth embodiments The second and fourth conductive layers are also designed in parallel, so the application of these embodiments can reduce the load impedance of the electrode lines. In this way, it is possible to avoid the occurrence of crosstalk when the display panel in the photovoltaic device displays the surface. In addition, the electrode line having the level described in the above embodiment of the present invention is a common electrode line (Vc〇m) having a common level, but is not limited thereto, and may have a variable level. Electrode wire or its level of electricity 1361493

TW3530PA-D pole line (eg: gate level, or other level). a Figure 12 is a schematic view of the photovoltaic device of the present invention. The photovoltaic device 8 is a halogen structure 2〇〇~7〇〇 as described in the above embodiments. The optoelectronic device 800 - further has - an electronic component 82 - connected to the display panel 810, such as: control element, operating element, processing element, input element, memory element, driving element, lighting element, protection element, sensing element, Detecting components, or their components, or combinations thereof. The types of photovoltaic devices include portable products (such as mobile phones, cameras, cameras, notebook computers, game consoles, watches, music players, electronic photos, electronic mail transceivers, call map navigators or the like). ), audio and video products (such as audio and video projectors or similar products), screens, televisions, indoor or outdoor billboards, panels in projectors, etc. In addition, the display panel 81A includes a liquid crystal display panel (eg, a transmissive panel, a transflective panel, a reflective panel, a double-sided display panel, a vertical alignment panel (VA), a horizontal switching panel (ips), Multi-domain vertical alignment type panel (MVA), twisted nematic type panel (TN), super twisted nematic type panel (STN), pattern vertical alignment type panel (PVA), super pattern vertical alignment type panel (S-PVA), Advanced Large Viewing Panel (ASV), Edge Electric Field Switching Type Panel (FFS), Continuous Fireworks Arrangement Panel (CPA), Axis Symmetrical Micro Cell Panel (ASM), Optically Compensated Curved Arrangement Panel (〇cB), Super horizontal switching panel (s-ips), advanced super horizontal switching panel - (AS-IPS), extreme edge electric field switching panel (UFFS), polymer stabilized alignment panel (PSA), dual viewing panel (dual -view), triple-view, or color-diffuse film integrated into a matrix (c〇i〇r filter on array; COA) type panel, or matrix integrated on color filter 32 1361493 *

TW3530PA-D (array on color filter; AOC) type panel, or other type of panel, or a combination of the above. ), an organic electroluminescent display panel, depending on the material of the panel, such as a liquid crystal layer or an organic light-emitting layer (eg, small molecule, polymer, Or a combination of the above, or a combination of the above. In the above, the present invention has been disclosed in the above preferred embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. [Simple description of the drawing] Fig. 1 is a cross-sectional view showing the structure of a conventional pixel. Fig. 2A is a schematic view showing the pixel structure of the first embodiment of the present invention. Fig. 2B is a cross-sectional view showing the structure of the halogen in Fig. 2A. • Figs. 3A to 3F are flowcharts showing a method of forming a halogen structure in Fig. 2B. Fig. 4 is a cross-sectional view showing another pixel structure of the first embodiment. FIG. 5A is a view showing the structure of the halogen element of the second embodiment of the present invention. Fig. 5B is a cross-sectional view showing the pixel structure of Fig. 5A. Figs. 6A to 6G are views showing a flow chart of a method of forming a halogen structure in Fig. 5B. 33 1361493

TW3530PA-D Fig. 7A is a schematic view showing the pixel structure of the third embodiment of the present invention. Fig. 7B is a cross-sectional view showing the structure of the halogen in Fig. 7A. Figs. 8A to 8F are views showing a flow chart of a method of forming a halogen structure in Fig. 7B. Figure 9 is a cross-sectional view showing another unitary structure of the third embodiment. Fig. 10A is a top plan view showing the structure of a halogen substrate according to a fourth embodiment of the present invention. Fig. 10B is a cross-sectional view showing the structure of the halogen in Fig. 10A. 11A to 11G are flowcharts showing a method of forming the halogen structure of Fig. 10B. Figure 12 is a schematic view of the photovoltaic device of the present invention. [Description of main component symbols] 100, 200, 300, 400, 500, 600, 700: pixel structure 101: capacitor electrodes 102, 280, 380, 480, 580, 680, 780: protective layer 103: pixel electrode 109 ' 209 ' 409 ' 509 ' 709 : substrate 112 , 212 , 412 , 512 , 712 : drains 114 , 214 , 414 , 514 , 714 : source 116 , 216 , 416 , 516 , 716 : gates 120 , 220 , 420 , 520, 620, 720: semiconductor layer 150, 250, 450, 550, 650, 750: insulating layer 34 1361493

TW3530PA-D 162, 231a, 231b, 282, 292, 431a, 431b, 482, 492, 531a, 531b, 582, 592, $92, 731a, 731b, 782, 792: open. π • 163: contact hole 190, 290 390, 490, 590, 690, 790: inner dielectric layers 222, 422, 522, 722: intrinsic regions 224a, 224b, 424a, 424b, 524a, 524b, 624a, 724a, 724b: doped regions) 241 341, 441, 541, 641, 741: first conductive layer 242, 342, 442, 542, 642, 742: second conductive layer 243, 343, 443, 543, 643, 743: third conductive layer 444 ' 744: Fourth conductive layer 800: photoelectric device 810: display panel 820: electronic component ^ Csl: storage capacitor CS21, Cs31, CS41, Cs51, Cs61, CS71: first storage capacitor Cs52, cs62, cs72: second storage capacitor cs53, cs63 , cs73: third storage capacitor DT2, DT41, DT42 ' DT5, DT71, DT72: data line 'SC2, SC4, SC5, SC7: scan line

Vc〇m2, Vcom4, Vcom5, Vcom7 · Common electrode line 35

Claims (1)

I36M93 101.02月09日桉正换页2012/2/9_1sl Shen Fu & Amendment 7. Patent scope: 1. A pixel structure comprising: at least one transistor; a semiconductor layer; an insulating layer, Covering the semiconductor layer, and having at least two first openings; a first storage capacitor and a second storage capacitor electrically connected to the transistor; a first conductive layer formed on the insulating layer; An inner dielectric layer covering the first conductive layer and having at least one second opening; 'a second conductive layer formed on a portion of the inner dielectric layer, and a portion of the second conductive layer The second opening is electrically connected to the first conductive layer, wherein the second conductive layer connected to the first conductive layer is connected to the semiconductor layer, and the second conductive layer connected to the first conductive layer is The semiconductor layers are separated from each other; a protective layer covering the transistor and the second conductive layer, and having at least one third opening; a third conductive layer forming part of the protective layer, and via the Third opening electrical connection In the transistor, the first storage capacitor is composed of the second conductive layer, the protective layer and the second conductive layer. The second storage capacitor is composed of the first conductive layer, the insulating layer and the portion. The semiconductor layer is composed of. 2. For the structure of the element as described in the first paragraph of the patent application, 10013:0030: 1013047.241:-0 36 1361493 _l February 09, 2011 Shuttle replacement page 2012/2/9_1sl Application & Amendment The material of at least one of the second conductive layer and the third conductive layer includes a light transmissive material, a reflective material, or a combination thereof. 3. The pixel structure of claim 1, further comprising: a third storage capacitor, the second conductive layer, the inner dielectric layer, the insulating layer and a portion of the semiconductor layer. 4. The pixel structure of claim 1, wherein the semiconductor layer comprises at least one tweeter region, at least one intrinsic region, or a combination thereof. 5. The halogen structure according to claim 1, wherein the first conductive layer and the second conductive layer have substantially the same level. 6. The halogen structure of claim 1, wherein the levels of the first conductive layer and the second conductive layer comprise a common level. 7. The pixel structure of claim 1, wherein the material of the first conductive layer comprises a reflective material. 8. The halogen structure according to claim 1, wherein the first conductive layer is connected to a common electrode line. 9. The pixel structure of claim 1, further comprising: a data line electrically connected to one of a source and a drain of the transistor; and a scan line, electrical Connected to one of the gates of the transistor. 10. The pixel structure of claim 1, wherein a portion of the second conductive layer constitutes a source and a drain of the transistor, and the source of the transistor and the source The second conductive layer of the drain is not connected to the second conductive layer connected to the first conductive layer, and the second conductive layer constituting the source of the transistor and the drain is coupled to the first conductive layer Layer 100130030; 1013047241:-0 37 I36M93 Modified on February 09, 2011 Revision page 2012/2/9_1sl Application & Corrected second conductive layers are separated from each other. 11. The pixel structure of claim 1, wherein no other conductive layer is present between the semiconductor layer and the first conductive layer. 12. A display panel comprising a plurality of pixel structures as described in claim 1 of the scope of the patent application. 13. An optoelectronic device comprising a display panel as described in claim 12 of the patent application. A method for forming a pixel structure, the pixel structure having at least one transistor, a first storage capacitor and a second storage capacitor electrically connected to the transistor, the forming method comprising: forming a semiconductor layer; Covering an insulating layer on the semiconductor layer, the insulating layer has at least two first openings; forming a first conductive layer on the insulating layer; covering an inner dielectric layer on the first conductive layer, and having a Forming a second conductive layer on a portion of the inner dielectric layer, wherein a portion of the second conductive layer is electrically connected to the first conductive layer via the second opening, wherein the first conductive layer is connected to the first The second conductive layer of the conductive layer is not connected to the semiconductor layer, and the second conductive layer connected to the first conductive layer is separated from the semiconductor layer; covering a protective layer on the transistor and the second conductive layer And having a third opening; and forming a third conductive layer on a portion of the protective layer, and via the third 10013^0030** ... . 10130.47241:-0 38 1361493 _ February 2011 Corrected page on 09th The second and second storage layers are electrically connected to the transistor, wherein the first storage capacitor is composed of the second conductive layer, the protective layer and the second conductive layer. The storage capacitor is composed of the first conductive layer, the insulating layer, and a portion of the semiconductor layer. 15. The method according to claim 14, wherein the material of at least one of the second conductive layer and the third conductive layer comprises a light transmissive material, a reflective material, or a combination thereof. 16. The method according to claim 14, wherein the pixel structure further comprises a third storage capacitor, the second conductive layer, the inner dielectric layer, the insulating layer and a portion of the semiconductor layer Composition. 17. The method of forming of claim 14, wherein the semiconductor layer comprises at least one doped region, at least one intrinsic region, or a combination thereof. 18. The method of forming the method of claim 14, wherein the first conductive layer and the second conductive layer have substantially the same level. 19. The method of forming the method of claim 14, wherein the levels of the first conductive layer and the second conductive layer comprise a common level. 20. The method according to claim 14, wherein the material of the first conductive layer comprises a reflective material. 21. The method of forming of claim 14, wherein the first conductive layer is connected to a common electrode line. 22. The method of forming according to claim 14, further comprising: forming a data line electrically connected to one of a source and a drain of the transistor; and 100130030 .* · . 1013047.241-0 39 1361493 101. February 09 Yongzheng Replacement Page 2012/2/9_1sl Application & Correction Form a scan line electrically connected to one of the gates of the transistor. 23. The method of forming the method of claim 14, wherein a portion of the second conductive layer constitutes a source and a drain of the transistor, and the source of the transistor and the anode The second conductive layer is not connected to the second conductive layer connected to the first conductive layer, and the source and the second conductive layer constituting the gate are coupled to the first conductive layer The second conductive layers are separated from each other. 24. The method of forming of claim 14, wherein no other conductive layer is formed between the semiconductor layer and the first conductive layer. A method of forming a display panel comprising the method of forming a halogen structure as described in claim 14. A method of forming a photovoltaic device, comprising the method of forming a display panel according to claim 25 of the patent application. 10013Ό030; 1013 Q47.2 41:-〇 40