201201633 六、發明說明： 【發明所屬之技術領域】 種印 本發明係有關於-種電子構件，特別係有關於 刷電路板。 【先前技術】 1因應電子產品輕、薄、短、小等需求，基板 -凡的體積也需縮小。加上半導體元件因為高速了 和多功能運作的需求，而導致輸入輸出端數目持續增^ 因此，需要大幅增加印刷電路板與晶片的接如^ =高印:電路板的線路密度，卿 鋼板開产及^而’在習知的印刷電路板製程中，係利用 門璟：二“P刷方式形成焊錫凸塊’因而受限於鋼板 b:=制’容易在印卿—後’產生錫一 塗佈:問二’技術於印刷電路板之綠漆 ϊ製焊錫凸塊之方式，可於後段封 然而，m〜曰曰片上的凸塊接合’解決錫橋的問題。 顯影及熱處J等::綠^土形成銅柱’共需塗佈、曝光、 上方、主且凡成綠漆層後，尚需於綠漆開環 杂複雜'仃影像轉移，並搭配電鍍鋼形成銅柱。製程相 二的負擔。舉例來說，“ 彳，而要]〇片光罩來完成影像轉移 201201633 之製作。 根據上述，業界需要一種印刷電路板及其製作方法， 以改善上述缺點。 【發明内容】 本發明提供一種印刷電路板，包括一電路基板，電路 基板具有一第一線路結構；至少一增層線路結構，設置於 該電路基板之第一線路結構上；一頂絕緣層，設置於該至 少一增層線路結構上；一導電盲孔，設置於該頂絕緣層中； 及一金屬凸塊，設置於該頂絕緣層中之導電盲孔上，其中 該金屬凸塊與該導電盲孔具有不同的形狀或尺寸。 本發明另提供一種印刷電路板，包括一電路基板，電 路基板具有一第一線路結構；至少一增層線路結構，設置 於該電路基板之第一線路結構上；一頂絕緣層，設置於該 至少一增層線路結構上；複數個導電盲孔，設置於該頂絕 緣層中；及一金屬墊，設置於該頂絕緣層中之複數個導電 盲孔上，其中該金屬墊之尺寸大於上述導電盲孔之尺寸， 且經由上述導電盲孔電性連接該至少一增層線路結構之電 性連接墊。 為讓本發明之上述目的、特徵及優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 【實施方式】 以下以各實施例詳細說明並伴隨著圖式說明之範例， 201201633 做為本發明之參考依據。在圖式或說明書描述中，相似或 相同,部分皆使用相同之圖號，且在圖式中，實施例之形 狀或是厚度可擴大，並以方便、簡化的方式予以標示。再 者:圖式中各元件之部分將以分別描述說明之’值得注意 的是’圖中未綠示或描述之元件，為所屬技術領域中且^ 通常知識者所知的形式，另外，特定之實施例僅為揭示本 發明使用之特定方式，並非用以限定本發明。 第1A〜II圖為本發明一實施例之印刷電路板之製程剖 面圖。請參考第1’首先’提供-電路基板⑽，其具 有-第-表面102和相對的—第二表面1()4，電路基板⑽ 之核心材質可包括紙質祕樹脂(paper Phenolic resin)、複 合環氧樹脂（咖pGsite epGxy)、聚亞醯胺樹脂⑽細如 res^«^^(glass^^ ^ 基^ 100的部分第_表自102和第二表自1〇4，且藉由通201201633 VI. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to an electronic component, and more particularly to a brush circuit board. [Prior Art] 1 In response to the demand for light, thin, short, and small electronic products, the volume of the substrate must be reduced. In addition, due to the high-speed and multi-function operation of semiconductor components, the number of input and output terminals continues to increase. Therefore, it is necessary to greatly increase the connection between the printed circuit board and the chip, such as the high density: the circuit density of the circuit board. Production and ^ and 'in the conventional printed circuit board process, the use of threshold: two "P brush way to form solder bumps" and thus limited by the steel plate b: = system 'easy to print in the after- Coating: Q2's the way of green soldering solder bumps on printed circuit boards, which can be sealed in the back section, however, the bumps on the m~ bismuth sheet are used to solve the problem of the tin bridge. Development and heat J, etc. :: Green ^ soil forms a copper column 'a total of coating, exposure, top, main and where the green paint layer, it is still necessary to open the green paint complex '仃 image transfer, and with the galvanized steel to form a copper column. The burden of phase two. For example, "彳, but want" a reticle reticle to complete the production of image transfer 201201633. In light of the foregoing, there is a need in the industry for a printed circuit board and method of making the same to improve the above disadvantages. SUMMARY OF THE INVENTION The present invention provides a printed circuit board including a circuit substrate having a first circuit structure, at least one build-up line structure disposed on the first circuit structure of the circuit substrate, and a top insulating layer. Provided on the at least one build-up line structure; a conductive via hole disposed in the top insulating layer; and a metal bump disposed on the conductive via hole in the top insulating layer, wherein the metal bump is Conductive blind holes have different shapes or sizes. The present invention further provides a printed circuit board comprising a circuit substrate having a first line structure; at least one build-up line structure disposed on the first line structure of the circuit substrate; a top insulating layer disposed on the At least one layered circuit structure; a plurality of conductive blind holes disposed in the top insulating layer; and a metal pad disposed on the plurality of conductive blind holes in the top insulating layer, wherein the metal pad has a size larger than the above The size of the conductive via hole is electrically connected to the electrical connection pad of the at least one build-up line structure via the conductive via hole. The above described objects, features, and advantages of the present invention will become more apparent from the aspects of the appended claims appended claims 201201633 is used as a reference for the present invention along with examples of schema descriptions. In the drawings or the description of the specification, the same reference numerals are used for the same or the same, and in the drawings, the shapes or thicknesses of the embodiments may be enlarged and indicated in a convenient and simplified manner. Further, parts of the various elements in the drawings will be described as "notable" in the figures, which are not shown or described in the drawings, and are known in the art and known to those skilled in the art, and The embodiments are merely illustrative of specific ways of using the invention and are not intended to limit the invention. 1A to II are cross-sectional views showing a process of a printed circuit board according to an embodiment of the present invention. Please refer to the first 'first' supply-circuit substrate (10) having a -first surface 102 and an opposite - second surface 1 () 4, the core material of the circuit substrate (10) may include paper Phenolic resin, composite Epoxy resin (coffee pGsite epGxy), polyamidamine resin (10) as fine as res ^ « ^ ^ (glass ^ ^ ^ base ^ 100 part of the _ table from 102 and the second table from 1 〇 4, and by pass
2貫穿電路基板_，並在通孔中形成灌細旨11G 發明一貫施例中，第一螬玖钍进π A ± 4 弟、線路、U冓可包括貫穿電路基板100 、^ 8、填滿通孔之灌孔樹脂110和覆蓋電路美板 100的部分第-表面102和第一夺電路基板 — 柙弟一表面1〇4的第一線路1〇6。 在本發明-貫施例中’第_線路106的材質可包括錦、金、 錫、船、銅、叙、銀、鉻、鶴、石夕或其組合及上述之合金。 ^路]06的形成方式包括先利用常用 塗佈製程分別於電路基板】00的第一表 2 r上全面性形成一導電層(圖未顯示)。在^ 球側表面。接著，利用影像轉移製程，即經由覆蓋光阻載 201201633 曝光、顯影（developing)的步驟，形成一圖案化光阻層，以 曝露出部分導電層。之後，再分別於曝露出導電層的部分 第一表面102和第二表面104上形成第一線路106。接著， 於電路基板100的第一表面102和第二表面104和第一電 路106上形成一第一絕緣層112。在本發明一實施例中， 第一絕緣層112是以壓合之方式形成於電路基板100之第 一表面102和第二表面104上，第一絕緣層112可以是環 氧樹脂（epoxy resin)、雙馬來亞醯胺-三氮雜苯樹脂 (bismaleimie triacine，BT)、聚亞醯胺(polyimide，PI)、ABF 膜（ajinomoto build-up film)、聚苯&|(poly phenylene oxide, PPE)、聚丙稀（polypropylene, PP)、基丙稀酸甲脂 (polymethyl methacrylate, PMMA)或聚四氟乙烯 (polytetrafluorethylene，PTFE)等。 請參考第IB圖，可使用例如雷射鑽孔之方式於電路基 板100之第一表面102和第二表面104上之第一絕緣層112 形成孔洞114。在本發明一實施例中，孔洞114係暴露第一 線路106，以於後續步驟形成第一導電盲孔。 接著，請參考第1C圖，可利用貼附、塗佈、印刷、壓 合等方式，於第一絕緣層112上形成一光阻層（未繪示）。再 進行曝光、顯影（developing)步驟，以於第一絕緣層112上 形成圖案化光阻層116。請參考第1D圖，可進行一電鍍製 程（因預先形成導電層為電鍍製程之習知技術，故省略未再 詳加說明），於未被圖案化光阻層116覆蓋之第一絕緣層112 上和孔洞114中分別形成一第一增層線路120、第一電性 連接墊122和第一導電盲孔118。在本發明一實施例中， 201201633 第一導電盲孔118、第一電性連接墊]22和第一增層線路 120可包括鎳、金、錫、紹、銅、銘、銀、鉻、鶴、石夕或 “ °且5及上述之合金。然後，進行去膜（striping)步驟，移 除圖案化光阻層116。 之後，如第]E圖所示，可重複第〗B圖至第1D圖之 製程，再於第—絕緣層】22、第一增層線路12〇和第一電 性連接墊122上形成第二絕緣層124、第二導電盲孔126、 第一電性連接墊128和第二增層線路130，以形成包括複 數個第二絕緣層124、第二導電盲孔126、第二電性連接墊 128和第一增層線路丨3〇垂直堆疊而成的第二增層線路結 構（為了方便顯示，本發明實施例僅顯示由兩層絕緣層構成 的增層線路結構，增層線路結構的層數可依產品設計的需 求變更）。 请參考第1F圖’於電路基板1〇〇的第一表面1〇2和第 二表面104最上方之增層線路上形成一頂絕緣層132。在 本發明一實施例中’頂絕緣層132是以壓合之方式形成在 電路基板100之第一表面102和第二表面104上方之第二 增層線路結構上。頂絕緣層132可以包括環氧樹腊（ep〇xy resin)、雙馬來亞酿胺-二氮雜苯樹脂（bismaleimie triacine， BT)、聚亞醯胺(polyimide, PI)、ABF 膜（ajinomoto build-up film)、聚苯醚（poly phenylene oxide，PPE)、聚丙稀 (polypropylene, PP)、基丙稀酸甲脂(polymethyl methacrylate, PMMA)或聚四氟乙烯(polytetrafluorethylene，PTFE)等。 請參考第〗G圖，使用例如雷射鐵孔之方式於電路基 板100之第一表面102和第二表面104上方之頂絕緣層丨32 201201633 形成孔洞]34。在本發明-實施例中，孔洞i34係暴露最 上層之增層線路結構（亦即第二增層線路13〇及/或 性連接墊128)，以於後續步驟形成導電盲孔。〆2 penetrating the circuit board _, and forming a fine-grained 11G in the through-hole. In the consistent embodiment of the invention, the first π A ± 4, the line, the U 冓 may include the through-circuit substrate 100, ^ 8, filling The through hole resin 110 and the portion of the first surface 102 covering the circuit board 100 and the first circuit board - the first line 1〇6 of the surface 1〇4. In the present invention, the material of the 'th row 106' may include brocade, gold, tin, boat, copper, sulphur, silver, chromium, crane, shoal or combinations thereof and the alloys described above. The way of forming the circuit 06 includes first forming a conductive layer (not shown) on the first surface 2 r of the circuit substrate 00 by using a common coating process. On the side of the ball. Next, a patterned photoresist layer is formed by an image transfer process, i.e., by a step of exposure and development of the photoresist resist 201201633, to expose a portion of the conductive layer. Thereafter, a first line 106 is formed on portions of the first surface 102 and the second surface 104 that expose the conductive layer, respectively. Next, a first insulating layer 112 is formed on the first surface 102 and the second surface 104 of the circuit substrate 100 and the first circuit 106. In an embodiment of the invention, the first insulating layer 112 is formed on the first surface 102 and the second surface 104 of the circuit substrate 100 in a press-fit manner, and the first insulating layer 112 may be an epoxy resin. , bismaleimie triacine (BT), polyimide (PI), abinomoto build-up film, polyphenylene oxide, PPE), polypropylene (PP), polymethyl methacrylate (PMMA) or polytetrafluorethylene (PTFE). Referring to Figure IB, holes 114 may be formed in the first surface 102 of the circuit substrate 100 and the first insulating layer 112 on the second surface 104 using, for example, laser drilling. In one embodiment of the invention, the holes 114 expose the first line 106 to form a first conductive blind via in a subsequent step. Next, referring to FIG. 1C, a photoresist layer (not shown) may be formed on the first insulating layer 112 by means of attaching, coating, printing, pressing, or the like. An exposure and development step is further performed to form a patterned photoresist layer 116 on the first insulating layer 112. Referring to FIG. 1D, an electroplating process (a conventional technique in which a conductive layer is formed into a plating process in advance, and therefore not described in detail) is omitted, and the first insulating layer 112 is not covered by the patterned photoresist layer 116. A first build-up line 120, a first electrical connection pad 122 and a first conductive blind via 118 are formed in the upper and the holes 114, respectively. In an embodiment of the present invention, the 201201633 first conductive blind via 118, the first electrical connection pad 22, and the first build-up line 120 may include nickel, gold, tin, sho, copper, m, silver, chrome, crane , Shi Xi or " ° and 5 and the above alloy. Then, a stripping step is performed to remove the patterned photoresist layer 116. Thereafter, as shown in Fig. E, the image can be repeated a process of the 1D pattern, a second insulating layer 124, a second conductive via 126, and a first electrical connection pad are formed on the first insulating layer 22, the first build-up line 12A, and the first electrical connection pad 122. 128 and the second build-up line 130 to form a second stack comprising a plurality of second insulating layers 124, second conductive blind vias 126, second electrical connection pads 128, and first build-up traces 〇3〇 In order to facilitate the display, the embodiment of the present invention only shows the build-up line structure composed of two insulating layers, and the number of layers of the build-up line structure can be changed according to the requirements of product design. Please refer to FIG. 1F' Forming on the first surface 1〇2 of the circuit substrate 1 and the build-up line at the top of the second surface 104 A top insulating layer 132. In an embodiment of the invention, the top insulating layer 132 is formed on the second build-up line structure over the first surface 102 and the second surface 104 of the circuit substrate 100 in a press-fit manner. The insulating layer 132 may include ep〇xy resin, bismaleimie triacine (BT), polyimide (PI), ABF film (ajinomoto build). -up film), polyphenylene oxide (PPE), polypropylene (PP), polymethyl methacrylate (PMMA) or polytetrafluoroethylene (PTFE), etc. Please refer to In the first embodiment, a hole] 34 is formed on the first surface 102 of the circuit substrate 100 and the top insulating layer 201 32 201201633 above the second surface 104. In the present invention-embodiment, the hole i34 The topmost build-up line structure (ie, the second build-up line 13 and/or the connection pads 128) is exposed to form conductive vias in subsequent steps.
請參考f 1H目，可利用貼附、塗佈、印刷、壓合等 方式’於頂絕緣層】32上形成一光阻層（未緣示）。再進行 曝光、顯影(deVeioping)步驟，以於頂絕緣層132上形成圖 案化光阻層136。值得注意的是，本實施例之圖案化光阻 層136除了覆蓋頂絕緣層132，尚覆蓋於部分之孔洞134 ^方’且於孔洞134上方包括特定形狀之開口 135，例如 第2A圖所示’圖案化光阻層136於頂絕緣層⑶之孔洞 134上包括十字形之開口 135，或如第2b圖所示，圖案化 光阻層m於頂絕緣層132之孔洞m上包括圓形之開口 135’該圓形之開口 135的直徑小於其下孔洞之直徑。 接下來，請參照第„ _，進行—魏製程（因預先形 成導電層為電料程之習知技術，故省略未再詳加說明）， 於未被圖案化光阻層136覆蓋之頂絕緣層132上和孔洞134 令刀別形成-金屬凸塊138和導電盲孔14〇。然後，進行 ，膜（striping)步驟，移除圖案化光阻層136。值得注意的 是’本實施例電鐘製程會經由圖案化光阻層136之開:將 ^材料填滿孔洞134 ’形成導電盲孔140,並可根據圖案 ^且層⑶之開口 135的特定形狀，形成具有特定形狀 :屬凸塊138。例如，由於第2八圖所示之圖案化光阻層 於頂絕緣層132之孔㈣134上係包括十字形之開口 你UI·’本其會如第3A圖和第3B目所示（第3A義示本實施 i之上視圖’第3B圖顯示本實施例此步驟之立體 201201633 圖）’於導電盲孔14〇上形成十字形之金屬凸塊138。 在另一實施例中，由於第2B圖所示之圖案化光阻層 136於頂絕緣層132之孔洞]34上包括圓形之開口 135，其 會如第4A圖和帛4B圖所示（第4A _示本實施例此步驟 之上視圖，第4B圖顯示本實施例此步驟之立體圖，其更产 楚的描述圓形之金屬凸塊]38和導電盲孔14〇之形狀、: 寸和位置關係），於導電盲孔刚上形成圓柱形之金屬凸塊 ⑽，且圓柱形之金屬凸塊138的直徑小於導電盲孔之 直徑。本發明不限定導電盲孔14〇上金屬凸塊138的形狀 或尺寸，其可依與印刷電路板搭接的晶片的設計需求決Referring to the f 1H mesh, a photoresist layer (not shown) may be formed on the top insulating layer 32 by attaching, coating, printing, pressing, or the like. A step of exposure and development (deVeioping) is further performed to form a patterned photoresist layer 136 on the top insulating layer 132. It should be noted that, in addition to the top insulating layer 132, the patterned photoresist layer 136 covers a portion of the hole 134 square and includes a specific shape opening 135 above the hole 134, for example, as shown in FIG. 2A. The patterned photoresist layer 136 includes a cross-shaped opening 135 on the hole 134 of the top insulating layer (3), or as shown in FIG. 2b, the patterned photoresist layer m includes a circular shape on the hole m of the top insulating layer 132. The diameter of the opening 135 of the opening 135' is smaller than the diameter of the lower hole. Next, please refer to the first „ _, performing the Wei process (the prior art is formed by the prior art, the conductive layer is a conventional technique), and the top insulating layer 132 is not covered by the patterned photoresist layer 136. The upper and the holes 134 cause the knives to form - the metal bumps 138 and the conductive blind holes 14 。. Then, a stripping step is performed to remove the patterned photoresist layer 136. It is noted that the electric clock process of the present embodiment Via the patterned photoresist layer 136: the material fills the holes 134' to form the conductive blind vias 140, and can be formed into a specific shape according to the pattern and the specific shape of the openings 135 of the layer (3): the bumps 138. For example, since the patterned photoresist layer shown in FIG. 8A includes a cross-shaped opening on the hole (four) 134 of the top insulating layer 132, the UI will be as shown in FIG. 3A and FIG. 3B (3A). The top view of the present embodiment is shown in FIG. 3B, which shows the three-dimensional 201201633 diagram of this step of the present embodiment. 'The cross-shaped metal bump 138 is formed on the conductive blind hole 14〇. In another embodiment, due to the second BB The patterned photoresist layer 136 is shown in the hole of the top insulating layer 132] The circular opening 135 is included, as shown in FIG. 4A and FIG. 4B (the fourth embodiment shows the top view of this step in the embodiment, and the fourth embodiment shows the perspective view of the step in the embodiment, which is more prolific. Describe the shape of the circular metal bumps 38 and the conductive blind holes 14 、, and the position and position relationship), the cylindrical metal bumps (10) are formed on the conductive blind holes, and the diameter of the cylindrical metal bumps 138 Less than the diameter of the conductive blind hole. The present invention does not limit the shape or size of the conductive bump 14 on the metal bump 138, which can be determined according to the design requirements of the wafer to which the printed circuit board is overlapped.
定。舉例來說，十字形之金屬凸塊138可同時連接晶片I 數個連接墊’具有較小尺寸之圓柱形金屬凸塊138可連接 晶片上較小尺寸的連接墊。 以 根據上述，本實施例印刷電路板及其製造方法具有 下特點：第-、本實施例印刷電路板及其製造方法因採電 鑛方式形成與晶片搭接之金屬塾，故不受限於鋼板開孔能 力的限制，可應用於更高線路密度之印刷電路板。第二、 本實施例印刷電路板於其最頂層制絕緣層取代綠漆了可 縮紐整體印刷電路板生產時間及製程成本1三、本實施 元 例可省略傳統錫膏印刷製程，並提供可與晶片搭接之多 化的金屬凸塊。 第5A〜5H圖顯示本發明另一實施例之印刷電路板之 ^程剖面圖。請參考第从圖，首先，提供—電路基板搬， /、具有-第-表面504和相對的一第二表面篇，電路基 板5〇2之核心材質可包括紙質⑽樹脂（PaPerphen〇lic 201201633 resin)、複合環氧樹脂（composite epoxy)、聚品 — 匕 人迎驅胺樹脂 (polyimide resin)或玻璃纖維（glass fiber)。一结 卑一線路結 構’覆盍電路基板502的部分第一表面5〇4和第一表面 506 ’且藉由通孔貫穿電路基板502，並在通孔中升< 成:霍孔 樹脂514。在本發明一實施例中，第一線路結構可包括貫 穿電路基板502的導通孔508、填滿通孔之滋π & 、 〜’隹孔樹脂514 和覆蓋電路基板502的部分第一表面504和筮_ * ^ 乐〜表面506set. For example, the cross-shaped metal bumps 138 can simultaneously connect the wafer I to a plurality of connection pads. A cylindrical metal bump 138 having a smaller size can be connected to a smaller size connection pad on the wafer. According to the above, the printed circuit board and the manufacturing method thereof of the present embodiment have the following features: - the printed circuit board of the present embodiment and the manufacturing method thereof are formed by metal rafting with the wafer by the mining method, and thus are not limited The limitation of the opening capacity of the steel plate can be applied to printed circuit boards with higher line density. Secondly, the printed circuit board of the embodiment replaces the green lacquer in the topmost insulating layer of the printed circuit board, and the manufacturing time and process cost of the whole printed circuit board are reduced. The third embodiment can omit the traditional solder paste printing process and provide A metal bump that overlaps the wafer. 5A to 5H are cross-sectional views showing a printed circuit board according to another embodiment of the present invention. Please refer to the following figure. First, the circuit substrate is moved, /, having a - surface 504 and an opposite second surface. The core material of the circuit substrate 5〇2 may include paper (10) resin (PaPerphen〇lic 201201633 resin) ), composite epoxy, poly-products - polyimide resin or glass fiber. A portion of the first line structure 〇4 and the first surface 506' of the circuit substrate 502 are covered by the through-hole and penetrate the circuit substrate 502 through the through hole, and are formed in the through hole by a hole-hole resin 514. In an embodiment of the invention, the first line structure may include a via hole 508 penetrating the circuit substrate 502, a π & 〜 隹 隹 树脂 resin 514 filled in the via hole, and a portion of the first surface 504 covering the circuit substrate 502和筮_ * ^ 乐〜面506
的第一線路510。在本發明一實施例中，第一線路51〇的 材質可包括鎳、金、錫、鉛、銅、鋁、銀、鉻、鶴、石夕咬 其組合及上述之合金。在本發明一實施例中，第一表面5〇4 可為晶片側表面’第二表面506可為載球侧表面。接著， 於電路基板502的第一表面504和第二表面5〇6和第一線 路510上形成一第一絕緣層512。在本發明一實施例中， 第一絕緣層512是以壓合之方式形成在電路基板5〇2之第 一表面504和第二表面506上’第一絕緣層512可以是環 氧樹脂（epoxy resin)、雙馬來亞醯胺三氮雜苯樹脂 (bismaleimie triacine，BT)、聚亞醯胺(polyimide，PI)、ABF 膜(ajinomoto build-up film)、聚苯醚(poly phenylene oxide, PPE)、聚丙烯（polypropylene，PP)、基丙烯酸甲脂 (polymethyl methacrylate, PMMA)或聚四氟乙稀 (polytetrafluorethylene, PTFE)等。 請參考第5B圖，可使用例如雷射鑽孔之方式於電路基 板502之第一表面5 04和第二表面506上之第一絕緣層512 中形成孔洞516。在本發明一實施例中，孔洞516係暴露 第一線路510，以於後續步驟形成導電盲孔。 201201633 ’二參考綱’可利用貼附、塗佈、印刷、壓 Π—絕緣層512上形成-光阻層(未繪示)。 再^先、顯影（developing)步驟，以於第一絕緣層512 上形成圖案化光阻層518。請參考第5D圖，可進行一電鍵 製程（因預先形成導電層為電鍍製程之f知技術，故省略未 再評加說明），於未被圖案化光阻層518覆蓋之第—絕緣層 512和孔洞516中分別形成一第一增層線路524、第-電性 連接墊520和第—遙雷言$ 第-導電盲孔功、第一電性連接明一實施例中， ^可包括鎳、金二m第一增層線路 。1 m链、銀、鉻、鶴、石夕或 一、、’ a及上述之δ金。然後，進行去膜（也扣吨)步驟，移 除圖案化光阻層518。 之後’請參考第5E圖’可重複第5b圖至第5D圖之 1私再於第絕緣層512、第一增層線路似和第一電 =塾=，第二絕緣層细、第二電性連接塾 、/、第一導電目孑匕528和第二增層料532,以形成包括 複數個第二絕緣層526、第二電性連接墊530、第二導電盲 孔528和第二增屛綠妨 矛守电目 結構(為了方便顯;=!直堆叠而成的第二增層線路 成的增㈣路結構)。本發財施例僅顯^由樣絕緣層構 I 21丨圖’於電路基板502的第一表面504和第 :發明-實Γ例中方=層線路上形成一頂絕緣層別。在 電路基板502之第」==是以壓合之方式形成在 增層線路結構上。頂^ 1 —表面506上方之第二 項'、、邑緣層534可以包括環氧樹脂(ep〇xy 12 201201633 resin)、雙馬來亞酿胺-三氣雜笨樹脂（bismaleimie triacine, BT)、聚亞酿胺（polyimide, PI)、ABF 膜（ajinomotobuild-up film)、聚苯醚（poly phenylene oxide, PPE)、聚丙烯 (polypropylene, PP)、基丙稀酸曱脂(poiymethyl methacrylate, PMMA)或聚四氟乙烯(polytetrafluorethylene, PTFE)等。 請參考第5G圖’使用例如雷射鑽孔之方式於電路基 板502之第一表面504和第二表面506上方之頂絕緣層534 形成孔洞536。在本發明一實施例中，孔洞536係暴露最 上層之增層線路及/或電性連接墊（亦即第二增層線路532 及/或第二電性連接墊530)，以於後續步驟形成導電盲孔。 在此步驟需注意的是，由於本實施例印刷電路板之下側（第 二表面506側）之金屬墊是要與母板(mother board)之球格 陣列（ball grid array，BGA)接合，其尺寸相對較印刷電路板 之上側（第一表面504側）的金屬墊大。一般來說，印刷電 路板之下側（第二表面506側）之金屬墊之尺寸約為 400~500μιη(亦可依客戶之需求而加大或縮小），而使用雷射 鑽孔之方式只能形成直徑約為3 0〜7 0 μπι的孔洞。根據上 述，本實施例以雷射鑽孔所形成之孔洞，會小於後續形成 的金屬墊。因此，本實施例可如第5Η圖所示’以雷射鑽 孔之方式於電路基板502之第二表面506上方之頂絕緣層 534形成複數個孔洞536。 接著，請繼續參考第5Η圖，可利用貼附、塗佈、印 刷、壓合等方式，於頂絕緣層534上形成一光阻層（未繪 示）。再進行曝光、顯影（developing)步驟’以於頂絕緣層 534上形成圖案化光阻層538。值得注意的是，本實施例之 201201633 1路基板502之第二表面5〇6上方之圖案化光阻層538之 ITtt’ 暴露上述複數個雷射鑽孔方式形成之孔洞 者’ #參照第5；[圖，進行—f料程，於未被圖 案化光阻層538覆蓋之頂絕緣層534上和上述孔洞別中 分別形成-金屬墊542和柱形之導電盲孔54〇。缺後，進 行去膜（striping)步驟，移除圖案化光阻層538。 第6A圖顯示本發明一貫施例部分印刷電路板下侧（第 二表面506側）部分上視圖1 6β圖為沿第6八圖^，剖面 ，之剖面圖’以更詳細的顯示金屬塾和導電盲孔之位置和 關係。在第6A圖和第紐圖之實施例中，上述雷射鑽孔只 形成一個孔洞’因此，在電鍍製程之後，金屬墊602僅以、 :較^尺寸的柱形導電盲孔_連接第二增層線路結構之 第=性連接娜第7A圖顯示本發明另一實 職之上視圖，第7B圖係沿第7a圖w，剖面線之 ::r形成UA圖和第^圖之實施例中，上述雷射鑽孔 衣釭形成稷數個孔洞，因此，在電鍍製程之後，金 可以複數個的導電盲孔7〇4連接第二增層線路結構 電性連接塾706。 一 第Μ圖和第7B圓之實施例的印刷電路板相對於 =第6Β圖之實施例的印刷電路板由於以較多的柱 ’盲孔連接金屬塾和第二增層線路結構之第二電性 墊，因此可提供較好的支撐性和信賴性。 雖然本發明已揭露較佳實施例如上，然 定本發明’任何熟悉此項技藝者，在不脫離本發日;:: 和範圍内’當可做些許更動麵飾，因此本發;^ 圍當視後附之申請專利範圍所界定為準。 保瘦乾 201201633 【圖式簡單說明】 第1A〜II圖顯示本發明一實施例之印刷電路板之製程 剖面圖。 第2A圖顯示本發明一實施例之印刷電路板在頂絕緣層 上形成圖案化光阻層後之上視圖。 第2B圖顯示本發明另一實施例之印刷電路板在頂絕緣 層上形成圖案化光阻層後之上視圖。 第3A圖顯示本發明一實施例之印刷電路板形成十字型 金屬凸塊步驟後之上視圖。 第3B圖顯示本發明一實施例之印刷電路板形成十字型 金屬凸塊步驟後之立體圖。 第4A圖顯示本發明一實施例之印刷電路板形成圓型金 屬凸塊步驟後之上視圖。 第4B圖顯示本發明一實施例之印刷電路板形成圓型金 屬凸塊步驟後之立體圖。 第5A〜51圖顯示本發明另一實施例之印刷電路板之製 程剖面圖。 第6A圖顯示本發明一實施例之印刷電路板形成連接球 格陣列結構之金屬墊後之上視圖。 第6B圖顯示本發明一實施例之印刷電路板形成連接球 格陣列結構之金屬墊後之剖面圖。 第7A圖顯示本發明另一實施例之印刷電路板形成連接 球格陣列結構之金屬墊後之上視圖。 第7B圖顯示本發明另一實施例之印刷電路板形成連接 球格陣列結構之金屬墊後之剖面圖。 201201633 【主要元件符號說明】 100〜電路基板； 104〜第二表面； 108〜導通孔； 112〜第一絕緣層； 116〜圖案化光阻層； 120〜第一增層線路； 124〜第二絕緣層； 128〜第二電性連接墊； 132〜頂絕緣層； 135〜開口； 138〜金屬凸塊； 502〜電路基板， 506〜第二表面； 510〜第一線路； 514〜灌孔樹脂； 518〜圖案化光阻層； 522〜第一導電盲孔； 526〜第二絕緣層； 530〜第二電性連接墊； 534〜頂絕緣層； 538〜圖案化光阻層； 542〜金屬墊； 604〜導電盲孔； 702〜金屬墊； 706〜第二電性連接墊。 102〜第一表面； 106〜第一線路； 110〜灌孔樹脂； 114〜孔洞； 118〜第一導電盲孔； 122〜第一電性連接墊； 126〜第二導電盲孔； 130〜第二增層線路； 134〜孔洞； 136〜圖案化光阻層； 140〜導電盲孔； 504〜第一表面； 508〜導通孔； 512〜第一絕緣層； 516〜孔洞； 520〜第一電性連接墊； 524〜第一增層線路； 528〜第二導電盲孔； 532〜第二增層線路； 536〜孔洞； 540〜導電盲孔； 602〜金屬墊； 606〜第二電性連接墊； 704〜導電盲孔；The first line 510. In an embodiment of the invention, the material of the first line 51A may include a combination of nickel, gold, tin, lead, copper, aluminum, silver, chromium, crane, and stone stalk and the alloy described above. In an embodiment of the invention, the first surface 5〇4 may be a wafer side surface. The second surface 506 may be a ball side surface. Next, a first insulating layer 512 is formed on the first surface 504 and the second surface 5?6 of the circuit substrate 502 and the first line 510. In an embodiment of the invention, the first insulating layer 512 is formed on the first surface 504 and the second surface 506 of the circuit substrate 5〇2 by pressing. The first insulating layer 512 may be epoxy (epoxy). Resin), bismaleimie triacine (BT), polyimide (PI), abinomoto build-up film, polyphenylene oxide (PPE) ), polypropylene (PP), polymethyl methacrylate (PMMA) or polytetrafluoroethylene (PTFE). Referring to Figure 5B, holes 516 may be formed in the first insulating layer 512 of the circuit substrate 502 and the first insulating layer 512 on the second surface 506 using, for example, laser drilling. In one embodiment of the invention, the holes 516 expose the first lines 510 to form conductive vias in subsequent steps. 201201633 The 'two reference frame' can be formed by attaching, coating, printing, and compressing the insulating layer 512 to form a photoresist layer (not shown). Then, a developing step is performed to form a patterned photoresist layer 518 on the first insulating layer 512. Referring to FIG. 5D, a key process can be performed (the first insulating layer 512 is not covered by the patterned photoresist layer 518 because the conductive layer is formed in advance as a plating process). And forming a first build-up line 524, a first-electrode connection pad 520, and a first-to-first conductive connection in the hole 516, the first electrical connection, in the embodiment, ^ may include nickel , Jin Er m first layered line. 1 m chain, silver, chrome, crane, stone eve or one, ' a and the above δ gold. Then, a film removal (also deducting) step is performed to remove the patterned photoresist layer 518. After that, please refer to FIG. 5E, which can repeat the 5th to 5D drawings, and then the first insulating layer 512, the first build-up line and the first electric=塾=, the second insulating layer is fine, and the second electric The first connection 孑匕, 528, and the second build-up layer 532 are formed to include a plurality of second insulating layers 526, a second electrical connection pad 530, a second conductive blind via 528, and a second increase.屛 妨 妨 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守 守The present invention can only form a top insulating layer on the first surface 504 of the circuit substrate 502 and the first-layer circuit of the invention-implemented example. The "==" of the circuit board 502 is formed on the build-up line structure by press-fitting. The top item 1 - the second item above the surface 506, the edge layer 534 may comprise epoxy resin (ep〇xy 12 201201633 resin), bismaleimie triacine (BT) , polyimide (PI), ABF film (ajinomoto build-up film), polyphenylene oxide (PPE), polypropylene (PP), acrylic acid bismuth (POI) ) or polytetrafluoroethylene (PTFE). Referring to Figure 5G, a hole 536 is formed in the top surface 504 of the circuit substrate 502 and the top insulating layer 534 above the second surface 506 using, for example, laser drilling. In an embodiment of the invention, the holes 536 are exposed to the uppermost layer of the build-up line and/or the electrical connection pads (ie, the second build-up line 532 and/or the second electrical connection pad 530) for subsequent steps. A conductive blind hole is formed. It should be noted in this step that since the metal pad on the lower side (the second surface 506 side) of the printed circuit board of this embodiment is to be bonded to a ball grid array (BGA) of a mother board, The size is relatively larger than the metal pad on the upper side of the printed circuit board (the first surface 504 side). Generally, the size of the metal pad on the lower side of the printed circuit board (the side of the second surface 506) is about 400~500μm (can also be increased or decreased according to the needs of the customer), and only the laser drilling method is used. A hole having a diameter of about 30 to 70 μm can be formed. According to the above, the hole formed by the laser drilling in this embodiment will be smaller than the metal pad formed later. Therefore, the present embodiment can form a plurality of holes 536 in the top insulating layer 534 above the second surface 506 of the circuit substrate 502 by laser drilling as shown in Fig. 5. Next, referring to FIG. 5, a photoresist layer (not shown) may be formed on the top insulating layer 534 by attaching, coating, printing, pressing, or the like. Further, an exposure and development step is performed to form a patterned photoresist layer 538 on the top insulating layer 534. It should be noted that the ITtt' of the patterned photoresist layer 538 above the second surface 5〇6 of the 201201633 one-way substrate 502 of the present embodiment exposes the hole formed by the plurality of laser drilling methods. # #第第5 [FIG., performing a f-process, forming a metal pad 542 and a column-shaped conductive blind via 54 on the top insulating layer 534 not covered by the patterned photoresist layer 538 and the above-mentioned holes. After the absence, a stripping step is performed to remove the patterned photoresist layer 538. Figure 6A shows a partial view of the lower side (second surface 506 side) of the portion of the printed circuit board according to a consistent embodiment of the present invention. Figure 6 is a cross-sectional view along section 6-8, showing the metal 塾 in more detail. The location and relationship of conductive blind holes. In the embodiment of FIG. 6A and FIG. 1, the above-mentioned laser drilling hole forms only one hole. Therefore, after the electroplating process, the metal pad 602 is only connected to the second-sized cylindrical conductive blind hole_ The fourth embodiment of the layered wiring structure shows another top view of the present invention, and the seventh drawing is taken along the 7th drawing w, the section line::r forms the UA diagram and the figure in the embodiment. The laser drilling casket forms a plurality of holes. Therefore, after the electroplating process, the gold may be connected to the second build-up wiring structure electrical connection 706 by a plurality of conductive blind holes 7 〇 4 . The printed circuit board of the embodiment of the first and seventh rounds is opposite to the printed circuit board of the embodiment of the sixth drawing because of the plurality of column 'blind hole connection metal 塾 and the second second layer structure Electrical pads provide better support and reliability. Although the present invention has been disclosed as a preferred embodiment, it is to be understood that the present invention may be used in a manner that does not depart from the present invention; The scope of the patent application attached is subject to the definition. [Simplified Description of the Drawings] Figs. 1A to 1 are sectional views showing the process of a printed circuit board according to an embodiment of the present invention. Fig. 2A is a top plan view showing a printed circuit board according to an embodiment of the present invention after forming a patterned photoresist layer on a top insulating layer. Fig. 2B is a top plan view showing the printed circuit board of another embodiment of the present invention after forming a patterned photoresist layer on the top insulating layer. Fig. 3A is a top plan view showing a step of forming a cross-shaped metal bump of a printed circuit board according to an embodiment of the present invention. Fig. 3B is a perspective view showing the step of forming a cross-shaped metal bump of the printed circuit board according to an embodiment of the present invention. Fig. 4A is a top plan view showing a step of forming a circular metal bump of a printed circuit board according to an embodiment of the present invention. Fig. 4B is a perspective view showing a step of forming a circular metal bump on a printed circuit board according to an embodiment of the present invention. 5A to 51 are cross-sectional views showing the process of a printed circuit board according to another embodiment of the present invention. Fig. 6A is a top plan view showing a printed circuit board according to an embodiment of the present invention in which a metal pad of a ball grid array structure is formed. Fig. 6B is a cross-sectional view showing the printed circuit board of one embodiment of the present invention after forming a metal pad connected to the grid array structure. Fig. 7A is a top plan view showing the printed circuit board of another embodiment of the present invention forming a metal pad connected to the ball grid array structure. Fig. 7B is a cross-sectional view showing the printed circuit board of another embodiment of the present invention after forming a metal pad connected to the ball grid array structure. 201201633 [Description of main component symbols] 100~ circuit substrate; 104~ second surface; 108~ via hole; 112~ first insulating layer; 116~ patterned photoresist layer; 120~ first build-up line; 124~ second Insulation layer; 128~second electrical connection pad; 132~top insulation layer; 135~opening; 138~metal bump; 502~circuit substrate, 506~second surface; 510~first line; 514~filling resin 518~ patterned photoresist layer; 522~first conductive blind via; 526~second insulating layer; 530~second electrical connection pad; 534~top insulating layer; 538~patterned photoresist layer; 542~metal Pad; 604~ conductive blind hole; 702~ metal pad; 706~ second electrical connection pad. 102~first surface; 106~first line; 110~perforation resin; 114~hole; 118~first conductive blind hole; 122~first electrical connection pad; 126~second conductive blind hole; 130~ Two build-up lines; 134 ~ holes; 136 ~ patterned photoresist layer; 140 ~ conductive blind holes; 504 ~ first surface; 508 ~ vias; 512 ~ first insulating layer; 516 ~ holes; 520 ~ first electricity Connection pad; 524~ first build-up line; 528~ second conductive blind hole; 532~ second build-up line; 536~ hole; 540~ conductive blind hole; 602~ metal pad; 606~ second electrical connection Pad; 704~ conductive blind hole;
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