TW201116985A - Generator circuit for control signal of mother board - Google Patents

Abstract

A generator circuit for a control signal of a mother board adapt to a mother board system with receive a transformer power is provided. The generator circuit includes a comparison unit, a delay unit, a wave regulator unit, and a determination unit. The comparison unit outputs a voltage level ready signal according to a first voltage power, a second voltage power, and a third voltage power. The first voltage power, the second voltage power, and the third voltage power is converted by the transformer power. The delay unit is delayed the voltage level ready signal. The wave regulator unit is reduced a status change time of the voltage level ready signal. The determination unit outputs a power ready signal according the voltage level ready signal, a standby state signal, and the transformer power, which the standby state signal outputted by a south bridge of the mother board.

Description

201116985 2009-024 32406twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a signal generating circuit, and (4) relates to a signal generating circuit for simulating a motherboard control signal. [Prior Art] With the advent of the information age, the penetration rate of computer products has also increased year by year. Modern people can not only process files and store data through computers, but also connect to network peaks through the system. The sister is contacted by the Internet and others. This (4) side application of the brain has greatly improved the concept of life. For this reason, the product is suitable for modern people. (10) Silk life forest can be used as a tool - ^ Ο - In general, portable computers are usually designed to be more convenient. On the other hand, desktop-type electrical tests are not able to be moved, so desktop computers are usually bulky and heavy. At present, the rise of the concept of integration and integration has caused the mainframe of the desktop computer to be oriented toward light and pure materials. In the desktop type _ medium: -, the transformer replaces the smaller area and the lesser power supply]: On the surface, the transformer can only replace the power supply source such as the power ready signal. U's example of W, therefore, in order to enable the thin and light host to operate under the authority of the Chuan, so - the signal generating circuit to operate according to the power supply of the transformer ^ 201116985 2009-024 32406twf.doc / n required power ready signal SUMMARY OF THE INVENTION The present invention provides a power supply for a motherboard control signal to generate a power transformer and simulates the production of the ATX power supply: No. 2 to drive the motherboard to operate. The power supply is, and the present invention proposes a motherboard control signal generation receiving-transformer power_-board system. The host ^ ; includes a comparison unit, a delay unit, a whole wave unit, and a t-product parent unit that receives the first voltage source, the second power source - the early voltage source, the second voltage source, and the third voltage source Signal. Wherein, the first voltage source and the second voltage regulator are converted, and the voltage levels of the first voltage source are different from each other. The delay unit 兀 is used to delay the voltage level ready signal. The whole wave unit = whole = Shorten the transition time of the voltage level ready signal. Judging the unit light element, and receiving the power supply and standby status signal of the voltage regulator, in order to output the power supply I according to the ready ^, Lai (4) money and voltage level Lin signal, ^ ' The standby state signal is output by the south bridge of the motherboard. In the embodiment of the invention, the comparison unit includes a first-second comparator and a third comparator. The first comparator receives the first=1, Judging whether the first voltage is ready, and outputting the first ^ according to the first. The first device receives the second voltage source, and is used to determine the second electric quantity, "the second level voltage." The third comparator is connected to 201116985 2009-024 32406twf.doc/n with = the third voltage source is ready, and according to this, the first comparator, the second comparator and the third input terminal are coupled to - The voltage level ready signal is output according to the first level voltage, the second level, and the second level. In the embodiment, the first comparator includes a first connection; and the first one of the first resistors of the first resistor and the first resistor are lightly connected to the first resistor. The terminal and the ground receive the first-divided voltage, and the first and the second are the wheel-in terminal voltage, and the negative input terminal of the first I receives the reference-level voltage of the output terminal of the reference electric power differential amplification. In the embodiment of the present invention, the second comparator described above includes the first and the second operational amplifier. The end source of the third resistor. The fourth electric_connected to the other end of the third resistor and the ground for the second partial pressure. The positive input terminal of the second operational amplifier receives a voltage of 7 knives, the negative input terminal of the second operational amplifier, and the output of the second operational amplifier outputs a second level of electrical waste. Xibao In this turn--implementation, the third comparator package mentioned above is the S-resistance and the third operational amplifier. One end of the fifth resistor is light and two: the second resistor is coupled to the other end of the fifth resistor and is connected: "^^^ the third operational amplifier of the positive input 1 dust, :: the negative input of the two mains Receiving the reference power in this = the real off towel, the motherboard (four) is more including the seventh resistor and the eighth resistor. The seventh resistor is 1_第-= 201116985 2009-024 32406twf.doc/n machine voltage source. The resistor is secreted between the seventh terminal and the ground voltage, and provides a reference voltage. In a consistent embodiment of the invention, the whole wave unit includes a ninth resistor, a tenth resistor, and a fourth operational amplifier. Nine resistance _

Delay unit. The positive input of the fourth operational amplifier H is connected to the other end of the ninth resistor, the negative input terminal of the f-four operational amplifier receives the reference voltage, and the output terminal of the fourth operational amplifier outputs the voltage value after the transition time is shortened. The tenth electric_ is connected to the fourth operational amplification (four) positive input end disc fourth ^ between the output terminals of the amplifier 'where the resistance of the tenth resistor is much larger than the resistance of the resistor. In the present invention, the delay unit described above includes the tenth: heterogeneous and first-capacitor. The tenth-resistance-end receives the first-standby voltage, the original, the younger-electrical_the other-end_ is better than the round-out end of the fresh element and the single-wave end. The first capacitor is the first detection unit, the second detection unit, and the input (four) resistor. The first-(fourth) unit, state signal, ―, according to the standby state signal output fourth level power out the fifth standard _ according to the transformer power supply output fifth level secret. The end of the output resistor receives the second standby power supply = the turn-off end of the other end of the resistor, the first side of the unit, the output unit of the first-side unit ^ and the second unit, to the output level of the unit. Benedictine - New / towel signal. The first pre-measurement unit mentioned above includes 201116985 2009-024 32406twf.doc/n twelfth resistor, thirteenth resistor, first transistor, two transistor. The twelfth resistor 1 receives the standby state signal = the resistance - the end receives the transformer power supply 1 - the transistor has the first end and the control end, the first transistor control one #楚一中曰scale λα - coupled with the ten The other end of the other H-electrode body of the two resistors is coupled to the other end of the thirteenth resistor, and the second transistor of the first transistor is connected to the ground voltage. The fourteenth resistor _ between the 笫-end of the transistor and the grounded electric enchantment H (four) is provided with ^ the control end of the second transistor consuming the first transistor, and the first end of the first electric day is lightly connected to the output At the other end of the resistor, the second terminal of the second transistor is coupled to the ground voltage. In the present invention, the second unit includes the fifteenth resistor, the sixteenth resistor, the seventeenth resistor, and the third transistor. The - terminal of the fifteenth resistor receives the transformer power supply. Feed six electric adapter ^ between the other end of the resistor and the ground voltage. The end of the seventeenth resistor receives the other end of the fifteenth resistor. The third transistor has a first end, a second end, and a control end of the third transistor is connected to the other end of the seventeenth resistor, and the first end of the third transistor is off the other end of the output resistor. The second end of the second end is coupled to the ground voltage. ??? Based on the above, the motherboard control signal generating circuit of the present invention has a comparison unit that generates a voltage level ready signal according to the first electric (four), the second voltage source, and the third voltage source. And ^, through the delay unit and ^ 兀 · delay voltage level ready signal and shorten its transition time to meet the timing requirements of the main board control signal. The judging unit controls the power-good signal according to the standby state signal and the AC power source. In this way, the power supply signal can be simulated by the power supply 201116985 2009-024 32406twf.doc/n, and the power supply ready signal of the 5th sequence is not applied, and when the power supply is turned off, the motherboard is not started or the board is standby or becomes the invention. The above features and excellent shutdown of the motherboard. Special _, 钱合所式式, the following [Embodiment] In general, the motherboard requires two kinds of power supply called operation power supply) to provide the host power supply (the following is a simple power supply (below) Referred to as the standby power supply ^ required voltage, the voltage required by the component. The standby power supply is continuous θ for the motherboard to stand in the state of the motherboard' while operating the power supply only on the motherboard without limiting the current of the operating power supply. The two sets of power supplies can be converted from the transformer power supply to the power supply. The up-converted host touches the transformer H electric power correction, and it will be used as a light power source and a standby power source. Converting to a voltage source of the operating voltage level, and making a power supply = similar to a plurality of voltage sources having different machine power supplies. The present invention is a motherboard control letter of the present invention. 2, please refer to Figure b. In this embodiment, the motherboard control = circuit can be applied to the motherboard system of the receiving device power supply = 1, the sub-main system (stationary) will be transformed into the operating power supply And rhyme power supply. Domain board The signal generation button comparison unit U0, the delay list W20, the whole wave single magic 3〇, and the judgment unit 40. The comparison unit 100 receives the first voltage source VCC1, the second voltage alarm 201116985 2009-024 32406twf.doc/n VCC2 and the A voltage source VCC3 ′ is based on the first electric motor source vcci, the second voltage source VCC2 and the third voltage source ν (χ3 is ready to output the voltage level ready signal Vready, the first voltage source VCC1, the second voltage source VCC2 and the third source V (X3 is the operating voltage source. The delay unit 120 is coupled to the comparison unit ι1〇 for delaying the voltage level ready signal Vready, wherein the delay unit 12 〇 will be ready for the voltage level Vready Delay hundreds of milliseconds (ms) to meet the timing requirements of the motherboard control signals. And, delay unit u. Can be used as a buffer for its upper and lower circuits to avoid the voltage level ready signal Vread is affected and the waveform is distorted. Wave unit 13. _ single == the transition time of the voltage level ready signal Vready. In other words, the whole wave single = 130 shortened voltage level ready signal Vready is converted from the low level voltage to the south standard voltage or by the high level voltage Switch to low accuracy The judging unit 140 is coupled to the whole-wave unit 13〇, and receives the transformer power supply=AD and the standby state signal commit “%.” The judging unit 14〇 is based on the variable voltage=power supply VCCAD, the standby state signal SLP_S3, and the voltage level. Ready nickname Vready decides whether to generate and output the power-good signal PWR—〇K 'the standby state signal SLP-S3 is output by the south bridge of the motherboard to indicate whether the motherboard is in standby state. Accordingly, when the host When the board is not in the standby state and the transformer power supply VCCAD is present, the judging unit 140 generates the power ready signal < PWKJ3K ' according to the voltage level ready signal Vready and transmits it to the motherboard. The motherboard will perform the initial action when it receives the power-good signal PWR for an OK to avoid an initialization when the voltage source is not ready. 201116985 2009-024 32406twf.doc/n Error. Thereby, the motherboard control signal generating circuit 100 can simulate the control signal timing of the power supply to generate the power-good signal PWR_OK 'and prevent the power-good signal PWR_OK from causing the motherboard operation error when the motherboard is in standby, and in the transformer power supply. When VCCAD does not exist, 'the power supply ready signal pwRj3K is used to immediately notify the motherboard to shut down. Referring again to FIG. 1, in the present embodiment, the comparison unit 11A includes a first φ comparator 111, a second comparator 112, and a third comparator 113. The first comparator hi receives the first voltage source VCC1 for determining whether the first voltage source vcci is ready, and outputs a corresponding level voltage accordingly. For example, if the first voltage source VCC1 is not ready (that is, the first voltage source VCC1 does not reach the critical dust of the system), then the first comparison can output a low level to represent the battery; When the voltage source VCC1 is ready (that is, the first voltage source VCC1 reaches the ready threshold voltage), then the second

Output high level voltage to indicate. ° lT wins Similarly 'The second comparator 112 receives the second voltage source VCC2 _ turns off the second voltage source like 2 is ready, and accordingly outputs the corresponding bit voltage. The third comparator 113 receives the third voltage source VCC3 for breaking the third voltage source VCC3 is ready, and according to the corresponding strip t, the second comparator m and the third comparator 113_ can be: A description of the comparator lu will not be repeated here. Further, the outputs of the first comparator m, the second comparators 112, and 113 are coupled together. Therefore, at the first comparator I. The voltage level output by the wide-band comparator 112 and the third comparator 113 is at least one 11 201116985 2009-024 32406twf.d〇c/n, the voltage level ready signal Vready will be low And ί:: is strictly low level voltage 'to indicate that the first voltage source - the electric ridge source VCC2 and the third voltage source VCC3 are at least one of the first comparator 11 and the second comparator 112 and the level ready signal Vrea " = : "level voltage 犄 ' then voltage source vrn, flute will be south level voltage ' to indicate the first voltage. - In the present embodiment, the voltage source VCC2 and the third voltage source VCC3 include the first detector (4), the second debt measurement unit (4), and the output resistor R. The first test list: 2 S3, the domain standby state signal standby mode ^r·/ should be the level voltage. For example, when the motherboard is in standby mode (that is, the standby signal sLp, the first detection unit (4) can turn out the low level money ^ bit reverse \s), the 3 board is not in standby _ ( That is, the standby state signal 仏 = bit voltage) 'the first side unit 141 can output the high level electric house, the second detecting element 141 Wei class iiUVCCAD, and (4), the voltage source VCCAD outputs the corresponding level voltage. For example, when the second detecting unit 142 receives the transformer power supply VCCAD, one: the board also receives the transformer power supply VCCAD, and the second detecting unit can output a high level voltage to indicate; otherwise, when the second detecting unit is Μ When the board indicates that the motherboard has not received the same ^ ^ VCXAD ' " two _ unit ί42 can output low level 12 201116985 2009-024 324 〇 6twf.doc / n voltage to indicate. Output resistance R. - end receive second The other end of the standby power supply resistor R〇 is connected to the rounding of the whole wave unit 13〇, the output of the rounding unit H1 and the wheel of the second detecting unit 142=the first detecting voltage level ready signal Vready, the first detecting The measuring unit ^ is based on the voltage and the level electric potential number PWR_OK outputted by the second_unit 142. For example, the voltage level ready signal-side unit 141 outputs the level voltage and the second detected The quasi-position electric station is less - when the fresh (four) voltage is pressed, then the PWR-OK will be affected by the low-level voltage and the low-level voltage is '7. The anti-5 Tibetan electric appliance level ready signal Vready, the first unit丨4丨= voltage and the level voltage output by the second detecting unit 142 are all high-level electric The power-good signal PWR-OK is a high-level ink. Figure 2 is a circuit diagram of the motherboard control signal generating circuit of Figure 1. Referring to Figure 2, in the comparing unit 110, the first comparator U1 includes a second resistor. The first resistor R1 and the second resistor R2 are coupled in series between the first voltage source VCC1 and the ground voltage, and the first resistor R1 and the second resistor R2 are coupled in series, and the first resistor R1 and the second resistor R2 are coupled in series between the first voltage source VCC1 and the ground voltage. A resistor R1 and a second resistor R2 are coupled to generate a voltage division Va to the positive input terminal of the first operational amplifier OP1. The seventh resistor R7 and the eighth resistor are coupled in series to the first standby voltage source VSB1. Between the ground voltages, and the coupling of the seventh resistor R7 and the eighth resistor R8, the reference voltage Vref is generated and transmitted to the negative input terminal of the first operational amplifier OP1, wherein the first standby voltage source VSB1 is the standby voltage. The voltage source. The first operational amplifier ορι 13 201116985 2009-024 32406twf.doc/n ^ than the car and its positive input and its negative input voltage determines the output high level voltage or low level voltage. Yes, because the standby power is earlier than the operation The voltage is ready. The first-in-one differential amplifier P1 can operate before the first voltage source ΙΟ ready f, and the reference voltage Vref will first provide the negative input of the first operational amplifier OP1. In addition, the 'seventh resistor R7 and The eighth resistor ^ is not limited to be placed in the first - compare 〒 ln +, and can be set at the other position of the motherboard control, number generation circuit (10), and the reference voltage ref can also be generated. And in other embodiments, the reference voltage can also be input. For example, suppose the reference voltage Vref is 2 5V, the first source vca is i2v', the first standby voltage source is 5V, and the first resistor and the second resistor R2 have a voltage dividing ratio of about mm. According to the above, the threshold voltage of the first voltage source vcci is about 1G 7V. Therefore, before the first voltage source VCC1 exceeds 1〇.7V, the 'divided voltage Va' will be less than or equal to the reference voltage Vref, @the first operation Α|§ ιρι will output a low level voltage (about ground voltage); Conversely, after the first voltage source 乂(:(:1 exceeds i〇.7V, the divided voltage Va will be greater than the reference voltage V): ef, so the __ operational amplifier (10) will rotate the high-level voltage (about 5V). The second comparison H 112 includes a third circuit and R3, a fourth resistor, and a second operational amplifier OP2. The third resistor R3 and the fourth resistor R4 are connected in series to the second voltage source VCC2 and the ground voltage. Between, and the coupling of the third resistor R3 and the fourth resistor R4 will generate a voltage divider Vb to the positive input terminal of the second transistor amplifier OP2. The second operation of the rose 〇p2 ^2 2 201116985 2009- 024 32406twf.doc / n termination, reference voltage Vref, and compare the positive input terminal and its negative input terminal to determine the output high level voltage or low level voltage. # For example, assume second The voltage source VCC2 is 5V, and the voltage dividing ratio of the second resistor R3 and the fourth power |^ and R4 is about 0 56, and other conditions are referred to First - compare the setting of n (1). Therefore, the threshold voltage of the second voltage source m is about 4.5 V. That is, before the second voltage source VCC2 exceeds 4.5 V, the divided voltage Vb is less than or equal to the reference voltage Vref. The differential amplification will output a low level voltage (approximately ground voltage); conversely, after the second voltage source VCC2 exceeds 4 5V, the voltage vb will be greater than the reference voltage %吋, the second operational amplifier 〇1> Will: a high level voltage (about 5V). The comparator 113 includes a fifth resistor R5, a sixth resistor R6, and a second operational amplifier OP3. The fifth resistor 5 and the sixth resistor are connected in series. Between the second voltage source VCC3 and the ground voltage, and the coupling of the fifth resistor R5 and the sixth resistor R6 generates a voltage division Vc to the positive input terminal of the third operational amplifier OP3. The negative terminal of p3 receives the reference voltage Vi*ef, and the field determines the output high-level voltage or low-level voltage compared with the voltage of the reading terminal. For example, the third voltage source is assumed here. Also (: (: 3 is 3.3 乂, and the voltage division ratio of the fifth resistor R5 and the sixth resistor R6 is approximately 〇 85, the other bars refer to the setting of the first comparator 111. Therefore, the threshold voltage of the third voltage source is about 2.94V. That is, before the third voltage VCC3 exceeds 2.94V, the partial voltage Vc will be less than or equal to Spring Vref' therefore the third operational amplifier (10) will output a low level voltage 15 201116985 2009-024 32406twf.doc / n ground voltage); conversely, a M _ two wide partial pressure Vc will be greater than Yan Laojiao "Electric Fort source VCC3 exceeded After 2.94V, the combined 隹 / with multiple test voltage % Du, so the third op amp 0P3 曰 output level pen pressure (about 5V). The delay single 12G το includes a tenth-resistor Rn and a resistance c, and a tenth resistor R11. The end receives the first standby voltage source vsbi, and the other end of the eleventh power is connected to the output end of the comparison unit 110 and the whole-wave unit, . The electric valley C1 is lightly connected to the tenth - the other end of the resistor R11 /, the ground: between the Lu. As can be seen from Figure 2, the delay of 12 〇 is an RC delay.

The circuit 'by delaying the electric transfer Vmady, and the delay time can be determined by the RC constant. π

The monolithic single t1 130 includes a ninth resistor R9, a tenth resistor Ri, and a fourth operational amplifier OP4. The ninth resistor R9 is switched between the delay unit 12 〇 and the fourth transmission, between the positive input terminal of the ϋ〇Ρ 4 . The tenth resistor R is connected to the fourth operational amplifier ||〇Ρ4 between the positive wheel terminal and the output terminal of the fourth operational amplifier 〇p4. The resistance of the tenth resistor is much larger than the resistance of the ninth resistor R9. . The fourth operational amplifier, the negative input of 〇p4, receives the reference voltage Vref. According to the circuit, the whole wave unit 13 is a non-inverting comparator with hysteresis function, which can prevent the voltage level ready signal Vready from rising too slowly, and the power supply ready signal pWR_〇κ is unstable. The state can increase the speed of the rise or fall of the voltage level ready signal Vready, and the transition time of the voltage level ready signal Vready can be shortened and output to the judging unit 14A. . The first detecting unit 141 includes a twelfth resistor R12, a thirteenth resistor R13, a first transistor TR1, a fourteenth resistor R14, and a second transistor. 16 201116985 2009-024 32406twf.doc/n

Ml. The standby cancer ##8!^_83 is transmitted to the base (i.e., the control terminal) of the first transistor TR1 through the twelfth resistor R12. The collector (i.e., the first end) of the first transistor is received through the thirteenth resistor R13 to receive the emitter (i.e., the second terminal) of the transformer VCOVD/the transistor TR1. The fourteenth resistor R14 is coupled between the emitter of the first transistor 11A and the ground voltage. The gate (i.e., control terminal) surface of the second transistor M1 is the collector of the transistor TR1, and the drain (i.e., the first terminal) of the second transistor M1 is reduced in output resistance R. The other end of the second transistor is coupled to the ground voltage. I is b. For example, the 5 brothers are assumed. The standby state signal SLP-S3 is assumed to be at a high level. The pressure gauge is not in the standby state, and the fresh voltage is indicated as being in the standby state. When the standby state signal SLp_S3 is low, the power of the gate is 0^TR1 and is in the cut-off region, that is, the first transistor Tf_ has a current flowing. At this time, the thirteenth resistor R13 and the fourteenth RH divide the (four) power supply VCCAD, and provide the idle pole of the 曰1 body. a skirt - emperor's foot · after the first 曰 曰 曰 曰 接收 接收 _ _ 弟 弟 冤 冤 冤 冤 冤 冤 M M M M M M M M M M M M

Ro caused the cake. At this time, the 1 a31M1 ^ (four) rounds the power supply ί signal PWR - 0K voltage level. When the power is reduced by δ, the λ_standby state signal SLP_S3 will flow a large amount of current to the high level power 7 and the thirteenth resistor R13. The collector (four) pressure level of this TR1 will be close to the ground voltage, (4) Call = 17 201116985 2009-024 32406twf.doc/n

Ml cannot be turned on. Therefore, the second ferrets are the same as the quiescent voltage level of the M-Electric Day M1 ^ Gate at the power supply (4) PWR-οκ voltage level

Vready and mu... quasi-control package pressure level ready signal Vready and the first detection early element 142 output electrical level. The second side single Tt 142 includes a fifteenth resistance milk (10), a seventeenth resistor Rl7, and a third transistor TR2J: = between the transformer power supply VCCAD and the sixteenth resistor. The +j blocking leg is between the fifteenth resistor Rl5 and the ground voltage. It is between the sixteenth resistor coffee and the fifteenth resistor phantom 5 and the base of the third transistor TR2 (special end). =, the emitter of the body TR2 (ie, the first end) is connected to the output resistor r〇 of the collector of the third transistor TR2 (ie, the second end) is connected to the grounding power. For example, the motherboard receives the color. The power supply VCCAD^2 detection unit 142 is also connected to the transformer power supply V (XAD. Moreover, the two resistors R15 and the sixteenth resistor Rl6 divide the transformer power supply, and transmit to the first through the seventeenth resistor R17. The base of the transistor TR2, the pressure obtained by the partial pressure of the towel will be greater than the voltage of the second == source. Since the voltage of the base of the third transistor TR2 is greater than the voltage of the emitter, the third transistor TR2 will be in the cut-off area, that is, no current flows through the second transistor TR2. At this time, the voltage level of the emitter of the third transistor is the same as that of the power-good signal pwR^〇K曰曰, and the power supply The voltage level of the ready index PWR_OK is controlled by the voltage level ready signal Vready and the voltage output by the first detecting unit 141 is 201116985 2009-024 32406twf.d〇c/n. On the other hand, the motherboard is not When receiving the transformer power supply VCCAD, the first detecting unit 142 is also unable to receive the transformer The power supply vccAD causes the voltage of the base of the second transistor TR2 to be close to the ground voltage. At this time, the voltage of the base of the transistor II of the second transistor is lower than the voltage of the emitter, so the transistor TR2 will be in the saturation region. That is, the third transistor TR2 will flow a large amount of current, and cause a large amount of current to flow through the output resistor R〇 and φ to cause a voltage drop. At this time, the voltage level of the emitter of the third transistor TR2 will be close to the ground voltage (ie, low). The voltage level of the power-good signal PWR__〇K is pulled down at the same time. It is to be understood that the voltages and values used in the above examples are for illustrative purposes and are not intended to limit the embodiments of the present invention. Moreover, those skilled in the art can use their knowledge to adjust the resistance value or voltage value, and still determine whether the voltage source is ready, and pull down the power-good signal pWR when the motherboard is in standby or when the transformer power supply VCCAD disappears. The voltage level of K. - Qianxin Figure 3 is the waveform of the main board control signal generation circuit of Figure 1 without the whole wave unit; the waveform of the original ready ##. Figure 4 is the motherboard control letter of Figure 1. Waveform diagram of the power-good signal of the circuit. Please refer to Figure 3 and Figure 3 for the time axis of 20 nanoseconds (ns) per point, and the time axis of Figure 4 for 4 nanoseconds (ns) per point. The whole wave unit 13〇 shortens the voltage level ready signal to the voltage level ready signal Vready

Vready's transition time, and subject to the reference voltage Vref (here 2.5V as an example) to amplify the voltage level ready signal Vready close to 2.5V.

19 201116985 2009-024 32406twf.d〇c/n Therefore, the whole wave unit 130 can filter the unstable waveform of the power-good signal PWR_OK as shown in FIG. . . Figure 5 is a waveform diagram of the power-good signal of the motherboard control signal generating circuit of Figure 1 without the second detecting unit. Fig. 6 is a waveform diagram of a power-good signal of the motherboard control signal generating circuit of Fig. i. Please refer to FIG. 5 and FIG. 5 for the time_8 () nanoseconds per point (η〇, the time axis of the figure (4) is 100 picoseconds per second (ps). Since the first voltage source and the second voltage source VCC2 and The third electric dust source VCC3 is converted from the transformer power supply VCCAD. Therefore, after the transformer power supply VCCAD disappears, the first voltage source vcu, the second voltage source VCC2, and the third voltage source vcc start to fall and fall to the ground. Therefore, in the motherboard control signal generating circuit 1 without the second detecting unit 142, the output = power ready signal PWR - ΟΚ must pass - the segment is picked up to turn the low 2 voltage The motherboard control signal generation % road 100 having the second debt measuring unit 142, after the dust collector power supply VCCAD disappears, pulls the power ready signal PWR_OK to the fresh bit surface. The result is as shown in the figure. Figure 5 shows the bee delay time T1w. 〇 72 milliseconds (ms), and the delay time T2 shown in Fig. 6 is 636.7 nanoseconds (ns). As described above, the motherboard control signal generating circuit of the embodiment of the present invention: The comparison unit is based on the first electrical source, the second voltage source, and the third voltage source. The voltage value is a secret, and the voltage level f domain is generated when the first electric source, the second voltage source, and the third voltage source are all ready, and the delay is performed by the delay unit and the whole wave unit. , and the signal and shorten the transition time to meet the control signal of the motherboard, and avoid the transition time is too long and the waveform is unstable. The judgment unit is based on Voltage level ready signal, standby status signal and transformer power = generate power ready signal. By this, it can simulate the power supply to produce the matching/timing power supply code, and the social machine board standby or Wei ^ power off when 'not Starting the motherboard or immediately shutting down the motherboard. - Although the invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art, without departing from the spirit and scope of the invention, When it can be used as the more axis of the (10), the scope of the invention is defined as the scope of the patent application, which is defined by the scope of the application. The block diagram = county invention - implementation of the motherboard (four) money generation circuit ,! Motherboard circuit diagram of the control signal generation.

3 is the power supply and ready signal of the comparator having the hysteresis function of the main board control signal generated in FIG. 1; the power supply ready circuit of the circuit does not have the power ready signal of the second detecting circuit. FIG. The waveform of the motherboard control signal generation number. FIG. 5 is a waveform diagram of the power-good signal of the test board of FIG. 1 for generating a test signal. Fig. 6 is a waveform diagram of the control signal generation number of the motherboard of Fig. 1. 21 201116985 2009-024 32406twf.doc/n [Description of main component symbols] 100: Motherboard control signal generation circuit 110: Comparison unit 111, 112, 113: Comparator 120: Delay unit 130: Whole wave unit 140: Judging unit 141 142: Detection unit VCC1, VCC2, VCC3: voltage source VSB Bu VSB2: standby voltage source SLP_S3: standby state signal P WR_OK: power supply ready signal VCCAD: transformer power supply

Vready: voltage level ready signal

Ro, R1~R17: Resistor OP1~OP4: Operational amplifier C1: Capacitor

Vref: reference voltage

Va, Vb, Vc: partial pressure TR1, TR2, Ml: transistor Ή, T2: time 22

Claims (1)

201116985 2009-024 32406twf.doc/n VII. Patent application scope: 1. - Motherboard control signal generation circuit voltage power supply - motherboard system, including: B, Cai, - - change - comparison unit, receive, - a second voltage source, and according to the first electrical plane, the second voltage source, and the third voltage source output-voltage level ready signal, wherein the first/following, the second voltage source, and the The voltage source of the third voltage source is changed, and the voltage levels of the first voltage source, the third source, and the source are different from each other; and the voltage delay unit is coupled to the comparison unit. Ready to be healthy, · Xiao Xiao Lai voltage quasi-one-wave unit, coupled to the delay unit, the - (four) time of the bit ready signal; money with · _ voltage quasi-one judgment unit, coupled to the whole wave unit, source and - standby state The signal is output according to the transformer transformer electrical signal and the voltage level ready signal-power: the state, the standby state signal is output by the south bridge of the motherboard, and the second is as claimed. The raw circuit, the towel unit Included: the occupational control machine produces a first comparator, receives whether the voltage source is ready, and outputs the first voltage source according to the output-first-level power, and receives the second voltage source Use: to judge the mth veto, and according to this output "second quasi-third comparator" to receive the first: tracing 'to \ step a private 7 strong, used to judge the 23 201116985 2009-024 32406twf.doc/n Whether the two voltage sources are ready, and according to this, a third level voltage is rotated; wherein the first comparator, the second comparator, and the third comparator output terminal are at - The first level voltage, the bit voltage, and the third level output the voltage level ready signal. In the field of electricity generation, the signal is generated by a first resistor, one end of which is coupled to the first voltage source; the ground Φ is a first resistor, and is connected between the other end of the first resistor and the voltage connected to the voltage and provides a first-divided-pressure; and a first-in-one reducer's positive input terminal receives the first partial pressure, and the negative input terminal receives - reference · 'the output terminal outputs the first reference power 4 · ΜThe third line of the full-time division is based on the production circuit, and the second shouting of the towel includes: Η. a third resistor, one end of which is coupled to the second voltage source; a fourth resistor coupled to the other end of the third resistor, and provides a second partial pressure: It is also known that the second operational amplifier has its positive input terminal, the input terminal receives the reference voltage, and the output terminal outputs the output signal of the first generation of the power generation system. The device includes: a fifth resistor, one end of which is coupled to the third voltage source; a sixth resistor that is connected to the other end of the fifth resistor and the voltage of the 辏24 201116985 2009-024 32406twf.doc/n Between, and provide a third point; and pressure-third operation amplification H 'the positive input terminal receives the third partial pressure, ^ the negative input terminal receives the reference voltage 'the output terminal outputs the third level Electricity 6. Production circuit (4) 3 sales of the domain board shop signal production „ 'The one end consumes a first standby power source; and - the brother eight resistance' _ between the seventh power _ another ground voltage, and Providing the reference voltage. 鸰>, the mid-shun (four) signal produces a ninth resistor, One end is coupled to the delay unit; - the fourth operational amplifier, the positive input terminal-end's negative terminal receives the reference voltage, and the other voltage state of the resistance is ready for the voltage level; The ten-resistance' is connected between the fourth terminal and the output terminal of the fourth operational amplifier, and its positive input resistance is much larger than the resistance of the ninth resistor. D-electrical resistance of the ten-resistance (four) plate" The signal-tenth-resistor's terminal receives the first one, and the output of the comparison unit and the whole-wave unit: 'its ♦ w '(4) in the tenth-electron-input voltage between. 9. The motherboard control signal generating circuit according to claim 1, wherein the determining unit comprises: a first detecting unit that receives the standby a status signal for outputting a fourth level voltage according to the standby state signal; a second detecting unit receiving the transformer power source to output a fifth level voltage according to the transformer power source; and an output resistor receiving one at one end a second standby power supply, the other end of which is coupled to the output end of the whole wave unit, the output end of the first detecting unit, and the output end of the second detecting unit, according to the voltage level ready signal, the fourth The level voltage and the fifth level voltage output the power ready signal. 10. The motherboard control signal generating circuit of claim 9, wherein the first detecting unit comprises: a twelfth resistor, one end of which receives the standby state signal; and a thirteenth resistor, one end of which Receiving the transformer power supply; a first transistor having a first end, a second end, and a control end, the control end of the first transistor being coupled to the other end of the twelfth resistor, the first The first end of the crystal is coupled to the other end of the thirteenth resistor, the second end of the first transistor is coupled to a ground voltage; and the fourteenth resistor is coupled to the first transistor Between the one end and the ground voltage; and a second transistor having a first end, a second end, and a control end, the control end of the second transistor being coupled to the second transistor of the first transistor The first end of the second transistor is coupled to the other end of the output resistor, and the two ends of the second transistor are connected to a ground voltage. The circuit board control signal generating circuit of claim 9, wherein the second detecting unit comprises: a fifteenth resistor, one end of which receives the transformer power supply a sixteenth resistor coupled between the other end of the fifteenth resistor and a ground voltage; a seventeenth resistor, one end of which receives the other end of the fifteenth resistor; and a third transistor Having a first end, a second end, and a control end, the control end of the third transistor is coupled to the other end of the seventeenth resistor, and the first end of the third transistor is coupled to the output resistor The other end of the third transistor is coupled to a ground voltage. 27