TWI392999B - Generator circuit for control signal of mother board - Google Patents

Description

Motherboard control signal generation circuit

The present invention relates to a signal generating circuit, and more particularly to a signal generating circuit for simulating a motherboard control signal.

With the advent of the information age, the popularity of computer products has also increased year by year. Modern people can not only use computers to process files and store data, but also connect to the Internet through computers to obtain information, or through the Internet. The road communicates with others, and the related applications of these computers undoubtedly greatly enhance the convenience of modern people's lives. For this reason, computer products have undoubtedly become an indispensable tool for modern people.

In general, portable computers are usually designed to be lighter and thinner for portability. On the other hand, desktop computers are more efficient and are not often moved, so desktop computers are usually larger and heavier. Nowadays, due to the advancement of technology and the rise of the concept of integration, the mainframe of the desktop computer has also been designed to be light and thin. In the thinning process of the mainframe of the desktop computer, the transformer is generally replaced by a smaller and smaller power supply. However, on the functional side, the transformer can only replace the power supply's power supply and cannot generate the signals needed to operate the motherboard in the host, such as the power-good signal.

Therefore, in order to make the thin and light host operate smoothly, a signal generating circuit is designed to generate a power ready signal required for the operation of the motherboard according to the power of the transformer.

The invention provides a motherboard control signal generating circuit, which can drive the motherboard to operate according to the power supply of the transformer and simulate the ATX power supply to generate a power ready signal.

The invention provides a motherboard control signal generating circuit suitable for receiving a motherboard power supply system. The motherboard control signal generating circuit includes a comparing unit, a delay unit, a whole wave unit, and a determining unit. The comparison unit receives the first voltage source, the second voltage source, and the third voltage source, and outputs a voltage level ready signal according to the first voltage source, the second voltage source, and the third voltage source. The first voltage source, the second voltage source, and the third voltage source are converted by using a transformer power source, and voltage levels of the first voltage source, the second voltage source, and the third voltage source are different from each other. The delay unit is coupled to the comparison unit for delaying the voltage level ready signal. The whole wave unit is coupled to the delay unit to shorten the transition time of the voltage level ready signal. The determining unit is coupled to the whole wave unit and receives the transformer power supply and the standby state signal to output a power ready signal according to the transformer power supply, the standby state signal and the voltage level ready signal, wherein the standby state signal is output by the south bridge of the motherboard.

In an embodiment of the invention, the comparing unit includes a first comparator, a second comparator, and a third comparator. The first comparator receives the first voltage source to determine whether the first voltage source is ready, and outputs the first level voltage accordingly. The second comparator receives the second voltage source to determine whether the second voltage source is ready, and outputs a second level voltage accordingly. The third comparator receives the third voltage source for determining whether the third voltage source is ready, and outputting the third level voltage accordingly. The output ends of the first comparator, the second comparator, and the third comparator are coupled together to output a voltage level ready signal according to the first level voltage, the second level voltage, and the third level.

In an embodiment of the invention, the first comparator includes a first resistor, a second resistor, and a first operational amplifier. One end of the first resistor is coupled to the first voltage source. The second resistor is coupled between the other end of the first resistor and the ground voltage, and provides a first partial pressure. The positive input terminal of the first operational amplifier receives the first partial voltage, the negative input terminal of the first operational amplifier receives the reference voltage, and the output terminal of the first operational amplifier outputs the first potential voltage.

In an embodiment of the invention, the second comparator includes a third resistor, a fourth resistor, and a second operational amplifier. One end of the third resistor is coupled to the second voltage source. The fourth resistor is coupled between the other end of the third resistor and the ground voltage, and provides a second partial pressure. The positive input terminal of the second operational amplifier receives the second divided voltage, the negative input terminal of the second operational amplifier receives the reference voltage, and the output terminal of the second operational amplifier outputs the second potential voltage.

In an embodiment of the invention, the third comparator includes a fifth resistor, a sixth resistor, and a third operational amplifier. One end of the fifth resistor is coupled to the third voltage source. The sixth resistor is coupled between the other end of the fifth resistor and the ground voltage, and provides a third partial pressure. The positive input terminal of the third operational amplifier receives the third divided voltage, the negative input terminal of the third operational amplifier receives the reference voltage, and the output terminal of the third operational amplifier outputs the third potential voltage.

In an embodiment of the invention, the motherboard control signal generating circuit further includes a seventh resistor and an eighth resistor. One end of the seventh resistor is coupled to the first standby voltage source. The eighth resistor is coupled between the other end of the seventh resistor and the ground voltage, and provides a reference voltage.

In an embodiment of the invention, the whole wave unit includes a ninth resistor, a tenth resistor, and a fourth operational amplifier. One end of the ninth resistor is coupled to the delay unit. The positive input terminal of the fourth operational amplifier is coupled to the other end of the ninth resistor, the negative input terminal of the fourth operational amplifier receives the reference voltage, and the output terminal of the fourth operational amplifier outputs the voltage level ready signal after shortening the transition time. The tenth resistor is coupled between the positive input terminal of the fourth operational amplifier and the output terminal of the fourth operational amplifier, wherein the resistance of the tenth resistor is much larger than the resistance of the ninth resistor.

In an embodiment of the invention, the delay unit includes an eleventh resistor and a first capacitor. One end of the eleventh resistor receives the first standby voltage source, and the other end of the eleventh resistor is coupled to the output end of the comparison unit and the input end of the whole wave unit. The first capacitor is coupled between the other end of the eleventh resistor and the ground voltage.

In an embodiment of the invention, the determining unit includes a first detecting unit, a second detecting unit, and an output resistor. The first detecting unit receives the standby state signal to output the fourth level voltage according to the standby state signal. The second detecting unit receives the transformer power supply to output a fifth level voltage according to the transformer power source. One end of the output resistor receives the second standby power supply, and the other end of the output resistor is coupled to the output end of the whole wave unit, the output end of the first detecting unit, and the output end of the second detecting unit, according to the voltage level ready signal, The fourth level voltage and the fifth level voltage output a power ready signal.

In an embodiment of the invention, the first detecting unit includes a twelfth resistor, a thirteenth resistor, a first transistor, a fourteenth resistor, and a second transistor. One end of the twelfth resistor receives a standby state signal. One end of the thirteenth resistor receives the transformer power supply. The first transistor has a first end, a second end, and a control end, and the control end of the first transistor is coupled to the other end of the twelfth resistor, and the first end of the first transistor is coupled to the other end of the thirteenth resistor The second end of the first transistor is coupled to a ground voltage. The fourteenth resistor is coupled between the first end of the first transistor and the ground voltage. The second transistor has a first end, a second end, and a control end. The control end of the second transistor is coupled to the second end of the first transistor, and the first end of the second transistor is coupled to the other end of the output resistor. The second end of the second transistor is coupled to the ground voltage.

In an embodiment of the invention, the second detecting unit includes a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, and a third transistor. One end of the fifteenth resistor receives the transformer power supply. The sixteenth resistor is coupled between the other end of the fifteenth resistor and the ground voltage. One end of the seventeenth resistor receives the other end of the fifteenth resistor. The third transistor has a first end, a second end and a control end, the control end of the third transistor is coupled to the other end of the seventeenth resistor, and the first end of the third transistor is coupled to the other end of the output resistor, The second end of the three transistors is coupled to the ground voltage.

Based on the above, the motherboard control signal generating circuit of the present invention has a comparison unit that generates a voltage level ready signal according to whether the first voltage source, the second voltage source, and the third voltage source are ready. Moreover, the voltage level ready signal is delayed by the delay unit and the whole wave unit, and the transition time is shortened to meet the timing specification of the motherboard control signal. The judging unit controls the power ready signal according to the standby state signal and the transformer power supply. In this way, the power supply can be simulated to generate a timing-compliant power-good signal, and the motherboard is not started or the motherboard is turned off immediately when the motherboard is in standby or the transformer is powered off.

The above described features and advantages of the present invention will be more apparent from the following description.

In general, the motherboard requires two power supplies. One power supply (hereinafter referred to as the operating power supply) is used to provide the voltage required for the operation of the motherboard, and the other power supply (hereinafter referred to as the standby power supply) provides the standby components of the motherboard. The voltage required. The standby power supply is continuously provided to the motherboard without being limited by the state of the motherboard, and the operating power is provided only when the motherboard is operating. Accordingly, the current used to operate the power supply is typically greater than the power supply to the standby power source. Both sets of power supplies can be converted from the transformer power supply. In other words, when the thin and light host receives the transformer power, it converts the transformer power into an operating power supply and a standby power supply, wherein the operating power supply and the standby power supply each have multiple voltage sources of different voltage levels, and operate multiple voltages of the power supply. The source is similar to multiple voltage sources for the standby power supply.

1 is a block diagram of a motherboard control signal generating circuit according to an embodiment of the present invention. Referring to FIG. 1, in the embodiment, the motherboard control signal generating circuit 100 can be applied to a motherboard system (or a host) that receives a transformer power supply, and the motherboard system (or host) converts the transformer power into an operating power supply and Standby power supply. The motherboard control signal generating circuit 100 includes a comparing unit 110, a delay unit 120, a whole wave unit 130, and a determining unit 140. The comparing unit 100 receives the first voltage source VCC1, the second voltage source VCC2, and the third voltage source VCC3, and according to whether the first voltage source VCC1, the second voltage source VCC2, and the third voltage source VCC3 are ready to output the voltage level ready signal Vready The first voltage source VCC1, the second voltage source VCC2, and the third voltage source VCC3 are voltage sources for operating the power source.

The delay unit 120 is coupled to the comparison unit 110 for delaying the voltage level ready signal Vready, wherein the delay unit 120 delays the voltage level ready signal Vready by several hundred milliseconds (ms) to comply with the timing specification of the motherboard control signal. Moreover, the delay unit 120 can be used as a buffer for its upper and lower stage circuits to prevent the voltage level ready signal Vready from being distorted by the load effect. The whole wave unit 130 is coupled to the delay unit 120 for shortening the transition time of the voltage level ready signal Vready. In other words, the whole wave unit 130 shortens the time during which the voltage level ready signal Vready is switched from the low level voltage to the high level voltage or from the high level voltage to the low level voltage.

The determining unit 140 is coupled to the whole wave unit 130 and receives the transformer power supply VCCAD and the standby state signal SLP_S3. The determining unit 140 determines whether to generate and output a power ready signal PWR_OK according to the transformer power supply VCCAD, the standby state signal SLP_S3 and the voltage level ready signal Vready, wherein the standby state signal SLP_S3 is output by the south bridge of the motherboard to indicate whether the motherboard is in standby. status. Accordingly, when the motherboard is not in the standby state and the transformer power supply VCCAD is present, the determination unit 140 generates the power-good signal PWR_OK according to the voltage level ready signal Vready and transmits it to the motherboard.

The motherboard will initiate the action when it receives the power-good signal PWR_OK to avoid an error when the voltage source is not ready. Thereby, the motherboard control signal generating circuit 100 can generate the power-good signal PWR_OK by simulating the control signal timing of the ATX power supply, and prevent the power-good signal PWR_OK from causing the motherboard operation error when the motherboard is in standby, and not in the transformer power supply VCCAD. When present, the power board ready signal PWR_OK immediately informs the motherboard to shut down.

Referring again to FIG. 1, in the present embodiment, the comparison unit 110 includes a first comparator 111, a second comparator 112, and a third comparator 113. The first comparator 111 receives the first voltage source VCC1 for determining whether the first voltage source VCC1 is ready, and accordingly outputs a corresponding level voltage. For example, if the first voltage source VCC1 is ready (that is, the first voltage source VCC1 does not reach the ready threshold voltage), the first comparator 111 can output a low level voltage to indicate; otherwise, if the first voltage When the source VCC1 is ready (that is, the first voltage source VCC1 reaches the ready threshold voltage), the first comparator 111 can output a high level voltage to indicate.

Similarly, the second comparator 112 receives the second voltage source VCC2 for determining whether the second voltage source VCC2 is ready, and accordingly outputs a corresponding level voltage. The third comparator 113 receives the third voltage source VCC3 for determining whether the third voltage source VCC3 is ready, and accordingly outputs a corresponding level voltage. For the operations of the second comparator 112 and the third comparator 113, reference may be made to the description of the first comparator 111, and details are not described herein again.

In addition, the outputs of the first comparator 111, the second comparator 112, and the third comparator 113 are coupled together. Therefore, when at least one of the voltage levels output by the first comparator 111, the second comparator 112, and the third comparator 113 is a low level voltage, the voltage level ready signal Vready is affected by the low level voltage. The low level voltage indicates that at least one of the first voltage source VCC1, the second voltage source VCC2, and the third voltage source VCC3 is not ready. On the other hand, when the voltage levels output by the first comparator 111, the second comparator 112, and the third comparator 113 are all high level voltages, the voltage level ready signal Vready will be a high level voltage to indicate the first A voltage source VCC1, a second voltage source VCC2, and a third voltage source VCC3 are all ready.

In this embodiment, the determining unit 140 includes a first detecting unit 141, a second detecting unit 142, and an output resistor Ro. The first detecting unit 141 receives the standby state signal SLP_S3 to output a corresponding level voltage according to the standby state signal SLP_S3. For example, when the motherboard is in the standby state (that is, the standby state signal SLP_S3 is a low level voltage), the first detecting unit 141 can output a low level voltage to indicate; otherwise, when the motherboard is not in standby. In the state (that is, the standby state signal SLP_S3 is a high level voltage), the first detecting unit 141 can output a high level voltage to indicate.

The second detecting unit 141 receives the transformer power supply VCCAD to output a corresponding level voltage according to the transformer power supply VCCAD. For example, when the second detecting unit 142 receives the transformer power supply VCCAD, indicating that the motherboard also receives the transformer power supply VCCAD, the second detecting unit 142 can output a high-level voltage to indicate; When the measurement unit 142 does not receive the transformer power supply VCCAD, it indicates that the motherboard does not receive the transformer power supply VCCAD, and the second detection unit 142 can output a low level voltage to indicate.

One end of the output resistor Ro receives the second standby power supply VSB2, and the other end of the output resistor Ro is coupled to the output end of the whole wave unit 130, the output end of the first detecting unit 141, and the output end of the second detecting unit 142. The voltage level ready signal Vready, the level voltage output by the first detecting unit 141, and the level voltage output by the second detecting unit 142 output a power ready signal PWR_OK. For example, when at least one of the voltage level ready signal Vready, the level voltage output by the first detecting unit 141, and the level voltage output by the second detecting unit 142 is a low level voltage, the power ready signal PWR_OK will be It is a low level voltage due to the low level voltage. On the other hand, when the voltage level ready signal Vready, the level voltage output by the first detecting unit 141, and the level voltage output by the second detecting unit 142 are all high level voltages, the power ready signal PWR_OK is a high level voltage. .

2 is a circuit diagram of a motherboard control signal generating circuit of FIG. 1. Referring to FIG. 2, in the comparing unit 110, the first comparator 111 includes a first resistor R1, a second resistor R2, a seventh resistor R7, an eighth resistor R8, and a first operational amplifier OP1. The first resistor R1 and the second resistor R2 are coupled in series between the first voltage source VCC1 and the ground voltage, and the coupling between the first resistor R1 and the second resistor R2 generates a voltage division Va to the first operational amplifier OP1. Positive input. The seventh resistor R7 and the eighth resistor R8 are coupled in series between the first standby voltage source VSB1 and the ground voltage, and the coupling between the seventh resistor R7 and the eighth resistor R8 generates a reference voltage Vref and is transmitted to the first A negative input terminal of the operational amplifier OP1, wherein the first standby voltage source VSB1 is a voltage source of the standby voltage. The first operational amplifier OP1 compares the voltage of its positive input terminal and its negative input terminal to determine the output high-level voltage or low-level voltage.

It is worth mentioning that the standby power supply is ready before the operating voltage. Therefore, the first operational amplifier OP1 can operate before the first voltage source VCC1 is ready, and the reference voltage Vref first provides the negative input terminal of the first operational amplifier OP1. In addition, the seventh resistor R7 and the eighth resistor R8 are not limited to be disposed in the first comparator 111, and may be disposed at other positions of the motherboard control signal generating circuit 100, and the reference voltage Vref may also be generated. Also, in other embodiments, the reference voltage Vref may also be input externally.

For example, assuming that the reference voltage Vref is 2.5V, the first voltage source VCC1 is 12V, the first standby voltage source is 5V, and the voltage dividing ratio of the first resistor R1 and the second resistor R2 is about 0.233. According to the above, the threshold voltage at which the first voltage source VCC1 is ready is about 10.7V. Therefore, before the first voltage source VCC1 exceeds 10.7V, the divided voltage Va will be less than or equal to the reference voltage Vref, so the first operational amplifier OP1 will output a low level voltage (about ground voltage); otherwise, the first voltage source After VCC1 exceeds 10.7V, the divided voltage Va will be greater than the reference voltage Vref, so the first operational amplifier OP1 will output a high level voltage (about 5V).

The second comparator 112 includes a third resistor R3, a fourth resistor R4, and a second operational amplifier OP2. The third resistor R3 and the fourth resistor R4 are coupled in series between the second voltage source VCC2 and the ground voltage, and the coupling of the third resistor R3 and the fourth resistor R4 generates a voltage divider Vb to the second operational amplifier OP2. Positive input. The negative input terminal of the second operational amplifier OP2 receives the reference voltage Vref and compares the voltage of its positive input terminal and its negative input terminal to determine the output high-level voltage or low-level voltage.

For example, it is assumed here that the second voltage source VCC2 is 5V, and the voltage dividing ratio of the third resistor R3 and the fourth resistor R4 is about 0.56, and other conditions refer to the setting of the first comparator 111. Therefore, the threshold voltage at which the second voltage source VCC2 is ready is about 4.5V. That is, before the second voltage source VCC2 exceeds 4.5V, the divided voltage Vb will be less than or equal to the reference voltage Vref, so the second operational amplifier OP2 will output a low level voltage (about ground voltage); After the voltage source VCC2 exceeds 4.5V, the divided voltage Vb will be greater than the reference voltage Vref, and the second operational amplifier OP2 will output a high level voltage (about 5V).

The third comparator 113 includes a fifth resistor R5, a sixth resistor R6, and a third operational amplifier OP3. The fifth resistor R5 and the sixth resistor R6 are coupled in series between the third voltage source VCC3 and the ground voltage, and the coupling of the fifth resistor R5 and the sixth resistor R6 generates a voltage divider Vc to the third operational amplifier OP3. Positive input. The negative input terminal of the third operational amplifier OP3 receives the reference voltage Vref and compares the voltage of its positive input terminal and its negative input terminal to determine the output high-level voltage or low-level voltage.

For example, it is assumed here that the third voltage source VCC3 is 3.3V, and the voltage dividing ratio of the fifth resistor R5 and the sixth resistor R6 is about 0.85, and other conditions refer to the setting of the first comparator 111. Therefore, the threshold voltage at which the third voltage source VCC3 is ready is about 2.94V. That is, before the third voltage source VCC3 exceeds 2.94V, the divided voltage Vc will be less than or equal to the reference voltage Vref, so the third operational amplifier OP3 will output a low level voltage (about ground voltage); After the voltage source VCC3 exceeds 2.94V, the divided voltage Vc will be greater than the reference voltage Vref, so the third operational amplifier OP3 will output a high level voltage (about 5V).

The delay single 120 yuan includes the eleventh resistor R11 and the resistor C1. One end of the eleventh resistor R11 receives the first standby voltage source VSB1, and the other end of the eleventh resistor R11 is coupled to the output end of the comparison unit 110 and the input end of the whole wave unit 130. The capacitor C1 is coupled between the other end of the eleventh resistor R11 and the ground voltage. As can be seen from FIG. 2, the delay unit 120 is an RC delay circuit, whereby the voltage level ready signal Vready is delayed, and the delay time can be determined by the RC constant.

The whole wave unit 130 includes a ninth resistor R9, a tenth resistor R10, and a fourth operational amplifier OP4. The ninth resistor R9 is coupled between the delay unit 120 and the positive input terminal of the fourth operational amplifier OP4. The tenth resistor R10 is coupled between the positive input terminal of the fourth operational amplifier OP4 and the output terminal of the fourth operational amplifier OP4, wherein the resistance of the tenth resistor R10 is much larger than the resistance of the ninth resistor R9. The negative input terminal of the fourth operational amplifier OP4 receives the reference voltage Vref. According to the circuit, the whole wave unit 130 is a non-inverting comparator with hysteresis function, which can prevent the voltage level ready signal Vready from rising too slowly, and the power ready signal PWR_OK is unstable. When the rising or falling speed of the voltage level ready signal Vready is raised, the transition time of the voltage level ready signal Vready can be shortened and output to the determining unit 140. .

The first detecting unit 141 includes a twelfth resistor R12, a thirteenth resistor R13, a first transistor TR1, a fourteenth resistor R14, and a second transistor M1. The standby state signal SLP_S3 is transmitted to the base (ie, the control terminal) of the first transistor TR1 through the twelfth resistor R12. The collector (ie, the first end) of the first transistor TR1 receives the transformer power supply VCCAD through the thirteenth resistor R13, and the emitter (ie, the second end) of the first transistor TR1 is coupled to the ground voltage. The fourteenth resistor R14 is coupled between the emitter of the first transistor TR1 and a ground voltage. The gate (ie, the control end) of the second transistor M1 is coupled to the collector of the first transistor TR1, and the drain (ie, the first end) of the second transistor M1 is coupled to the other end of the output resistor Ro. The source (ie, the second end) of the crystal M1 is coupled to the ground voltage.

For example, it is assumed that the standby state signal SLP_S3 indicates that the motherboard is not in the standby state with the high level voltage, and the motherboard is in the standby state with the low level voltage. When the standby state signal SLP_S3 is a low level voltage, the first transistor TR1 is in the cut-off region, that is, the first transistor TR1 does not have a current flowing. At this time, the thirteenth resistor R13 and the fourteenth resistor R14 divide the transformer power supply VCCAD and provide the gate to the second transistor M1. After the gate of the second transistor M1 receives the voltage, the second transistor M1 is turned on, causing a large amount of current to flow through the output resistor Ro to cause a voltage drop. At this time, the voltage level of the drain of the second transistor M1 is close to the ground voltage (ie, the low level voltage), and at the same time, the voltage level of the power-good signal PWR_OK is pulled low.

On the other hand, when the standby state signal SLP_S3 is at a high level voltage, the first transistor TR1 is in a saturation region, and a large amount of current flows through the first transistor TR1 and the thirteenth resistor R13. At this time, the voltage level of the collector of the first transistor TR1 is close to the ground voltage, and the transistor M1 cannot be turned on. Therefore, the voltage level of the drain of the second transistor M1 is the same as the voltage level of the power-good signal PWR_OK, and the voltage level of the power-good signal PWR_OK is controlled by the voltage level ready signal Vready and the second detecting unit. 142 output voltage level.

The second detecting unit 142 includes a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, and a third transistor TR2. The fifteenth resistor R15 is coupled between the transformer power supply VCCAD and the sixteenth resistor R16. The sixteenth resistor R16 is coupled between the fifteenth resistor R15 and the ground voltage. The seventeenth resistor R17 is coupled between the coupling of the sixteenth resistor R16 and the fifteenth resistor R15 and the base of the third transistor TR2 (ie, the control terminal). The emitter (ie, the first end) of the third transistor TR2 is coupled to the other end of the output resistor Ro, and the collector (ie, the second end) of the third transistor TR2 is coupled to the ground voltage.

For example, when the main board receives the transformer power supply VCCAD, the second detecting unit 142 also receives the transformer power supply VCCAD. Moreover, the fifteenth resistor R15 and the sixteenth resistor R16 divide the transformer power supply VCCAD, and are transmitted to the base of the third transistor TR2 through the seventeenth resistor R17, wherein the voltage obtained by the voltage division is greater than the second The voltage of the standby voltage source. Since the voltage of the base of the third transistor TR2 is greater than the voltage of its emitter, the third transistor TR2 is in the cut-off region, that is, no current flows through the third transistor TR2. At this time, the voltage level of the emitter of the third transistor TR2 is the same as the voltage level of the power-good signal PWR_OK, and the voltage level of the power-good signal PWK_OK is controlled by the voltage level ready signal Vready and the first detecting unit. 141 output voltage level.

On the other hand, when the main board does not receive the transformer power supply VCCAD, the second detecting unit 142 cannot receive the transformer power supply VCCAD, so that the voltage of the base of the third transistor TR2 is close to the ground voltage. At this time, the voltage of the base of the third transistor TR2 will be less than the voltage of its emitter, so the third transistor TR2 will be in the saturation region, that is, the third transistor TR2 will flow a large amount of current, and cause a large amount of current to flow. The output resistor Ro causes a voltage drop. At this time, the voltage level of the emitter of the third transistor TR2 is close to the ground voltage (ie, the low level voltage), and at the same time, the voltage level of the power-good signal PWR_OK is pulled low.

It is to be understood that the voltages and values used in the above examples are illustrative and are not intended to limit the embodiments of the invention. Moreover, those skilled in the art can use their knowledge to adjust the resistance value or the voltage value, and still determine whether the voltage source is ready, and pull down the voltage of the power-good signal PWR_OK when the motherboard is in standby or when the transformer power supply VCCAD disappears. Bit.

3 is a waveform diagram of a power supply ready signal of the motherboard control signal generating circuit of FIG. 1 without a full wave unit. 4 is a waveform diagram of a power-good signal of the motherboard control signal generating circuit of FIG. 1. Referring to FIGS. 3 and 4, the time axis of FIG. 3 is 20 nanoseconds (ns) per point, and the time axis of FIG. 4 is 4 nanoseconds (ns) per point. In the circuit operation, the whole wave unit 130 performs the transition time of the voltage level ready signal Vready on the voltage level ready signal Vready, and is subject to the reference voltage Vref (here, 2.5V as an example) and is amplified to be close to 2.5V. The voltage level ready signal Vready. Therefore, the whole wave unit 130 can filter the unstable waveform of the power-good signal PWR_OK as shown in FIG.

FIG. 5 is a waveform diagram of the power supply ready signal of the motherboard detecting signal generating circuit of FIG. 1 without the second detecting unit. 6 is a waveform diagram of a power-good signal of the motherboard control signal generating circuit of FIG. 1. Referring to Figures 5 and 6, the time axis of Figure 5 is 80 nanoseconds (ns) per point, and the time axis of Figure 6 is 100 picoseconds per second (ps). Since the first voltage source VCC1, the second voltage source VCC2, and the third voltage source VCC3 are converted by the transformer power supply VCCAD, after a transformer power supply VCCAD disappears, the first voltage source VCC1, the second voltage source VCC2, and the third The voltage source VCC will begin to drop and drop to ground. Therefore, in the motherboard control signal generating circuit 100 without the second detecting unit 142, the power-good signal PWR_OK outputted by it must be turned into a low-level voltage after a certain period of time. In the motherboard control signal generating circuit 100 having the second detecting unit 142, after the transformer power supply VCCAD disappears, the power ready signal PWR_OK is pulled down to the low level voltage. As a result, as shown in the figure, the delay time T1 shown in FIG. 5 is 3.072 milliseconds (ms), and the delay time T2 shown in FIG. 6 is 636.7 nanoseconds (ns).

In summary, the motherboard control signal generating circuit of the embodiment of the present invention determines whether the first voltage source, the second voltage source, and the third voltage source reach a corresponding voltage threshold according to whether the first voltage source, the second voltage source, and the third voltage source are ready. A voltage level ready signal is generated when a voltage source, a second voltage source, and a third voltage source are all ready. Moreover, the delay unit and the whole wave unit delay the voltage level ready signal and shorten the transition time thereof to meet the timing specification of the motherboard control signal, and avoid the waveform transition instability caused by the transition time being too long. The judging unit generates a power ready signal according to the voltage level ready signal, the standby state signal, and the transformer power supply. In this way, the power supply can be simulated to generate a timing-compliant power-good signal, and the motherboard is not started or the motherboard is turned off immediately when the motherboard is in standby or the transformer is powered off.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Motherboard control signal generation circuit

110. . . Comparison unit

111, 112, 113. . . Comparators

120. . . Delay unit

130. . . Whole wave unit

140. . . Judging unit

141, 142. . . Detection unit

VCC1, VCC2, VCC3. . . power source

VSB1, VSB2. . . Standby voltage source

SLP_S3. . . Standby signal

PWR_OK. . . Power ready signal

VCCAD. . . Transformer power supply

Vready. . . Voltage level ready signal

Ro, R1~R17. . . resistance

OP1~OP4. . . Operational Amplifier

C1. . . capacitance

Vref. . . Reference voltage

Va, Vb, Vc. . . Partial pressure

TR1, TR2, M1. . . Transistor

T1, T2. . . time

1 is a block diagram of a motherboard control signal generating circuit according to an embodiment of the present invention.

2 is a circuit diagram of a motherboard control signal generating circuit of FIG. 1.

3 is a waveform diagram of a power-good signal of a comparator having a hysteresis function composed of R9 and R10 in the motherboard control signal generating circuit of FIG. 1.

4 is a waveform diagram of a power-good signal of the motherboard control signal generating circuit of FIG. 1.

FIG. 5 is a waveform diagram of the power supply ready signal of the motherboard detecting signal generating circuit of FIG. 1 without the second detecting unit.

6 is a waveform diagram of a power-good signal of the motherboard control signal generating circuit of FIG. 1.

100. . . Motherboard control signal generation circuit

110. . . Comparison unit

111, 112, 113. . . Comparators

120. . . Delay unit

130. . . Whole wave unit

140. . . Judging unit

141, 142. . . Detection unit

VCC1, VCC2, VCC3. . . power source

VSB2. . . Standby voltage source

SLP_S3. . . Standby signal

PWR_OK. . . Power ready signal

VCCAD. . . Transformer power supply

Ro. . . resistance

Claims (11)

A motherboard control signal generating circuit is adapted to receive a transformer power supply of a motherboard system, comprising: a comparing unit, receiving a first voltage source, a second voltage source and a third voltage source, and according to the first The voltage source, the second voltage source, and the third voltage source output a voltage level ready signal, wherein the first voltage source, the second voltage source, and the third voltage source are converted by using the transformer power supply, and The voltage levels of the first voltage source, the second voltage source, and the third voltage source are different from each other; a delay unit coupled to the comparison unit for delaying the voltage level ready signal; a whole wave unit, The delay unit is coupled to shorten a transition time of the voltage level ready signal; and a determining unit coupled to the whole wave unit and receiving the transformer power supply and a standby state signal to be based on the transformer power supply, A standby state signal and the voltage level ready signal output a power ready signal, wherein the standby state signal is output by a south bridge of the motherboard. The motherboard control signal generating circuit of claim 1, wherein the comparing unit comprises: a first comparator, receiving the first voltage source, to determine whether the first voltage source is ready, and according to the Outputting a first level voltage; a second comparator receiving the second voltage source for determining whether the second voltage source is ready, and outputting a second level voltage accordingly; and a third comparator, Receiving the third voltage source for determining whether the third voltage source is ready, and outputting a third level voltage according to the output; wherein the first comparator, the second comparator, and the output of the third comparator And being coupled together to output the voltage level ready signal according to the first level voltage, the second level voltage, and the third level. The motherboard control signal generating circuit of claim 2, wherein the first comparator comprises: a first resistor coupled to the first voltage source at one end thereof; and a second resistor coupled to the first resistor Between the other end of the first resistor and a ground voltage, and providing a first voltage division; and a first operational amplifier, the positive input terminal receives the first divided voltage, the negative input terminal receives a reference voltage, and the output thereof The terminal outputs the first level voltage. The motherboard control signal generating circuit of claim 3, wherein the second comparator comprises: a third resistor coupled to the second voltage source at one end thereof; and a fourth resistor coupled to the second resistor a second resistor is coupled between the other end and the ground voltage, and provides a second voltage divider; and a second operational amplifier having a positive input terminal receiving the second divided voltage, a negative input terminal receiving the reference voltage, and an output thereof The terminal outputs the second level voltage. The motherboard control signal generating circuit of claim 3, wherein the third comparator comprises: a fifth resistor coupled to the third voltage source at one end thereof; and a sixth resistor coupled to the third resistor Between the other end of the fifth resistor and the ground voltage, and providing a third voltage division; and a third operational amplifier, the positive input terminal receives the third divided voltage, and the negative input terminal receives the reference voltage, and the output thereof The terminal outputs the third level voltage. The motherboard control signal generating circuit of claim 3, further comprising: a seventh resistor coupled to a first standby voltage source at one end thereof; and an eighth resistor coupled to the seventh resistor The other end is connected to the ground voltage and provides the reference voltage. The motherboard control signal generating circuit of claim 3, wherein the whole wave unit comprises: a ninth resistor, one end of which is coupled to the delay unit; and a fourth operational amplifier whose positive input terminal is coupled to the first The other end of the nine resistors, the negative input terminal receives the reference voltage, the output terminal outputs the voltage level ready signal after shortening the transition time; and a tenth resistor coupled to the positive of the fourth operational amplifier The input end is connected to the output end of the fourth operational amplifier, wherein the resistance of the tenth resistor is much larger than the resistance of the ninth resistor. The motherboard control signal generating circuit of claim 1, wherein the delay unit comprises: an eleventh resistor, one end of which receives a first standby voltage source, and the other end of which is coupled to the output end of the comparing unit And an input end of the whole wave unit; a first capacitor coupled between the other end of the eleventh resistor and a ground voltage. The motherboard control signal generating circuit of claim 1, wherein the determining unit comprises: a first detecting unit, receiving the standby state signal to output a fourth level voltage according to the standby state signal; a second detecting unit receives the transformer power supply to output a fifth level voltage according to the transformer power source; an output resistor, one end of which receives a second standby power source, and the other end of which is coupled to the output end of the whole wave unit The output end of the first detecting unit and the output end of the second detecting unit output the power ready signal according to the voltage level ready signal, the fourth level voltage, and the fifth level voltage The motherboard control signal generating circuit of claim 9, wherein the first detecting unit comprises: a twelfth resistor, one end of which receives the standby state signal; and a thirteenth resistor, one end of which receives the a first power transistor having a first end, a second end, and a control end, the control end of the first transistor being coupled to the other end of the twelfth resistor, the first transistor The first end is coupled to the other end of the thirteenth resistor, the second end of the first transistor is coupled to a ground voltage, and the fourteenth resistor is coupled to the first end of the first transistor And a second transistor having a first end, a second end, and a control end, the control end of the second transistor being coupled to the second end of the first transistor The first end of the second transistor is coupled to the other end of the output resistor, and the second end of the second transistor is coupled to a ground voltage. The motherboard control signal generating circuit of claim 9, wherein the second detecting unit comprises: a fifteenth resistor, one end of which receives the transformer power; and a sixteenth resistor coupled to the first Between the other end of the fifteenth resistor and a ground voltage; a seventeenth resistor, one end of which receives the other end of the fifteenth resistor; and a third transistor having a first end, a second end, and a a control end, the control end of the third transistor is coupled to the other end of the seventeenth resistor, the first end of the third transistor is coupled to the other end of the output resistor, the third end of the third transistor The two ends are coupled to a ground voltage.