201104814 六、發明說明： 【發明所屬之技術領域】 本發明係關於1半導體封裝構造、半導體封 造用載板及其f造料’制是關於—削以增加焊接 可罪度之半導體封震構造、半導體封裝構造錢板及立 製造方法。 【先前技術】 現今’半導體封I產業為了滿足各種高密度封裝之 需求，逐漸發展出各種不同型式之封裝構造，其中常見 具有基板(substrate)之封裝構造包含雜㈣封裝構造 加11 _抓吖’ BGA)、針腳陣列封裝構造(Pin grid array ’ PGA)、接點陣列封裝構造（land gdd &订吖，lga) 或基板上aa片封裝構造(board on chip , BOC)等。在上 述封裝構造中’該基板之—上表面承載有至少一晶片， 並經由打線(wire bonding)或凸塊(bum i )製 的數個接塾電性連接至該基板之上表面的 時，該基板之-下表面亦必需提供大量的潭塾， Ϊ個^端。再者，料湘錢衫w的基板而 吕，該基板通常選自-多層電路板，其在上表 面電路層以形成所需焊墊，且依產品需求，有時㈣ 可旎預先形成預焊料(pre_so〗der)，以增 p 之级人卞备# 興日曰片的凸塊 …口可靠度。因此，如何製造具有預焊料之 板’亦為封裝蓋業之-重要闕鍵技術。 、裝用基 201104814 請參照第1A及1B圖所示，其揭示一種習用具有預 焊料之封裝用基板及具有凸塊之晶片的構造及組裝示 意圖’其中—封裝用基板1〇選自-多層電路板，其在 上表面提供—電路層11及—防焊層12⑽der mask)。 該防焊層η覆蓋該電路層u，同時該防焊層η具有 數個開σ 12卜其曝露該電路層11之-部分表面，以 供形成-料⑴各該焊墊13上舰—步形成一預谭 料14再者’―晶片2〇係在一主動表面（未標示）上形 成數個電路層21、—保護層22、數個凸塊下金属層 (ΒΜ)23及數個凸塊24。該保護層22覆蓋韓電路層 U ’同時該保護層22具有數個開口（未標示），其曝露 該電路層21之—部分表面。該凸塊下金屬層23形成在 該開口内之電路層21上。該凸塊24形成在該凸塊下金 屬層23上。在利用高溫進行焊接時，該晶片20之電路 層21的凸塊24藉由該預焊料14之輔助而煤接結合於 該封裳用基板10之焊墊13上，且該預焊料14融入該 凸塊24内’因而完成焊接動作，使該晶片20電性連接 於該封裝用基板1〇上。 然而’該封裝用基板1〇之預焊料14在實際使用上 仍具有下述問題，例如：隨著半導體封裴構造的小型化 趨勢，該封裴用基板1〇之焊墊13的尺寸及間距日益縮 田該焊塾1 13的上表面外徑縮小至8〇微來（um)以下 及該烊塾13之相鄰間距縮小至160微米以下時’雖然 該預烊料14可提升該凸塊24與焊墊13之間的焊接性 201104814 質’但在後續對封裝產品進行可靠度測試(13(TC/濕度 85%持續96/168小時及在-55至125°C下進行500次循 環）時’卻容易在該電路層11與焊墊13之結合位置處 產生一破裂面（fracture)15而導致測試失敗。上述產生該 破裂面15的原因在於該電路層η與焊墊丨3雖為相同 材質（主要為銅），但因焊墊13為後來再電鍍上的，因 此在兩者之結合位置處之結合力相對較為脆弱，以致於 虽熱應力集中而在結合位置產生該破裂面15的測試缺 陷’進而影響測試良品率(yield)。 故，有必要提供一種半導體封裝構造、半導體封裝 構造用載板及其製造方法，以解決習知技術所存在的問 題。 【發明内容】 本發明之主要目的在於提供一種半導體封裝構造、 半導體封襄構造用载板及其製造方法，其係在載板的焊 塾内形成凹槽’以便填入焊料，並使焊料佈滿焊墊之上 表面’當焊墊及烊料進行焊接後’其可將熱應力集中位 置轉移至四槽之開口唇緣，以減少在焊墊及電路層之間 形成破裂面的風險’同時凹槽之構造也可減少熱應力最 大值’進而提升可靠度測試之良品率及產品使用壽命。 為達上述之目的，本發明提供一種半導體封裝構造 用载板，其係在一載板上設置：一電路層，形成在該載 板之一表面上；—絕緣層，覆蓋在該電路層上，且該絕 201104814 :層形成數個開口’以裸露-部分之該電路層;數個焊 播形成在該開Π内的電路層上，且各該焊墊凹設有一 :’及數個焊料，分卿成在各轉墊之凹槽内，並 佈滿各該悍墊之上表面。 在 =發明之一實_中，該触選自-電路基板， :焊料做為一預焊料；或者’該载板選自一 晶片’及 該4料做為一凸塊。 在本發明之一實施财，該焊墊之凹槽底部向下延 ::電路層之一凹陷部内；或者’該料之凹槽底部 向下貝穿通過該電路層。 在本發明之—實施例中，該载板之焊塾的相鄰間距 80微Γ。微米；以及’該載板之焊墊的上表面祕小於 再土者’本發明提供—種半導體封裝構造用載板之製 其包含步驟:提供一載板，其在-表面設有-及―絕緣層，該絕緣層覆蓋該電路層並形成數個 幵口 裸露—部分之該電路層；去除該開口内之電路 二，至y冑分厚度；形成—焊墊於各該開口内的電路 該烊塾具有一凹槽；以及，在各該焊塾之凹槽内 形成焊料，並使該焊料佈滿各該焊墊之上表面。 立、*月之一實施例中，在去除該電路層的至少一 部分厚以步财，選制雜繼(etehant)或電聚 )進行餘刻，以使該電路層形成一凹 選擇利用雷射錯孔…Uling)或機械:者孔 201104814 • (mechanical drilling)貫穿該開口内之電路層。 在本發明之一實施例中，在形成該焊墊的步驟中， 利用無電鍍(electroless plating)程序於各該開口内… 路層上形成具有該凹槽之該焊墊。 ^ 在本發明之一實施例中，在形成該焊料的步驟中， 利用電鍍(plating)或印刷（printing)在各該焊墊之凹槽内 填入該焊料，並使其佈滿各該焊墊之上表面。 在本發明之一實施例中，在形成該焊料的步驟後， 馨 另包含：對該焊料進行回焊(reflow)。 在本發明之一實施例中，該載板選自一電路基板， 及該知料做為一預焊料；或者，該載板選自一晶片，及 該焊料做為一凸塊。 在本發明之一實施例中，該載板之焊墊的相鄰間距 小於160微米；以及，該載板之焊墊的上表面外徑小於 80微米。 ' • 另外，本發明提供一種半導體封裝構造，其包含： 電路基板’其具有：一第一電路層，形成在該電路基 板之一表面上；一第一絕緣層，覆蓋在該第一電路層 上，且該第一絕緣層形成數個第一開口，以裸露一部分 之該第-電路層；錢個第—焊塾，形成在該第一開口 内的第-電路層上；—晶片，其具有：一第二電路層， 形成在該晶>{之—主動表面上；—第二絕緣層，覆蓋在 “第電路層上’且該第二絕緣層形成數個第二開口， 以裸露-部分之該第二電路層；及數個第三焊塾，形成 201104814 在該第二開口内的第二電路層上，其中該電路基板的第 一焊墊及該晶片的第二焊墊的至少其中一方係凹設有 一凹槽；以及，數個凸塊，連接於該第一焊墊及該第二 焊墊之間，且該凸塊之焊料填入該凹槽内。 在本發明之一實施例中，該第一焊墊設有該凹槽， 該凹槽底部向下延伸至該第一電路層之一凹陷部内；或 者，該凹槽底部向下貫穿通過該第一電路層。 在本發明之一實施例中，該第一焊墊設有該凹槽， 該第一焊墊的相鄰間距小於160微米；以及，該第一載 板之焊墊的上表面外徑小於80微米。 在本發明之一實施例中，該第二焊墊設有該凹槽， 該凹槽底部向下延伸至該第二電路層之一凹陷部内；或 者，該凹槽底部向下貫穿通過該第二電路層。 【實施方式】 為了讓本發明之上述及其他目的、特徵、優點能更 明顯易懂，下文將特舉本發明較佳實施例，並配合所附 圖式，作詳細說明如下。 在本發明之較佳實施例中，本發明之半導體封裝構 造用載板主要係在一載板上設置一電路層、一絕緣層、 數個焊墊及數個焊料。該載板主要選自封裝用基板，或 亦可能選自晶片。本發明用以在該載板之焊墊的中央位 置凹設形成一凹槽，以填充焊料並使其佈滿該焊墊之上 表面。例如，請參照第2圖所示，本發明第一實施例之 201104814 半導體封裝構造用載板主要係在一電路基板30上設 置：一電路層31，形成在該電路基板30之一表面上； 一絕緣層32，覆蓋在該電絡層31上，且該絕緣層32 形成數個開口 321，以裸露〆部分之該電路層31 ;數個 焊墊33，形成在該開口 321内的電路層31上，且各該 焊墊33凹設有一凹槽331 ;及數個焊料34，分別形成 在各該焊墊33之凹槽331内’並佈滿各該焊墊33之上 表面。本發明將於下文利用第3A至3D圖逐一詳細說 明第2圖之半導體封襞構造用載板的製造流程及其細 部構造。 睛參照第3A圖所示，本發明第一實施例之半導體 封裝構造用載板之製造方法第一步驟係：提供一電路基 板30，其在一表面設有一電路層31及一絕緣層32，該 絕緣層32覆蓋該電路層31並形成數個開口 321，以裸 露一部分之該電路層31。在本步驟中，該電路基板3〇(亦 即载板)係選自一半導體封裝用電路基板，例如選自單 層或多層之印刷電路基板、陶瓷電路基板或軟性電路 板，且該電路基板30較佳係選自一覆晶（flipchip，FC) 封裝用基板。該電路基板3〇在一表面（例如上表面）設 有該電路層31，且該電路基板3〇視其應用之封裝構造 可能具有其他電路設計，例如該電路基板3〇可能在其 内部設有其他相互連揍之内部電路層（未標示），並在另 —表面設有另一表面電路層（未標示），以提供數個輸入 /輪出端（input/output ’ 10)。在本實施例中，該電路層 201104814 31之材質較佳選自鋼、鋁、金、銀或其等效導電金屬。 該絕緣層32覆蓋該電路層31，且該絕緣層32較佳係 由液態感光材料所形成之防焊層(s〇ldei· mask)，其可通 過曝光及顯影等既有加工手段形成該數個開口 321，以 裸露一部分之該電路層31。 請參照第3B圖所示，本發明第一實施例之半導體201104814 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor package structure, a semiconductor package carrier, and a semiconductor device for manufacturing a semiconductor sealing structure for increasing the degree of soldering sin , semiconductor package construction currency board and vertical manufacturing method. [Prior Art] Nowadays, in order to meet the needs of various high-density packaging, the semiconductor packaging industry has gradually developed various types of package structures. Among them, the package structure with a substrate has a heterogeneous (four) package structure plus 11 _ BGA), pin grid array 'PGA', contact array package structure (land gdd & order, lga) or on-board aa chip package (BOC). In the above package structure, when the upper surface of the substrate carries at least one wafer and is electrically connected to the upper surface of the substrate via a plurality of wires made of wire bonding or bump (bum i ), The bottom surface of the substrate must also provide a large number of pools, one end. Furthermore, the substrate of the kanban w is the substrate, which is usually selected from a multi-layer circuit board, which is formed on the upper surface circuit layer to form a desired solder pad, and sometimes (4) may be pre-formed as a pre-solder depending on the product requirements. (pre_so〗 der), to increase the level of the person's level of preparation #兴日曰片的凸块... mouth reliability. Therefore, how to manufacture a board with pre-solder is also an important key technology for the package cover industry. Mounting base 201104814 Please refer to FIGS. 1A and 1B, which discloses a structure and an assembly diagram of a conventional package substrate with pre-solder and a wafer having bumps. [The package substrate 1 is selected from a multilayer circuit. A board is provided on the upper surface - a circuit layer 11 and a solder mask 12 (10) der mask. The solder resist layer η covers the circuit layer u, and the solder resist layer η has a plurality of openings σ 12 and a portion of the surface on which the circuit layer 11 is exposed for forming a material (1) on each of the pads 13 Forming a pre-tank 14 and then "wafer 2" is formed on an active surface (not labeled) to form a plurality of circuit layers 21, a protective layer 22, a plurality of under bump metal layers (ΒΜ) 23 and a plurality of bumps Block 24. The protective layer 22 covers the Korean circuit layer U' while the protective layer 22 has a plurality of openings (not shown) that expose portions of the surface of the circuit layer 21. The under bump metal layer 23 is formed on the circuit layer 21 in the opening. The bump 24 is formed on the under bump metal layer 23. When soldering is performed at a high temperature, the bumps 24 of the circuit layer 21 of the wafer 20 are coal-bonded to the pads 13 of the boarding substrate 10 with the aid of the pre-solder 14, and the pre-solder 14 is incorporated In the bump 24, the soldering operation is completed, and the wafer 20 is electrically connected to the package substrate 1A. However, the pre-solder 14 of the package substrate 1 has the following problems in practical use, for example, the size and pitch of the pad 13 of the package substrate 1 with the trend toward miniaturization of the semiconductor package structure. Increasingly, the outer diameter of the upper surface of the soldering iron 1 13 is reduced to less than 8 μm and the adjacent spacing of the crucible 13 is reduced to less than 160 μm, although the pre-twist 14 can lift the bump The weldability between 24 and the pad 13 is good, but the subsequent reliability test of the packaged product (13 (TC/humidity 85% for 96/168 hours and 500 cycles at -55 to 125 °C) At the same time, it is easy to generate a fracture 15 at the bonding position of the circuit layer 11 and the bonding pad 13 to cause a test failure. The reason for the occurrence of the fracture surface 15 is that the circuit layer η and the pad 3 are The same material (mainly copper), but because the solder pad 13 is later electroplated, the bonding force at the joint position of the two is relatively weak, so that the thermal crack is generated at the bonding position despite the thermal stress concentration. Test defect 'and thus affect test yield (yield) Therefore, it is necessary to provide a semiconductor package structure, a carrier for a semiconductor package structure, and a method of manufacturing the same to solve the problems of the prior art. SUMMARY OF THE INVENTION The main object of the present invention is to provide a semiconductor package structure and a semiconductor package. a carrier plate for construction and a method of manufacturing the same, which form a groove in a soldering pad of a carrier plate to fill the solder and fill the surface of the pad with solder after the solder pad and the solder material are soldered Transfer the thermal stress concentration position to the open lip of the four slots to reduce the risk of forming a rupture surface between the pad and the circuit layer. At the same time, the structure of the groove can also reduce the maximum thermal stress, thereby improving the reliability test. The present invention provides a carrier for a semiconductor package structure, which is provided on a carrier board: a circuit layer is formed on one surface of the carrier; an insulating layer, Covering the circuit layer, and the anode 201104814: the layer forms a plurality of openings 'to expose the portion of the circuit layer; a plurality of solder layers are formed in the circuit layer of the opening And each of the pads is concavely provided with one: 'and a plurality of solders, which are divided into the grooves of the respective pads, and are covered with the upper surfaces of the pads. In the invention, the touch Selecting from - a circuit substrate: solder as a pre-solder; or 'the carrier is selected from a wafer' and the 4 material as a bump. In one embodiment of the invention, the bottom of the groove of the pad Deferred:: a recess in one of the circuit layers; or 'the bottom of the recess of the material passes through the circuit layer. In the embodiment of the invention, the adjacent spacing of the solder fillets of the carrier is 80 micro. Micron; and 'the upper surface of the pad of the carrier plate is less than the re-earther'. The invention provides a carrier for a semiconductor package structure comprising the steps of: providing a carrier plate provided on the surface - and ― an insulating layer covering the circuit layer and forming a plurality of the exposed portions of the circuit layer; removing the circuit 2 in the opening to a thickness of y ;; forming a circuit for solder pads in each of the openings The crucible has a recess; and a solder is formed in the recess of each of the solder fillets and the solder is covered The upper surface of each of the pads. In one embodiment of the first month, in the embodiment, at least a portion of the circuit layer is removed to make a step, and an etehant or electropolymer is selected to make a residual, so that the circuit layer forms a concave selection laser. (Uling) or mechanical: hole 201104814 • (mechanical drilling) through the circuit layer inside the opening. In an embodiment of the invention, in the step of forming the pad, the pad having the groove is formed on each of the openings by an electroless plating process. In an embodiment of the present invention, in the step of forming the solder, the solder is filled in the grooves of each of the pads by plating or printing, and is filled with the solder. The top surface of the mat. In an embodiment of the invention, after the step of forming the solder, the scent further comprises: reflowing the solder. In an embodiment of the invention, the carrier is selected from a circuit substrate, and the material is used as a pre-solder; or the carrier is selected from a wafer, and the solder is used as a bump. In one embodiment of the invention, the pads of the carrier have an adjacent pitch of less than 160 microns; and the pads of the carrier have an outer diameter of less than 80 microns. In addition, the present invention provides a semiconductor package structure comprising: a circuit substrate having: a first circuit layer formed on a surface of the circuit substrate; a first insulating layer covering the first circuit layer And the first insulating layer forms a plurality of first openings to expose a portion of the first circuit layer; the first solder bump is formed on the first circuit layer in the first opening; Having: a second circuit layer formed on the active surface of the crystal; a second insulating layer covering the "first circuit layer" and the second insulating layer forming a plurality of second openings to expose a portion of the second circuit layer; and a plurality of third solder pads forming a second circuit layer in the second opening, wherein the first pad of the circuit substrate and the second pad of the wafer At least one of the recesses is recessed; and a plurality of bumps are connected between the first solder pad and the second solder pad, and the solder of the bump is filled in the recess. In one embodiment, the first pad is provided with the recess, the recess The bottom portion extends downwardly into one of the recesses of the first circuit layer; or the bottom of the recess penetrates through the first circuit layer downward. In an embodiment of the invention, the first solder pad is provided with the recess The first pad has an adjacent pitch of less than 160 micrometers; and the upper surface of the pad of the first carrier has an outer diameter of less than 80 micrometers. In an embodiment of the invention, the second pad is provided with the a groove extending downwardly into a recess of one of the second circuit layers; or the bottom of the groove penetrating downwardly through the second circuit layer. [Embodiment] For the above and other purposes of the present invention The features and advantages of the invention will be more apparent and understood. The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the preferred embodiment of the present invention, the semiconductor package structure of the present invention is used. The carrier board is mainly provided with a circuit layer, an insulating layer, a plurality of solder pads and a plurality of solders on a carrier board. The carrier board is mainly selected from a substrate for packaging or may be selected from a wafer. The central position of the pad of the carrier is recessed Forming a recess to fill the solder and fill the upper surface of the solder pad. For example, as shown in FIG. 2, the 201104814 semiconductor package structure carrier of the first embodiment of the present invention is mainly used for a circuit substrate. A circuit layer 31 is disposed on a surface of the circuit substrate 30; an insulating layer 32 is disposed on the electrical layer 31, and the insulating layer 32 forms a plurality of openings 321 to expose the exposed portion The circuit layer 31 has a plurality of pads 33 formed on the circuit layer 31 in the opening 321, and each of the pads 33 is recessed with a recess 331; and a plurality of solders 34 are formed on each of the pads 33. The inside of the groove 331 is filled with the upper surface of each of the pads 33. The present invention will be described in detail below with reference to FIGS. 3A to 3D to explain the manufacturing process and the detailed structure of the carrier plate for the semiconductor sealing structure of FIG. . Referring to FIG. 3A, a first step of a method for manufacturing a carrier for a semiconductor package according to a first embodiment of the present invention is to provide a circuit substrate 30 having a circuit layer 31 and an insulating layer 32 on a surface thereof. The insulating layer 32 covers the circuit layer 31 and forms a plurality of openings 321 to expose a portion of the circuit layer 31. In this step, the circuit board 3 (ie, the carrier board) is selected from a circuit board for semiconductor packaging, for example, a single-layer or multi-layer printed circuit board, a ceramic circuit board, or a flexible circuit board, and the circuit board 30 is preferably selected from a flip chip (FC) package substrate. The circuit board 3 is provided with a circuit layer 31 on a surface (for example, an upper surface), and the circuit board 3 may have other circuit designs depending on the package configuration of the application, for example, the circuit board 3 may be provided therein. Other interconnected internal circuit layers (not shown) and another surface circuit layer (not labeled) on the other surface to provide several inputs/outputs (input/output '10). In this embodiment, the material of the circuit layer 201104814 31 is preferably selected from the group consisting of steel, aluminum, gold, silver or its equivalent conductive metal. The insulating layer 32 covers the circuit layer 31, and the insulating layer 32 is preferably a solder resist layer formed of a liquid photosensitive material, which can be formed by existing processing means such as exposure and development. An opening 321 is formed to expose a portion of the circuit layer 31. Referring to FIG. 3B, the semiconductor of the first embodiment of the present invention
封裝構造用載板之製造方法第二步驟係：去除該開口 321内之電路層31的至少一部分厚度。在本步驟中， 本發明選擇利用ϋ刻液(etehant)或錢恤麵)進行餘 刻，以去除該開口 321内之電路層31的至少一部分厚 度’但適當控制成不貫穿該電路層3卜如此不但可清 潔該電路層31的表面’並可形成一凹陷部扣，以增 加該電路層與後續形成之焊墊33的結合面積，進而 增加兩者之結合強度。在上述㈣程序中，僅會因產生 了該凹陷部m而增加該開口 321之深度，但通常不會 擴大該開口 321之内經尺寸。 請參照第3C圖所示，本發明第—實施例之半導體 封裝構造用載板之製造方法第三步驟係：形成一焊墊 33於各該開口 321内的電路層31上，該焊塾％具有 -凹槽3M。在本步驟中’本發明較佳利用無電鍛 (eleCtr〇leSS咖㈣程序來形成該焊塾33，且在進行無 電鍍程序之前，較佳預先形成一圖 32上，該圖案化光阻層對應該二】形 成數個窗口（未繪示），以便藉由該窗口來定義㈣墊33 201104814 之上表面外經。該谭墊33之材質較 銀或其等效導電金屬。I菸、自銅、鋁、金、 守电金屬本發明並不限制 積厚度’但該焊塾33之上表面外徑較 3之沈 微米’及該焊塾33的相鄰間距較佳 於:: 米。藉由適當㈣無電難序之加I條件，該 將沈積形成在各該開口 321内的電路層31之凹陷部扣 上’並沿著該開口 321之孔壁向外延伸至該絕緣層32The second step of the method of manufacturing the carrier for package structure is to remove at least a portion of the thickness of the circuit layer 31 in the opening 321 . In this step, the present invention selects the engraving liquid (etehant) or the cashmere surface to remove the at least a portion of the thickness of the circuit layer 31 in the opening 321 but is suitably controlled so as not to penetrate the circuit layer 3 Thus, not only the surface of the circuit layer 31 can be cleaned and a recessed portion buckle can be formed to increase the bonding area of the circuit layer and the subsequently formed solder pad 33, thereby increasing the bonding strength between the two. In the above (4) procedure, only the depth of the opening 321 is increased by the occurrence of the depressed portion m, but the inner diameter of the opening 321 is generally not enlarged. Referring to FIG. 3C, the third step of the method for manufacturing a carrier for a semiconductor package according to the first embodiment of the present invention is to form a pad 33 on the circuit layer 31 in each of the openings 321, and the solder % is With a groove 3M. In this step, the present invention preferably forms the solder bump 33 by an electroless forging (eleCtr〇leSS coffee (4) program, and before forming an electroless plating process, it is preferably formed in advance on FIG. 32, the patterned photoresist layer pair Two windows (not shown) are formed to define (4) the outer surface of the pad 33 201104814 by the window. The material of the pad 33 is more silver or its equivalent conductive metal. I smoke, from copper The present invention does not limit the thickness of the metal, but the outer diameter of the upper surface of the solder bump 33 is smaller than 3 and the adjacent pitch of the solder bump 33 is preferably:: m. Appropriate (4) an uncharged sequence of I conditions, which will deposit the depressed portion of the circuit layer 31 formed in each of the openings 321 and extend outward along the hole wall of the opening 321 to the insulating layer 32.
之上表面’⑽焊墊33將於其中央位置形成該凹槽 331。該凹槽331之形狀係對應該開口 321之形狀，通 常兩者皆為圓柱形，但並不限於此。各該焊墊33具有 的該凹槽331之數量較佳為1個，但亦不限於此。 請參照第3D圖所示，本發明第一實施例之半導體 封裝構造用載板之製造方法第四步驟係：在各該焊墊 33之凹槽331内形成一焊料34,並使該焊料34佈滿各 該焊塾33之上表面。在本步驟中，本發明可選擇利用 電鑛(plating)或印刷（printing)的程序在各該焊墊33之 凹槽331内填入該焊料34。該焊料34之材質可選自錫、 含鉛焊料或無鉛焊料，例如：上述含鉛焊料可選自 Sn63/Pb37(含63%之錫及37%的錯）’及上述無錯焊料 可選自 SnO_7Cu(含 0.7%之銅）、Sn3.5Ag (含 3.5%之銅）、 8113.5人8〇.7(1：11(含3.5%之銀及0.7%之銅）、8119211(含9% 之鋅）、Sn5Sb(含 5%之銻）、Sn58Bi(含 58%之鉍）、Sn52In (含52%之銦）、In3Ag(含97%之銦及3%之銀）、 Au20Sn(含80%之金及20%之錫）’但並不限於此。在完 12 201104814 成電鑛或印刷程序後，該焊料34將填滿該凹槽33i並 溢外至佈滿該焊塾33之整個上表面，以做為^焊料使 用。再者，在-實施例中，如第2圖所示，本發明另可 在形成該焊料34後，進-步對該焊料％回焊__， 使該烊料34炼融時因内聚力而形成圓弧狀外觀。 請參照第4圖所示’本發明第—實施例之電路基板 30係-封裝用基板’其係可用以結合一晶片4〇，以構 & —覆晶式半導體封裝構造。在-實施例中，該晶片 零 4〇係選自由半導體晶圓切割而成之矽晶片，其係在一 主動表面（未標示）上形成數個電路層4卜一絕緣層U、 數個凸塊下金屬層43及數個凸塊44。該絕緣層42覆 蓋該電路層41，同時該絕緣層42具有數個開口 421， 其曝露該電路層41之-部分表面。該凸塊下金屬層43 形成在該開口 421内之電路層41上。該凸塊44形成在 該凸塊下金屬層43上。該凸塊44可選自相同或相異於 # 該焊料34之材質，例如選自錫或各種含鉛焊料或無鉛 焊料。 請參照第5圖所示，在利用高溫進行焊接時，該晶 片40之電路層41的凸塊44藉由該焊料34之輔助而焊 接結合於該電路基板30之焊塾33上，且該焊塾33之 上表面及凹槽331内的焊料34融入該凸塊44内成為一 焊接構造，因而使該晶片40電性連接於該電路基板 上。在元成製做該覆晶式半導體封裝構造之後，接著本 發明對其進行可靠度測試（130。(：/濕度85%持續96/168 13 201104814 小時及在-55至赋下進行次循環）。測試結果顯 不，即使該電路基板30之焊塾。33的上表面外徑縮小至 80微米以下及該焊墊33之相鄰間距縮小至⑽微米以 下’該凸塊44與雜33之_焊接構造仍足以承受因 熱膨脹係數(CTE)差異所造成的熱應力，且未形成破裂 面(fracture)。經過分析證實，由於本發明的電路基板3〇 之焊墊33設置該凹槽331來容置該焊料34，因此該凹 槽331可提供更大的表面積，使得該焊塾33與凸塊44 之間具有更大的焊接結合面積。同時，該焊接構造的熱 應力集中點S也將轉移至該焊墊33之凹槽％的開口唇 緣處，而熱應力之最大值也會顯著的降低許多。是以， 本發明利用該凹槽331來容置該焊料34的設計確實能 在间;jnL 4接期間強化該凸塊44與焊塾3 3之間的焊接結 合強度，並降低測試缺陷發生率，進而提升測試之良品 率(yield)及產品使用壽命。 φ 請參照第6A至6D圖所示，本發明第二實施例之半 導體封裝構造用載板之製造方法係相似於本發明第一 實施例，並大致沿用相同圖號，但不同之處在於該第二 實施例在第一步驟中係選擇利用雷射鑽孔(iaser drilling) 或機械鑽孔(mechanical drilling)貫穿該絕緣層32之開 口 321内的電路層31。因此，在第三步驟中，該焊墊 33之凹槽331底部將會向下貫穿通過該電路層31約一 小段預定長度’該貫穿長度係可依產品需求適當加以調 整。藉此，可進一步增加該電路層31與後續形成之焊 201104814 墊33的結合面積，進而增加兩者之結合強度。再者， 在第四步驟中，該凹槽331將可容置更多的該焊料34。 當該電路基板30結合於一晶片40時(相似於第4及5 圖所示），該凹槽331也可提供更大的表面積，使得該 焊墊33與凸塊44之間具有更大的焊接結合面積。同 時，該焊墊33與凸塊44之焊接構造的熱應力集中點S 也將轉移至該焊墊33之凹槽33的開口唇緣，而熱應力 之最大值也會顯著降低。是以，本發明第二實施例可更 進一步強化該凸塊44之焊接結合強度。 請參照第7圖所示，本發明第三實施例之半導體封 裝構造係相似於本發明第一實施例，並大致沿用相同圖 號，但不同之處在於該第三實施例係將凹槽設計應用至 該晶片40上，其中先利用蝕刻液或電漿對該晶片40之 絕緣層42的開口 421所裸露的該電路層41上進行蝕 刻，以去除該開口 421内之電路層41的至少一部分厚 度，但不貫穿該電路層41，如此可在該電路層41的表 面形成一凹陷部411。接著，並在該晶片40之電路層 41的凹陷部411上形成一焊墊45,且各該焊墊45在其 中央位置凹設形成一凹槽451，並使一焊料46填入該 凹槽451内並佈滿各該焊墊45之上表面。該焊料46更 可進一步回焊形成凸塊(bump)形狀。再者，在第三實施 例中，該電路基板30係一覆晶封裝用基板，其上表面 的焊墊33同樣可具有該凹槽331的設計，以容置該焊 料34做為預焊料使用。藉此，在高溫焊接結合該晶片 15 201104814 4〇及電路基板30時，該晶片40之焊墊45的凹槽451 同樣可以增加該焊墊45與焊料46之間的焊接結合強 度’並改變熱應力集中點S至該凹槽451的開口唇緣 處’且能減少熱應力最大值，並提升可靠度測試之良品 率及產品使用寿命。 再者，在第三實施例中，為了使該焊墊45具有足夠 的高度(厚度）’本發明可在該晶片40之主動表面上的 保護層42a上進一步額外製做一重佈絕緣層 (redistribution insulation layer)42b 做為該絕緣層 42，以 達到增加該焊墊45的高度(厚度)之目的。另外，若該 晶片40之主動表面的電路層41設計允許，則亦可能選 擇利用雷射鑽孔或機械鑽孔貫穿該絕緣層42之開口 421内的電路層41 ’使該焊墊45之凹槽451底部向下 貫穿通過該電路層41約一小段預定長度(未繪示），以 進一步增加該電路層41與後續形成之焊墊45的結合面 參積，進而增加結合強度。或者，在另一實施例中，在該 晶片40之焊墊45已具備該凹槽451的前題下，該電路 基板30之焊墊33的上表面亦可保持平坦，省略設置誃 凹槽331的設計，並僅在該焊墊33的上表面佈設傳= 如上所述，相較於第1及2圖習用封裝用義板 之悍墊13上的預焊料14在與該晶片2〇 之凸塊24 10 結合後’仍容易在該電路層11與焊塾13之纟士八 因熱應力集中而產生該破裂面15等問題，第3 埤接 置處 5圖 201104814 之本發明藉由在該電路基板30等載板構造的焊塾33内 形成該凹槽331，以便填入該焊料34，並使該焊料34 佈，該焊塾33之上表面，其確實可有效增加該焊料％ 與焊墊33之間的結合面積及結合強度。再者，當該焊 塾33及焊料34進行焊接後，其可將熱應力集中^轉 移至該凹槽331的開口唇緣，以減少在該焊塾31的凹 陷部311表面形成破裂面的風險，同時該凹槽331之構 •造也可減少熱應力最大值，進而提升可靠度測試之良品 率及產品使用壽命。 雖然本發明已簡佳實_揭露，然其並非用以限 制本發明，任何熟習此項技藝之人士，在不脫離本發明 之精神和1㈣内，當可作各種更動_飾，因此本發明 之保護範圍當視後附之申請專利範園所界定者為準。 【圖式簡單說明】 具有預焊料之封裝用基板及具有 鲁 第1A及1B圖：習用 凸塊之晶片的示意圖。 第2圖·本發明第—實施例之 示意圖。 半導體封裴構造用載板之 第3A至3D圖：本發明第一實施例之半導體封裝構遠 用載板之製造方法之流程圖。 第4圖二本發明第—實施例之半導體料構造在進行踩 接結合前之示意圖。 第5圖：本發明第—實施例之半導體料構造在進行择 17 201104814 接結合後之不意圖。 第6A至6D圖：本發明第二實施例之半導體封裝構造 用載板之製造方法之流程圖。 第7圖：本發明第三實施例之半導體封裝構造在進行焊 接結合前之示意圖。 【主要元件符號說明】 10 封裝用基板 11 電路層 12 防焊層 121 開口 13 焊墊 14 預焊料 15 破裂面 20 晶片 21 電路層 22 保護層 23 凸塊下金屬層 24 .凸塊 30 電路基板 31 電路層 311 凹陷部 32 絕緣層 321 開口 33 焊墊 331 凹槽 34 焊料 40 晶片 41 電路層 411 凹陷部 42 絕緣層 42a 保護層 42b 重佈絕緣層 421 開口 43 凸塊下金屬層 44 凸塊 45 焊墊 451 凹槽 46 焊料 S 熱應力集中點The upper surface '(10) pad 33 will form the groove 331 at its central position. The shape of the groove 331 corresponds to the shape of the opening 321 and is generally cylindrical, but is not limited thereto. The number of the grooves 331 of each of the pads 33 is preferably one, but is not limited thereto. Referring to FIG. 3D, a fourth step of the method for manufacturing a carrier for a semiconductor package according to the first embodiment of the present invention is to form a solder 34 in the recess 331 of each of the pads 33 and to make the solder 34. The upper surface of each of the pads 33 is covered. In this step, the present invention may optionally fill the recesses 331 of the pads 33 with the solder 34 by means of a plating or printing process. The material of the solder 34 may be selected from tin, lead-containing solder or lead-free solder. For example, the lead-containing solder may be selected from the group consisting of Sn63/Pb37 (containing 63% tin and 37% wrong) and the above-mentioned error-free solder may be selected from SnO_7Cu (containing 0.7% copper), Sn3.5Ag (containing 3.5% copper), 8113.5 people 8〇.7 (1:11 (containing 3.5% silver and 0.7% copper), 8119211 (containing 9% zinc) ), Sn5Sb (containing 5% of bismuth), Sn58Bi (containing 58% of bismuth), Sn52In (including 52% of indium), In3Ag (containing 97% of indium and 3% of silver), Au20Sn (including 80% of gold) And 20% tin) 'but not limited to this. After 12 201104814 into the electric ore or printing process, the solder 34 will fill the groove 33i and overflow to cover the entire upper surface of the pad 33, Further, in the embodiment, as shown in FIG. 2, the present invention may further reflow the solder __ after the solder 34 is formed. In the case of the smelting, the arc-like appearance is formed by the cohesive force. Referring to Fig. 4, the circuit board 30-package substrate of the first embodiment of the present invention can be used to bond a wafer 4 to ; - flip chip semiconductor package In an embodiment, the wafer is selected from the group consisting of a semiconductor wafer, and is formed by forming a plurality of circuit layers 4 and an insulating layer U on an active surface (not shown). a bump under metal layer 43 and a plurality of bumps 44. The insulating layer 42 covers the circuit layer 41, and the insulating layer 42 has a plurality of openings 421 exposing a portion of the surface of the circuit layer 41. A layer 43 is formed on the circuit layer 41 in the opening 421. The bump 44 is formed on the under bump metal layer 43. The bump 44 may be selected from the same or different material of the solder 34, for example, From tin or various lead-containing solders or lead-free solders. Referring to FIG. 5, when soldering is performed at a high temperature, the bumps 44 of the circuit layer 41 of the wafer 40 are soldered to the circuit by the aid of the solder 34. The soldering surface 33 of the substrate 30, and the solder 34 on the upper surface of the solder bump 33 and the recess 331 are integrated into the bump 44 to form a solder structure, thereby electrically connecting the wafer 40 to the circuit substrate. After the semiconductor device is fabricated into the flip chip semiconductor package structure, the present invention Line reliability test (130. (: / humidity 85% for 96/168 13 201104814 hours and -55 to sub-cycle for the second cycle). The test results are not even if the circuit board 30 is soldered. The upper surface of 33 The outer diameter is reduced to less than 80 microns and the adjacent pitch of the pad 33 is reduced to less than (10) micrometers. The soldered structure of the bump 44 and the hybrid 33 is still sufficient to withstand the thermal stress caused by the difference in thermal expansion coefficient (CTE), and No fracture was formed. It has been confirmed by analysis that since the pad 33 of the circuit substrate 3 of the present invention is provided with the groove 331 to accommodate the solder 34, the groove 331 can provide a larger surface area, so that the pad 33 and the bump 44 are There is a larger weld joint area between. At the same time, the thermal stress concentration point S of the welded structure will also be transferred to the opening lip of the groove % of the pad 33, and the maximum value of the thermal stress will be significantly reduced. Therefore, the design of the present invention using the recess 331 to accommodate the solder 34 can indeed strengthen the solder joint strength between the bump 44 and the solder tab 3 during the connection of the jnL 4 and reduce the incidence of test defects. , thereby improving the yield of the test and the service life of the product. φ. Referring to FIGS. 6A to 6D, the manufacturing method of the carrier for semiconductor package structure according to the second embodiment of the present invention is similar to the first embodiment of the present invention, and substantially the same drawing number is used, but the difference is that In the second embodiment, in the first step, the circuit layer 31 in the opening 321 of the insulating layer 32 is selected by laser drilling or mechanical drilling. Therefore, in the third step, the bottom of the groove 331 of the pad 33 will penetrate downward through the circuit layer 31 for a predetermined length of length. The through length can be appropriately adjusted according to product requirements. Thereby, the bonding area of the circuit layer 31 and the subsequently formed solder 201104814 pad 33 can be further increased, thereby increasing the bonding strength between the two. Furthermore, in the fourth step, the recess 331 will accommodate more of the solder 34. When the circuit substrate 30 is bonded to a wafer 40 (similar to the fourth and fifth figures), the recess 331 can also provide a larger surface area, so that the pad 33 and the bump 44 have a larger Welding joint area. At the same time, the thermal stress concentration point S of the soldering structure of the pad 33 and the bump 44 is also transferred to the opening lip of the recess 33 of the pad 33, and the maximum value of the thermal stress is also remarkably lowered. Therefore, the second embodiment of the present invention can further enhance the solder joint strength of the bumps 44. Referring to FIG. 7, the semiconductor package structure of the third embodiment of the present invention is similar to the first embodiment of the present invention, and generally uses the same drawing number, but the difference is that the third embodiment has a groove design. Applied to the wafer 40, the circuit layer 41 exposed by the opening 421 of the insulating layer 42 of the wafer 40 is first etched with an etchant or plasma to remove at least a portion of the circuit layer 41 in the opening 421. The thickness, but not the circuit layer 41, is formed so that a depressed portion 411 can be formed on the surface of the circuit layer 41. Then, a pad 45 is formed on the recess 411 of the circuit layer 41 of the wafer 40, and each of the pads 45 is recessed at a central position thereof to form a recess 451, and a solder 46 is filled into the recess. The upper surface of each of the pads 45 is covered in 451. The solder 46 can be further reflowed to form a bump shape. Furthermore, in the third embodiment, the circuit substrate 30 is a flip chip substrate, and the pad 33 on the upper surface thereof can also have the design of the recess 331 to accommodate the solder 34 as a pre-solder. . Thereby, when the wafer 15 201104814 4〇 and the circuit substrate 30 are soldered at a high temperature, the groove 451 of the pad 45 of the wafer 40 can also increase the solder joint strength between the pad 45 and the solder 46 and change the heat. The stress concentration point S is at the opening lip of the groove 451' and can reduce the maximum thermal stress, and improve the yield of the reliability test and the service life of the product. Furthermore, in the third embodiment, in order to make the pad 45 have a sufficient height (thickness), the present invention can further form a re-distribution layer on the protective layer 42a on the active surface of the wafer 40 (redistribution). The insulating layer 42b serves as the insulating layer 42 for the purpose of increasing the height (thickness) of the bonding pad 45. In addition, if the design of the circuit layer 41 of the active surface of the wafer 40 permits, it is also possible to select the hole of the pad 45 by laser drilling or mechanical drilling through the circuit layer 41' in the opening 421 of the insulating layer 42. The bottom of the groove 451 penetrates through the circuit layer 41 for a predetermined length (not shown) to further increase the joint area of the circuit layer 41 and the subsequently formed pad 45, thereby increasing the bonding strength. Alternatively, in another embodiment, under the premise that the pad 45 of the wafer 40 already has the recess 451, the upper surface of the pad 33 of the circuit substrate 30 may also remain flat, and the recess 331 is omitted. Designed and disposed only on the upper surface of the pad 33. As described above, the pre-solder 14 on the pad 13 of the package for use in the first and second drawings is convex with the pad 2 After the combination of the block 24 10, it is still easy to cause the problem of the rupture surface 15 due to the thermal stress concentration of the gentleman's eight of the circuit layer 11 and the pad 13 , and the present invention of the third 埤 junction 5 FIG. The groove 331 is formed in the pad 33 of the carrier structure such as the circuit board 30 to fill the solder 34, and the solder 34 is disposed on the upper surface of the pad 33, which can effectively increase the solder % and the solder. Bonding area and bonding strength between the pads 33. Furthermore, when the solder bumps 33 and the solder 34 are soldered, they can transfer thermal stress to the opening lip of the recess 331 to reduce the risk of forming a rupture surface on the surface of the recess 311 of the solder fillet 31. At the same time, the structure of the groove 331 can also reduce the maximum thermal stress, thereby improving the yield of the reliability test and the service life of the product. Although the present invention has been described in detail, it is not intended to limit the present invention, and those skilled in the art can make various modifications and modifications without departing from the spirit and scope of the present invention. The person defined in the attached Patent Application Park shall prevail. BRIEF DESCRIPTION OF THE DRAWINGS A substrate having a pre-solder package and a schematic view of a wafer having a conventional bump 1A and 1B. Fig. 2 is a schematic view showing the first embodiment of the present invention. 3A to 3D of the carrier plate for semiconductor package structure: A flow chart of a method of manufacturing a semiconductor package for a semiconductor package according to the first embodiment of the present invention. Fig. 4 is a schematic view showing the structure of the semiconductor material of the first embodiment of the present invention before the stepping and bonding. Fig. 5 is a view showing the construction of the semiconductor material of the first embodiment of the present invention after the combination of the selection of 2011-04814. 6A to 6D are flowcharts showing a method of manufacturing a carrier for a semiconductor package structure according to a second embodiment of the present invention. Fig. 7 is a view showing the semiconductor package structure of the third embodiment of the present invention before solder bonding. [Description of main components] 10 Package substrate 11 Circuit layer 12 Solder mask 121 Opening 13 Pad 14 Pre-solder 15 Fracture surface 20 Wafer 21 Circuit layer 22 Protective layer 23 Under bump metal layer 24. Bump 30 Circuit board 31 Circuit layer 311 recess 32 insulating layer 321 opening 33 pad 331 groove 34 solder 40 wafer 41 circuit layer 411 recess 42 insulating layer 42a protective layer 42b re-insulating layer 421 opening 43 under bump metal layer 44 bump 45 soldering Pad 451 groove 46 solder S thermal stress concentration point