TWI462255B - Package structure, substrate structure and preparation method thereof - Google Patents

Description

Package structure, substrate structure and preparation method thereof

The invention relates to a package structure, a substrate structure and a preparation method thereof, in particular to a square-sided leadless package structure, a substrate structure and a preparation method thereof.

A quad flat no-lead (QFN) semiconductor package is a package unit that exposes the wafer holder and the bottom surface of the pin to the bottom surface of the package layer, and is generally surface mount technology (SMT). A quadrilateral planar leadless semiconductor package is attached to the printed circuit board to form a circuit module having a specific function.

Referring to Figure 1, a cross-sectional view of a conventional quad flat no-lead (QFN) package structure is shown. As shown in the figure, the conventional QFN packaging process places the semiconductor wafer 11 on the lead frame 12, and is electrically connected by a wire-bonding process, and covers the encapsulant 13 to protect the semiconductor wafer 11. Not subject to external environment interference.

However, after the singulation process of the foregoing package structure, the cutting of the tool causes the pin 14 of the package structure to have a burr. When the distance between the two pins 14 is small, the excessive burr contacts the adjacent pin. 14 causes a short circuit; in addition, during the molding process, the encapsulant 13 easily overflows to contaminate the lower surface of the lead 14, so that a process for removing the residue of the pin 14 is additionally added.

In view of the lack of the aforementioned prior art, a new generation of QFN package structures have been developed (for example, Japanese Patent Nos. 11-251505, 09-312355, 2001-024135, and 2005-317998), as shown in FIG. 2, but this After the package structure is connected to the printed circuit board (PCB) by soldering, if the rework is required, the package structure is removed from the printed circuit board, which often causes the coplanarity of the pins to be poor or induced. The plating on the foot falls off, which in turn makes the overall package structure less reworkability and is prone to pin drop problems.

Therefore, how to avoid various problems in the above-mentioned prior art, and solve the problem that the pins of the square-sided planar leadless package structure are prone to burrs and poor reworkability have become a problem to be solved at present.

In view of the above-mentioned deficiencies of the prior art, the present invention provides a substrate structure including: a carrier having a plurality of recesses on one surface thereof; a first insulating protective layer formed on a surface of the carrier having the recess and formed a plurality of first insulating protective layer openings corresponding to the recesses; solder is formed in each of the recesses; and a patterned metal layer is formed on the first insulating protective layer and the solder, and the solder is connected The patterned metal layer has a plurality of electrical connection pads; and a second insulation protection layer is formed on the patterned metal layer and the first insulation protection layer, and has a plurality of second insulation corresponding to each of the electrical connection pads The protective layer is opened.

The present invention further provides a package structure, comprising: a substrate comprising: a first insulating protective layer having opposite first and second surfaces, and a plurality of first insulating layers extending through the first surface and the second surface a protective layer is formed in the opening of each of the first insulating protective layer and protrudes from the first surface; and the patterned metal layer is formed on the second surface of the first insulating protective layer and the solder And connecting the solder and having a plurality of electrical connection pads; and a second insulation protection layer formed on the second surface of the patterned metal layer and the first insulation protection layer, and having a plurality of corresponding exposed electrical connections a second insulating protective layer of the pad; the semiconductor wafer is disposed on the substrate and electrically connected to the patterned metal layer; and the encapsulant is formed on the second insulating protective layer and coated A semiconductor wafer and an electrical connection pad.

The present invention provides a method for fabricating a substrate structure, comprising: forming a first insulating protective layer on a surface of a carrier member, the first insulating protective layer having a plurality of first insulating protective layers exposing a portion of the surface of the carrier member a hole, wherein the carrier has a plurality of recesses corresponding to the first insulating protective layer opening; solder is filled in each of the recesses; and a patterned metal layer is formed on the first insulating protective layer and the solder, the patterned metal layer And a plurality of electrical connection pads; and forming a second insulation protection layer on the patterned metal layer and the first insulation protection layer, the second insulation protection layer having a plurality of second insulation protection corresponding to each of the electrical connection pads Layer opening.

The invention provides a method for manufacturing a package structure, comprising: providing a substrate structure, comprising: a carrier having a plurality of recesses on a surface thereof; and a first insulating protective layer formed on a surface of the carrier having the recess; And forming a plurality of first insulating protective layer openings corresponding to the recesses; solder is filled into each of the recesses; a patterned metal layer is formed on the first insulating protective layer and the solder, and the solder is connected The patterned metal layer has a plurality of electrical connection pads; and a second insulation protection layer is formed on the patterned metal layer and the first insulation protection layer, and has a plurality of corresponding portions of the electrical connection pads a second insulating protective layer is provided; a semiconductor wafer is disposed on the substrate structure, and the semiconductor wafer is electrically connected to the patterned metal layer; and an encapsulant is formed on the second insulating protective layer to encapsulate the semiconductor wafer And electrically connecting the pad; and removing the carrier to expose the first insulating protective layer and each of the solder.

As can be seen from the above, since the present invention is to form a solder (solder ball) firmly on the lead in the process, and the solder is exposed in the final step, the coplanarity and bonding of the solder are good, and the residual The stress is low, and thus has better reworkability; in addition, the process of the invention is relatively simple, and no burrs are generated at the pins, which is beneficial to the overall cost reduction and the increase of the yield.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper" and "one" as used in the specification are merely for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship is changed or adjusted. Substantially changing the technical content is also considered to be within the scope of the invention.

Please refer to FIGS. 3A to 3M, which are cross-sectional views showing the substrate structure, the package structure, and the method of manufacturing the same according to the present invention.

First, as shown in FIG. 3A, a carrier 30 is provided, and a first insulating protective layer 31 is formed on one surface of the carrier 30. The material of the carrier 30 can be a conductive material, such as aluminum or copper. Or a material that can be electrically conductive, and the first insulating protective layer 31 can be a solder resist layer (such as green paint) or the material of the first insulating protective layer 31 can be an insulating material, and the insulating material can be a photosensitive material. .

Then, as shown in FIG. 3B, a portion of the first insulating protective layer 31 is removed, so that a plurality of first insulating protective layer openings are formed in the first insulating protective layer 31 to expose a portion of the surface of the carrier 30. 310, the first insulating protective layer opening 310 can be designed according to the circuit layout when the product is to be soldered to the circuit board. In this embodiment, after the positive photoresist is used, after the exposure and development process, a portion of the first insulating protective layer 31 is removed to form the first insulating protective layer opening 310. In other embodiments, a negative photoresist can also be utilized to achieve the above results.

As shown in FIG. 3C, a portion of the carrier 30 in each of the first insulating protective layer openings 310 is removed to form a plurality of recesses 300, wherein the carrier 30 can be removed by etching or computer numerical control. (CNC) processing.

As shown in FIG. 3D, each of the recesses 300 is filled with a solder 32, wherein the solder 32 is filled in by electroplating or printing, and after the solder 32 is filled, a reflow step can be performed to remove the solder 32. A void in the solder 32.

As shown in FIG. 3E, a conductive layer 33 is formed on the first insulating protective layer 31 and the solder 32. The conductive layer 33 is formed by electroless plating, sputtering, or electron beam evaporation.

As shown in FIG. 3F, a resist layer 34 is formed on the conductive layer 33, and the resist layer 34 has a plurality of resistive opening 340 of the conductive layer 33 exposed.

As shown in FIG. 3G, a metal layer 35 is formed on the conductive layer 33 in each of the barrier layer openings 340, and the material of the metal layer 35 is, for example, copper.

As shown in FIGS. 3H to 3I, the resist layer 34 and the conductive layer 33 covered thereon are removed. At this time, the metal layer 35 and the conductive layer 33 constitute the patterned metal layer 36, and the patterned metal layer 36 is formed. There is a plurality of electrical connection pads 361. The patterned metal layer 36 is a single layer structure and is disposed flat on the first insulating protective layer 31.

As shown in FIG. 3J, a second insulating protective layer 37 is formed on the patterned metal layer 36 and the first insulating protective layer 31. The second insulating protective layer 37 has a plurality of corresponding portions of the electrical connecting pads 361. Two insulating protective layer openings 370. A portion of the first insulating protective layer 31 is in direct contact with a portion of the second insulating protective layer 37.

As shown in FIG. 3K, a surface treatment layer 38 is formed on each of the electrical connection pads 361. The surface treatment layer 38 is made of nickel/gold. This constitutes the substrate structure of the present invention.

As shown in FIG. 3L, a semiconductor wafer 40 is disposed on the second insulating protective layer 37, and the semiconductor wafer 40 and the electrical connection pad 361 are electrically connected by a plurality of bonding wires 41, and the second insulating protective layer is disposed on the second insulating protective layer 37. The encapsulant 42 is formed on the 37, and the encapsulant 42 covers the semiconductor wafer 40, the bonding wire 41 and the electrical connection pad 361.

As shown in FIG. 3M, the carrier 30 is removed, and the solder 32 is exposed; for example, an alkaline etching solution can be used for etching to etch the carrier 30 without etching the solder. 32; at this time, the re-reflow process is included. This constitutes the package structure of the present invention.

The present invention provides a substrate structure, comprising: a carrier 30 having a plurality of recesses 300 on one surface thereof; a first insulating protective layer 31 formed on the surface of the carrier 30 having the recess 300 and having a plurality of corresponding portions The first insulating protective layer opening 310 of each of the recesses 300 is exposed; the solder 32 is formed in each of the recesses 300; the patterned metal layer 36 is formed on the first insulating protective layer 31 and the solder 32, and has a plurality of electrical connection pads 361; and a second insulation protection layer 37 formed on the patterned metal layer 36 and the first insulation protection layer 31, and having a plurality of second insulation protection corresponding to the external connection pads 361 Layer opening 370.

The present invention further provides a package structure, comprising: a first insulation protection layer 31 having a first surface 31a and a second surface 31b opposite thereto, and a plurality of first insulation protections penetrating the first surface 31a and the second surface 31b The layer 32 is formed in each of the first insulating protective layer openings 310 and protrudes from the first surface 31a. The patterned metal layer 36 is formed on the first insulating protective layer 31. The second surface 31b and the solder 32 have a plurality of electrical connection pads 361; the second insulating protection layer 37 is formed on the second surface 31b of the patterned metal layer 36 and the first insulating protection layer 31, and has a plurality of Corresponding to the second insulating protective layer opening 370 of each of the electrical connecting pads 361; the semiconductor wafer 40 is disposed on the second insulating protective layer 37; the plurality of bonding wires 41 are electrically connected to the semiconductor wafer 40 and the electric The bonding pad 361 and the encapsulant 42 are formed on the second insulating protective layer 37 and cover the semiconductor wafer 40, the bonding wire 41 and the electrical connection pad 361.

In the foregoing substrate structure and package structure, a surface treatment layer 38 is further formed on each of the electrical connection pads 361.

In the substrate structure and package structure of the present invention, the surface treatment layer 38 is made of nickel/gold.

In the substrate structure and the package structure, the solder 32 is flush with the surface of the first insulating protective layer 31.

It should be noted that the present invention is also applicable to a flip chip package structure under the same implementation concept.

In summary, compared with the prior art, since the present invention is to form a solder on the pin stably in the process, and the solder is exposed in the final step, the coplanarity and bonding of the solder are compared. Good, and the residual stress is low, and thus has better reworkability; in addition, the process of the invention is relatively simple, and no burrs are generated at the lead, which is beneficial to the overall cost reduction and the increase of the yield.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

11,40. . . Semiconductor wafer

12. . . Lead frame

13,42. . . Encapsulant

14. . . Pin

30. . . Carrier

300. . . Concave

31. . . First insulating protective layer

31a. . . First surface

31b. . . Second surface

310. . . First insulating protective layer opening

32. . . solder

33. . . Conductive layer

34. . . Resistance layer

340. . . Resistive opening

35. . . Metal layer

36. . . Patterned metal layer

361. . . Electrical connection pad

37. . . Second insulating protective layer

370. . . Second insulating protective layer opening

38. . . Surface treatment layer

41. . . Welding wire

Figure 1 is a cross-sectional view of a conventional quad flat no-lead package structure;

Figure 2 is a cross-sectional view of another conventional quad flat no-lead package structure;

3A to 3M are cross-sectional views showing a substrate structure, a package structure, and a method of manufacturing the same according to the present invention.

30. . . Carrier

300. . . Concave

31. . . First insulating protective layer

310. . . First insulating protective layer opening

32. . . solder

33. . . Conductive layer

35. . . Metal layer

36. . . Patterned metal layer

361. . . Electrical connection pad

37. . . Second insulating protective layer

370. . . Second insulating protective layer opening

Claims (11)

A substrate structure includes: a carrier having a plurality of recesses on a surface thereof; a first insulating protective layer formed on a surface of the carrier having the recess, and forming a plurality of first insulation protection corresponding to each of the recesses a layer of openings; a solder is formed in each of the recesses; a patterned metal layer is formed on the first insulating protective layer and the solder, and the solder is connected to the patterned metal layer and has a plurality of electrical connection pads; And a second insulating protective layer formed on the patterned metal layer and the first insulating protective layer, and having a plurality of second insulating protective layer openings corresponding to the respective electrical connecting pads. A package structure includes: a substrate comprising: a first insulating protective layer having opposite first and second surfaces; and a plurality of first insulating protective layers opening through the first surface and the second surface Solder is formed in each of the first insulating protective layer openings and protrudes from the first surface; a patterned metal layer is formed on the second surface of the first insulating protective layer and solder and is connected to the solder And having a plurality of electrical connection pads; and a second insulation protection layer formed on the second surface of the patterned metal layer and the first insulation protection layer, and having a plurality of corresponding corresponding to each of the electrical connection pads An insulating protective layer is formed on the substrate, and is electrically connected to the patterned metal layer; and an encapsulant is formed on the second insulating protective layer and encapsulates the semiconductor wafer and the electric Sex connection pad. The structure according to claim 1 or 2, further comprising a surface treatment layer formed on each of the electrical connection pads. The structure of claim 3, wherein the surface treatment layer is made of nickel/gold. A method for fabricating a substrate structure, comprising: forming a first insulating protective layer on a surface of a carrier member, wherein the first insulating protective layer has a plurality of first insulating protective layer openings exposing a part of a surface of the carrier member, wherein The carrier has a recess corresponding to each of the openings of the first insulating protective layer; solder is filled in each of the recesses; and a patterned metal layer is formed on the first insulating protective layer and the solder, the patterned metal layer has a plurality of And forming a second insulating protective layer on the patterned metal layer and the first insulating protective layer, the second insulating protective layer having a plurality of second insulating protective layer openings corresponding to the exposed electrical connecting pads . A method for manufacturing a package structure, comprising: providing a substrate structure, comprising: a carrier having a plurality of recesses on a surface thereof; a first insulating protective layer formed on a surface of the carrier having the recess and formed with a plurality of Corresponding to the opening of the first insulating protective layer exposing each of the recesses; solder is filled into each of the recesses; a patterned metal layer is formed on the first insulating protective layer and the solder, and the solder is connected, the patterning a metal layer having a plurality of electrical connection pads; and a second insulation protection layer formed on the patterned metal layer and the first insulation protection layer, and having a plurality of second insulation layers corresponding to the respective electrical connection pads a semiconductor wafer is disposed on the substrate structure, and the semiconductor wafer is electrically connected to the patterned metal layer; and an encapsulant is formed on the second insulating protective layer to encapsulate the semiconductor wafer and electrically connect a pad; and removing the carrier to expose the first insulating protective layer and each of the solder. The method of fabricating the structure of claim 5, wherein the step of forming the patterned metal layer comprises: forming a conductive layer on the first insulating protective layer and the solder; forming a resistance on the conductive layer a layer having a plurality of exposed portions of the conductive layer; a metal layer formed on the conductive layer in each of the barrier layers; and removing the resist layer and the conductive layer covered thereby, the metal The layer and the conductive layer form the patterned metal layer. A method of fabricating a structure as described in claim 5 or 6, further comprising forming a surface treatment layer on each of the electrical connection pads. The method of fabricating the structure of claim 8, wherein the surface treatment layer is made of nickel/gold. The method of fabricating the structure of claim 5, wherein the method of filling the solder is electroplating or printing. The method of fabricating the structure of claim 7, wherein the conductive layer is formed by electroless plating, sputtering or electron beam evaporation.