1332696 •九、發明·說明： •【發明所屬之技術領域】 本發明係有關於一種半導體封裝基板結構及其製 法，更詳而言之，係關於一種於形成絕緣保護層之前形成 導電柱之半導體封裝基板結構及其製法。 【先前技術】 自從IBM公司在I960年早期引入覆晶封裝（Flip Chip Package)技術以來，相較於打線（Wire Bond)技術，覆晶技 術之特徵在於半導體晶片與基板間的電性連接係透過焊錫 ' 凸塊而非一般之金線；而該種覆晶技術之優點在於該技術 可提高封裝結構佈線密度，且可降低封裝結構整體尺寸， 同時，該種覆晶技術不需使用導電路徑較長之金線，故可 提高電性功能。有鑑於此，業界在陶瓷基板上使用高溫焊 錫，即所謂控制崩解之晶片連接技術（Control-Collapse Chip Connection, C4)，已有多年之久。近年來，由於高密 鲁度、高速度以及低成本之半導體元件需求之增加，同時因 應電子產品之體積逐漸縮小的趨勢，將覆晶元件設置於低 * 成本的有機電路板（例如，印刷電路板或基板），並以環氧 /樹脂底膠（Underfill resin)填充於晶片下方以減少矽晶片與 有機電路板之結構間因熱膨脹差異所產生的熱應力。 在現行覆晶技術中，半導體積體電路（1C)晶片的表面 上配置有電極塾（electronic pad )而有機電路板亦具有相 對應的電性連接墊，於該晶片以及電路板之間可以適當地 設置焊錫凸塊或其他導電黏著材料，使該晶片係以電性接 5 110140 觸面朝下·的方式設置於該電路板上，盆 電黏著材料係提-令"知錫凸塊或導 械性的連接。片及電路板間的電性連接以及機 動而盘f 1圖所不’覆晶技術係將-半導體晶片1〇之主 凸塊12,㈣二二’於該電極塾101上形成有-導電 電路板U 有複數電性連接墊11卜並於兮 二路板u及電性連接塾η…形成 ：： =該=層13形成有開一露出該電= 該絕緣保=v:=r導電柱14,並且凸出於 日υ衣面’於该導電枝14 了苜品u 焊錫材料15，使哕預丨曰總## 、上形成有—預 應m 預斗錫材料15與該導電凸塊12相對 ❹箱 ㈣預焊騎料15㈣之迴烊溫度條件下， 使忒預焊錫材料15結合該導電凸 ^下 充材料16填充於嗲半導麵a * ，後以一底部填 保該半導體曰片1〇與電路板11之間，以確 可靠2 ^ 1G與電路板U之間的電性連接完整性與 電路材料16係為具有流動性之材質，習知 ’’°又计可對其流動位置進行限制之社構，告1 广 16填充於該半導體晶片與電路板:間時： 3充材料16易產生溢流’而影響該電路板"之表面 =第2入至20圖’係為該電路 '成導電柱之製程’主要係於-包含有電性連接塾= 110140 1332696 上形成一絕緣保護層21，並形成有開孔210以 ^备出毛路板20之電性連接塾2〇1，如第Μ圖所示 ί =錢緣保護層21及其開孔叫中之表面形成-導ΐ =二於該導電層22表面形成有—阻層23，且該阻層 形成有開孔230以外露出該電性連接墊2〇ι上之導電声 22,且該阻層開孔23G大於該絕緣保護層開孔训，如^ 2B圖所示，·㈣藉由該導電層22作為電鍍製程之電 導路從’以於該阻層開孔230中之電性連接墊加上 形成導電柱24，並且於該阻層開孔23〇中形成凸緣24ι; 如弟2C圖所示；最後移除該阻層23及其所覆蓋之導❹ 22，亚於該導電柱24外露之凸緣241表面形成一接心 25 ’以保護該導電柱24夕卜露之凸緣241表面，如第2 所示。 然’上述習知製法中’該絕緣保護層開孔21〇之尺寸 及該阻層開孔230之尺寸皆十分微細，一般約介於2〇_ 至3 0㈣之間’故對位極為不易，為使該阻層開孔2 3 〇可 與該絕緣保護層開孔210對位，通常將該阻層開孔23〇之 尺寸加大，藉以降低對位的困奠隹度及提高製程對位準破度。 惟加大該阻層開孔230之尺寸，導致該導電柱24&之 頂面產生凸緣241，使該些導電柱24之間的間距必須加 大，如此即無法於該導電柱24頂面上形成細間距之預焊 凸塊。 此外，上述習知製法中，該導電柱24與其下之電性 連接塾201之間具有導電層22，因額外以化學沉積或物理 7 110140 1332696 ‘二積:形成之導電層，其與導電柱及電性連 因此Λ Λ担 連接塾201之間的結合力。 免底部埴充二二出一種半導體封裝基板及其製法，以避 免底。Ν真充材料產生溢流、無法形成細間 = 加製程困難度及時間、以及導 主、、 力不佳科與電性連純之間結合 I【發明内容】 成為目前業界亟待克服之難題。 供缺點’本發明…目的在於提 種+V組封裴基板結構及其製法，得於電腺如夕 連接墊上形成細間距之導電柱。 、 私 構於提供-種半導體封裝基板結 太：法传叫升導電柱與電性連接墊之間…力。 構及其=之^;免目广的Λ於提供—種半導體封震基板結 衣法传避免底部填充材料之流動位置。 為達上述目的，本發明提供— 構，係包括：電路板，至少體封裝基板結 ，複數導電柱，係分別形成於該電路板=^性連接墊； .以及絕緣輕層，係形狀該㈣m面之電性連接塾； 層表面來士 表面’且於該絕緣保護 ^成凹部以露出各該導•之頂部及其周圍表面。 該電表面復包括有介電層，於該介電層表面具有 介電層與電性連接塾之間具有-導 與線路層=包括有複數線路’並於該介電層 錫、鎳^ ¥ 該導電層之材料係選自銅、 、。、欽及銅·鉻合金所㈣纽之其中-者，或該導 110140 8 1332696 電層可為導電向分子材料。 該導電柱之材料係選自錯、錫、銀、銅、金、叙、録 鋅、鎳、鍅、鎂、銦、碲以及鎵等金屬之其中一者。 依上述之結構，本發明之導電柱之外表面復包括有 接著層，以供後續接S-主動面具有導電凸塊之半導體, 本發明復提供-種半導體㈣基板結構之製法，係包 括·提供一至少一表面具有複數電性連接塾之電路板；於 各該電性連接墊上形成導電柱；以及於該電路板表面形成 ::: 象保護層’且該絕緣保護層表面形成凹部以露出各該 導毛柱之頂部及其周圍表面。 括有：製法，該電路板具有電性連接塾之表面復包 路，該電性連㈣及線路之製程係包括 電層之電路板；於該介電層表面形成-導電 成複數$層上形成—第—阻層，且於該第—阻層中形 #心以露出部份該導電層；以及於各該開 形成該電性連接墊及線路。 私，又 金所:❹m鉻' 鈦及銅·鉻合 該導電柱之萝稆仫a 々夺电间刀子材枓。 二阻層，且二:包括：於該第一阻層上形成有-第 開口；於該等且層中對應該電性連接塾位置形成有 成該導電柱.二梦之電性連接墊表面以電鍍或化學鍍形 電層。电柱，以及移除該第二、第一阻層及其所覆蓋之導 110140 9 鎳 =導電柱可選自鉛、錫、銀，銅、金、絲、銻、鋅、 ·、鋼、碲以及鎵等金屬之i中一者.禮白乜 該導電杈之外夺而报士一心鸯之者，復包括於 且古道φ 、形成接著層，以供後續接置一主動面 八有v電凸塊之半導體晶片。 要得葬i*所迷’本發明之半導體封裝基板結構及其製法主 電路^声形成線路所需之導電層作爲電流傳導路徑，於該 於兮電路2電連接墊上直接錢形成導電柱，之後復 >形成絕緣保制，且於賴緣保護層一表 ^ ，電柱，因此，本發明係於該形 形成该絕緣保護層，俾可避免習知 係於電路板表面形成絕绫 衣矛中 哆丨、4保4層，之後復利用钱製程於 路板表面之電性連接塾上形成導電 緣保護層之間對位問題，故阻 户層，、、、，邑 Α ^ 丨層曝先顯影之開孔須略大於 ::護層之開孔，而導致導電柱具形成於 時 有凸緣，進而料妹之間距無法料，収夺 ，性連接^料在料電層，料料妹與電接^ 之間結合力降低等問題。 < # & 此外’本發明中，該絕緣保護層表面係形成—用 出導電柱之凹部，因此，在進行後續之半導體晶 業填充底部填充材料，可藉由該凹部有效限㈣以= 充材料之流動位置，避免產生溢膠的情況。 ^ 【實施方式】 以下之實施例係進-步詳細說明本發明之觀點，但並 非以任何觀點限制本發明之範_。 ” Π0140 10 電結:㈤兒明本發明之電路板底面之導 貝她例之剖面示意圖。 請參閲第3Α R - . t λ1 , ^ 圖，百先提供至少—表面形成有介 31之電路板3〇， 恭 四小取韦；丨电層 導電層32主要作" _ 1上形成一導電I 32，該 種，Α可由金’’’] ^電鐘金屬材料所需之電流傳導路 鋅、鉻、鈦'V沉積數層金屬層所構成’如選自銅、锡、 你、聚苯單層或多層結構’或可使用例如聚乙 、1妝或有機硫聚合物等導電高分子材料。 點人=第Μ，於該導電層32上利用印刷、旋塗或 光形成一第一阻層33 ’且該第-阻層33藉由曝 雷路拓Ml ” 形成有钹數個開口 330,以露出 電：„分之導電層32,該第—阻層Μ可為—例 D乾Μ或液態光阻等光阻層（ph〇t〇resist)。 請參閱第3C圖，於該第—阻層33之開口 33()中之導 電^2,面進行電_e伽plating)製程藉由該導電層 Ά電特性，俾在進行電料作為電流傳導路徑，以在 该等開口 330中電鑛形成有線路34及電性連接墊μ，且 該線路34或電性連接塾341電性連接該電路板％内之線 路層（圖式中未表示）；㈣於電路板形成導電線路及電性 連接塾之製程技術繁多，乃業界所周知之製程技術，非本 I月之重點’為避免核糊本發明之技術特徵，故未再予贅 述。 請參閱第3D圖，於該第_阻層33上以印刷、旋塗或 貼合等方式形成-第二阻層35’該第二阻層％係為一例 110140 11 如乾膜或液態光阻等光阻層⑽—灿 影等圖案化製程使該第二阻声）再猎由曝光、顯 電性連接墊341之開口 35〇 複數個相對應於該 〇 ’俾以露出該電性連接熱341。 请參閲第3E圖，_路板30進由 該導電層32具導電特性作為電流傳導路等= 乃〇中之电性連接墊341上電鍍形 柱36係以化學鍍形成於該開π 350中：6 導電 表面；該導電柱36之材料 锡、、：41 鉍、銻、鋅、鋅U加 錫、銀、銅、金、 者.…鎂、銦、碲以及鎵等金屬之其中-者，准，依貫際操作之經驗，由 且成本較低，該導電柱為成熟之被電鍍材料 非以此為限。 6 μ讀鋼所構成者為較佳，但 請參閲第3F圖，移除該第二 其所覆蓋弟阻層33及 ::閱第3〇圖’於該電路板3〇之介電層 ，：::Π:37;於本實施例中，係利用印刷、旋塗丄 Γ 及導電桂36表面，該絕緣保護層37 絕緣防烊材料，例如以環氧樹脂為基材之綠漆 亦可為錫與防焊特性之材料所製成，該絕緣保護層37 之材料所制及無機之抗氧_之任—具有縮_防輝特性 之材t所製成’並非以綠漆為限。 30矣月/閲第3H圖，於該絕緣保護層37中對應該電路板 面之導電柱區域形成-凹部37〇，以露出該等導電 110140 1332696 柱。於本實施例中，係於該絕緣保護 未示)，並於未覆蓋有有導電柱部分之絕光罩(圖 曝光’使該絕緣保護層37被曝光部份進行局進仃 爾後移除該絕緣保護層37未被曝光部份（未硬化 =於該絕緣保護層37表面形成該凹部37。露:等 ^=6頂部及其周圍表面，之後該絕緣保護層、37 = 下未被曝光部份再進行曝光，使該 化成形。 凡全硬 請參閲第31圖，之後復可於等導電柱^之 形成一層接著層38;該接著層38之材料係選自銅路^面 :;銀、鎳、金、-、鱗及其個別成份之合金，或該接著 層38可由一有機保焊劑（OSP)製成。 請參閱第4圖，之後復可將—半導體晶片4G接置於 δ亥導電柱36上，立中兮车道曰y 电徑蛩4U1上形成有—導電凸塊41，而 二腐路板3〇之‘電柱36表面形成有-接著層38,使該接 ^層38與該導電凸塊41相對應使其電性連接；之後以底 Ρ真充材料42填充於該半導體晶片4G與絕緣保護層 之凹部370之間，以將該半導體晶片4〇結合該電路板％。 依上述製法，本發明復提出一種半導體封裝基板結 八係包括.屯路板3〇，至少一表面具有複數電性連接 、341 ·’複數導電柱36，係形成於該電路板3G表面之電性 連接塾341 ±，以及絕緣保護層37，係形成於該電路板％ 面且於忒絕緣保濩層37表面形成一凹部以露出該等導 110140 13 丄： ==:部二於後續之半導體晶片覆晶作業填充底 流動方向，值、H亥凹部有效限制該底部填充材料之 邻二卩避免造成溢流；又該絕緣保護層中形成凹 部，可由該凹部容納邻八夕道+ 支S τ小成凹 而可降低半導-㈣/ 4每兀件及底部填充材料，進 降低體封裝件之整體厚度。 上述貫施例僅例示性說明^ ^ ^ 非用於限财發明。任何觀其功效’而 Jb , , 7痛白此項技蟄之人士均可在X凌 月本魯明之精神及範疇 逆 變。因此，本發明之權利伴二述V:進 範圍所列。 ㈣保4乾圍’應如後述之申請專利 【圖式簡單說明】 第1圖係顯示習知之覆晶元件剖面示意圖； 製純之電㈣接端結構 及其==:=發明之半導體封裝基板結構 第4圖係顯示經由本發明之劁 板上接晉本蜜μ曰ΰ 形成的半導體封裝基 极上接置丰導體晶片之剖面視圖。 【主要元件符號說明】 10 ' 40 半導體晶片 101、401 電極墊 11 ' 20 ' 30 電路板 ⑴、201 、 341 12、41 電性連接墊 導電凸塊 110140 15 13326961332696 • IX, invention, description: • Technical field to which the invention pertains. The present invention relates to a semiconductor package substrate structure and a method of fabricating the same, and more particularly to a semiconductor for forming a conductive pillar before forming an insulating protective layer Package substrate structure and its manufacturing method. [Prior Art] Since IBM introduced the Flip Chip Package technology in the early I960, the flip chip technology is characterized by the electrical connection between the semiconductor wafer and the substrate compared to the Wire Bond technology. Solder 'bumps instead of the usual gold wires; and the advantage of this flip chip technology is that the technology can increase the package structure wiring density and reduce the overall size of the package structure. At the same time, the flip chip technology does not need to use conductive paths. The long gold wire can improve the electrical function. In view of this, the industry has used high-temperature solder on ceramic substrates, the so-called Control-Collapse Chip Connection (C4), which has been used for many years. In recent years, due to the increasing demand for high-density, high-speed, and low-cost semiconductor components, and in response to the trend of shrinking the size of electronic products, flip-chip components have been placed on low-cost organic circuit boards (for example, printed circuit boards). Or a substrate) and filled under the wafer with an epoxy/underfill resin to reduce the thermal stress caused by the difference in thermal expansion between the structure of the germanium wafer and the organic circuit board. In the current flip chip technology, an electronic pad is disposed on the surface of the semiconductor integrated circuit (1C) wafer, and the organic circuit board also has a corresponding electrical connection pad, and the chip and the circuit board can be appropriately disposed. Solder bumps or other conductive adhesive materials are disposed on the circuit board in such a manner that the electrical contact is electrically connected to the circuit board, and the pot is electrically adhered to the material. Guided connection. The electrical connection between the chip and the circuit board and the maneuvering of the disk f 1 are not the flip chip technology, the main bump 12 of the semiconductor wafer 1 , ( 4 ) 22 ' is formed with a conductive circuit on the electrode 101 The board U has a plurality of electrical connection pads 11 and is formed on the second board u and the electrical connection ...η:: = = the layer 13 is formed with an opening to expose the electricity = the insulation guarantee = v: = r conductive column 14, and protruded from the sundial clothing surface 'in the conductive branch 14 of the product u solder material 15, so that the 哕 丨曰 丨曰 total # #, formed on the - pre-m pre-powder tin material 15 and the conductive bump 12 ❹ ❹ ( 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 预 四 预 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 Between the chip 1 and the circuit board 11, to ensure reliable electrical connection integrity between the 2 ^ 1G and the circuit board U and the circuit material 16 is a material having fluidity, the conventional ''° The structure in which the flow position is restricted is reported to be filled between the semiconductor wafer and the circuit board: 3: the filling material 16 is prone to overflow and affects the circuit The surface of the plate " the second into the 20th figure is the process of forming the conductive column into the circuit. The main process is to form an insulating protective layer 21 on the electrical connection 110 = 110140 1332696, and the opening is formed. 210 to prepare the electrical connection 毛2〇1 of the hairboard 20, as shown in the figure ί = the edge of the edge protection layer 21 and its opening is formed - guide ΐ = two in the conductive layer 22 a resistive layer 23 is formed on the surface, and the resistive layer is formed with an opening 230 to expose the conductive sound 22 on the electrical connection pad 2〇, and the resistive opening 23G is larger than the insulating protective layer opening, such as ^B, as shown in FIG. 2B, by using the conductive layer 22 as an electrical conduction path for the electroplating process, the conductive pillars 24 are formed from the electrical connection pads in the barrier layer 230, and the barrier layer is opened. A flange 24 is formed in the 23 ;; as shown in FIG. 2C; finally, the resist layer 23 and the guide rib 22 covered thereon are formed, and a surface 25 ′ is formed on the surface of the exposed flange 241 of the conductive post 24 to The surface of the flange 241 of the conductive post 24 is protected as shown in FIG. However, in the above conventional method, the size of the insulating protective layer opening 21〇 and the size of the resistive opening 230 are very fine, generally between 2〇_ and 30 (four), so the alignment is extremely difficult. In order to make the barrier opening 2 3 对 align with the insulating protection layer opening 210, the size of the barrier opening 23 通常 is generally increased, thereby reducing the difficulty of alignment and improving the process alignment. Quasi-breakage. However, the size of the opening 230 of the resist layer is increased, so that the top surface of the conductive pillar 24 & generates a flange 241, so that the spacing between the conductive pillars 24 must be increased, so that the top surface of the conductive pillar 24 cannot be A fine pitch pre-solder bump is formed thereon. In addition, in the above conventional manufacturing method, the conductive pillar 24 and the electrical connection port 201 therewith have a conductive layer 22, because of additional chemical deposition or physical 7 110140 1332696 'two product: formed conductive layer, which is combined with the conductive pillar And the electrical connection is therefore the bonding force between the ports 201. A semiconductor package substrate and a method of manufacturing the same are omitted from the bottom to avoid the bottom. ΝThere is no problem with the overflow of the material, the inability to form the fineness = the difficulty and time of the process, and the combination of the main conductor, the poor force and the electrical integrity Disadvantages of the present invention... The object of the invention is to provide a +V group sealing substrate structure and a method for producing the same, which are obtained by forming fine pitch conductive pillars on the electrical gland such as the mat. , privately provided - a kind of semiconductor package substrate junction too: the law is called between the conductive column and the electrical connection pad ... force. The structure and the ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ To achieve the above object, the present invention provides a circuit board comprising: a circuit board, at least a body package substrate, and a plurality of conductive pillars respectively formed on the circuit board=^ connection pad; and an insulating light layer, the shape of the (four) m The electrical connection of the surface is 塾; the surface of the layer of the celestial surface is 'and the insulation is protected into a recess to expose the top of each of the guides and its surrounding surface. The electrical surface further includes a dielectric layer having a dielectric layer and an electrical connection between the dielectric layer and the conductive layer = including a plurality of lines □ and the dielectric layer tin, nickel The material of the conductive layer is selected from the group consisting of copper and . , Chin and copper · chrome alloy (four) New Zealand - or the guide 110140 8 1332696 electrical layer can be conductive molecular materials. The material of the conductive pillar is selected from the group consisting of metal such as erbium, tin, silver, copper, gold, ruthenium, zinc, nickel, strontium, magnesium, indium, bismuth and gallium. According to the above structure, the outer surface of the conductive pillar of the present invention further includes an adhesive layer for subsequently connecting the semiconductor having the conductive bump to the S-active surface. The present invention provides a method for fabricating a semiconductor (four) substrate structure, including Providing a circuit board having at least one surface having a plurality of electrical connections; forming a conductive pillar on each of the electrical connection pads; and forming a surface on the surface of the circuit board: and forming a recess to expose the surface of the insulating protective layer The top of each of the hair guide columns and its surrounding surface. The method includes: a method, the circuit board has a surface-covered circuit of an electrical connection, and the electrical connection (four) and the process of the circuit comprise a circuit board of the electrical layer; forming a conductive layer on the surface of the dielectric layer Forming a first-resistive layer, and forming a #心 in the first resist layer to expose a portion of the conductive layer; and forming the electrical connection pads and lines in each of the openings. Private, and gold: ❹m chrome 'titanium and copper · chrome. The conductive column of the radish a 々 电 电 electric knife 枓. a second resist layer, and two: comprising: forming a first opening on the first resistive layer; forming a conductive pillar in the layer corresponding to the electrical connection 塾. Electroplated or electrolessly electroformed. The electric column, and the second and first resist layers and the covered 110140 9 nickel = conductive pillars may be selected from the group consisting of lead, tin, silver, copper, gold, silk, bismuth, zinc, steel, ruthenium And one of the metals such as gallium. The white 乜 乜 乜 乜 乜 杈 杈 杈 杈 杈 杈 杈 杈 杈 杈 杈 杈 杈 杈 杈 杈 杈 报 报 报 报 报 报 报 报 报 报 报 报 报 报 报 报 报 报 报 报 报 报 报 报A bumped semiconductor wafer. To be buried in the semiconductor package substrate structure of the present invention and the main circuit of the method for forming the circuit, the conductive layer required for forming the circuit is used as a current conduction path, and the conductive column is directly formed on the electrical connection pad of the circuit 2, after which The insulation layer is formed and insulated from the surface of the protective layer. Therefore, the present invention forms the insulating protective layer in the shape, and the structure can be prevented from being formed on the surface of the circuit board.哆丨, 4, 4 layers, after the re-use of the money process on the electrical connection on the surface of the road surface to form a conductive edge protection layer between the alignment problem, so the barrier layer,,,,, 邑Α ^ 丨 layer exposure The opening of the development must be slightly larger than: the opening of the sheath, and the conductive column is formed with a flange at the time, and the distance between the sisters is unpredictable, and the material is connected to the material layer. Problems such as reduced adhesion between the electrical connection and the electrical connection. <#& In addition, in the present invention, the surface of the insulating protective layer is formed by using a concave portion of the conductive pillar, and therefore, the filling of the underfill material in the subsequent semiconductor crystal industry can be effectively limited by the concave portion (four) to = Fill the material's flow position to avoid spillage. [Embodiment] The following examples are intended to describe the present invention in detail, but do not limit the scope of the invention in any way. Π0140 10 Electric junction: (5) A schematic view of the bottom of the circuit board of the present invention. Please refer to Section 3 R - . t λ1 , ^ Figure, providing at least a surface-forming circuit Plate 3 〇, 恭四小取韦; 丨 electrically conductive layer 32 mainly for " _ 1 to form a conductive I 32, this kind, Α can be gold '''] ^ electric clock metal material required current conduction path Zinc, chromium, titanium 'V deposited several layers of metal layer 'such as selected from copper, tin, you, polystyrene single layer or multi-layer structure' or can use conductive polymers such as polyethylene, 1 makeup or organic sulfur polymer Material: dot person=third, a first resist layer 33' is formed on the conductive layer 32 by printing, spin coating or light, and the first resist layer 33 is formed with a plurality of openings by exposing the lightning path M1" 330, to expose electricity: „ separate conductive layer 32, the first resist layer Μ can be - such as D dry or liquid photoresist photoresist layer (ph〇t〇resist). Please refer to Figure 3C, The conductive layer 2 in the opening 33 () of the first resist layer 33 is subjected to an electric galvanic plating process, and the electric current is used as a current conduction. a path for electrically forming a line 34 and an electrical connection pad μ in the opening 330, and the line 34 or the electrical connection 341 is electrically connected to the circuit layer in the circuit board % (not shown in the drawing) (4) There are many process technologies for forming conductive lines and electrical connections on the circuit board. It is a well-known process technology in the industry. It is not the focus of this month. In order to avoid the technical features of the invention, it will not be repeated. Referring to FIG. 3D, the second resist layer 35 is formed on the first resist layer 33 by printing, spin coating or lamination. The second resist layer is an example 110140 11 such as a dry film or a liquid photoresist. The photoresist layer (10) - a patterning process such as a smear and the like, causes the second snoring to be hunted by the opening 35 of the exposed, galvanic connection pad 341, corresponding to the 〇' 俾 to expose the electrical connection heat 341 Referring to FIG. 3E, the conductive layer 32 has a conductive property as a current conduction path, etc., and the electrical connection pad 341 on the electrical connection pad 341 is formed by electroless plating on the π. 350: 6 conductive surface; the material of the conductive pillar 36 is tin,: 41 铋, 锑, zinc, U plus tin, silver, copper, gold, .... Magnesium, indium, antimony and gallium, among other metals, quasi-internal operation experience, low cost, the conductive column is mature The material is not limited to this. It is better to construct the 6 μ steel, but please refer to the 3F figure, remove the second cover layer 33 and: see the third diagram 'in the circuit The dielectric layer of the board 3::::: 37; in this embodiment, the surface of the printed, spin-coated, and conductive guinea 36 is used, and the insulating protective layer 37 is insulated from the ruthenium-proof material, for example, epoxy resin. The green paint for the substrate can also be made of tin and solder-proof material, and the material of the insulating protective layer 37 is made of inorganic anti-oxidation-- 'Not limited to green paint. 30 矣 / 3H, in the insulating protective layer 37 corresponding to the conductive column area of the circuit board surface forming a recess 37 〇 to expose the conductive 110140 1332696 column. In this embodiment, the insulation protection is not shown), and the insulating cover that is not covered with the conductive pillar portion (the exposure is performed to remove the exposed portion of the insulating protective layer 37) The insulating protective layer 37 is not exposed (unhardened = the recess 37 is formed on the surface of the insulating protective layer 37. Dew: etc. ^=6 top and its surrounding surface, after which the insulating protective layer, 37 = unexposed portion And then performing exposure to form the film. For all hard, please refer to Fig. 31, and then form a layer of subsequent layer 38 on the conductive pillars; the material of the layer 38 is selected from the copper surface: An alloy of silver, nickel, gold, -, scales and individual components thereof, or the backing layer 38 may be made of an organic solder resist (OSP). Referring to Figure 4, the semiconductor wafer 4G is then attached to δ. On the conductive pillar 36, a conductive bump 41 is formed on the 兮 电 电 U 4U1 of the middle 兮 lane, and the surface of the electric ram 36 of the second rot board is formed with a layer 38 to make the layer 38 Corresponding to the conductive bumps 41, they are electrically connected; then, the semiconductor wafer 4G is filled with the bottom dummy material 42 Between the recesses 370 of the protective layer, the semiconductor wafer 4 is bonded to the circuit board %. According to the above method, the present invention further provides a semiconductor package substrate comprising eight types of circuit boards, at least one surface having a plurality of electric The 341.' plurality of conductive pillars 36 are electrically connected to the surface of the circuit board 3G, and the insulating protective layer 37 is formed on the surface of the circuit board and on the surface of the insulating layer 37. Forming a recess to expose the conductive guide 110140 13 丄: ==: the second portion of the semiconductor wafer flip-chip operation fills the bottom flow direction, and the value H H recess effectively limits the adjacent defect of the underfill material to avoid overflow; Further, a concave portion is formed in the insulating protective layer, and the concave portion can accommodate the adjacent Ba-Xi channel + the support S τ to form a concave shape, thereby reducing the semi-conductive - (4) / 4 pieces and the underfill material, and reducing the overall thickness of the body package. The above-mentioned examples are only illustrative of the fact that ^ ^ ^ is not used for the invention of limited wealth. Anyone who looks at the effect of 'Jb , , 7 Pain this technology can invert the spirit and scope of X Lingyue Ben Luming Therefore, the present invention The second paragraph of V is as follows: (4) Bao 4 dry circumference 'should be patented as described later [Simple description of the drawing] Fig. 1 shows a schematic cross-sectional view of a conventional flip chip element; pure electric (four) terminal structure And ==:=Invention of the semiconductor package substrate structure Fig. 4 is a cross-sectional view showing the connection of the abundance conductor wafer on the semiconductor package base formed by the bonding of the present invention. DESCRIPTION OF SYMBOLS 10 ' 40 Semiconductor wafer 101, 401 Electrode pad 11 ' 20 ' 30 Circuit board (1), 201, 341 12, 41 Electrical connection pad Conductive bump 110140 15 1332696
13、 2,1、37 絕緣保護層 130 ' 210 絕緣保護層開孔 14、 24、36 導電柱 15 預焊錫材料 16、 42 底部填充材料 22、 32 導電層 23 阻層 230 阻層開孔 241 凸緣 25、 38 接著層 31 介電層 33 第一阻層 330 第一阻層開口 34 線路 35 第二阻層 350 第二阻層開口 370 凹部 16 11014013, 2, 1, 37 Insulating protective layer 130 ' 210 Insulating protective layer opening 14, 24, 36 Conductive column 15 Pre-solder material 16, 42 Underfill material 22, 32 Conductive layer 23 Resistive layer 230 Resistive layer opening 241 convex Edge 25, 38 Next Layer 31 Dielectric Layer 33 First Resistive Layer 330 First Resistive Layer Opening 34 Line 35 Second Resistive Layer 350 Second Resistive Layer Opening 370 Concave 16 110140