TW201036114A - Wafer level chip scale package and its fabricating method - Google Patents

Abstract

Disclosed are a wafer level chip scale package and its fabricating method. The chip package mainly comprises a bumped chip and an encapsulant. The chip has an active surface, a back surface, and a plurality of sides between the active and back surfaces. The active surface, the back surface, and the sides of the chip are covered with the encapsulant to completely encapsulate the chip and to partially embed the bumps with the bumps are visibly extruded from the bottom of the encapsulant. Therefore, the encapsulant can completely protect the chip and fasten the bumps to prevent from mechanical damage or moisture intrusion, and provide a better stress distribution against the bumps broken.

Description

201036114 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a Wafer Level Chip Seale Paekage (WLCSP) and a method of fabricating the same. [Prior Art] In the conventional chip package structure, the wafer is disposed on a larger-sized base plate, and the internal electrical connection between the wafer and the substrate can be divided into a flip chip bonding and a wire bonding (wire). B〇nding). The flip chip bonding system previously provides bumps on the wafer, and then flips the wafer to be placed on the substrate, and the bumps are electrically connected. Usually, the wafer package structure after fabrication is re-bonded to the external printed circuit board for use as an electronic component, so the chip package structure still needs to be electrically connected to the external printed circuit board by the substrate, and the wafer cannot be reached. The components of the wafer size package are miniaturized. Referring to FIG. 1, a conventional flip chip type package structure 100 includes a wafer 110, a plurality of bumps 120, an underfill 130, a substrate 140, and a plurality of solder balls 15A. The wafer 11 has an active surface 111, an opposite back surface 1, 2 side surfaces 3, and a plurality of pads 114 formed on the active surface 111. The bumps 120 are disposed on the pads 11 4 . The wafer 11 is flip-chip bonded to the substrate 140 by the bumps 120. The underfill 1 30 is formed between the wafer 110 and the substrate 1 4 to seal the bumps 120. Therefore, the flip chip type wafer package structure 1 must be bonded to the external printed circuit board by the substrate 1 40 3 201036114 and the solder balls 150 disposed under the substrate 140. In addition, the underfill 130 is typically used to protect or secure the bumps 12〇. However, the portion not covered by the underfill 13 ,, for example, the back surface 112 of the wafer 110 and the portions 113 of the wafer 110 are easily damaged by the infiltration of moisture. Further, since the coefficients of thermal expansion between the wafer 110 and the substrate 140 are not the same, when the coefficients of thermal expansion do not match, the warpage of the substrate 140 is liable to occur. In particular, when the difference in size between the substrate 140 and the wafer 110 is larger, the warpage is more pronounced and the miniaturization of the wafer level wafer size is not achieved. Wafer-level wafer size package means that the package structure has a size close to or equal to the size of the wafer, and the semiconductor package operation is completed in a crystalline (quad) state, usually a component that does not include a substrate.

China's invention patent certificate number 1303870, whose patent name is "wafer package structure k and its manufacturing method", discloses that a constituent element of a wafer level wafer size package structure does not include a substrate. Although the (4) prior art technique does not require the provision of a substrate, the encapsulation system for protecting the wafer is formed on the back side of the wafer and the four sides are not invaded by the exposed active surface. When the matching coefficient does not match, it will cause the active surface of the crystal to cover the wafer, and the moisture will still be 'when the sealing body is solidified or the difference between the stress on the active surface and the back surface of the thermal expansion sheet becomes larger, resulting in warpage of the wafer, even Cracked. In addition, the conductive bumps for external bonding are completely exposed to the sealant without being protected by the sealant. Therefore, the conductive bumps are susceptible to breakage or deformation due to the influence of the force, or the electrical function is degraded by the influence of moisture. . 4 201036114 SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a wafer level wafer size package structure and a manufacturing method thereof, which can omit the substrate and have the effect of comprehensively protecting the wafer to avoid mechanical damage or Water vapor π into 'can avoid wafer warpage caused by the difference in thermal expansion coefficient between the wafer and the sealant.次 次 The second object of the present invention is to provide a wafer level wafer size sealing structure and a manufacturing method thereof, which can provide a good stress distribution to avoid bump breakage and prevent deformation of the bump under temperature cycling. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a wafer level wafer size package structure, which mainly comprises a wafer, a plurality of bumps and a glue material. The wafer has an active surface, a back surface, and a plurality of sides between the active surface and the surface, and a plurality of pads are disposed on the active surface. The bumps are disposed on the pads. The sealant covers the active surface of the wafer, the back surface and the sides to completely seal the wafer and partially embed the bumps, and the bumps protrudely protrude from the sealant a bottom surface. The present invention further discloses a method of fabricating the above wafer level wafer size sealing structure. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing wafer level wafer size package construction, the protrusions of the bumps may be between one third and one third of the height of the bumps. The protrusions of the bumps may be arcuate surfaces in the wafer level wafer package structure described above. In the former "wafer-level wafer size system can be used to prepare for the λ 傅 傅 傅 丁 匕 匕 匕 匕 匕 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 In the size package structure, the sealant is a G-material or an underfill. In the wafer-level wafer size package structure of the :::, the sealant covers: the thickness of the dynamic surface is not less than the coverage The thickness of the back side is two minutes

The wafer level you are tracking is a columnar bump. In the wafer level wafer size package structure of the solder material, a plurality of layers may be further included to cover the portions of the bump material protruding from the sealant. In the wafer level wafer size sealing structure described, the bumps may comprise copper. In the wafer level wafer size package construction described above, the size of the sealant is compatible with wafer level wafer size packages. It can be seen from the above technical solution that the wafer level wafer size package structure of the present invention has the following advantages and effects: the chip can be completely sealed by the sealing material and the partial embedded bumps are simultaneously used as one of the technical means. Wafer-level wafer size package architecture can omit the base plate and completely seal the wafer and only partially expose the bumps, so that the wafer can be comprehensively protected to avoid mechanical damage or moisture reversal, and to avoid wafer and sealant The warpage of the wafer is caused by the difference in thermal expansion coefficient. 6 201036114 The specific sealing pattern of the sealing material of the wafer and the bump can be sealed by the sealing material as a technical means, and the bump is partially embedded in the sealing material and has a protruding portion locally exposed in the sealing material, which can provide Good f-force distribution to avoid bump breakage and prevent deformation of 6 blocks under temperature cycling. Third, the use of substrates and underfills for wafer-level packaging technology for fully sealed wafers can be achieved by stepping the wafers onto the stencil, cutting the wafer stencil, and cutting the sealant. Forming a sealant material, can provide a kind of first and can be omitted. Fourth, the gap between the wafer and the template can be formed in the step of the combination, and the wafer can be singulated separately before the step of sealing. The sealant is completely sealed in the sealing step to avoid the problem of wafer warpage caused by the stress generated by the sealant during curing shrinkage. The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. Therefore, only the components and combinations related to the case are shown. The components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some ratios of dimensions and other related dimensions are either exaggerated or simplified. To provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. In accordance with a first embodiment of the present invention, a wafer level wafer size package configuration is illustrated in cross-section of Fig. 2. The wafer level crystal 7 201036114 Ο 片 chip size package structure 200 mainly comprises a wafer 210, a plurality of bumps 220 and a glue 23 〇. The wafer 21 has an active surface 21, a back surface 212, and a plurality of side surfaces 2 1 3 between the active surface 211 and the back surface 212. Usually, the wafer 2 is usually in the shape of a rectangular block or a square block, so that it has four wafer-cut sides 2丨3. The main material of the wafer 210 is a semiconductor such as germanium. The active surface 211 refers to a surface on which a wafer is used to form an integrated circuit or an active component. After forming an integrated circuit or component, a passivation layer is usually covered on the active surface 211 to serve as a surface insulation. Protection. Referring to Fig. 2 again, a plurality of pads 214 are provided on the active surface 2n. The pads 214 can be arranged in an array, arranged in a perimeter, or in a single/multiple row center; & dry y researcher u琛 arranged. Preferably, it can be arranged in an array. The pads 214 may be made of copper or aluminum. A metal layer of a material such as gold, titanium, tungsten, copper or the like is formed on the pads 214 to increase the bonding strength between the pads 214 and the bumps 22 . Referring to Fig. 2, the two sleeves 220 are disposed on the pads 214 as external input/output electrodes of the wafers 21. In the application, the wafer level wafer package package and the package structure 200 are bonded to an external printed circuit 妒r& tower (not shown) by the bumps 220. In the present embodiment, the bumps 220 can be 踔枓 几 , , , , , , , , , , , , , σ σ σ σ σ σ σ σ σ σ σ σ σ σ σ σ σ σ σ σ σ σ σ σ σ σ σ σ Substrate. The convex bumps 220 may be formed by electroplating or printing, and the bumps 220 are generally made of tin-lead or lead-free solder, or may include copper, silver, nickel, gold, Materials such as platinum or palladium. 8 201036114 Please refer to the figure 2, the active surface 211, 1 of the sealant 230 210 is in the next day and the side surface 213 is provided to provide the day 21G Completely airtight sealed environment. That is to say, h is completely sealed by the 23G of the glue material, so the complete sealing of the sealing material 230 of the wafer can reach a few golden magic protection. In this embodiment, the thick cover of the active surface 211, the thickness 效T1 of the effect sealing material 230 can be not less than one-half of the thickness T2 of the cover 212, and the wafer is finely balanced by the surface.热 Thermal stress of the bearing surface 211 and the main bearing of the back surface 212. The thickness of the thick coffin 230 covering the sides 213 may be less than the thickness T1 of the encapsulant 2U. Please refer to the third material (4) not only to completely seal the wafer 21. The block 220 is not blocked, and the block 2 is embedded with the protrusions 220 to protrude prominently from the bottom surface 231 of the sealant 23'. Specifically, the packaged block 220 is bonded to the wafer 21/', sealing the four positions of the convex moon to avoid breakage at the joint, and affecting the quality of the telecommunication connection to produce the protrusion yH1 of the block 220. In this embodiment, the ridges and the protrusions H1 are between the convex ones and the thirds, and the 丨, , p 疋·the degree H2 is protruded. The bumps (four) can be round (four). The sealant 2 may comprise an epoxy compound. Specifically, the sealant 230 can be molded. And the sealing material 23 can be used to fix the bumps, so that the bumps can be prevented from being displaced during the reflow process: the conventional underfill or the amount of underfill is reduced. This is the round wafer size package for today's yen. In other words, the size of the wafer-level wafer size structure is roughly equivalent to 9 201036114 = the size of the sheet 210, and not more than 15 times, so the wafer-level cymbal size has a slit structure. Small package size and suitable for electronic product chip packages that emphasize thin, light and short features.

Therefore, in summary, the sealant 23Q can completely seal the crystal _ and at the same time partially (4) the seal pattern of the bumps, and the substrate can be omitted in the package wood to completely seal the wafer (4) and The bumps 220 are only partially exposed. And 'the wafer 21 can be completely protected by the sealing material 230, so as to achieve the comprehensive protection of the wafer 21' function" not only can avoid the wafer 210 from causing angular collapse 'mechanical damage or moisture infiltration' is more avoidable The wafer generated by the difference in thermal expansion coefficient between the wafer 21A and the sealant 23〇 is intended to be curved. In addition, since the bumps 220 are partially embedded in the sealant 23 and have a protruding portion partially exposed to the sealant 230, the sealant 23() can provide a good stress distribution. The bumps are prevented from being broken, and the bumps 22 are prevented from being deformed under temperature cycling. The present invention also discloses a method of fabricating the wafer level wafer package structure described above, which can be exemplified in the cross-sectional view of the device in the process of the third embodiment. First, please refer to the 'providing-wafer defect' shown in Figure 3A. The wafer 10 includes a plurality of the above-mentioned wafers 210'. The main surfaces 211 of the wafers 21 are provided with the turns 214' and the bumps 22 are disposed on the pads 214. The wafer 10 has a plurality of dicing streets 11' that are perpendicular to each other on the X and γ axes to define the locations at which the wafers 210 are formed. 10 201036114 Ο Ο Next, referring to FIG. 3, the wafer 1 is pressed to a template 20, and the wafer 10 is pressed in such a direction that the bumps 22 are oriented toward the template 2〇. Referring to Figures 3 and 3C, before the pressing, the template 20 is formed with a protective adhesive layer 3〇, so that after the pressing, the bumps 220 are partially embedded in the protective layer. A gap S1 is formed between the wafer and the protective layer 30 (as shown in a partially enlarged view of FIG. 3c) as a cover thickness of the sealant 23 on the active surface 211. The main function of the protective adhesive layer 3 is to fix the wafer ί and protect the bumps 22 when the wafer 10 is cut, to prevent the bumps 220 from being damaged by stress, and further fixing the bumps Wafer 2 1 〇 so that it does not scatter after cutting. Preferably, the protective adhesive layer w is a photo-sensitive adhesive tape, and the adhesiveness of the protective adhesive layer 30 can be reduced or lost by light irradiation in a subsequent process. The template 2 can have a light transmissive property to facilitate illumination of the illumination light through the template 2 to the protective adhesive layer 30. Specifically, the wafer 1 is not in close contact with the template 20 and can be supported by the template 20 as a hard material to support the protective layer 30 ′ to ensure the wafer 丨〇 relative to the template The parallelism of 2〇' is such that the gap S1 between the wafer 10 and the protective layer 30 can be controlled to be equal. Then, as shown in FIGS. 3C and 3D, the wafer 10 is cut, and the <RTI ID=0.0># </ RTI> </ RTI> has a plurality of sides 213 between the active surface 211 and the back surface 212. . In this embodiment, the wafer 10 can be separated into a single wafer by using a cutting tool 40 /α. The method of cutting the wafer 10 can be performed in different embodiments. Adopt 11 201036114 laser light. Preferably, in the step of cutting and cutting the wafer, the cutting tool 40 does not cut the layer 3 and the template 2, and the board 20 can be repeated. When the mold is used, the rubber layer 30 is not adhered to the mold. In the cutting, the round 1 Λ (5) 5 Xuanbao 隹 knife mouth] on the day 0 round 10, the gap S1 between the wafer 1 〇 and the layer 30 can be cut from the * decorative glue ^ ', the system 7 The depth of the wafer 1 可 can tolerate the error 'to ensure that the cutting tool 40 can cut through the wafer i&quot; and will not cut the protective layer 30 and the template 20. Please refer to the section of the map

As shown in the enlarged view of the ,, after the dicing, a slit S2 is formed between the side faces 213 of the crystal mo. In this embodiment, the slit S2 between the sides 2 1 3 of the wafers 21 is smaller than the gap s 1 between the wafers and the protective layer 30. Next, please refer to the Fig. 3E. figure, which is formed by a transfer molding technique to form the sealant 23 on the template. Referring to FIG. 3E and a partial enlarged view thereof, the sealant 23 is filled into the gap S1 ′ through the cutting slit s 2 between the sides 21 3 of the wafers 210 to completely seal the wafers. 210 and partially embed the bumps 22〇. The sealant 230 can cover the active surface 21 1 , the back surface 2 1 2 and the side surface 21 1 of the wafer 210 at the same time to avoid stress imbalance caused by the sealant 2 3 固化 during curing shrinkage. The sealant 203 warps. In the step of forming the sealant 230, the wafers 210 have been singulated and not integrally connected, so that the stress generated by the sealant 230 during curing shrinkage can be dispersed without a whole piece. The problem of wafer surface curvature. After the sealing step, please refer to the 3E and 3F drawings, the template 20 and the protective layer 30' are removed to expose the bumps 220 to the ground surface 12 201036114 for one of the bottom surfaces of the sealing material 230 231. Preferably, the protective adhesive layer 30 can be a photosensitive adhesive tape, so that when the protective adhesive layer 3 is removed, the adhesiveness of the protective adhesive layer 3 can be reduced by light irradiation, which is convenient. The protective adhesive layer 30 is peeled off, and part of the protective adhesive layer 3 is still adhered to the exposed portions of the bumps 220 without affecting the electrical connection quality of the bumps 220. In addition, in the foregoing sealing step, &lt; using the template 20 to make the protective adhesive layer 3 〇 have a flat surface, so that the bottom surface 231 of the ◎ seal (four) 230 can be formed into a relatively flat surface, avoiding the shape of the sealant 230 Irregular or the problem that the bottom surface 231 of the sealant 23 is uneven. Thereafter, as shown in Fig. 3G, the sealing material 23 can be cut by a cutting tool 50 such as a mechanical cutter or laser light to form a plurality of wafer-level wafer size package structures. In the step of cutting the sealant 23, the cutting slit s 3 formed by cutting the sealant 2 3 可 can be aligned and smaller than the cutting slit S2 between the sides 2 1 3 of the wafer 2 1 〇 2 The thickness of the cutting tool 50 used in the step of cutting the sealing material is less than that in the cutting. The thickness of the cutting tool used in the wafer 1 step. Therefore, the sealing material 230 is not cut to the wafers 2m, and the wafers are further prevented from being damaged. From the above, it is known that the manufacturing method can provide a wafer-level packaging technology that is the first to completely seal the ruthenium, so that it can be directly bonded to the left to omit the conventional substrate' and the use of the underfill can be omitted or reduced. Further, by using 13 201036114, the substrate wafer 210 and the sealant 210 have an anti-bending increase. The formation positions of the 230s are separately singulated before the sealing step, so that the 曰-曰/7 efficiency can be achieved. The shape of the bumps of the present invention is not limited to the following. In accordance with a second embodiment of the present invention, another wafer-level wafer size package structure 〇0 is illustrated in a cross-sectional view of FIG. The wafer-level wafer-scale package structure 300 includes the main components of the wafer 3, which are substantially the same as the wafer 210, the bumps 0 20, and the sealant 230 of the first embodiment, so that the first embodiment is The same reference numerals are given to the J 7L parts and the description is partially omitted. The wafer 210 has a main surface 211, a back surface 212, and a plurality of side surfaces 213 between the active surface 211 and the back surface 212, and a plurality of pads 214 are disposed on the active surface 211. The bumps 220 are disposed on the pads 214.兮〆 4 This seal 230 completely seals the crystal

The tabs 210 are partially embedded with the bumps 22, and the bumps 22 are exposed to the bottom surface 231 of the sealant 230. In this embodiment, the bumps 22G may be columnar bumps. Preferably, the bumps 220 are made of a high temperature resistant metal such as copper, and the bumps 220 can be used to maintain the level of external bonding of the wafer level wafer scale package structure 300. . In various embodiments, the material of the bumps 22 may comprise gold, copper, or aluminum or an alloy metal thereof. Referring to FIG. 4, in the embodiment, the wafer level wafer size package structure 300 may further include a plurality of solders 34, and the solders 34 are coated with the bumps 220 to protrude from the package. The part of the rubber material is used for welding to the outside. Therefore, the wafer level wafer size sealing structure 300 14 201036114 can save the substrate and achieve the comprehensive protection of the wafer, and can avoid the wafer warpage and the bump breakage. In addition, the wafer-level wafer size package teaches the manufacturing process of the method 300. The main steps involved in the manufacturing process are substantially the same as the main steps of the first device and the body embodiment, for example, providing a wafer, pressing a zigzag yen To the stencil, to cut the wafer, to form the sealant on the stencil, to remove the ruthenium to remove the stencil and the protective layer, and to cut the sealant. Manufacturing method of the wafer level wafer size 衮 structure 300

The middle portion may further include a step of forming a plurality of solders. The solder 340 is coated with the bumps 220 to protrude from the portion of the w β sealant 230. Wherein, the step of forming the solder 340 is exemplified; after the step of removing the template 20 and the protective layer 3〇. The present invention has been described in terms of a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The skilled person can do anything simple without departing from the technical scope of the present invention. Modifications, equivalent changes and modifications are still within the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional flip chip type wafer level wafer size package structure. Figure 2 is a cross-sectional view showing a wafer level wafer size package structure in accordance with a first embodiment of the present invention. 3A to 3G are diagrams showing the component wearing surface of the wafer level wafer size package structure in the process according to the first embodiment of the present invention. 15 201036114 FIG. 4 is a crystal according to a second embodiment of the present invention. A schematic cross-sectional view of a circular wafer size package construction. [Main component symbol description]

The protrusion T1 of the H1 bump and the dimension T1 of the H2 bump cover the thickness T2 of the active surface of the wafer. The thickness of the sealant covering the back surface of the wafer S1 The gap between the wafer and the protective layer S2 The side of the wafer Inter-cut slit S3 Cutting slit formed by cutting sealant 10 Wafer 11 Cutting pass 20 Template 30 Protective adhesive layer 40 Cutting tool 50 Cutting tool 100 Flip-chip wafer level wafer size package structure 110 Wafer 111 Active surface 112 Back 113 Side 114 Soldering Tip 120 Bump 130 Underfill 140 Substrate 150 Solder Ball 200 Wafer Level Wafer Size Package Construction 210 Wafer 211 Active Surface 212 Back Side 213 Side 214 Pad 220 Bump 221 Projection Surface 230 Sealant 231 Bottom Surface 16 201036114 300 wafer level wafer size package construction 3 4 0 solder

17

Claims (1)

201036114 VII. Patent application scope Ο 2 〇 4 kinds of wafer level wafer size package structure, including · 曰曰 片 ' has an active surface, a back surface and a plurality of sides between the active surface and the back surface, 1 a plurality of pads are disposed on the active surface; a plurality of bumps are disposed on the pads; and a sealant covering the active surface of the wafer, the back surface and the two sides are completely The wafer is sealed and partially embedded, and the bumps are exposed to protrude from one of the bottom surfaces of the sealant. Xizhu, according to the patent application model, in which the wafer-level wafer size package structure, the human dog height is between one-third and two-thirds of the peptide bump t-ancientity. - The bump is still manufactured according to the scope of the patent application, wherein the surface of the dog of the bump is a circular arc surface. According to the application of the scope of the patent application, the material of the slab is a, the size of the slab, and the material of the seal is called (eP〇xy). 3 by oxygen compound, according to the wafer level crystal of the scope of the patent application, the sealant is # θ size package structure, you insult the compound; according to the scope of claim 1 / Ge bottom filling gel. Wafer-level wafer:: The cover material is covered by the active: the thickness of the cover layer covering the back side is not less than the Japanese yen-level crystal film of the i-$ according to the patent application scope. Dimensional package 18 6 Ο 201036114 made these bumps as columnar bumps. 8. The wafer-level wafer size according to item 7 of the patent application scope&apos; further comprises a plurality of solders covering the portions of the bump sealing materials. 9. According to the wafer-level wafer size of claim 7 of the patent application, wherein the materials of the bumps comprise copper. 10. A wafer level wafer scale construction according to the scope of claim patent i, wherein the size of the sealant material conforms to a wafer level wafer seal. 11. A method of fabricating a wafer level wafer size package structure, the following steps: providing a wafer comprising a plurality of wafers, each wafer being an active surface and a back surface, and having a retanning on the active surface a bump is disposed on the pads; pressing the wafer to a template, the template is formed with a layer, the bumps are partially embedded in the protective layer, rounded and the protective layer Form a gap between them; knife. J is rounded so that each wafer has a plurality of sides between the back surface and the back surface; forming a sealant on the template, the sealant is filled through the cutting gap between the sides of the sheet After the gap is completed, the two bumps are partially embedded and partially embedded; the protective layer is removed, and the protective layer is exposed so that the bumps appear out of the flapping & And the package is formed to have a plurality of soldering protective adhesives and the active surface is completely sealed to expose the sealing material 19 201036114 to form a plurality of wafer level wafers Size package construction. 12. The method of fabricating a wafer level wafer size package according to claim 11 wherein after the template and the protective layer are removed, the bumps have a large exit angle between the bumps. The height is three-thirds / to two-thirds. The manufacturing method of the wafer level wafer size package structure according to claim 11, wherein after the template and the protective layer are removed, the protruding surfaces of the bumps are arcuate faces. 14. A method of fabricating a wafer-level wafer size package according to the U of the patent application scope wherein the template is light transmissive. 15. The method of fabricating a wafer level wafer size package according to claim U, wherein the protective layer and the template are not cut in the step of cutting the wafer. 16. A method of fabricating a wafer level wafer size package structure according to claim n, wherein the material of the sealant material comprises an epoxy compound. 17. A method of fabricating a wafer level wafer size package according to claim U of the patent application, wherein the sealant is a mold compound or an underfill. 18. The method of manufacturing a wafer level wafer size package according to the nth aspect of the patent application, wherein in the step of forming the sealing material, the sealing material covers the active covering of the wafers. Not less than 1/2 of the thickness of the back side of the wafers. 201036114 1 , according to the patent application scope of the flute 1 1 TS structure manufacturing method, the round wafer size package, in, in the step of cutting the sealant, the cutting slit formed by the escape of the sealant is aligned and smaller A slit is formed between the sides of the wafer so that the sealant still covers the sides of the wafer after cutting. 20 21 Ο The manufacturing method of the wafer level wafer size package structure according to the scope of the patent application, wherein the bumps are columnar bumps. According to the method of manufacturing the wafer level wafer package structure of the second aspect of the patent application, after the template and the protective layer are removed, the method further comprises: forming a plurality of solders to cover the plurality of solders The bump protrudes from the portion of the sealant. twenty one